[mirror_ubuntu-artful-kernel.git] / drivers / ata / pata_mpiix.c

/*
 * pata_mpiix.c 	- Intel MPIIX PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * The MPIIX is different enough to the PIIX4 and friends that we give it
 * a separate driver. The old ide/pci code handles this by just not tuning
 * MPIIX at all.
 *
 * The MPIIX also differs in another important way from the majority of PIIX
 * devices. The chip is a bridge (pardon the pun) between the old world of
 * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
 * IDE controller is not decoded in PCI space and the chip does not claim to
 * be IDE class PCI. This requires slightly non-standard probe logic compared
 * with PCI IDE and also that we do not disable the device when our driver is
 * unloaded (as it has many other functions).
 *
 * The driver conciously keeps this logic internally to avoid pushing quirky
 * PATA history into the clean libata layer.
 *
 * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
 * hard disk present this driver will not detect it. This is not a bug. In this
 * configuration the secondary port of the MPIIX is disabled and the addresses
 * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
 * to operate.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_mpiix"
#define DRV_VERSION "0.7.6"

enum {
	IDETIM = 0x6C,		/* IDE control register */
	IORDY = (1 << 1),
	PPE = (1 << 2),
	FTIM = (1 << 0),
	ENABLED = (1 << 15),
	SECONDARY = (1 << 14)
};

static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };

	if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
		return -ENOENT;

	return ata_std_prereset(link, deadline);
}

/**
 *	mpiix_error_handler		-	probe reset
 *	@ap: ATA port
 *
 *	Perform the ATA probe and bus reset sequence plus specific handling
 *	for this hardware. The MPIIX has the enable bits in a different place
 *	to PIIX4 and friends. As a pure PIO device it has no cable detect
 */

static void mpiix_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	mpiix_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. The MPIIX allows us to program the
 *	IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
 *	prefetching or IORDY are used.
 *
 *	This would get very ugly because we can only program timing for one
 *	device at a time, the other gets PIO0. Fortunately libata calls
 *	our qc_issue_prot command before a command is issued so we can
 *	flip the timings back and forth to reduce the pain.
 */

static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	int control = 0;
	int pio = adev->pio_mode - XFER_PIO_0;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 idetim;
	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	pci_read_config_word(pdev, IDETIM, &idetim);

	/* Mask the IORDY/TIME/PPE for this device */
	if (adev->class == ATA_DEV_ATA)
		control |= PPE;		/* Enable prefetch/posting for disk */
	if (ata_pio_need_iordy(adev))
		control |= IORDY;
	if (pio > 1)
		control |= FTIM;	/* This drive is on the fast timing bank */

	/* Mask out timing and clear both TIME bank selects */
	idetim &= 0xCCEE;
	idetim &= ~(0x07  << (4 * adev->devno));
	idetim |= control << (4 * adev->devno);

	idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	pci_write_config_word(pdev, IDETIM, idetim);

	/* We use ap->private_data as a pointer to the device currently
	   loaded for timing */
	ap->private_data = adev;
}

/**
 *	mpiix_qc_issue_prot	-	command issue
 *	@qc: command pending
 *
 *	Called when the libata layer is about to issue a command. We wrap
 *	this interface so that we can load the correct ATA timings if
 *	necessary. Our logic also clears TIME0/TIME1 for the other device so
 *	that, even if we get this wrong, cycles to the other device will
 *	be made PIO0.
 */

static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;

	/* If modes have been configured and the channel data is not loaded
	   then load it. We have to check if pio_mode is set as the core code
	   does not set adev->pio_mode to XFER_PIO_0 while probing as would be
	   logical */

	if (adev->pio_mode && adev != ap->private_data)
		mpiix_set_piomode(ap, adev);

	return ata_qc_issue_prot(qc);
}

static struct scsi_host_template mpiix_sht = {
	ATA_PIO_SHT(DRV_NAME),
};

static struct ata_port_operations mpiix_port_ops = {
	.set_piomode	= mpiix_set_piomode,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= mpiix_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= ata_cable_40wire,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= mpiix_qc_issue_prot,
	.data_xfer	= ata_data_xfer,

	.irq_clear	= ata_noop_irq_clear,
	.irq_on		= ata_irq_on,

	.port_start	= ata_sff_port_start,
};

static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	/* Single threaded by the PCI probe logic */
	static int printed_version;
	struct ata_host *host;
	struct ata_port *ap;
	void __iomem *cmd_addr, *ctl_addr;
	u16 idetim;
	int cmd, ctl, irq;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");

	host = ata_host_alloc(&dev->dev, 1);
	if (!host)
		return -ENOMEM;
	ap = host->ports[0];

	/* MPIIX has many functions which can be turned on or off according
	   to other devices present. Make sure IDE is enabled before we try
	   and use it */

	pci_read_config_word(dev, IDETIM, &idetim);
	if (!(idetim & ENABLED))
		return -ENODEV;

	/* See if it's primary or secondary channel... */
	if (!(idetim & SECONDARY)) {
		cmd = 0x1F0;
		ctl = 0x3F6;
		irq = 14;
	} else {
		cmd = 0x170;
		ctl = 0x376;
		irq = 15;
	}

	cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
	ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
	if (!cmd_addr || !ctl_addr)
		return -ENOMEM;

	ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);

	/* We do our own plumbing to avoid leaking special cases for whacko
	   ancient hardware into the core code. There are two issues to
	   worry about.  #1 The chip is a bridge so if in legacy mode and
	   without BARs set fools the setup.  #2 If you pci_disable_device
	   the MPIIX your box goes castors up */

	ap->ops = &mpiix_port_ops;
	ap->pio_mask = 0x1F;
	ap->flags |= ATA_FLAG_SLAVE_POSS;

	ap->ioaddr.cmd_addr = cmd_addr;
	ap->ioaddr.ctl_addr = ctl_addr;
	ap->ioaddr.altstatus_addr = ctl_addr;

	/* Let libata fill in the port details */
	ata_std_ports(&ap->ioaddr);

	/* activate host */
	return ata_host_activate(host, irq, ata_interrupt, IRQF_SHARED,
				 &mpiix_sht);
}

static const struct pci_device_id mpiix[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },

	{ },
};

static struct pci_driver mpiix_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= mpiix,
	.probe 		= mpiix_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

static int __init mpiix_init(void)
{
	return pci_register_driver(&mpiix_pci_driver);
}

static void __exit mpiix_exit(void)
{
	pci_unregister_driver(&mpiix_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, mpiix);
MODULE_VERSION(DRV_VERSION);

module_init(mpiix_init);
module_exit(mpiix_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_mpiix.c - Intel MPIIX PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* The MPIIX is different enough to the PIIX4 and friends that we give it
	7	* a separate driver. The old ide/pci code handles this by just not tuning
	8	* MPIIX at all.
	9	*
	10	* The MPIIX also differs in another important way from the majority of PIIX
	11	* devices. The chip is a bridge (pardon the pun) between the old world of
	12	* ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
	13	* IDE controller is not decoded in PCI space and the chip does not claim to
	14	* be IDE class PCI. This requires slightly non-standard probe logic compared
	15	* with PCI IDE and also that we do not disable the device when our driver is
	16	* unloaded (as it has many other functions).
	17	*
	18	* The driver conciously keeps this logic internally to avoid pushing quirky
	19	* PATA history into the clean libata layer.
	20	*
c961922b	21	* Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
669a5db4 JG	22	* hard disk present this driver will not detect it. This is not a bug. In this
	23	* configuration the secondary port of the MPIIX is disabled and the addresses
	24	* are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
	25	* to operate.
	26	*/
	27
	28	#include <linux/kernel.h>
	29	#include <linux/module.h>
	30	#include <linux/pci.h>
	31	#include <linux/init.h>
	32	#include <linux/blkdev.h>
	33	#include <linux/delay.h>
	34	#include <scsi/scsi_host.h>
	35	#include <linux/libata.h>
	36
	37	#define DRV_NAME "pata_mpiix"
a0fcdc02	38	#define DRV_VERSION "0.7.6"
669a5db4 JG	39
	40	enum {
	41	IDETIM = 0x6C, /* IDE control register */
	42	IORDY = (1 << 1),
	43	PPE = (1 << 2),
	44	FTIM = (1 << 0),
	45	ENABLED = (1 << 15),
	46	SECONDARY = (1 << 14)
	47	};
	48
cc0680a5	49	static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	50	{
cc0680a5	51	struct ata_port *ap = link->ap;
669a5db4	52	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
92ae7849	53	static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
669a5db4	54
92ae7849	55	if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
c961922b	56	return -ENOENT;
d4b2bab4	57
cc0680a5	58	return ata_std_prereset(link, deadline);
669a5db4 JG	59	}
	60
	61	/**
	62	* mpiix_error_handler - probe reset
	63	* @ap: ATA port
	64	*
	65	* Perform the ATA probe and bus reset sequence plus specific handling
	66	* for this hardware. The MPIIX has the enable bits in a different place
	67	* to PIIX4 and friends. As a pure PIO device it has no cable detect
	68	*/
	69
	70	static void mpiix_error_handler(struct ata_port *ap)
	71	{
	72	ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	73	}
	74
	75	/**
	76	* mpiix_set_piomode - set initial PIO mode data
	77	* @ap: ATA interface
	78	* @adev: ATA device
	79	*
	80	* Called to do the PIO mode setup. The MPIIX allows us to program the
7b4f1a13 SS	81	* IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
7b4f1a13 SS	82	* prefetching or IORDY are used.
669a5db4 JG	83	*
	84	* This would get very ugly because we can only program timing for one
	85	* device at a time, the other gets PIO0. Fortunately libata calls
	86	* our qc_issue_prot command before a command is issued so we can
	87	* flip the timings back and forth to reduce the pain.
	88	*/
	89
	90	static void mpiix_set_piomode(struct ata_port ap, struct ata_device adev)
	91	{
	92	int control = 0;
	93	int pio = adev->pio_mode - XFER_PIO_0;
	94	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	95	u16 idetim;
	96	static const /* ISP RTC */
	97	u8 timings[][2] = { { 0, 0 },
	98	{ 0, 0 },
	99	{ 1, 0 },
	100	{ 2, 1 },
	101	{ 2, 3 }, };
	102
	103	pci_read_config_word(pdev, IDETIM, &idetim);
7b4f1a13 SS	104
7b4f1a13 SS	105	/* Mask the IORDY/TIME/PPE for this device */
669a5db4	106	if (adev->class == ATA_DEV_ATA)
7b4f1a13	107	control \|= PPE; /* Enable prefetch/posting for disk */
669a5db4	108	if (ata_pio_need_iordy(adev))
7b4f1a13 SS	109	control \|= IORDY;
7b4f1a13 SS	110	if (pio > 1)
669a5db4 JG	111	control \|= FTIM; /* This drive is on the fast timing bank */
	112
	113	/* Mask out timing and clear both TIME bank selects */
	114	idetim &= 0xCCEE;
7b4f1a13 SS	115	idetim &= ~(0x07 << (4 * adev->devno));
7b4f1a13 SS	116	idetim \|= control << (4 * adev->devno);
669a5db4 JG	117
	118	idetim \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
	119	pci_write_config_word(pdev, IDETIM, idetim);
	120
	121	/* We use ap->private_data as a pointer to the device currently
	122	loaded for timing */
	123	ap->private_data = adev;
	124	}
	125
	126	/**
	127	* mpiix_qc_issue_prot - command issue
	128	* @qc: command pending
	129	*
	130	* Called when the libata layer is about to issue a command. We wrap
	131	* this interface so that we can load the correct ATA timings if
3a4fa0a2	132	* necessary. Our logic also clears TIME0/TIME1 for the other device so
669a5db4 JG	133	* that, even if we get this wrong, cycles to the other device will
	134	* be made PIO0.
	135	*/
	136
	137	static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc)
	138	{
	139	struct ata_port *ap = qc->ap;
	140	struct ata_device *adev = qc->dev;
	141
	142	/* If modes have been configured and the channel data is not loaded
	143	then load it. We have to check if pio_mode is set as the core code
	144	does not set adev->pio_mode to XFER_PIO_0 while probing as would be
	145	logical */
	146
	147	if (adev->pio_mode && adev != ap->private_data)
	148	mpiix_set_piomode(ap, adev);
	149
	150	return ata_qc_issue_prot(qc);
	151	}
	152
	153	static struct scsi_host_template mpiix_sht = {
68d1d07b	154	ATA_PIO_SHT(DRV_NAME),
669a5db4 JG	155	};
	156
	157	static struct ata_port_operations mpiix_port_ops = {
669a5db4 JG	158	.set_piomode = mpiix_set_piomode,
	159
	160	.tf_load = ata_tf_load,
	161	.tf_read = ata_tf_read,
	162	.check_status = ata_check_status,
	163	.exec_command = ata_exec_command,
	164	.dev_select = ata_std_dev_select,
	165
	166	.freeze = ata_bmdma_freeze,
	167	.thaw = ata_bmdma_thaw,
	168	.error_handler = mpiix_error_handler,
	169	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	170	.cable_detect = ata_cable_40wire,
669a5db4 JG	171
	172	.qc_prep = ata_qc_prep,
	173	.qc_issue = mpiix_qc_issue_prot,
0d5ff566	174	.data_xfer = ata_data_xfer,
669a5db4	175
358f9a77	176	.irq_clear = ata_noop_irq_clear,
246ce3b6	177	.irq_on = ata_irq_on,
669a5db4	178
81ad1837	179	.port_start = ata_sff_port_start,
669a5db4 JG	180	};
	181
	182	static int mpiix_init_one(struct pci_dev dev, const struct pci_device_id id)
	183	{
	184	/* Single threaded by the PCI probe logic */
669a5db4	185	static int printed_version;
5d728824 TH	186	struct ata_host *host;
5d728824 TH	187	struct ata_port *ap;
0d5ff566	188	void __iomem cmd_addr, ctl_addr;
669a5db4	189	u16 idetim;
cbcdd875	190	int cmd, ctl, irq;
669a5db4 JG	191
	192	if (!printed_version++)
	193	dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
	194
5d728824 TH	195	host = ata_host_alloc(&dev->dev, 1);
	196	if (!host)
	197	return -ENOMEM;
cbcdd875	198	ap = host->ports[0];
5d728824	199
669a5db4 JG	200	/* MPIIX has many functions which can be turned on or off according
	201	to other devices present. Make sure IDE is enabled before we try
	202	and use it */
	203
	204	pci_read_config_word(dev, IDETIM, &idetim);
	205	if (!(idetim & ENABLED))
	206	return -ENODEV;
	207
92ae7849	208	/* See if it's primary or secondary channel... */
0d5ff566	209	if (!(idetim & SECONDARY)) {
cbcdd875 TH	210	cmd = 0x1F0;
cbcdd875 TH	211	ctl = 0x3F6;
0d5ff566	212	irq = 14;
0d5ff566	213	} else {
cbcdd875 TH	214	cmd = 0x170;
cbcdd875 TH	215	ctl = 0x376;
0d5ff566	216	irq = 15;
0d5ff566 TH	217	}
0d5ff566 TH	218
cbcdd875 TH	219	cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
cbcdd875 TH	220	ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
0d5ff566 TH	221	if (!cmd_addr \|\| !ctl_addr)
	222	return -ENOMEM;
	223
cbcdd875 TH	224	ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);
cbcdd875 TH	225
669a5db4 JG	226	/* We do our own plumbing to avoid leaking special cases for whacko
	227	ancient hardware into the core code. There are two issues to
	228	worry about. #1 The chip is a bridge so if in legacy mode and
	229	without BARs set fools the setup. #2 If you pci_disable_device
	230	the MPIIX your box goes castors up */
	231
5d728824 TH	232	ap->ops = &mpiix_port_ops;
	233	ap->pio_mask = 0x1F;
	234	ap->flags \|= ATA_FLAG_SLAVE_POSS;
92ae7849	235
5d728824 TH	236	ap->ioaddr.cmd_addr = cmd_addr;
	237	ap->ioaddr.ctl_addr = ctl_addr;
	238	ap->ioaddr.altstatus_addr = ctl_addr;
669a5db4 JG	239
669a5db4 JG	240	/* Let libata fill in the port details */
5d728824	241	ata_std_ports(&ap->ioaddr);
669a5db4	242
5d728824 TH	243	/* activate host */
	244	return ata_host_activate(host, irq, ata_interrupt, IRQF_SHARED,
	245	&mpiix_sht);
669a5db4 JG	246	}
669a5db4 JG	247
669a5db4	248	static const struct pci_device_id mpiix[] = {
2d2744fc JG	249	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
	250
	251	{ },
669a5db4 JG	252	};
	253
	254	static struct pci_driver mpiix_pci_driver = {
	255	.name = DRV_NAME,
	256	.id_table = mpiix,
	257	.probe = mpiix_init_one,
24dc5f33	258	.remove = ata_pci_remove_one,
438ac6d5	259	#ifdef CONFIG_PM
30ced0f0 AC	260	.suspend = ata_pci_device_suspend,
30ced0f0 AC	261	.resume = ata_pci_device_resume,
438ac6d5	262	#endif
669a5db4 JG	263	};
	264
	265	static int __init mpiix_init(void)
	266	{
	267	return pci_register_driver(&mpiix_pci_driver);
	268	}
	269
669a5db4 JG	270	static void __exit mpiix_exit(void)
	271	{
	272	pci_unregister_driver(&mpiix_pci_driver);
	273	}
	274
669a5db4 JG	275	MODULE_AUTHOR("Alan Cox");
	276	MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
	277	MODULE_LICENSE("GPL");
	278	MODULE_DEVICE_TABLE(pci, mpiix);
	279	MODULE_VERSION(DRV_VERSION);
	280
	281	module_init(mpiix_init);
	282	module_exit(mpiix_exit);