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3c929c6f DD |
1 | /* |
2 | * Driver for the Octeon bootbus compact flash. | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
43f01da0 | 8 | * Copyright (C) 2005 - 2012 Cavium Inc. |
3c929c6f DD |
9 | * Copyright (C) 2008 Wind River Systems |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/libata.h> | |
43f01da0 | 15 | #include <linux/hrtimer.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
43f01da0 DD |
17 | #include <linux/irq.h> |
18 | #include <linux/of.h> | |
19 | #include <linux/of_platform.h> | |
3c929c6f | 20 | #include <linux/platform_device.h> |
3c929c6f DD |
21 | #include <scsi/scsi_host.h> |
22 | ||
23 | #include <asm/octeon/octeon.h> | |
24 | ||
25 | /* | |
26 | * The Octeon bootbus compact flash interface is connected in at least | |
27 | * 3 different configurations on various evaluation boards: | |
28 | * | |
29 | * -- 8 bits no irq, no DMA | |
30 | * -- 16 bits no irq, no DMA | |
31 | * -- 16 bits True IDE mode with DMA, but no irq. | |
32 | * | |
33 | * In the last case the DMA engine can generate an interrupt when the | |
34 | * transfer is complete. For the first two cases only PIO is supported. | |
35 | * | |
36 | */ | |
37 | ||
38 | #define DRV_NAME "pata_octeon_cf" | |
43f01da0 DD |
39 | #define DRV_VERSION "2.2" |
40 | ||
41 | /* Poll interval in nS. */ | |
42 | #define OCTEON_CF_BUSY_POLL_INTERVAL 500000 | |
3c929c6f | 43 | |
43f01da0 DD |
44 | #define DMA_CFG 0 |
45 | #define DMA_TIM 0x20 | |
46 | #define DMA_INT 0x38 | |
47 | #define DMA_INT_EN 0x50 | |
3c929c6f DD |
48 | |
49 | struct octeon_cf_port { | |
43f01da0 | 50 | struct hrtimer delayed_finish; |
3c929c6f DD |
51 | struct ata_port *ap; |
52 | int dma_finished; | |
43f01da0 DD |
53 | void *c0; |
54 | unsigned int cs0; | |
55 | unsigned int cs1; | |
56 | bool is_true_ide; | |
57 | u64 dma_base; | |
3c929c6f DD |
58 | }; |
59 | ||
60 | static struct scsi_host_template octeon_cf_sht = { | |
61 | ATA_PIO_SHT(DRV_NAME), | |
62 | }; | |
63 | ||
43f01da0 DD |
64 | static int enable_dma; |
65 | module_param(enable_dma, int, 0444); | |
66 | MODULE_PARM_DESC(enable_dma, | |
67 | "Enable use of DMA on interfaces that support it (0=no dma [default], 1=use dma)"); | |
68 | ||
3c929c6f DD |
69 | /** |
70 | * Convert nanosecond based time to setting used in the | |
71 | * boot bus timing register, based on timing multiple | |
72 | */ | |
73 | static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs) | |
74 | { | |
75 | unsigned int val; | |
76 | ||
77 | /* | |
78 | * Compute # of eclock periods to get desired duration in | |
79 | * nanoseconds. | |
80 | */ | |
1fa25ab2 | 81 | val = DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000), |
3c929c6f DD |
82 | 1000 * tim_mult); |
83 | ||
84 | return val; | |
85 | } | |
86 | ||
43f01da0 | 87 | static void octeon_cf_set_boot_reg_cfg(int cs, unsigned int multiplier) |
3c929c6f DD |
88 | { |
89 | union cvmx_mio_boot_reg_cfgx reg_cfg; | |
43f01da0 DD |
90 | unsigned int tim_mult; |
91 | ||
92 | switch (multiplier) { | |
93 | case 8: | |
94 | tim_mult = 3; | |
95 | break; | |
96 | case 4: | |
97 | tim_mult = 0; | |
98 | break; | |
99 | case 2: | |
100 | tim_mult = 2; | |
101 | break; | |
102 | default: | |
103 | tim_mult = 1; | |
104 | break; | |
105 | } | |
106 | ||
3c929c6f DD |
107 | reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); |
108 | reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */ | |
43f01da0 | 109 | reg_cfg.s.tim_mult = tim_mult; /* Timing mutiplier */ |
3c929c6f DD |
110 | reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */ |
111 | reg_cfg.s.sam = 0; /* Don't combine write and output enable */ | |
112 | reg_cfg.s.we_ext = 0; /* No write enable extension */ | |
113 | reg_cfg.s.oe_ext = 0; /* No read enable extension */ | |
114 | reg_cfg.s.en = 1; /* Enable this region */ | |
115 | reg_cfg.s.orbit = 0; /* Don't combine with previous region */ | |
116 | reg_cfg.s.ale = 0; /* Don't do address multiplexing */ | |
117 | cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64); | |
118 | } | |
119 | ||
120 | /** | |
121 | * Called after libata determines the needed PIO mode. This | |
122 | * function programs the Octeon bootbus regions to support the | |
123 | * timing requirements of the PIO mode. | |
124 | * | |
125 | * @ap: ATA port information | |
126 | * @dev: ATA device | |
127 | */ | |
128 | static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev) | |
129 | { | |
43f01da0 | 130 | struct octeon_cf_port *cf_port = ap->private_data; |
3c929c6f | 131 | union cvmx_mio_boot_reg_timx reg_tim; |
3c929c6f DD |
132 | int T; |
133 | struct ata_timing timing; | |
134 | ||
43f01da0 | 135 | unsigned int div; |
3c929c6f DD |
136 | int use_iordy; |
137 | int trh; | |
138 | int pause; | |
139 | /* These names are timing parameters from the ATA spec */ | |
140 | int t1; | |
141 | int t2; | |
142 | int t2i; | |
143 | ||
43f01da0 DD |
144 | /* |
145 | * A divisor value of four will overflow the timing fields at | |
146 | * clock rates greater than 800MHz | |
147 | */ | |
148 | if (octeon_get_io_clock_rate() <= 800000000) | |
149 | div = 4; | |
150 | else | |
151 | div = 8; | |
152 | T = (int)((1000000000000LL * div) / octeon_get_io_clock_rate()); | |
3c929c6f DD |
153 | |
154 | if (ata_timing_compute(dev, dev->pio_mode, &timing, T, T)) | |
155 | BUG(); | |
156 | ||
157 | t1 = timing.setup; | |
158 | if (t1) | |
159 | t1--; | |
160 | t2 = timing.active; | |
161 | if (t2) | |
162 | t2--; | |
163 | t2i = timing.act8b; | |
164 | if (t2i) | |
165 | t2i--; | |
166 | ||
43f01da0 | 167 | trh = ns_to_tim_reg(div, 20); |
3c929c6f DD |
168 | if (trh) |
169 | trh--; | |
170 | ||
43f01da0 DD |
171 | pause = (int)timing.cycle - (int)timing.active - |
172 | (int)timing.setup - trh; | |
173 | if (pause < 0) | |
174 | pause = 0; | |
3c929c6f DD |
175 | if (pause) |
176 | pause--; | |
177 | ||
43f01da0 DD |
178 | octeon_cf_set_boot_reg_cfg(cf_port->cs0, div); |
179 | if (cf_port->is_true_ide) | |
3c929c6f | 180 | /* True IDE mode, program both chip selects. */ |
43f01da0 | 181 | octeon_cf_set_boot_reg_cfg(cf_port->cs1, div); |
3c929c6f DD |
182 | |
183 | ||
184 | use_iordy = ata_pio_need_iordy(dev); | |
185 | ||
43f01da0 | 186 | reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0)); |
3c929c6f DD |
187 | /* Disable page mode */ |
188 | reg_tim.s.pagem = 0; | |
189 | /* Enable dynamic timing */ | |
190 | reg_tim.s.waitm = use_iordy; | |
191 | /* Pages are disabled */ | |
192 | reg_tim.s.pages = 0; | |
193 | /* We don't use multiplexed address mode */ | |
194 | reg_tim.s.ale = 0; | |
195 | /* Not used */ | |
196 | reg_tim.s.page = 0; | |
197 | /* Time after IORDY to coninue to assert the data */ | |
198 | reg_tim.s.wait = 0; | |
199 | /* Time to wait to complete the cycle. */ | |
200 | reg_tim.s.pause = pause; | |
201 | /* How long to hold after a write to de-assert CE. */ | |
202 | reg_tim.s.wr_hld = trh; | |
203 | /* How long to wait after a read to de-assert CE. */ | |
204 | reg_tim.s.rd_hld = trh; | |
205 | /* How long write enable is asserted */ | |
206 | reg_tim.s.we = t2; | |
207 | /* How long read enable is asserted */ | |
208 | reg_tim.s.oe = t2; | |
209 | /* Time after CE that read/write starts */ | |
43f01da0 | 210 | reg_tim.s.ce = ns_to_tim_reg(div, 5); |
3c929c6f DD |
211 | /* Time before CE that address is valid */ |
212 | reg_tim.s.adr = 0; | |
213 | ||
214 | /* Program the bootbus region timing for the data port chip select. */ | |
43f01da0 DD |
215 | cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64); |
216 | if (cf_port->is_true_ide) | |
3c929c6f | 217 | /* True IDE mode, program both chip selects. */ |
43f01da0 DD |
218 | cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1), |
219 | reg_tim.u64); | |
3c929c6f DD |
220 | } |
221 | ||
222 | static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev) | |
223 | { | |
43f01da0 DD |
224 | struct octeon_cf_port *cf_port = ap->private_data; |
225 | union cvmx_mio_boot_pin_defs pin_defs; | |
3c929c6f DD |
226 | union cvmx_mio_boot_dma_timx dma_tim; |
227 | unsigned int oe_a; | |
228 | unsigned int oe_n; | |
229 | unsigned int dma_ackh; | |
230 | unsigned int dma_arq; | |
231 | unsigned int pause; | |
232 | unsigned int T0, Tkr, Td; | |
233 | unsigned int tim_mult; | |
43f01da0 | 234 | int c; |
3c929c6f DD |
235 | |
236 | const struct ata_timing *timing; | |
237 | ||
238 | timing = ata_timing_find_mode(dev->dma_mode); | |
239 | T0 = timing->cycle; | |
240 | Td = timing->active; | |
241 | Tkr = timing->recover; | |
242 | dma_ackh = timing->dmack_hold; | |
243 | ||
244 | dma_tim.u64 = 0; | |
245 | /* dma_tim.s.tim_mult = 0 --> 4x */ | |
246 | tim_mult = 4; | |
247 | ||
248 | /* not spec'ed, value in eclocks, not affected by tim_mult */ | |
249 | dma_arq = 8; | |
250 | pause = 25 - dma_arq * 1000 / | |
43f01da0 | 251 | (octeon_get_io_clock_rate() / 1000000); /* Tz */ |
3c929c6f DD |
252 | |
253 | oe_a = Td; | |
254 | /* Tkr from cf spec, lengthened to meet T0 */ | |
255 | oe_n = max(T0 - oe_a, Tkr); | |
256 | ||
43f01da0 DD |
257 | pin_defs.u64 = cvmx_read_csr(CVMX_MIO_BOOT_PIN_DEFS); |
258 | ||
259 | /* DMA channel number. */ | |
260 | c = (cf_port->dma_base & 8) >> 3; | |
261 | ||
262 | /* Invert the polarity if the default is 0*/ | |
263 | dma_tim.s.dmack_pi = (pin_defs.u64 & (1ull << (11 + c))) ? 0 : 1; | |
3c929c6f DD |
264 | |
265 | dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n); | |
266 | dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a); | |
267 | ||
268 | /* | |
269 | * This is tI, C.F. spec. says 0, but Sony CF card requires | |
270 | * more, we use 20 nS. | |
271 | */ | |
87c8b22b | 272 | dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, 20); |
3c929c6f DD |
273 | dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh); |
274 | ||
275 | dma_tim.s.dmarq = dma_arq; | |
276 | dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause); | |
277 | ||
278 | dma_tim.s.rd_dly = 0; /* Sample right on edge */ | |
279 | ||
280 | /* writes only */ | |
281 | dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n); | |
282 | dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a); | |
283 | ||
284 | pr_debug("ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60, | |
285 | ns_to_tim_reg(tim_mult, 60)); | |
43f01da0 | 286 | pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n", |
3c929c6f DD |
287 | dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s, |
288 | dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause); | |
289 | ||
43f01da0 | 290 | cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64); |
3c929c6f DD |
291 | } |
292 | ||
293 | /** | |
294 | * Handle an 8 bit I/O request. | |
295 | * | |
296 | * @dev: Device to access | |
297 | * @buffer: Data buffer | |
298 | * @buflen: Length of the buffer. | |
299 | * @rw: True to write. | |
300 | */ | |
301 | static unsigned int octeon_cf_data_xfer8(struct ata_device *dev, | |
302 | unsigned char *buffer, | |
303 | unsigned int buflen, | |
304 | int rw) | |
305 | { | |
306 | struct ata_port *ap = dev->link->ap; | |
307 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
308 | unsigned long words; | |
309 | int count; | |
310 | ||
311 | words = buflen; | |
312 | if (rw) { | |
313 | count = 16; | |
314 | while (words--) { | |
315 | iowrite8(*buffer, data_addr); | |
316 | buffer++; | |
317 | /* | |
318 | * Every 16 writes do a read so the bootbus | |
319 | * FIFO doesn't fill up. | |
320 | */ | |
321 | if (--count == 0) { | |
322 | ioread8(ap->ioaddr.altstatus_addr); | |
323 | count = 16; | |
324 | } | |
325 | } | |
326 | } else { | |
327 | ioread8_rep(data_addr, buffer, words); | |
328 | } | |
329 | return buflen; | |
330 | } | |
331 | ||
332 | /** | |
333 | * Handle a 16 bit I/O request. | |
334 | * | |
335 | * @dev: Device to access | |
336 | * @buffer: Data buffer | |
337 | * @buflen: Length of the buffer. | |
338 | * @rw: True to write. | |
339 | */ | |
340 | static unsigned int octeon_cf_data_xfer16(struct ata_device *dev, | |
341 | unsigned char *buffer, | |
342 | unsigned int buflen, | |
343 | int rw) | |
344 | { | |
345 | struct ata_port *ap = dev->link->ap; | |
346 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
347 | unsigned long words; | |
348 | int count; | |
349 | ||
350 | words = buflen / 2; | |
351 | if (rw) { | |
352 | count = 16; | |
353 | while (words--) { | |
354 | iowrite16(*(uint16_t *)buffer, data_addr); | |
355 | buffer += sizeof(uint16_t); | |
356 | /* | |
357 | * Every 16 writes do a read so the bootbus | |
358 | * FIFO doesn't fill up. | |
359 | */ | |
360 | if (--count == 0) { | |
361 | ioread8(ap->ioaddr.altstatus_addr); | |
362 | count = 16; | |
363 | } | |
364 | } | |
365 | } else { | |
366 | while (words--) { | |
367 | *(uint16_t *)buffer = ioread16(data_addr); | |
368 | buffer += sizeof(uint16_t); | |
369 | } | |
370 | } | |
371 | /* Transfer trailing 1 byte, if any. */ | |
372 | if (unlikely(buflen & 0x01)) { | |
373 | __le16 align_buf[1] = { 0 }; | |
374 | ||
375 | if (rw == READ) { | |
376 | align_buf[0] = cpu_to_le16(ioread16(data_addr)); | |
377 | memcpy(buffer, align_buf, 1); | |
378 | } else { | |
379 | memcpy(align_buf, buffer, 1); | |
380 | iowrite16(le16_to_cpu(align_buf[0]), data_addr); | |
381 | } | |
382 | words++; | |
383 | } | |
384 | return buflen; | |
385 | } | |
386 | ||
387 | /** | |
388 | * Read the taskfile for 16bit non-True IDE only. | |
389 | */ | |
390 | static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf) | |
391 | { | |
392 | u16 blob; | |
393 | /* The base of the registers is at ioaddr.data_addr. */ | |
394 | void __iomem *base = ap->ioaddr.data_addr; | |
395 | ||
396 | blob = __raw_readw(base + 0xc); | |
397 | tf->feature = blob >> 8; | |
398 | ||
399 | blob = __raw_readw(base + 2); | |
400 | tf->nsect = blob & 0xff; | |
401 | tf->lbal = blob >> 8; | |
402 | ||
403 | blob = __raw_readw(base + 4); | |
404 | tf->lbam = blob & 0xff; | |
405 | tf->lbah = blob >> 8; | |
406 | ||
407 | blob = __raw_readw(base + 6); | |
408 | tf->device = blob & 0xff; | |
409 | tf->command = blob >> 8; | |
410 | ||
411 | if (tf->flags & ATA_TFLAG_LBA48) { | |
412 | if (likely(ap->ioaddr.ctl_addr)) { | |
413 | iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr); | |
414 | ||
415 | blob = __raw_readw(base + 0xc); | |
416 | tf->hob_feature = blob >> 8; | |
417 | ||
418 | blob = __raw_readw(base + 2); | |
419 | tf->hob_nsect = blob & 0xff; | |
420 | tf->hob_lbal = blob >> 8; | |
421 | ||
422 | blob = __raw_readw(base + 4); | |
423 | tf->hob_lbam = blob & 0xff; | |
424 | tf->hob_lbah = blob >> 8; | |
425 | ||
426 | iowrite8(tf->ctl, ap->ioaddr.ctl_addr); | |
427 | ap->last_ctl = tf->ctl; | |
428 | } else { | |
429 | WARN_ON(1); | |
430 | } | |
431 | } | |
432 | } | |
433 | ||
434 | static u8 octeon_cf_check_status16(struct ata_port *ap) | |
435 | { | |
436 | u16 blob; | |
437 | void __iomem *base = ap->ioaddr.data_addr; | |
438 | ||
439 | blob = __raw_readw(base + 6); | |
440 | return blob >> 8; | |
441 | } | |
442 | ||
443 | static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes, | |
444 | unsigned long deadline) | |
445 | { | |
446 | struct ata_port *ap = link->ap; | |
447 | void __iomem *base = ap->ioaddr.data_addr; | |
448 | int rc; | |
449 | u8 err; | |
450 | ||
451 | DPRINTK("about to softreset\n"); | |
452 | __raw_writew(ap->ctl, base + 0xe); | |
453 | udelay(20); | |
454 | __raw_writew(ap->ctl | ATA_SRST, base + 0xe); | |
455 | udelay(20); | |
456 | __raw_writew(ap->ctl, base + 0xe); | |
457 | ||
458 | rc = ata_sff_wait_after_reset(link, 1, deadline); | |
459 | if (rc) { | |
a9a79dfe | 460 | ata_link_err(link, "SRST failed (errno=%d)\n", rc); |
3c929c6f DD |
461 | return rc; |
462 | } | |
463 | ||
464 | /* determine by signature whether we have ATA or ATAPI devices */ | |
465 | classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err); | |
466 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); | |
467 | return 0; | |
468 | } | |
469 | ||
470 | /** | |
471 | * Load the taskfile for 16bit non-True IDE only. The device_addr is | |
472 | * not loaded, we do this as part of octeon_cf_exec_command16. | |
473 | */ | |
474 | static void octeon_cf_tf_load16(struct ata_port *ap, | |
475 | const struct ata_taskfile *tf) | |
476 | { | |
477 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
478 | /* The base of the registers is at ioaddr.data_addr. */ | |
479 | void __iomem *base = ap->ioaddr.data_addr; | |
480 | ||
481 | if (tf->ctl != ap->last_ctl) { | |
482 | iowrite8(tf->ctl, ap->ioaddr.ctl_addr); | |
483 | ap->last_ctl = tf->ctl; | |
484 | ata_wait_idle(ap); | |
485 | } | |
486 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
487 | __raw_writew(tf->hob_feature << 8, base + 0xc); | |
488 | __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2); | |
489 | __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4); | |
490 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
491 | tf->hob_feature, | |
492 | tf->hob_nsect, | |
493 | tf->hob_lbal, | |
494 | tf->hob_lbam, | |
495 | tf->hob_lbah); | |
496 | } | |
497 | if (is_addr) { | |
498 | __raw_writew(tf->feature << 8, base + 0xc); | |
499 | __raw_writew(tf->nsect | tf->lbal << 8, base + 2); | |
500 | __raw_writew(tf->lbam | tf->lbah << 8, base + 4); | |
501 | VPRINTK("feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
502 | tf->feature, | |
503 | tf->nsect, | |
504 | tf->lbal, | |
505 | tf->lbam, | |
506 | tf->lbah); | |
507 | } | |
508 | ata_wait_idle(ap); | |
509 | } | |
510 | ||
511 | ||
512 | static void octeon_cf_dev_select(struct ata_port *ap, unsigned int device) | |
513 | { | |
514 | /* There is only one device, do nothing. */ | |
515 | return; | |
516 | } | |
517 | ||
518 | /* | |
519 | * Issue ATA command to host controller. The device_addr is also sent | |
520 | * as it must be written in a combined write with the command. | |
521 | */ | |
522 | static void octeon_cf_exec_command16(struct ata_port *ap, | |
523 | const struct ata_taskfile *tf) | |
524 | { | |
525 | /* The base of the registers is at ioaddr.data_addr. */ | |
526 | void __iomem *base = ap->ioaddr.data_addr; | |
527 | u16 blob; | |
528 | ||
529 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
530 | VPRINTK("device 0x%X\n", tf->device); | |
531 | blob = tf->device; | |
532 | } else { | |
533 | blob = 0; | |
534 | } | |
535 | ||
536 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
537 | blob |= (tf->command << 8); | |
538 | __raw_writew(blob, base + 6); | |
539 | ||
540 | ||
541 | ata_wait_idle(ap); | |
542 | } | |
543 | ||
43f01da0 | 544 | static void octeon_cf_ata_port_noaction(struct ata_port *ap) |
3c929c6f | 545 | { |
3c929c6f DD |
546 | } |
547 | ||
3c929c6f DD |
548 | static void octeon_cf_dma_setup(struct ata_queued_cmd *qc) |
549 | { | |
550 | struct ata_port *ap = qc->ap; | |
551 | struct octeon_cf_port *cf_port; | |
552 | ||
2d1299aa | 553 | cf_port = ap->private_data; |
3c929c6f DD |
554 | DPRINTK("ENTER\n"); |
555 | /* issue r/w command */ | |
556 | qc->cursg = qc->sg; | |
557 | cf_port->dma_finished = 0; | |
558 | ap->ops->sff_exec_command(ap, &qc->tf); | |
559 | DPRINTK("EXIT\n"); | |
560 | } | |
561 | ||
562 | /** | |
563 | * Start a DMA transfer that was already setup | |
564 | * | |
565 | * @qc: Information about the DMA | |
566 | */ | |
567 | static void octeon_cf_dma_start(struct ata_queued_cmd *qc) | |
568 | { | |
43f01da0 | 569 | struct octeon_cf_port *cf_port = qc->ap->private_data; |
3c929c6f DD |
570 | union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg; |
571 | union cvmx_mio_boot_dma_intx mio_boot_dma_int; | |
572 | struct scatterlist *sg; | |
573 | ||
574 | VPRINTK("%d scatterlists\n", qc->n_elem); | |
575 | ||
576 | /* Get the scatter list entry we need to DMA into */ | |
577 | sg = qc->cursg; | |
578 | BUG_ON(!sg); | |
579 | ||
580 | /* | |
581 | * Clear the DMA complete status. | |
582 | */ | |
583 | mio_boot_dma_int.u64 = 0; | |
584 | mio_boot_dma_int.s.done = 1; | |
43f01da0 | 585 | cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64); |
3c929c6f DD |
586 | |
587 | /* Enable the interrupt. */ | |
43f01da0 | 588 | cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64); |
3c929c6f DD |
589 | |
590 | /* Set the direction of the DMA */ | |
591 | mio_boot_dma_cfg.u64 = 0; | |
592 | mio_boot_dma_cfg.s.en = 1; | |
593 | mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0); | |
594 | ||
595 | /* | |
596 | * Don't stop the DMA if the device deasserts DMARQ. Many | |
597 | * compact flashes deassert DMARQ for a short time between | |
598 | * sectors. Instead of stopping and restarting the DMA, we'll | |
599 | * let the hardware do it. If the DMA is really stopped early | |
600 | * due to an error condition, a later timeout will force us to | |
601 | * stop. | |
602 | */ | |
603 | mio_boot_dma_cfg.s.clr = 0; | |
604 | ||
605 | /* Size is specified in 16bit words and minus one notation */ | |
606 | mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1; | |
607 | ||
608 | /* We need to swap the high and low bytes of every 16 bits */ | |
609 | mio_boot_dma_cfg.s.swap8 = 1; | |
610 | ||
611 | mio_boot_dma_cfg.s.adr = sg_dma_address(sg); | |
612 | ||
613 | VPRINTK("%s %d bytes address=%p\n", | |
614 | (mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length, | |
615 | (void *)(unsigned long)mio_boot_dma_cfg.s.adr); | |
616 | ||
43f01da0 | 617 | cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64); |
3c929c6f DD |
618 | } |
619 | ||
620 | /** | |
621 | * | |
622 | * LOCKING: | |
623 | * spin_lock_irqsave(host lock) | |
624 | * | |
625 | */ | |
626 | static unsigned int octeon_cf_dma_finished(struct ata_port *ap, | |
627 | struct ata_queued_cmd *qc) | |
628 | { | |
629 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
43f01da0 | 630 | struct octeon_cf_port *cf_port = ap->private_data; |
3c929c6f DD |
631 | union cvmx_mio_boot_dma_cfgx dma_cfg; |
632 | union cvmx_mio_boot_dma_intx dma_int; | |
3c929c6f DD |
633 | u8 status; |
634 | ||
635 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
636 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
637 | ||
638 | ||
639 | if (ap->hsm_task_state != HSM_ST_LAST) | |
640 | return 0; | |
641 | ||
43f01da0 | 642 | dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG); |
3c929c6f DD |
643 | if (dma_cfg.s.size != 0xfffff) { |
644 | /* Error, the transfer was not complete. */ | |
645 | qc->err_mask |= AC_ERR_HOST_BUS; | |
646 | ap->hsm_task_state = HSM_ST_ERR; | |
647 | } | |
648 | ||
649 | /* Stop and clear the dma engine. */ | |
650 | dma_cfg.u64 = 0; | |
651 | dma_cfg.s.size = -1; | |
43f01da0 | 652 | cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64); |
3c929c6f DD |
653 | |
654 | /* Disable the interrupt. */ | |
655 | dma_int.u64 = 0; | |
43f01da0 | 656 | cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64); |
3c929c6f DD |
657 | |
658 | /* Clear the DMA complete status */ | |
659 | dma_int.s.done = 1; | |
43f01da0 | 660 | cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64); |
3c929c6f DD |
661 | |
662 | status = ap->ops->sff_check_status(ap); | |
663 | ||
664 | ata_sff_hsm_move(ap, qc, status, 0); | |
665 | ||
666 | if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA)) | |
667 | ata_ehi_push_desc(ehi, "DMA stat 0x%x", status); | |
668 | ||
669 | return 1; | |
670 | } | |
671 | ||
672 | /* | |
673 | * Check if any queued commands have more DMAs, if so start the next | |
674 | * transfer, else do end of transfer handling. | |
675 | */ | |
676 | static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance) | |
677 | { | |
678 | struct ata_host *host = dev_instance; | |
679 | struct octeon_cf_port *cf_port; | |
680 | int i; | |
681 | unsigned int handled = 0; | |
682 | unsigned long flags; | |
683 | ||
684 | spin_lock_irqsave(&host->lock, flags); | |
685 | ||
686 | DPRINTK("ENTER\n"); | |
687 | for (i = 0; i < host->n_ports; i++) { | |
688 | u8 status; | |
689 | struct ata_port *ap; | |
690 | struct ata_queued_cmd *qc; | |
691 | union cvmx_mio_boot_dma_intx dma_int; | |
692 | union cvmx_mio_boot_dma_cfgx dma_cfg; | |
3c929c6f DD |
693 | |
694 | ap = host->ports[i]; | |
2d1299aa | 695 | cf_port = ap->private_data; |
43f01da0 DD |
696 | |
697 | dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT); | |
698 | dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG); | |
3c929c6f DD |
699 | |
700 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
701 | ||
43f01da0 DD |
702 | if (!qc || (qc->tf.flags & ATA_TFLAG_POLLING)) |
703 | continue; | |
704 | ||
705 | if (dma_int.s.done && !dma_cfg.s.en) { | |
706 | if (!sg_is_last(qc->cursg)) { | |
707 | qc->cursg = sg_next(qc->cursg); | |
3c929c6f | 708 | handled = 1; |
43f01da0 DD |
709 | octeon_cf_dma_start(qc); |
710 | continue; | |
3c929c6f | 711 | } else { |
43f01da0 | 712 | cf_port->dma_finished = 1; |
3c929c6f DD |
713 | } |
714 | } | |
43f01da0 DD |
715 | if (!cf_port->dma_finished) |
716 | continue; | |
717 | status = ioread8(ap->ioaddr.altstatus_addr); | |
718 | if (status & (ATA_BUSY | ATA_DRQ)) { | |
719 | /* | |
720 | * We are busy, try to handle it later. This | |
721 | * is the DMA finished interrupt, and it could | |
722 | * take a little while for the card to be | |
723 | * ready for more commands. | |
724 | */ | |
725 | /* Clear DMA irq. */ | |
726 | dma_int.u64 = 0; | |
727 | dma_int.s.done = 1; | |
728 | cvmx_write_csr(cf_port->dma_base + DMA_INT, | |
729 | dma_int.u64); | |
730 | hrtimer_start_range_ns(&cf_port->delayed_finish, | |
731 | ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL), | |
732 | OCTEON_CF_BUSY_POLL_INTERVAL / 5, | |
733 | HRTIMER_MODE_REL); | |
734 | handled = 1; | |
735 | } else { | |
736 | handled |= octeon_cf_dma_finished(ap, qc); | |
737 | } | |
3c929c6f DD |
738 | } |
739 | spin_unlock_irqrestore(&host->lock, flags); | |
740 | DPRINTK("EXIT\n"); | |
741 | return IRQ_RETVAL(handled); | |
742 | } | |
743 | ||
43f01da0 | 744 | static enum hrtimer_restart octeon_cf_delayed_finish(struct hrtimer *hrt) |
3c929c6f | 745 | { |
43f01da0 | 746 | struct octeon_cf_port *cf_port = container_of(hrt, |
3c929c6f | 747 | struct octeon_cf_port, |
43f01da0 | 748 | delayed_finish); |
3c929c6f DD |
749 | struct ata_port *ap = cf_port->ap; |
750 | struct ata_host *host = ap->host; | |
751 | struct ata_queued_cmd *qc; | |
752 | unsigned long flags; | |
753 | u8 status; | |
43f01da0 | 754 | enum hrtimer_restart rv = HRTIMER_NORESTART; |
3c929c6f DD |
755 | |
756 | spin_lock_irqsave(&host->lock, flags); | |
757 | ||
758 | /* | |
759 | * If the port is not waiting for completion, it must have | |
760 | * handled it previously. The hsm_task_state is | |
761 | * protected by host->lock. | |
762 | */ | |
763 | if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished) | |
764 | goto out; | |
765 | ||
766 | status = ioread8(ap->ioaddr.altstatus_addr); | |
767 | if (status & (ATA_BUSY | ATA_DRQ)) { | |
768 | /* Still busy, try again. */ | |
43f01da0 DD |
769 | hrtimer_forward_now(hrt, |
770 | ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL)); | |
771 | rv = HRTIMER_RESTART; | |
3c929c6f DD |
772 | goto out; |
773 | } | |
774 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
43f01da0 | 775 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
3c929c6f DD |
776 | octeon_cf_dma_finished(ap, qc); |
777 | out: | |
778 | spin_unlock_irqrestore(&host->lock, flags); | |
43f01da0 | 779 | return rv; |
3c929c6f DD |
780 | } |
781 | ||
782 | static void octeon_cf_dev_config(struct ata_device *dev) | |
783 | { | |
784 | /* | |
785 | * A maximum of 2^20 - 1 16 bit transfers are possible with | |
786 | * the bootbus DMA. So we need to throttle max_sectors to | |
787 | * (2^12 - 1 == 4095) to assure that this can never happen. | |
788 | */ | |
789 | dev->max_sectors = min(dev->max_sectors, 4095U); | |
790 | } | |
791 | ||
3c929c6f DD |
792 | /* |
793 | * We don't do ATAPI DMA so return 0. | |
794 | */ | |
795 | static int octeon_cf_check_atapi_dma(struct ata_queued_cmd *qc) | |
796 | { | |
797 | return 0; | |
798 | } | |
799 | ||
800 | static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc) | |
801 | { | |
802 | struct ata_port *ap = qc->ap; | |
803 | ||
804 | switch (qc->tf.protocol) { | |
805 | case ATA_PROT_DMA: | |
806 | WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); | |
807 | ||
808 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ | |
809 | octeon_cf_dma_setup(qc); /* set up dma */ | |
810 | octeon_cf_dma_start(qc); /* initiate dma */ | |
811 | ap->hsm_task_state = HSM_ST_LAST; | |
812 | break; | |
813 | ||
814 | case ATAPI_PROT_DMA: | |
815 | dev_err(ap->dev, "Error, ATAPI not supported\n"); | |
816 | BUG(); | |
817 | ||
818 | default: | |
819 | return ata_sff_qc_issue(qc); | |
820 | } | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static struct ata_port_operations octeon_cf_ops = { | |
826 | .inherits = &ata_sff_port_ops, | |
827 | .check_atapi_dma = octeon_cf_check_atapi_dma, | |
828 | .qc_prep = ata_noop_qc_prep, | |
829 | .qc_issue = octeon_cf_qc_issue, | |
830 | .sff_dev_select = octeon_cf_dev_select, | |
43f01da0 DD |
831 | .sff_irq_on = octeon_cf_ata_port_noaction, |
832 | .sff_irq_clear = octeon_cf_ata_port_noaction, | |
3c929c6f DD |
833 | .cable_detect = ata_cable_40wire, |
834 | .set_piomode = octeon_cf_set_piomode, | |
835 | .set_dmamode = octeon_cf_set_dmamode, | |
836 | .dev_config = octeon_cf_dev_config, | |
837 | }; | |
838 | ||
839 | static int __devinit octeon_cf_probe(struct platform_device *pdev) | |
840 | { | |
841 | struct resource *res_cs0, *res_cs1; | |
842 | ||
43f01da0 DD |
843 | bool is_16bit; |
844 | const __be32 *cs_num; | |
845 | struct property *reg_prop; | |
846 | int n_addr, n_size, reg_len; | |
847 | struct device_node *node; | |
848 | const void *prop; | |
3c929c6f DD |
849 | void __iomem *cs0; |
850 | void __iomem *cs1 = NULL; | |
851 | struct ata_host *host; | |
852 | struct ata_port *ap; | |
3c929c6f DD |
853 | int irq = 0; |
854 | irq_handler_t irq_handler = NULL; | |
855 | void __iomem *base; | |
856 | struct octeon_cf_port *cf_port; | |
43f01da0 | 857 | int rv = -ENOMEM; |
3c929c6f | 858 | |
3c929c6f | 859 | |
43f01da0 DD |
860 | node = pdev->dev.of_node; |
861 | if (node == NULL) | |
3c929c6f DD |
862 | return -EINVAL; |
863 | ||
43f01da0 DD |
864 | cf_port = kzalloc(sizeof(*cf_port), GFP_KERNEL); |
865 | if (!cf_port) | |
866 | return -ENOMEM; | |
3c929c6f | 867 | |
43f01da0 | 868 | cf_port->is_true_ide = (of_find_property(node, "cavium,true-ide", NULL) != NULL); |
3c929c6f | 869 | |
43f01da0 DD |
870 | prop = of_get_property(node, "cavium,bus-width", NULL); |
871 | if (prop) | |
872 | is_16bit = (be32_to_cpup(prop) == 16); | |
873 | else | |
874 | is_16bit = false; | |
3c929c6f | 875 | |
43f01da0 DD |
876 | n_addr = of_n_addr_cells(node); |
877 | n_size = of_n_size_cells(node); | |
3c929c6f | 878 | |
43f01da0 DD |
879 | reg_prop = of_find_property(node, "reg", ®_len); |
880 | if (!reg_prop || reg_len < sizeof(__be32)) { | |
881 | rv = -EINVAL; | |
882 | goto free_cf_port; | |
883 | } | |
884 | cs_num = reg_prop->value; | |
885 | cf_port->cs0 = be32_to_cpup(cs_num); | |
886 | ||
887 | if (cf_port->is_true_ide) { | |
888 | struct device_node *dma_node; | |
889 | dma_node = of_parse_phandle(node, | |
890 | "cavium,dma-engine-handle", 0); | |
891 | if (dma_node) { | |
892 | struct platform_device *dma_dev; | |
893 | dma_dev = of_find_device_by_node(dma_node); | |
894 | if (dma_dev) { | |
895 | struct resource *res_dma; | |
896 | int i; | |
897 | res_dma = platform_get_resource(dma_dev, IORESOURCE_MEM, 0); | |
898 | if (!res_dma) { | |
899 | of_node_put(dma_node); | |
900 | rv = -EINVAL; | |
901 | goto free_cf_port; | |
902 | } | |
903 | cf_port->dma_base = (u64)devm_ioremap_nocache(&pdev->dev, res_dma->start, | |
904 | resource_size(res_dma)); | |
905 | ||
906 | if (!cf_port->dma_base) { | |
907 | of_node_put(dma_node); | |
908 | rv = -EINVAL; | |
909 | goto free_cf_port; | |
910 | } | |
911 | ||
912 | irq_handler = octeon_cf_interrupt; | |
913 | i = platform_get_irq(dma_dev, 0); | |
914 | if (i > 0) | |
915 | irq = i; | |
916 | } | |
917 | of_node_put(dma_node); | |
918 | } | |
919 | res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
920 | if (!res_cs1) { | |
921 | rv = -EINVAL; | |
922 | goto free_cf_port; | |
923 | } | |
3c929c6f | 924 | cs1 = devm_ioremap_nocache(&pdev->dev, res_cs1->start, |
43f01da0 | 925 | res_cs1->end - res_cs1->start + 1); |
3c929c6f DD |
926 | |
927 | if (!cs1) | |
43f01da0 DD |
928 | goto free_cf_port; |
929 | ||
930 | if (reg_len < (n_addr + n_size + 1) * sizeof(__be32)) { | |
931 | rv = -EINVAL; | |
932 | goto free_cf_port; | |
933 | } | |
934 | cs_num += n_addr + n_size; | |
935 | cf_port->cs1 = be32_to_cpup(cs_num); | |
3c929c6f DD |
936 | } |
937 | ||
43f01da0 DD |
938 | res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
939 | ||
940 | if (!res_cs0) { | |
941 | rv = -EINVAL; | |
942 | goto free_cf_port; | |
943 | } | |
944 | ||
945 | cs0 = devm_ioremap_nocache(&pdev->dev, res_cs0->start, | |
946 | resource_size(res_cs0)); | |
947 | ||
948 | if (!cs0) | |
949 | goto free_cf_port; | |
3c929c6f DD |
950 | |
951 | /* allocate host */ | |
952 | host = ata_host_alloc(&pdev->dev, 1); | |
953 | if (!host) | |
954 | goto free_cf_port; | |
955 | ||
956 | ap = host->ports[0]; | |
957 | ap->private_data = cf_port; | |
43f01da0 | 958 | pdev->dev.platform_data = cf_port; |
3c929c6f DD |
959 | cf_port->ap = ap; |
960 | ap->ops = &octeon_cf_ops; | |
14bdef98 | 961 | ap->pio_mask = ATA_PIO6; |
9cbe056f | 962 | ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING; |
3c929c6f | 963 | |
43f01da0 DD |
964 | if (!is_16bit) { |
965 | base = cs0 + 0x800; | |
3c929c6f DD |
966 | ap->ioaddr.cmd_addr = base; |
967 | ata_sff_std_ports(&ap->ioaddr); | |
968 | ||
969 | ap->ioaddr.altstatus_addr = base + 0xe; | |
970 | ap->ioaddr.ctl_addr = base + 0xe; | |
971 | octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8; | |
43f01da0 DD |
972 | } else if (cf_port->is_true_ide) { |
973 | base = cs0; | |
3c929c6f DD |
974 | ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1; |
975 | ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1); | |
976 | ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1; | |
977 | ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1; | |
978 | ap->ioaddr.nsect_addr = base + (ATA_REG_NSECT << 1) + 1; | |
979 | ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1; | |
980 | ap->ioaddr.lbam_addr = base + (ATA_REG_LBAM << 1) + 1; | |
981 | ap->ioaddr.lbah_addr = base + (ATA_REG_LBAH << 1) + 1; | |
982 | ap->ioaddr.device_addr = base + (ATA_REG_DEVICE << 1) + 1; | |
983 | ap->ioaddr.status_addr = base + (ATA_REG_STATUS << 1) + 1; | |
984 | ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1; | |
985 | ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1; | |
986 | ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1; | |
987 | octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16; | |
988 | ||
43f01da0 | 989 | ap->mwdma_mask = enable_dma ? ATA_MWDMA4 : 0; |
3c929c6f | 990 | |
43f01da0 DD |
991 | /* True IDE mode needs a timer to poll for not-busy. */ |
992 | hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC, | |
993 | HRTIMER_MODE_REL); | |
994 | cf_port->delayed_finish.function = octeon_cf_delayed_finish; | |
3c929c6f DD |
995 | } else { |
996 | /* 16 bit but not True IDE */ | |
43f01da0 | 997 | base = cs0 + 0x800; |
3c929c6f DD |
998 | octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16; |
999 | octeon_cf_ops.softreset = octeon_cf_softreset16; | |
1000 | octeon_cf_ops.sff_check_status = octeon_cf_check_status16; | |
1001 | octeon_cf_ops.sff_tf_read = octeon_cf_tf_read16; | |
1002 | octeon_cf_ops.sff_tf_load = octeon_cf_tf_load16; | |
1003 | octeon_cf_ops.sff_exec_command = octeon_cf_exec_command16; | |
1004 | ||
1005 | ap->ioaddr.data_addr = base + ATA_REG_DATA; | |
1006 | ap->ioaddr.nsect_addr = base + ATA_REG_NSECT; | |
1007 | ap->ioaddr.lbal_addr = base + ATA_REG_LBAL; | |
1008 | ap->ioaddr.ctl_addr = base + 0xe; | |
1009 | ap->ioaddr.altstatus_addr = base + 0xe; | |
1010 | } | |
43f01da0 DD |
1011 | cf_port->c0 = ap->ioaddr.ctl_addr; |
1012 | ||
1013 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); | |
1014 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; | |
3c929c6f DD |
1015 | |
1016 | ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr); | |
1017 | ||
1018 | ||
43f01da0 DD |
1019 | dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n", |
1020 | is_16bit ? 16 : 8, | |
1021 | cf_port->is_true_ide ? ", True IDE" : ""); | |
3c929c6f | 1022 | |
43f01da0 DD |
1023 | return ata_host_activate(host, irq, irq_handler, |
1024 | IRQF_SHARED, &octeon_cf_sht); | |
3c929c6f DD |
1025 | |
1026 | free_cf_port: | |
1027 | kfree(cf_port); | |
43f01da0 DD |
1028 | return rv; |
1029 | } | |
1030 | ||
1031 | static void octeon_cf_shutdown(struct device *dev) | |
1032 | { | |
1033 | union cvmx_mio_boot_dma_cfgx dma_cfg; | |
1034 | union cvmx_mio_boot_dma_intx dma_int; | |
1035 | ||
1036 | struct octeon_cf_port *cf_port = dev->platform_data; | |
1037 | ||
1038 | if (cf_port->dma_base) { | |
1039 | /* Stop and clear the dma engine. */ | |
1040 | dma_cfg.u64 = 0; | |
1041 | dma_cfg.s.size = -1; | |
1042 | cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64); | |
1043 | ||
1044 | /* Disable the interrupt. */ | |
1045 | dma_int.u64 = 0; | |
1046 | cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64); | |
1047 | ||
1048 | /* Clear the DMA complete status */ | |
1049 | dma_int.s.done = 1; | |
1050 | cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64); | |
1051 | ||
1052 | __raw_writeb(0, cf_port->c0); | |
1053 | udelay(20); | |
1054 | __raw_writeb(ATA_SRST, cf_port->c0); | |
1055 | udelay(20); | |
1056 | __raw_writeb(0, cf_port->c0); | |
1057 | mdelay(100); | |
1058 | } | |
3c929c6f DD |
1059 | } |
1060 | ||
43f01da0 DD |
1061 | static struct of_device_id octeon_cf_match[] = { |
1062 | { | |
1063 | .compatible = "cavium,ebt3000-compact-flash", | |
1064 | }, | |
1065 | {}, | |
1066 | }; | |
1067 | MODULE_DEVICE_TABLE(of, octeon_i2c_match); | |
1068 | ||
3c929c6f DD |
1069 | static struct platform_driver octeon_cf_driver = { |
1070 | .probe = octeon_cf_probe, | |
1071 | .driver = { | |
1072 | .name = DRV_NAME, | |
1073 | .owner = THIS_MODULE, | |
43f01da0 DD |
1074 | .of_match_table = octeon_cf_match, |
1075 | .shutdown = octeon_cf_shutdown | |
3c929c6f DD |
1076 | }, |
1077 | }; | |
1078 | ||
1079 | static int __init octeon_cf_init(void) | |
1080 | { | |
1081 | return platform_driver_register(&octeon_cf_driver); | |
1082 | } | |
1083 | ||
1084 | ||
1085 | MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>"); | |
1086 | MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA"); | |
1087 | MODULE_LICENSE("GPL"); | |
1088 | MODULE_VERSION(DRV_VERSION); | |
1089 | MODULE_ALIAS("platform:" DRV_NAME); | |
1090 | ||
1091 | module_init(octeon_cf_init); |