[mirror_ubuntu-bionic-kernel.git] / drivers / ata / pata_optidma.c

/*
 * pata_optidma.c 	- Opti DMA PATA for new ATA layer
 *			  (C) 2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 *	The Opti DMA controllers are related to the older PIO PCI controllers
 *	and indeed the VLB ones. The main differences are that the timing
 *	numbers are now based off PCI clocks not VLB and differ, and that
 *	MWDMA is supported.
 *
 *	This driver should support Viper-N+, FireStar, FireStar Plus.
 *
 *	These devices support virtual DMA for read (aka the CS5520). Later
 *	chips support UDMA33, but only if the rest of the board logic does,
 *	so you have to get this right. We don't support the virtual DMA
 *	but we do handle UDMA.
 *
 *	Bits that are worth knowing
 *		Most control registers are shadowed into I/O registers
 *		0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
 *		Virtual DMA registers *move* between rev 0x02 and rev 0x10
 *		UDMA requires a 66MHz FSB
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_optidma"
#define DRV_VERSION "0.3.2"

enum {
	READ_REG	= 0,	/* index of Read cycle timing register */
	WRITE_REG 	= 1,	/* index of Write cycle timing register */
	CNTRL_REG 	= 3,	/* index of Control register */
	STRAP_REG 	= 5,	/* index of Strap register */
	MISC_REG 	= 6	/* index of Miscellaneous register */
};

static int pci_clock;	/* 0 = 33 1 = 25 */

/**
 *	optidma_pre_reset		-	probe begin
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Set up cable type and use generic probe init
 */

static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const struct pci_bits optidma_enable_bits = {
		0x40, 1, 0x08, 0x00
	};

	if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
		return -ENOENT;

	return ata_std_prereset(link, deadline);
}

/**
 *	optidma_probe_reset		-	probe reset
 *	@ap: ATA port
 *
 *	Perform the ATA probe and bus reset sequence plus specific handling
 *	for this hardware. The Opti needs little handling - we have no UDMA66
 *	capability that needs cable detection. All we must do is check the port
 *	is enabled.
 */

static void optidma_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	optidma_unlock		-	unlock control registers
 *	@ap: ATA port
 *
 *	Unlock the control register block for this adapter. Registers must not
 *	be unlocked in a situation where libata might look at them.
 */

static void optidma_unlock(struct ata_port *ap)
{
	void __iomem *regio = ap->ioaddr.cmd_addr;

	/* These 3 unlock the control register access */
	ioread16(regio + 1);
	ioread16(regio + 1);
	iowrite8(3, regio + 2);
}

/**
 *	optidma_lock		-	issue temporary relock
 *	@ap: ATA port
 *
 *	Re-lock the configuration register settings.
 */

static void optidma_lock(struct ata_port *ap)
{
	void __iomem *regio = ap->ioaddr.cmd_addr;

	/* Relock */
	iowrite8(0x83, regio + 2);
}

/**
 *	optidma_mode_setup	-	set mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: Mode to set
 *
 *	Called to do the DMA or PIO mode setup. Timing numbers are all
 *	pre computed to keep the code clean. There are two tables depending
 *	on the hardware clock speed.
 *
 *	WARNING: While we do this the IDE registers vanish. If we take an
 *	IRQ here we depend on the host set locking to avoid catastrophe.
 */

static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct ata_device *pair = ata_dev_pair(adev);
	int pio = adev->pio_mode - XFER_PIO_0;
	int dma = adev->dma_mode - XFER_MW_DMA_0;
	void __iomem *regio = ap->ioaddr.cmd_addr;
	u8 addr;

	/* Address table precomputed with a DCLK of 2 */
	static const u8 addr_timing[2][5] = {
		{ 0x30, 0x20, 0x20, 0x10, 0x10 },
		{ 0x20, 0x20, 0x10, 0x10, 0x10 }
	};
	static const u8 data_rec_timing[2][5] = {
		{ 0x59, 0x46, 0x30, 0x20, 0x20 },
		{ 0x46, 0x32, 0x20, 0x20, 0x10 }
	};
	static const u8 dma_data_rec_timing[2][3] = {
		{ 0x76, 0x20, 0x20 },
		{ 0x54, 0x20, 0x10 }
	};

	/* Switch from IDE to control mode */
	optidma_unlock(ap);


	/*
 	 *	As with many controllers the address setup time is shared
 	 *	and must suit both devices if present. FIXME: Check if we
 	 *	need to look at slowest of PIO/DMA mode of either device
	 */

	if (mode >= XFER_MW_DMA_0)
		addr = 0;
	else
		addr = addr_timing[pci_clock][pio];

	if (pair) {
		u8 pair_addr;
		/* Hardware constraint */
		if (pair->dma_mode)
			pair_addr = 0;
		else
			pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
		if (pair_addr > addr)
			addr = pair_addr;
	}

	/* Commence primary programming sequence */
	/* First we load the device number into the timing select */
	iowrite8(adev->devno, regio + MISC_REG);
	/* Now we load the data timings into read data/write data */
	if (mode < XFER_MW_DMA_0) {
		iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
		iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
	} else if (mode < XFER_UDMA_0) {
		iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
		iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
	}
	/* Finally we load the address setup into the misc register */
	iowrite8(addr | adev->devno, regio + MISC_REG);

	/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
	iowrite8(0x85, regio + CNTRL_REG);

	/* Switch back to IDE mode */
	optidma_lock(ap);

	/* Note: at this point our programming is incomplete. We are
	   not supposed to program PCI 0x43 "things we hacked onto the chip"
	   until we've done both sets of PIO/DMA timings */
}

/**
 *	optiplus_mode_setup	-	DMA setup for Firestar Plus
 *	@ap: ATA port
 *	@adev: device
 *	@mode: desired mode
 *
 *	The Firestar plus has additional UDMA functionality for UDMA0-2 and
 *	requires we do some additional work. Because the base work we must do
 *	is mostly shared we wrap the Firestar setup functionality in this
 *	one
 */

static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 udcfg;
	u8 udslave;
	int dev2 = 2 * adev->devno;
	int unit = 2 * ap->port_no + adev->devno;
	int udma = mode - XFER_UDMA_0;

	pci_read_config_byte(pdev, 0x44, &udcfg);
	if (mode <= XFER_UDMA_0) {
		udcfg &= ~(1 << unit);
		optidma_mode_setup(ap, adev, adev->dma_mode);
	} else {
		udcfg |=  (1 << unit);
		if (ap->port_no) {
			pci_read_config_byte(pdev, 0x45, &udslave);
			udslave &= ~(0x03 << dev2);
			udslave |= (udma << dev2);
			pci_write_config_byte(pdev, 0x45, udslave);
		} else {
			udcfg &= ~(0x30 << dev2);
			udcfg |= (udma << dev2);
		}
	}
	pci_write_config_byte(pdev, 0x44, udcfg);
}

/**
 *	optidma_set_pio_mode	-	PIO setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
	optidma_mode_setup(ap, adev, adev->pio_mode);
}

/**
 *	optidma_set_dma_mode	-	DMA setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
	optidma_mode_setup(ap, adev, adev->dma_mode);
}

/**
 *	optiplus_set_pio_mode	-	PIO setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
	optiplus_mode_setup(ap, adev, adev->pio_mode);
}

/**
 *	optiplus_set_dma_mode	-	DMA setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
	optiplus_mode_setup(ap, adev, adev->dma_mode);
}

/**
 *	optidma_make_bits	-	PCI setup helper
 *	@adev: ATA device
 *
 *	Turn the ATA device setup into PCI configuration bits
 *	for register 0x43 and return the two bits needed.
 */

static u8 optidma_make_bits43(struct ata_device *adev)
{
	static const u8 bits43[5] = {
		0, 0, 0, 1, 2
	};
	if (!ata_dev_enabled(adev))
		return 0;
	if (adev->dma_mode)
		return adev->dma_mode - XFER_MW_DMA_0;
	return bits43[adev->pio_mode - XFER_PIO_0];
}

/**
 *	optidma_set_mode	-	mode setup
 *	@link: link to set up
 *
 *	Use the standard setup to tune the chipset and then finalise the
 *	configuration by writing the nibble of extra bits of data into
 *	the chip.
 */

static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
{
	struct ata_port *ap = link->ap;
	u8 r;
	int nybble = 4 * ap->port_no;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int rc  = ata_do_set_mode(link, r_failed);
	if (rc == 0) {
		pci_read_config_byte(pdev, 0x43, &r);

		r &= (0x0F << nybble);
		r |= (optidma_make_bits43(&link->device[0]) +
		     (optidma_make_bits43(&link->device[0]) << 2)) << nybble;
		pci_write_config_byte(pdev, 0x43, r);
	}
	return rc;
}

static struct scsi_host_template optidma_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations optidma_port_ops = {
	.set_piomode	= optidma_set_pio_mode,
	.set_dmamode	= optidma_set_dma_mode,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.error_handler	= optidma_error_handler,
	.set_mode	= optidma_set_mode,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,

	.port_start	= ata_sff_port_start,
};

static struct ata_port_operations optiplus_port_ops = {
	.set_piomode	= optiplus_set_pio_mode,
	.set_dmamode	= optiplus_set_dma_mode,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.error_handler	= optidma_error_handler,
	.set_mode	= optidma_set_mode,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,

	.port_start	= ata_sff_port_start,
};

/**
 *	optiplus_with_udma	-	Look for UDMA capable setup
 *	@pdev; ATA controller
 */

static int optiplus_with_udma(struct pci_dev *pdev)
{
	u8 r;
	int ret = 0;
	int ioport = 0x22;
	struct pci_dev *dev1;

	/* Find function 1 */
	dev1 = pci_get_device(0x1045, 0xC701, NULL);
	if(dev1 == NULL)
		return 0;

	/* Rev must be >= 0x10 */
	pci_read_config_byte(dev1, 0x08, &r);
	if (r < 0x10)
		goto done_nomsg;
	/* Read the chipset system configuration to check our mode */
	pci_read_config_byte(dev1, 0x5F, &r);
	ioport |= (r << 8);
	outb(0x10, ioport);
	/* Must be 66Mhz sync */
	if ((inb(ioport + 2) & 1) == 0)
		goto done;

	/* Check the ATA arbitration/timing is suitable */
	pci_read_config_byte(pdev, 0x42, &r);
	if ((r & 0x36) != 0x36)
		goto done;
	pci_read_config_byte(dev1, 0x52, &r);
	if (r & 0x80)	/* IDEDIR disabled */
		ret = 1;
done:
	printk(KERN_WARNING "UDMA not supported in this configuration.\n");
done_nomsg:		/* Wrong chip revision */
	pci_dev_put(dev1);
	return ret;
}

static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_82c700 = {
		.sht = &optidma_sht,
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &optidma_port_ops
	};
	static const struct ata_port_info info_82c700_udma = {
		.sht = &optidma_sht,
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x07,
		.port_ops = &optiplus_port_ops
	};
	const struct ata_port_info *ppi[] = { &info_82c700, NULL };
	static int printed_version;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");

	/* Fixed location chipset magic */
	inw(0x1F1);
	inw(0x1F1);
	pci_clock = inb(0x1F5) & 1;		/* 0 = 33Mhz, 1 = 25Mhz */

	if (optiplus_with_udma(dev))
		ppi[0] = &info_82c700_udma;

	return ata_pci_init_one(dev, ppi);
}

static const struct pci_device_id optidma[] = {
	{ PCI_VDEVICE(OPTI, 0xD568), },		/* Opti 82C700 */

	{ },
};

static struct pci_driver optidma_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= optidma,
	.probe 		= optidma_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

static int __init optidma_init(void)
{
	return pci_register_driver(&optidma_pci_driver);
}

static void __exit optidma_exit(void)
{
	pci_unregister_driver(&optidma_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, optidma);
MODULE_VERSION(DRV_VERSION);

module_init(optidma_init);
module_exit(optidma_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_optidma.c - Opti DMA PATA for new ATA layer
	3	* (C) 2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* The Opti DMA controllers are related to the older PIO PCI controllers
	7	* and indeed the VLB ones. The main differences are that the timing
	8	* numbers are now based off PCI clocks not VLB and differ, and that
	9	* MWDMA is supported.
	10	*
	11	* This driver should support Viper-N+, FireStar, FireStar Plus.
	12	*
	13	* These devices support virtual DMA for read (aka the CS5520). Later
	14	* chips support UDMA33, but only if the rest of the board logic does,
	15	* so you have to get this right. We don't support the virtual DMA
	16	* but we do handle UDMA.
	17	*
	18	* Bits that are worth knowing
	19	* Most control registers are shadowed into I/O registers
	20	* 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
	21	* Virtual DMA registers move between rev 0x02 and rev 0x10
	22	* UDMA requires a 66MHz FSB
	23	*
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/blkdev.h>
	31	#include <linux/delay.h>
	32	#include <scsi/scsi_host.h>
	33	#include <linux/libata.h>
	34
	35	#define DRV_NAME "pata_optidma"
5c25bf0d	36	#define DRV_VERSION "0.3.2"
669a5db4 JG	37
	38	enum {
	39	READ_REG = 0, /* index of Read cycle timing register */
	40	WRITE_REG = 1, /* index of Write cycle timing register */
	41	CNTRL_REG = 3, /* index of Control register */
	42	STRAP_REG = 5, /* index of Strap register */
	43	MISC_REG = 6 /* index of Miscellaneous register */
	44	};
	45
	46	static int pci_clock; /* 0 = 33 1 = 25 */
	47
	48	/**
	49	* optidma_pre_reset - probe begin
cc0680a5	50	* @link: ATA link
d4b2bab4	51	* @deadline: deadline jiffies for the operation
669a5db4 JG	52	*
	53	* Set up cable type and use generic probe init
	54	*/
85cd7251	55
cc0680a5	56	static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	57	{
cc0680a5	58	struct ata_port *ap = link->ap;
669a5db4	59	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	60	static const struct pci_bits optidma_enable_bits = {
669a5db4 JG	61	0x40, 1, 0x08, 0x00
	62	};
	63
c961922b AC	64	if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
	65	return -ENOENT;
	66
cc0680a5	67	return ata_std_prereset(link, deadline);
669a5db4 JG	68	}
	69
	70	/**
	71	* optidma_probe_reset - probe reset
	72	* @ap: ATA port
	73	*
	74	* Perform the ATA probe and bus reset sequence plus specific handling
	75	* for this hardware. The Opti needs little handling - we have no UDMA66
	76	* capability that needs cable detection. All we must do is check the port
	77	* is enabled.
	78	*/
	79
	80	static void optidma_error_handler(struct ata_port *ap)
	81	{
	82	ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	83	}
	84
	85	/**
	86	* optidma_unlock - unlock control registers
	87	* @ap: ATA port
	88	*
	89	* Unlock the control register block for this adapter. Registers must not
	90	* be unlocked in a situation where libata might look at them.
	91	*/
85cd7251	92
669a5db4 JG	93	static void optidma_unlock(struct ata_port *ap)
669a5db4 JG	94	{
0d5ff566	95	void __iomem *regio = ap->ioaddr.cmd_addr;
85cd7251	96
669a5db4	97	/* These 3 unlock the control register access */
0d5ff566 TH	98	ioread16(regio + 1);
	99	ioread16(regio + 1);
	100	iowrite8(3, regio + 2);
669a5db4 JG	101	}
	102
	103	/**
	104	* optidma_lock - issue temporary relock
	105	* @ap: ATA port
	106	*
	107	* Re-lock the configuration register settings.
	108	*/
85cd7251	109
669a5db4 JG	110	static void optidma_lock(struct ata_port *ap)
669a5db4 JG	111	{
0d5ff566	112	void __iomem *regio = ap->ioaddr.cmd_addr;
85cd7251	113
669a5db4	114	/* Relock */
0d5ff566	115	iowrite8(0x83, regio + 2);
669a5db4 JG	116	}
	117
	118	/**
5c25bf0d	119	* optidma_mode_setup - set mode data
669a5db4 JG	120	* @ap: ATA interface
	121	* @adev: ATA device
	122	* @mode: Mode to set
	123	*
	124	* Called to do the DMA or PIO mode setup. Timing numbers are all
	125	* pre computed to keep the code clean. There are two tables depending
	126	* on the hardware clock speed.
	127	*
	128	* WARNING: While we do this the IDE registers vanish. If we take an
	129	* IRQ here we depend on the host set locking to avoid catastrophe.
	130	*/
	131
5c25bf0d	132	static void optidma_mode_setup(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	133	{
	134	struct ata_device *pair = ata_dev_pair(adev);
	135	int pio = adev->pio_mode - XFER_PIO_0;
	136	int dma = adev->dma_mode - XFER_MW_DMA_0;
0d5ff566	137	void __iomem *regio = ap->ioaddr.cmd_addr;
669a5db4 JG	138	u8 addr;
	139
	140	/* Address table precomputed with a DCLK of 2 */
	141	static const u8 addr_timing[2][5] = {
	142	{ 0x30, 0x20, 0x20, 0x10, 0x10 },
	143	{ 0x20, 0x20, 0x10, 0x10, 0x10 }
	144	};
	145	static const u8 data_rec_timing[2][5] = {
	146	{ 0x59, 0x46, 0x30, 0x20, 0x20 },
	147	{ 0x46, 0x32, 0x20, 0x20, 0x10 }
	148	};
	149	static const u8 dma_data_rec_timing[2][3] = {
	150	{ 0x76, 0x20, 0x20 },
	151	{ 0x54, 0x20, 0x10 }
	152	};
	153
	154	/* Switch from IDE to control mode */
	155	optidma_unlock(ap);
85cd7251	156
669a5db4 JG	157
	158	/*
	159	* As with many controllers the address setup time is shared
	160	* and must suit both devices if present. FIXME: Check if we
	161	* need to look at slowest of PIO/DMA mode of either device
	162	*/
	163
	164	if (mode >= XFER_MW_DMA_0)
	165	addr = 0;
	166	else
	167	addr = addr_timing[pci_clock][pio];
85cd7251	168
669a5db4 JG	169	if (pair) {
	170	u8 pair_addr;
	171	/* Hardware constraint */
	172	if (pair->dma_mode)
	173	pair_addr = 0;
	174	else
	175	pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
	176	if (pair_addr > addr)
	177	addr = pair_addr;
	178	}
85cd7251	179
669a5db4 JG	180	/* Commence primary programming sequence */
669a5db4 JG	181	/* First we load the device number into the timing select */
0d5ff566	182	iowrite8(adev->devno, regio + MISC_REG);
669a5db4 JG	183	/* Now we load the data timings into read data/write data */
669a5db4 JG	184	if (mode < XFER_MW_DMA_0) {
0d5ff566 TH	185	iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
0d5ff566 TH	186	iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
669a5db4	187	} else if (mode < XFER_UDMA_0) {
0d5ff566 TH	188	iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
0d5ff566 TH	189	iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
669a5db4 JG	190	}
669a5db4 JG	191	/* Finally we load the address setup into the misc register */
0d5ff566	192	iowrite8(addr \| adev->devno, regio + MISC_REG);
669a5db4 JG	193
669a5db4 JG	194	/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
0d5ff566	195	iowrite8(0x85, regio + CNTRL_REG);
85cd7251	196
669a5db4 JG	197	/* Switch back to IDE mode */
669a5db4 JG	198	optidma_lock(ap);
85cd7251	199
669a5db4 JG	200	/* Note: at this point our programming is incomplete. We are
	201	not supposed to program PCI 0x43 "things we hacked onto the chip"
	202	until we've done both sets of PIO/DMA timings */
	203	}
	204
	205	/**
5c25bf0d	206	* optiplus_mode_setup - DMA setup for Firestar Plus
669a5db4 JG	207	* @ap: ATA port
	208	* @adev: device
	209	* @mode: desired mode
	210	*
	211	* The Firestar plus has additional UDMA functionality for UDMA0-2 and
	212	* requires we do some additional work. Because the base work we must do
	213	* is mostly shared we wrap the Firestar setup functionality in this
	214	* one
	215	*/
	216
5c25bf0d	217	static void optiplus_mode_setup(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	218	{
	219	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	220	u8 udcfg;
	221	u8 udslave;
	222	int dev2 = 2 * adev->devno;
	223	int unit = 2 * ap->port_no + adev->devno;
	224	int udma = mode - XFER_UDMA_0;
85cd7251	225
669a5db4 JG	226	pci_read_config_byte(pdev, 0x44, &udcfg);
	227	if (mode <= XFER_UDMA_0) {
	228	udcfg &= ~(1 << unit);
5c25bf0d	229	optidma_mode_setup(ap, adev, adev->dma_mode);
669a5db4 JG	230	} else {
	231	udcfg \|= (1 << unit);
	232	if (ap->port_no) {
	233	pci_read_config_byte(pdev, 0x45, &udslave);
	234	udslave &= ~(0x03 << dev2);
	235	udslave \|= (udma << dev2);
	236	pci_write_config_byte(pdev, 0x45, udslave);
	237	} else {
	238	udcfg &= ~(0x30 << dev2);
	239	udcfg \|= (udma << dev2);
	240	}
	241	}
	242	pci_write_config_byte(pdev, 0x44, udcfg);
	243	}
	244
	245	/**
	246	* optidma_set_pio_mode - PIO setup callback
	247	* @ap: ATA port
	248	* @adev: Device
	249	*
	250	* The libata core provides separate functions for handling PIO and
	251	* DMA programming. The architecture of the Firestar makes it easier
	252	* for us to have a common function so we provide wrappers
	253	*/
85cd7251	254
669a5db4 JG	255	static void optidma_set_pio_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	256	{
5c25bf0d	257	optidma_mode_setup(ap, adev, adev->pio_mode);
669a5db4 JG	258	}
	259
	260	/**
	261	* optidma_set_dma_mode - DMA setup callback
	262	* @ap: ATA port
	263	* @adev: Device
	264	*
	265	* The libata core provides separate functions for handling PIO and
	266	* DMA programming. The architecture of the Firestar makes it easier
	267	* for us to have a common function so we provide wrappers
	268	*/
85cd7251	269
669a5db4 JG	270	static void optidma_set_dma_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	271	{
5c25bf0d	272	optidma_mode_setup(ap, adev, adev->dma_mode);
669a5db4 JG	273	}
	274
	275	/**
	276	* optiplus_set_pio_mode - PIO setup callback
	277	* @ap: ATA port
	278	* @adev: Device
	279	*
	280	* The libata core provides separate functions for handling PIO and
	281	* DMA programming. The architecture of the Firestar makes it easier
	282	* for us to have a common function so we provide wrappers
	283	*/
85cd7251	284
669a5db4 JG	285	static void optiplus_set_pio_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	286	{
5c25bf0d	287	optiplus_mode_setup(ap, adev, adev->pio_mode);
669a5db4 JG	288	}
	289
	290	/**
	291	* optiplus_set_dma_mode - DMA setup callback
	292	* @ap: ATA port
	293	* @adev: Device
	294	*
	295	* The libata core provides separate functions for handling PIO and
	296	* DMA programming. The architecture of the Firestar makes it easier
	297	* for us to have a common function so we provide wrappers
	298	*/
85cd7251	299
669a5db4 JG	300	static void optiplus_set_dma_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	301	{
5c25bf0d	302	optiplus_mode_setup(ap, adev, adev->dma_mode);
669a5db4 JG	303	}
	304
	305	/**
	306	* optidma_make_bits - PCI setup helper
	307	* @adev: ATA device
	308	*
	309	* Turn the ATA device setup into PCI configuration bits
	310	* for register 0x43 and return the two bits needed.
	311	*/
85cd7251	312
669a5db4 JG	313	static u8 optidma_make_bits43(struct ata_device *adev)
	314	{
	315	static const u8 bits43[5] = {
	316	0, 0, 0, 1, 2
	317	};
	318	if (!ata_dev_enabled(adev))
	319	return 0;
	320	if (adev->dma_mode)
	321	return adev->dma_mode - XFER_MW_DMA_0;
	322	return bits43[adev->pio_mode - XFER_PIO_0];
	323	}
	324
	325	/**
5c25bf0d	326	* optidma_set_mode - mode setup
0260731f	327	* @link: link to set up
669a5db4	328	*
5c25bf0d AC	329	* Use the standard setup to tune the chipset and then finalise the
	330	* configuration by writing the nibble of extra bits of data into
	331	* the chip.
669a5db4	332	*/
85cd7251	333
0260731f	334	static int optidma_set_mode(struct ata_link link, struct ata_device *r_failed)
669a5db4	335	{
0260731f	336	struct ata_port *ap = link->ap;
669a5db4 JG	337	u8 r;
	338	int nybble = 4 * ap->port_no;
	339	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0260731f	340	int rc = ata_do_set_mode(link, r_failed);
5c25bf0d AC	341	if (rc == 0) {
	342	pci_read_config_byte(pdev, 0x43, &r);
	343
	344	r &= (0x0F << nybble);
0260731f TH	345	r \|= (optidma_make_bits43(&link->device[0]) +
0260731f TH	346	(optidma_make_bits43(&link->device[0]) << 2)) << nybble;
5c25bf0d AC	347	pci_write_config_byte(pdev, 0x43, r);
	348	}
	349	return rc;
669a5db4 JG	350	}
	351
	352	static struct scsi_host_template optidma_sht = {
	353	.module = THIS_MODULE,
	354	.name = DRV_NAME,
	355	.ioctl = ata_scsi_ioctl,
	356	.queuecommand = ata_scsi_queuecmd,
	357	.can_queue = ATA_DEF_QUEUE,
	358	.this_id = ATA_SHT_THIS_ID,
	359	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	360	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	361	.emulated = ATA_SHT_EMULATED,
	362	.use_clustering = ATA_SHT_USE_CLUSTERING,
	363	.proc_name = DRV_NAME,
	364	.dma_boundary = ATA_DMA_BOUNDARY,
	365	.slave_configure = ata_scsi_slave_config,
afdfe899	366	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	367	.bios_param = ata_std_bios_param,
	368	};
	369
	370	static struct ata_port_operations optidma_port_ops = {
669a5db4 JG	371	.set_piomode = optidma_set_pio_mode,
	372	.set_dmamode = optidma_set_dma_mode,
	373
	374	.tf_load = ata_tf_load,
	375	.tf_read = ata_tf_read,
	376	.check_status = ata_check_status,
	377	.exec_command = ata_exec_command,
	378	.dev_select = ata_std_dev_select,
	379
	380	.freeze = ata_bmdma_freeze,
	381	.thaw = ata_bmdma_thaw,
	382	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	383	.error_handler = optidma_error_handler,
5c25bf0d AC	384	.set_mode = optidma_set_mode,
5c25bf0d AC	385	.cable_detect = ata_cable_40wire,
669a5db4 JG	386
	387	.bmdma_setup = ata_bmdma_setup,
	388	.bmdma_start = ata_bmdma_start,
	389	.bmdma_stop = ata_bmdma_stop,
	390	.bmdma_status = ata_bmdma_status,
	391
	392	.qc_prep = ata_qc_prep,
	393	.qc_issue = ata_qc_issue_prot,
bda30288	394
0d5ff566	395	.data_xfer = ata_data_xfer,
669a5db4 JG	396
	397	.irq_handler = ata_interrupt,
	398	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	399	.irq_on = ata_irq_on,
669a5db4	400
81ad1837	401	.port_start = ata_sff_port_start,
669a5db4 JG	402	};
	403
	404	static struct ata_port_operations optiplus_port_ops = {
669a5db4 JG	405	.set_piomode = optiplus_set_pio_mode,
	406	.set_dmamode = optiplus_set_dma_mode,
	407
	408	.tf_load = ata_tf_load,
	409	.tf_read = ata_tf_read,
	410	.check_status = ata_check_status,
	411	.exec_command = ata_exec_command,
	412	.dev_select = ata_std_dev_select,
	413
	414	.freeze = ata_bmdma_freeze,
	415	.thaw = ata_bmdma_thaw,
	416	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	417	.error_handler = optidma_error_handler,
5c25bf0d AC	418	.set_mode = optidma_set_mode,
5c25bf0d AC	419	.cable_detect = ata_cable_40wire,
669a5db4 JG	420
	421	.bmdma_setup = ata_bmdma_setup,
	422	.bmdma_start = ata_bmdma_start,
	423	.bmdma_stop = ata_bmdma_stop,
	424	.bmdma_status = ata_bmdma_status,
	425
	426	.qc_prep = ata_qc_prep,
	427	.qc_issue = ata_qc_issue_prot,
bda30288	428
0d5ff566	429	.data_xfer = ata_data_xfer,
669a5db4 JG	430
	431	.irq_handler = ata_interrupt,
	432	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	433	.irq_on = ata_irq_on,
669a5db4	434
81ad1837	435	.port_start = ata_sff_port_start,
669a5db4 JG	436	};
	437
	438	/**
	439	* optiplus_with_udma - Look for UDMA capable setup
	440	* @pdev; ATA controller
	441	*/
85cd7251	442
669a5db4 JG	443	static int optiplus_with_udma(struct pci_dev *pdev)
	444	{
	445	u8 r;
	446	int ret = 0;
	447	int ioport = 0x22;
	448	struct pci_dev *dev1;
85cd7251	449
669a5db4 JG	450	/* Find function 1 */
	451	dev1 = pci_get_device(0x1045, 0xC701, NULL);
	452	if(dev1 == NULL)
	453	return 0;
85cd7251	454
669a5db4 JG	455	/* Rev must be >= 0x10 */
	456	pci_read_config_byte(dev1, 0x08, &r);
	457	if (r < 0x10)
	458	goto done_nomsg;
	459	/* Read the chipset system configuration to check our mode */
	460	pci_read_config_byte(dev1, 0x5F, &r);
	461	ioport \|= (r << 8);
	462	outb(0x10, ioport);
	463	/* Must be 66Mhz sync */
	464	if ((inb(ioport + 2) & 1) == 0)
	465	goto done;
	466
	467	/* Check the ATA arbitration/timing is suitable */
	468	pci_read_config_byte(pdev, 0x42, &r);
	469	if ((r & 0x36) != 0x36)
	470	goto done;
	471	pci_read_config_byte(dev1, 0x52, &r);
	472	if (r & 0x80) /* IDEDIR disabled */
	473	ret = 1;
85cd7251	474	done:
669a5db4 JG	475	printk(KERN_WARNING "UDMA not supported in this configuration.\n");
	476	done_nomsg: /* Wrong chip revision */
	477	pci_dev_put(dev1);
	478	return ret;
	479	}
	480
	481	static int optidma_init_one(struct pci_dev dev, const struct pci_device_id id)
	482	{
1626aeb8	483	static const struct ata_port_info info_82c700 = {
669a5db4	484	.sht = &optidma_sht,
1d2808fd	485	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	486	.pio_mask = 0x1f,
	487	.mwdma_mask = 0x07,
	488	.port_ops = &optidma_port_ops
	489	};
1626aeb8	490	static const struct ata_port_info info_82c700_udma = {
669a5db4	491	.sht = &optidma_sht,
1d2808fd	492	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	493	.pio_mask = 0x1f,
	494	.mwdma_mask = 0x07,
	495	.udma_mask = 0x07,
	496	.port_ops = &optiplus_port_ops
	497	};
1626aeb8	498	const struct ata_port_info *ppi[] = { &info_82c700, NULL };
669a5db4 JG	499	static int printed_version;
	500
	501	if (!printed_version++)
	502	dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
	503
	504	/* Fixed location chipset magic */
	505	inw(0x1F1);
	506	inw(0x1F1);
	507	pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
85cd7251	508
669a5db4	509	if (optiplus_with_udma(dev))
1626aeb8	510	ppi[0] = &info_82c700_udma;
669a5db4	511
1626aeb8	512	return ata_pci_init_one(dev, ppi);
669a5db4 JG	513	}
	514
	515	static const struct pci_device_id optidma[] = {
2d2744fc JG	516	{ PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */
	517
	518	{ },
669a5db4 JG	519	};
	520
	521	static struct pci_driver optidma_pci_driver = {
2d2744fc	522	.name = DRV_NAME,
669a5db4 JG	523	.id_table = optidma,
669a5db4 JG	524	.probe = optidma_init_one,
30ced0f0	525	.remove = ata_pci_remove_one,
438ac6d5	526	#ifdef CONFIG_PM
30ced0f0 AC	527	.suspend = ata_pci_device_suspend,
30ced0f0 AC	528	.resume = ata_pci_device_resume,
438ac6d5	529	#endif
669a5db4 JG	530	};
	531
	532	static int __init optidma_init(void)
	533	{
	534	return pci_register_driver(&optidma_pci_driver);
	535	}
	536
669a5db4 JG	537	static void __exit optidma_exit(void)
	538	{
	539	pci_unregister_driver(&optidma_pci_driver);
	540	}
	541
669a5db4 JG	542	MODULE_AUTHOR("Alan Cox");
	543	MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
	544	MODULE_LICENSE("GPL");
	545	MODULE_DEVICE_TABLE(pci, optidma);
	546	MODULE_VERSION(DRV_VERSION);
	547
	548	module_init(optidma_init);
	549	module_exit(optidma_exit);