[mirror_ubuntu-bionic-kernel.git] / drivers / ata / pata_optidma.c

/*
 * pata_optidma.c 	- Opti DMA PATA for new ATA layer
 *			  (C) 2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 *	The Opti DMA controllers are related to the older PIO PCI controllers
 *	and indeed the VLB ones. The main differences are that the timing
 *	numbers are now based off PCI clocks not VLB and differ, and that
 *	MWDMA is supported.
 *
 *	This driver should support Viper-N+, FireStar, FireStar Plus.
 *
 *	These devices support virtual DMA for read (aka the CS5520). Later
 *	chips support UDMA33, but only if the rest of the board logic does,
 *	so you have to get this right. We don't support the virtual DMA
 *	but we do handle UDMA.
 *
 *	Bits that are worth knowing
 *		Most control registers are shadowed into I/O registers
 *		0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
 *		Virtual DMA registers *move* between rev 0x02 and rev 0x10
 *		UDMA requires a 66MHz FSB
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_optidma"
#define DRV_VERSION "0.3.2"

enum {
	READ_REG	= 0,	/* index of Read cycle timing register */
	WRITE_REG 	= 1,	/* index of Write cycle timing register */
	CNTRL_REG 	= 3,	/* index of Control register */
	STRAP_REG 	= 5,	/* index of Strap register */
	MISC_REG 	= 6	/* index of Miscellaneous register */
};

static int pci_clock;	/* 0 = 33 1 = 25 */

/**
 *	optidma_pre_reset		-	probe begin
 *	@ap: ATA port
 *
 *	Set up cable type and use generic probe init
 */

static int optidma_pre_reset(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const struct pci_bits optidma_enable_bits = {
		0x40, 1, 0x08, 0x00
	};

	if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
		return -ENOENT;

	return ata_std_prereset(ap);
}

/**
 *	optidma_probe_reset		-	probe reset
 *	@ap: ATA port
 *
 *	Perform the ATA probe and bus reset sequence plus specific handling
 *	for this hardware. The Opti needs little handling - we have no UDMA66
 *	capability that needs cable detection. All we must do is check the port
 *	is enabled.
 */

static void optidma_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	optidma_unlock		-	unlock control registers
 *	@ap: ATA port
 *
 *	Unlock the control register block for this adapter. Registers must not
 *	be unlocked in a situation where libata might look at them.
 */

static void optidma_unlock(struct ata_port *ap)
{
	void __iomem *regio = ap->ioaddr.cmd_addr;

	/* These 3 unlock the control register access */
	ioread16(regio + 1);
	ioread16(regio + 1);
	iowrite8(3, regio + 2);
}

/**
 *	optidma_lock		-	issue temporary relock
 *	@ap: ATA port
 *
 *	Re-lock the configuration register settings.
 */

static void optidma_lock(struct ata_port *ap)
{
	void __iomem *regio = ap->ioaddr.cmd_addr;

	/* Relock */
	iowrite8(0x83, regio + 2);
}

/**
 *	optidma_mode_setup	-	set mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: Mode to set
 *
 *	Called to do the DMA or PIO mode setup. Timing numbers are all
 *	pre computed to keep the code clean. There are two tables depending
 *	on the hardware clock speed.
 *
 *	WARNING: While we do this the IDE registers vanish. If we take an
 *	IRQ here we depend on the host set locking to avoid catastrophe.
 */

static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct ata_device *pair = ata_dev_pair(adev);
	int pio = adev->pio_mode - XFER_PIO_0;
	int dma = adev->dma_mode - XFER_MW_DMA_0;
	void __iomem *regio = ap->ioaddr.cmd_addr;
	u8 addr;

	/* Address table precomputed with a DCLK of 2 */
	static const u8 addr_timing[2][5] = {
		{ 0x30, 0x20, 0x20, 0x10, 0x10 },
		{ 0x20, 0x20, 0x10, 0x10, 0x10 }
	};
	static const u8 data_rec_timing[2][5] = {
		{ 0x59, 0x46, 0x30, 0x20, 0x20 },
		{ 0x46, 0x32, 0x20, 0x20, 0x10 }
	};
	static const u8 dma_data_rec_timing[2][3] = {
		{ 0x76, 0x20, 0x20 },
		{ 0x54, 0x20, 0x10 }
	};

	/* Switch from IDE to control mode */
	optidma_unlock(ap);


	/*
 	 *	As with many controllers the address setup time is shared
 	 *	and must suit both devices if present. FIXME: Check if we
 	 *	need to look at slowest of PIO/DMA mode of either device
	 */

	if (mode >= XFER_MW_DMA_0)
		addr = 0;
	else
		addr = addr_timing[pci_clock][pio];

	if (pair) {
		u8 pair_addr;
		/* Hardware constraint */
		if (pair->dma_mode)
			pair_addr = 0;
		else
			pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
		if (pair_addr > addr)
			addr = pair_addr;
	}

	/* Commence primary programming sequence */
	/* First we load the device number into the timing select */
	iowrite8(adev->devno, regio + MISC_REG);
	/* Now we load the data timings into read data/write data */
	if (mode < XFER_MW_DMA_0) {
		iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
		iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
	} else if (mode < XFER_UDMA_0) {
		iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
		iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
	}
	/* Finally we load the address setup into the misc register */
	iowrite8(addr | adev->devno, regio + MISC_REG);

	/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
	iowrite8(0x85, regio + CNTRL_REG);

	/* Switch back to IDE mode */
	optidma_lock(ap);

	/* Note: at this point our programming is incomplete. We are
	   not supposed to program PCI 0x43 "things we hacked onto the chip"
	   until we've done both sets of PIO/DMA timings */
}

/**
 *	optiplus_mode_setup	-	DMA setup for Firestar Plus
 *	@ap: ATA port
 *	@adev: device
 *	@mode: desired mode
 *
 *	The Firestar plus has additional UDMA functionality for UDMA0-2 and
 *	requires we do some additional work. Because the base work we must do
 *	is mostly shared we wrap the Firestar setup functionality in this
 *	one
 */

static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 udcfg;
	u8 udslave;
	int dev2 = 2 * adev->devno;
	int unit = 2 * ap->port_no + adev->devno;
	int udma = mode - XFER_UDMA_0;

	pci_read_config_byte(pdev, 0x44, &udcfg);
	if (mode <= XFER_UDMA_0) {
		udcfg &= ~(1 << unit);
		optidma_mode_setup(ap, adev, adev->dma_mode);
	} else {
		udcfg |=  (1 << unit);
		if (ap->port_no) {
			pci_read_config_byte(pdev, 0x45, &udslave);
			udslave &= ~(0x03 << dev2);
			udslave |= (udma << dev2);
			pci_write_config_byte(pdev, 0x45, udslave);
		} else {
			udcfg &= ~(0x30 << dev2);
			udcfg |= (udma << dev2);
		}
	}
	pci_write_config_byte(pdev, 0x44, udcfg);
}

/**
 *	optidma_set_pio_mode	-	PIO setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
	optidma_mode_setup(ap, adev, adev->pio_mode);
}

/**
 *	optidma_set_dma_mode	-	DMA setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
	optidma_mode_setup(ap, adev, adev->dma_mode);
}

/**
 *	optiplus_set_pio_mode	-	PIO setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
	optiplus_mode_setup(ap, adev, adev->pio_mode);
}

/**
 *	optiplus_set_dma_mode	-	DMA setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
	optiplus_mode_setup(ap, adev, adev->dma_mode);
}

/**
 *	optidma_make_bits	-	PCI setup helper
 *	@adev: ATA device
 *
 *	Turn the ATA device setup into PCI configuration bits
 *	for register 0x43 and return the two bits needed.
 */

static u8 optidma_make_bits43(struct ata_device *adev)
{
	static const u8 bits43[5] = {
		0, 0, 0, 1, 2
	};
	if (!ata_dev_enabled(adev))
		return 0;
	if (adev->dma_mode)
		return adev->dma_mode - XFER_MW_DMA_0;
	return bits43[adev->pio_mode - XFER_PIO_0];
}

/**
 *	optidma_set_mode	-	mode setup
 *	@ap: port to set up
 *
 *	Use the standard setup to tune the chipset and then finalise the
 *	configuration by writing the nibble of extra bits of data into
 *	the chip.
 */

static int optidma_set_mode(struct ata_port *ap, struct ata_device **r_failed)
{
	u8 r;
	int nybble = 4 * ap->port_no;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int rc  = ata_do_set_mode(ap, r_failed);
	if (rc == 0) {
		pci_read_config_byte(pdev, 0x43, &r);

		r &= (0x0F << nybble);
		r |= (optidma_make_bits43(&ap->device[0]) +
		     (optidma_make_bits43(&ap->device[0]) << 2)) << nybble;
		pci_write_config_byte(pdev, 0x43, r);
	}
	return rc;
}

static struct scsi_host_template optidma_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
#ifdef CONFIG_PM
	.resume			= ata_scsi_device_resume,
	.suspend		= ata_scsi_device_suspend,
#endif
};

static struct ata_port_operations optidma_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= optidma_set_pio_mode,
	.set_dmamode	= optidma_set_dma_mode,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.error_handler	= optidma_error_handler,
	.set_mode	= optidma_set_mode,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static struct ata_port_operations optiplus_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= optiplus_set_pio_mode,
	.set_dmamode	= optiplus_set_dma_mode,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.error_handler	= optidma_error_handler,
	.set_mode	= optidma_set_mode,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

/**
 *	optiplus_with_udma	-	Look for UDMA capable setup
 *	@pdev; ATA controller
 */

static int optiplus_with_udma(struct pci_dev *pdev)
{
	u8 r;
	int ret = 0;
	int ioport = 0x22;
	struct pci_dev *dev1;

	/* Find function 1 */
	dev1 = pci_get_device(0x1045, 0xC701, NULL);
	if(dev1 == NULL)
		return 0;

	/* Rev must be >= 0x10 */
	pci_read_config_byte(dev1, 0x08, &r);
	if (r < 0x10)
		goto done_nomsg;
	/* Read the chipset system configuration to check our mode */
	pci_read_config_byte(dev1, 0x5F, &r);
	ioport |= (r << 8);
	outb(0x10, ioport);
	/* Must be 66Mhz sync */
	if ((inb(ioport + 2) & 1) == 0)
		goto done;

	/* Check the ATA arbitration/timing is suitable */
	pci_read_config_byte(pdev, 0x42, &r);
	if ((r & 0x36) != 0x36)
		goto done;
	pci_read_config_byte(dev1, 0x52, &r);
	if (r & 0x80)	/* IDEDIR disabled */
		ret = 1;
done:
	printk(KERN_WARNING "UDMA not supported in this configuration.\n");
done_nomsg:		/* Wrong chip revision */
	pci_dev_put(dev1);
	return ret;
}

static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static struct ata_port_info info_82c700 = {
		.sht = &optidma_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &optidma_port_ops
	};
	static struct ata_port_info info_82c700_udma = {
		.sht = &optidma_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x07,
		.port_ops = &optiplus_port_ops
	};
	static struct ata_port_info *port_info[2];
	struct ata_port_info *info = &info_82c700;
	static int printed_version;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");

	/* Fixed location chipset magic */
	inw(0x1F1);
	inw(0x1F1);
	pci_clock = inb(0x1F5) & 1;		/* 0 = 33Mhz, 1 = 25Mhz */

	if (optiplus_with_udma(dev))
		info = &info_82c700_udma;

	port_info[0] = port_info[1] = info;
	return ata_pci_init_one(dev, port_info, 2);
}

static const struct pci_device_id optidma[] = {
	{ PCI_VDEVICE(OPTI, 0xD568), },		/* Opti 82C700 */

	{ },
};

static struct pci_driver optidma_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= optidma,
	.probe 		= optidma_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

static int __init optidma_init(void)
{
	return pci_register_driver(&optidma_pci_driver);
}

static void __exit optidma_exit(void)
{
	pci_unregister_driver(&optidma_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, optidma);
MODULE_VERSION(DRV_VERSION);

module_init(optidma_init);
module_exit(optidma_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_optidma.c - Opti DMA PATA for new ATA layer
	3	* (C) 2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* The Opti DMA controllers are related to the older PIO PCI controllers
	7	* and indeed the VLB ones. The main differences are that the timing
	8	* numbers are now based off PCI clocks not VLB and differ, and that
	9	* MWDMA is supported.
	10	*
	11	* This driver should support Viper-N+, FireStar, FireStar Plus.
	12	*
	13	* These devices support virtual DMA for read (aka the CS5520). Later
	14	* chips support UDMA33, but only if the rest of the board logic does,
	15	* so you have to get this right. We don't support the virtual DMA
	16	* but we do handle UDMA.
	17	*
	18	* Bits that are worth knowing
	19	* Most control registers are shadowed into I/O registers
	20	* 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
	21	* Virtual DMA registers move between rev 0x02 and rev 0x10
	22	* UDMA requires a 66MHz FSB
	23	*
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/blkdev.h>
	31	#include <linux/delay.h>
	32	#include <scsi/scsi_host.h>
	33	#include <linux/libata.h>
	34
	35	#define DRV_NAME "pata_optidma"
5c25bf0d	36	#define DRV_VERSION "0.3.2"
669a5db4 JG	37
	38	enum {
	39	READ_REG = 0, /* index of Read cycle timing register */
	40	WRITE_REG = 1, /* index of Write cycle timing register */
	41	CNTRL_REG = 3, /* index of Control register */
	42	STRAP_REG = 5, /* index of Strap register */
	43	MISC_REG = 6 /* index of Miscellaneous register */
	44	};
	45
	46	static int pci_clock; /* 0 = 33 1 = 25 */
	47
	48	/**
	49	* optidma_pre_reset - probe begin
	50	* @ap: ATA port
	51	*
	52	* Set up cable type and use generic probe init
	53	*/
85cd7251	54
669a5db4 JG	55	static int optidma_pre_reset(struct ata_port *ap)
	56	{
	57	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	58	static const struct pci_bits optidma_enable_bits = {
669a5db4 JG	59	0x40, 1, 0x08, 0x00
	60	};
	61
c961922b AC	62	if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
	63	return -ENOENT;
	64
669a5db4 JG	65	return ata_std_prereset(ap);
	66	}
	67
	68	/**
	69	* optidma_probe_reset - probe reset
	70	* @ap: ATA port
	71	*
	72	* Perform the ATA probe and bus reset sequence plus specific handling
	73	* for this hardware. The Opti needs little handling - we have no UDMA66
	74	* capability that needs cable detection. All we must do is check the port
	75	* is enabled.
	76	*/
	77
	78	static void optidma_error_handler(struct ata_port *ap)
	79	{
	80	ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	81	}
	82
	83	/**
	84	* optidma_unlock - unlock control registers
	85	* @ap: ATA port
	86	*
	87	* Unlock the control register block for this adapter. Registers must not
	88	* be unlocked in a situation where libata might look at them.
	89	*/
85cd7251	90
669a5db4 JG	91	static void optidma_unlock(struct ata_port *ap)
669a5db4 JG	92	{
0d5ff566	93	void __iomem *regio = ap->ioaddr.cmd_addr;
85cd7251	94
669a5db4	95	/* These 3 unlock the control register access */
0d5ff566 TH	96	ioread16(regio + 1);
	97	ioread16(regio + 1);
	98	iowrite8(3, regio + 2);
669a5db4 JG	99	}
	100
	101	/**
	102	* optidma_lock - issue temporary relock
	103	* @ap: ATA port
	104	*
	105	* Re-lock the configuration register settings.
	106	*/
85cd7251	107
669a5db4 JG	108	static void optidma_lock(struct ata_port *ap)
669a5db4 JG	109	{
0d5ff566	110	void __iomem *regio = ap->ioaddr.cmd_addr;
85cd7251	111
669a5db4	112	/* Relock */
0d5ff566	113	iowrite8(0x83, regio + 2);
669a5db4 JG	114	}
	115
	116	/**
5c25bf0d	117	* optidma_mode_setup - set mode data
669a5db4 JG	118	* @ap: ATA interface
	119	* @adev: ATA device
	120	* @mode: Mode to set
	121	*
	122	* Called to do the DMA or PIO mode setup. Timing numbers are all
	123	* pre computed to keep the code clean. There are two tables depending
	124	* on the hardware clock speed.
	125	*
	126	* WARNING: While we do this the IDE registers vanish. If we take an
	127	* IRQ here we depend on the host set locking to avoid catastrophe.
	128	*/
	129
5c25bf0d	130	static void optidma_mode_setup(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	131	{
	132	struct ata_device *pair = ata_dev_pair(adev);
	133	int pio = adev->pio_mode - XFER_PIO_0;
	134	int dma = adev->dma_mode - XFER_MW_DMA_0;
0d5ff566	135	void __iomem *regio = ap->ioaddr.cmd_addr;
669a5db4 JG	136	u8 addr;
	137
	138	/* Address table precomputed with a DCLK of 2 */
	139	static const u8 addr_timing[2][5] = {
	140	{ 0x30, 0x20, 0x20, 0x10, 0x10 },
	141	{ 0x20, 0x20, 0x10, 0x10, 0x10 }
	142	};
	143	static const u8 data_rec_timing[2][5] = {
	144	{ 0x59, 0x46, 0x30, 0x20, 0x20 },
	145	{ 0x46, 0x32, 0x20, 0x20, 0x10 }
	146	};
	147	static const u8 dma_data_rec_timing[2][3] = {
	148	{ 0x76, 0x20, 0x20 },
	149	{ 0x54, 0x20, 0x10 }
	150	};
	151
	152	/* Switch from IDE to control mode */
	153	optidma_unlock(ap);
85cd7251	154
669a5db4 JG	155
	156	/*
	157	* As with many controllers the address setup time is shared
	158	* and must suit both devices if present. FIXME: Check if we
	159	* need to look at slowest of PIO/DMA mode of either device
	160	*/
	161
	162	if (mode >= XFER_MW_DMA_0)
	163	addr = 0;
	164	else
	165	addr = addr_timing[pci_clock][pio];
85cd7251	166
669a5db4 JG	167	if (pair) {
	168	u8 pair_addr;
	169	/* Hardware constraint */
	170	if (pair->dma_mode)
	171	pair_addr = 0;
	172	else
	173	pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
	174	if (pair_addr > addr)
	175	addr = pair_addr;
	176	}
85cd7251	177
669a5db4 JG	178	/* Commence primary programming sequence */
669a5db4 JG	179	/* First we load the device number into the timing select */
0d5ff566	180	iowrite8(adev->devno, regio + MISC_REG);
669a5db4 JG	181	/* Now we load the data timings into read data/write data */
669a5db4 JG	182	if (mode < XFER_MW_DMA_0) {
0d5ff566 TH	183	iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
0d5ff566 TH	184	iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
669a5db4	185	} else if (mode < XFER_UDMA_0) {
0d5ff566 TH	186	iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
0d5ff566 TH	187	iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
669a5db4 JG	188	}
669a5db4 JG	189	/* Finally we load the address setup into the misc register */
0d5ff566	190	iowrite8(addr \| adev->devno, regio + MISC_REG);
669a5db4 JG	191
669a5db4 JG	192	/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
0d5ff566	193	iowrite8(0x85, regio + CNTRL_REG);
85cd7251	194
669a5db4 JG	195	/* Switch back to IDE mode */
669a5db4 JG	196	optidma_lock(ap);
85cd7251	197
669a5db4 JG	198	/* Note: at this point our programming is incomplete. We are
	199	not supposed to program PCI 0x43 "things we hacked onto the chip"
	200	until we've done both sets of PIO/DMA timings */
	201	}
	202
	203	/**
5c25bf0d	204	* optiplus_mode_setup - DMA setup for Firestar Plus
669a5db4 JG	205	* @ap: ATA port
	206	* @adev: device
	207	* @mode: desired mode
	208	*
	209	* The Firestar plus has additional UDMA functionality for UDMA0-2 and
	210	* requires we do some additional work. Because the base work we must do
	211	* is mostly shared we wrap the Firestar setup functionality in this
	212	* one
	213	*/
	214
5c25bf0d	215	static void optiplus_mode_setup(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	216	{
	217	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	218	u8 udcfg;
	219	u8 udslave;
	220	int dev2 = 2 * adev->devno;
	221	int unit = 2 * ap->port_no + adev->devno;
	222	int udma = mode - XFER_UDMA_0;
85cd7251	223
669a5db4 JG	224	pci_read_config_byte(pdev, 0x44, &udcfg);
	225	if (mode <= XFER_UDMA_0) {
	226	udcfg &= ~(1 << unit);
5c25bf0d	227	optidma_mode_setup(ap, adev, adev->dma_mode);
669a5db4 JG	228	} else {
	229	udcfg \|= (1 << unit);
	230	if (ap->port_no) {
	231	pci_read_config_byte(pdev, 0x45, &udslave);
	232	udslave &= ~(0x03 << dev2);
	233	udslave \|= (udma << dev2);
	234	pci_write_config_byte(pdev, 0x45, udslave);
	235	} else {
	236	udcfg &= ~(0x30 << dev2);
	237	udcfg \|= (udma << dev2);
	238	}
	239	}
	240	pci_write_config_byte(pdev, 0x44, udcfg);
	241	}
	242
	243	/**
	244	* optidma_set_pio_mode - PIO setup callback
	245	* @ap: ATA port
	246	* @adev: Device
	247	*
	248	* The libata core provides separate functions for handling PIO and
	249	* DMA programming. The architecture of the Firestar makes it easier
	250	* for us to have a common function so we provide wrappers
	251	*/
85cd7251	252
669a5db4 JG	253	static void optidma_set_pio_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	254	{
5c25bf0d	255	optidma_mode_setup(ap, adev, adev->pio_mode);
669a5db4 JG	256	}
	257
	258	/**
	259	* optidma_set_dma_mode - DMA setup callback
	260	* @ap: ATA port
	261	* @adev: Device
	262	*
	263	* The libata core provides separate functions for handling PIO and
	264	* DMA programming. The architecture of the Firestar makes it easier
	265	* for us to have a common function so we provide wrappers
	266	*/
85cd7251	267
669a5db4 JG	268	static void optidma_set_dma_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	269	{
5c25bf0d	270	optidma_mode_setup(ap, adev, adev->dma_mode);
669a5db4 JG	271	}
	272
	273	/**
	274	* optiplus_set_pio_mode - PIO setup callback
	275	* @ap: ATA port
	276	* @adev: Device
	277	*
	278	* The libata core provides separate functions for handling PIO and
	279	* DMA programming. The architecture of the Firestar makes it easier
	280	* for us to have a common function so we provide wrappers
	281	*/
85cd7251	282
669a5db4 JG	283	static void optiplus_set_pio_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	284	{
5c25bf0d	285	optiplus_mode_setup(ap, adev, adev->pio_mode);
669a5db4 JG	286	}
	287
	288	/**
	289	* optiplus_set_dma_mode - DMA setup callback
	290	* @ap: ATA port
	291	* @adev: Device
	292	*
	293	* The libata core provides separate functions for handling PIO and
	294	* DMA programming. The architecture of the Firestar makes it easier
	295	* for us to have a common function so we provide wrappers
	296	*/
85cd7251	297
669a5db4 JG	298	static void optiplus_set_dma_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	299	{
5c25bf0d	300	optiplus_mode_setup(ap, adev, adev->dma_mode);
669a5db4 JG	301	}
	302
	303	/**
	304	* optidma_make_bits - PCI setup helper
	305	* @adev: ATA device
	306	*
	307	* Turn the ATA device setup into PCI configuration bits
	308	* for register 0x43 and return the two bits needed.
	309	*/
85cd7251	310
669a5db4 JG	311	static u8 optidma_make_bits43(struct ata_device *adev)
	312	{
	313	static const u8 bits43[5] = {
	314	0, 0, 0, 1, 2
	315	};
	316	if (!ata_dev_enabled(adev))
	317	return 0;
	318	if (adev->dma_mode)
	319	return adev->dma_mode - XFER_MW_DMA_0;
	320	return bits43[adev->pio_mode - XFER_PIO_0];
	321	}
	322
	323	/**
5c25bf0d	324	* optidma_set_mode - mode setup
669a5db4 JG	325	* @ap: port to set up
669a5db4 JG	326	*
5c25bf0d AC	327	* Use the standard setup to tune the chipset and then finalise the
	328	* configuration by writing the nibble of extra bits of data into
	329	* the chip.
669a5db4	330	*/
85cd7251	331
5c25bf0d	332	static int optidma_set_mode(struct ata_port ap, struct ata_device *r_failed)
669a5db4 JG	333	{
	334	u8 r;
	335	int nybble = 4 * ap->port_no;
	336	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
5c25bf0d AC	337	int rc = ata_do_set_mode(ap, r_failed);
	338	if (rc == 0) {
	339	pci_read_config_byte(pdev, 0x43, &r);
	340
	341	r &= (0x0F << nybble);
	342	r \|= (optidma_make_bits43(&ap->device[0]) +
	343	(optidma_make_bits43(&ap->device[0]) << 2)) << nybble;
	344	pci_write_config_byte(pdev, 0x43, r);
	345	}
	346	return rc;
669a5db4 JG	347	}
	348
	349	static struct scsi_host_template optidma_sht = {
	350	.module = THIS_MODULE,
	351	.name = DRV_NAME,
	352	.ioctl = ata_scsi_ioctl,
	353	.queuecommand = ata_scsi_queuecmd,
	354	.can_queue = ATA_DEF_QUEUE,
	355	.this_id = ATA_SHT_THIS_ID,
	356	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	357	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	358	.emulated = ATA_SHT_EMULATED,
	359	.use_clustering = ATA_SHT_USE_CLUSTERING,
	360	.proc_name = DRV_NAME,
	361	.dma_boundary = ATA_DMA_BOUNDARY,
	362	.slave_configure = ata_scsi_slave_config,
afdfe899	363	.slave_destroy = ata_scsi_slave_destroy,
669a5db4	364	.bios_param = ata_std_bios_param,
438ac6d5	365	#ifdef CONFIG_PM
30ced0f0 AC	366	.resume = ata_scsi_device_resume,
30ced0f0 AC	367	.suspend = ata_scsi_device_suspend,
438ac6d5	368	#endif
669a5db4 JG	369	};
	370
	371	static struct ata_port_operations optidma_port_ops = {
	372	.port_disable = ata_port_disable,
	373	.set_piomode = optidma_set_pio_mode,
	374	.set_dmamode = optidma_set_dma_mode,
	375
	376	.tf_load = ata_tf_load,
	377	.tf_read = ata_tf_read,
	378	.check_status = ata_check_status,
	379	.exec_command = ata_exec_command,
	380	.dev_select = ata_std_dev_select,
	381
	382	.freeze = ata_bmdma_freeze,
	383	.thaw = ata_bmdma_thaw,
	384	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	385	.error_handler = optidma_error_handler,
5c25bf0d AC	386	.set_mode = optidma_set_mode,
5c25bf0d AC	387	.cable_detect = ata_cable_40wire,
669a5db4 JG	388
	389	.bmdma_setup = ata_bmdma_setup,
	390	.bmdma_start = ata_bmdma_start,
	391	.bmdma_stop = ata_bmdma_stop,
	392	.bmdma_status = ata_bmdma_status,
	393
	394	.qc_prep = ata_qc_prep,
	395	.qc_issue = ata_qc_issue_prot,
bda30288	396
0d5ff566	397	.data_xfer = ata_data_xfer,
669a5db4 JG	398
	399	.irq_handler = ata_interrupt,
	400	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	401	.irq_on = ata_irq_on,
246ce3b6 AI	402	.irq_ack = ata_irq_ack,
669a5db4 JG	403
669a5db4 JG	404	.port_start = ata_port_start,
669a5db4 JG	405	};
	406
	407	static struct ata_port_operations optiplus_port_ops = {
	408	.port_disable = ata_port_disable,
	409	.set_piomode = optiplus_set_pio_mode,
	410	.set_dmamode = optiplus_set_dma_mode,
	411
	412	.tf_load = ata_tf_load,
	413	.tf_read = ata_tf_read,
	414	.check_status = ata_check_status,
	415	.exec_command = ata_exec_command,
	416	.dev_select = ata_std_dev_select,
	417
	418	.freeze = ata_bmdma_freeze,
	419	.thaw = ata_bmdma_thaw,
	420	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	421	.error_handler = optidma_error_handler,
5c25bf0d AC	422	.set_mode = optidma_set_mode,
5c25bf0d AC	423	.cable_detect = ata_cable_40wire,
669a5db4 JG	424
	425	.bmdma_setup = ata_bmdma_setup,
	426	.bmdma_start = ata_bmdma_start,
	427	.bmdma_stop = ata_bmdma_stop,
	428	.bmdma_status = ata_bmdma_status,
	429
	430	.qc_prep = ata_qc_prep,
	431	.qc_issue = ata_qc_issue_prot,
bda30288	432
0d5ff566	433	.data_xfer = ata_data_xfer,
669a5db4 JG	434
	435	.irq_handler = ata_interrupt,
	436	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	437	.irq_on = ata_irq_on,
246ce3b6 AI	438	.irq_ack = ata_irq_ack,
669a5db4 JG	439
669a5db4 JG	440	.port_start = ata_port_start,
669a5db4 JG	441	};
	442
	443	/**
	444	* optiplus_with_udma - Look for UDMA capable setup
	445	* @pdev; ATA controller
	446	*/
85cd7251	447
669a5db4 JG	448	static int optiplus_with_udma(struct pci_dev *pdev)
	449	{
	450	u8 r;
	451	int ret = 0;
	452	int ioport = 0x22;
	453	struct pci_dev *dev1;
85cd7251	454
669a5db4 JG	455	/* Find function 1 */
	456	dev1 = pci_get_device(0x1045, 0xC701, NULL);
	457	if(dev1 == NULL)
	458	return 0;
85cd7251	459
669a5db4 JG	460	/* Rev must be >= 0x10 */
	461	pci_read_config_byte(dev1, 0x08, &r);
	462	if (r < 0x10)
	463	goto done_nomsg;
	464	/* Read the chipset system configuration to check our mode */
	465	pci_read_config_byte(dev1, 0x5F, &r);
	466	ioport \|= (r << 8);
	467	outb(0x10, ioport);
	468	/* Must be 66Mhz sync */
	469	if ((inb(ioport + 2) & 1) == 0)
	470	goto done;
	471
	472	/* Check the ATA arbitration/timing is suitable */
	473	pci_read_config_byte(pdev, 0x42, &r);
	474	if ((r & 0x36) != 0x36)
	475	goto done;
	476	pci_read_config_byte(dev1, 0x52, &r);
	477	if (r & 0x80) /* IDEDIR disabled */
	478	ret = 1;
85cd7251	479	done:
669a5db4 JG	480	printk(KERN_WARNING "UDMA not supported in this configuration.\n");
	481	done_nomsg: /* Wrong chip revision */
	482	pci_dev_put(dev1);
	483	return ret;
	484	}
	485
	486	static int optidma_init_one(struct pci_dev dev, const struct pci_device_id id)
	487	{
	488	static struct ata_port_info info_82c700 = {
	489	.sht = &optidma_sht,
	490	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	491	.pio_mask = 0x1f,
	492	.mwdma_mask = 0x07,
	493	.port_ops = &optidma_port_ops
	494	};
	495	static struct ata_port_info info_82c700_udma = {
	496	.sht = &optidma_sht,
	497	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	498	.pio_mask = 0x1f,
	499	.mwdma_mask = 0x07,
	500	.udma_mask = 0x07,
	501	.port_ops = &optiplus_port_ops
	502	};
	503	static struct ata_port_info *port_info[2];
	504	struct ata_port_info *info = &info_82c700;
	505	static int printed_version;
	506
	507	if (!printed_version++)
	508	dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
	509
	510	/* Fixed location chipset magic */
	511	inw(0x1F1);
	512	inw(0x1F1);
	513	pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
85cd7251	514
669a5db4 JG	515	if (optiplus_with_udma(dev))
	516	info = &info_82c700_udma;
	517
	518	port_info[0] = port_info[1] = info;
	519	return ata_pci_init_one(dev, port_info, 2);
	520	}
	521
	522	static const struct pci_device_id optidma[] = {
2d2744fc JG	523	{ PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */
	524
	525	{ },
669a5db4 JG	526	};
	527
	528	static struct pci_driver optidma_pci_driver = {
2d2744fc	529	.name = DRV_NAME,
669a5db4 JG	530	.id_table = optidma,
669a5db4 JG	531	.probe = optidma_init_one,
30ced0f0	532	.remove = ata_pci_remove_one,
438ac6d5	533	#ifdef CONFIG_PM
30ced0f0 AC	534	.suspend = ata_pci_device_suspend,
30ced0f0 AC	535	.resume = ata_pci_device_resume,
438ac6d5	536	#endif
669a5db4 JG	537	};
	538
	539	static int __init optidma_init(void)
	540	{
	541	return pci_register_driver(&optidma_pci_driver);
	542	}
	543
669a5db4 JG	544	static void __exit optidma_exit(void)
	545	{
	546	pci_unregister_driver(&optidma_pci_driver);
	547	}
	548
669a5db4 JG	549	MODULE_AUTHOR("Alan Cox");
	550	MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
	551	MODULE_LICENSE("GPL");
	552	MODULE_DEVICE_TABLE(pci, optidma);
	553	MODULE_VERSION(DRV_VERSION);
	554
	555	module_init(optidma_init);
	556	module_exit(optidma_exit);