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669a5db4 JG |
1 | /* |
2 | * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Ported to libata by: | |
10 | * Albert Lee <albertcc@tw.ibm.com> IBM Corporation | |
11 | * | |
12 | * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> | |
13 | * Portions Copyright (C) 1999 Promise Technology, Inc. | |
14 | * | |
15 | * Author: Frank Tiernan (frankt@promise.com) | |
16 | * Released under terms of General Public License | |
17 | * | |
18 | * | |
19 | * libata documentation is available via 'make {ps|pdf}docs', | |
20 | * as Documentation/DocBook/libata.* | |
21 | * | |
22 | * Hardware information only available under NDA. | |
23 | * | |
24 | */ | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/blkdev.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/device.h> | |
32 | #include <scsi/scsi.h> | |
33 | #include <scsi/scsi_host.h> | |
34 | #include <scsi/scsi_cmnd.h> | |
35 | #include <linux/libata.h> | |
669a5db4 JG |
36 | |
37 | #define DRV_NAME "pata_pdc2027x" | |
c961922b | 38 | #define DRV_VERSION "0.74-ac5" |
669a5db4 JG |
39 | #undef PDC_DEBUG |
40 | ||
41 | #ifdef PDC_DEBUG | |
42 | #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) | |
43 | #else | |
44 | #define PDPRINTK(fmt, args...) | |
45 | #endif | |
46 | ||
47 | enum { | |
48 | PDC_UDMA_100 = 0, | |
49 | PDC_UDMA_133 = 1, | |
50 | ||
51 | PDC_100_MHZ = 100000000, | |
52 | PDC_133_MHZ = 133333333, | |
53 | ||
54 | PDC_SYS_CTL = 0x1100, | |
55 | PDC_ATA_CTL = 0x1104, | |
56 | PDC_GLOBAL_CTL = 0x1108, | |
57 | PDC_CTCR0 = 0x110C, | |
58 | PDC_CTCR1 = 0x1110, | |
59 | PDC_BYTE_COUNT = 0x1120, | |
60 | PDC_PLL_CTL = 0x1202, | |
61 | }; | |
62 | ||
63 | static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); | |
669a5db4 JG |
64 | static void pdc2027x_error_handler(struct ata_port *ap); |
65 | static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev); | |
66 | static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
67 | static void pdc2027x_post_set_mode(struct ata_port *ap); | |
68 | static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc); | |
69 | ||
70 | /* | |
71 | * ATA Timing Tables based on 133MHz controller clock. | |
72 | * These tables are only used when the controller is in 133MHz clock. | |
73 | * If the controller is in 100MHz clock, the ASIC hardware will | |
74 | * set the timing registers automatically when "set feature" command | |
75 | * is issued to the device. However, if the controller clock is 133MHz, | |
76 | * the following tables must be used. | |
77 | */ | |
78 | static struct pdc2027x_pio_timing { | |
79 | u8 value0, value1, value2; | |
80 | } pdc2027x_pio_timing_tbl [] = { | |
81 | { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ | |
82 | { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */ | |
83 | { 0x23, 0x26, 0x64 }, /* PIO mode 2 */ | |
84 | { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */ | |
85 | { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ | |
86 | }; | |
87 | ||
88 | static struct pdc2027x_mdma_timing { | |
89 | u8 value0, value1; | |
90 | } pdc2027x_mdma_timing_tbl [] = { | |
91 | { 0xdf, 0x5f }, /* MDMA mode 0 */ | |
92 | { 0x6b, 0x27 }, /* MDMA mode 1 */ | |
93 | { 0x69, 0x25 }, /* MDMA mode 2 */ | |
94 | }; | |
95 | ||
96 | static struct pdc2027x_udma_timing { | |
97 | u8 value0, value1, value2; | |
98 | } pdc2027x_udma_timing_tbl [] = { | |
99 | { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ | |
100 | { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */ | |
101 | { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */ | |
102 | { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */ | |
103 | { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */ | |
104 | { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */ | |
105 | { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ | |
106 | }; | |
107 | ||
108 | static const struct pci_device_id pdc2027x_pci_tbl[] = { | |
2d2744fc JG |
109 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 }, |
110 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 }, | |
111 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 }, | |
112 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 }, | |
113 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 }, | |
114 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 }, | |
115 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 }, | |
116 | ||
669a5db4 JG |
117 | { } /* terminate list */ |
118 | }; | |
119 | ||
120 | static struct pci_driver pdc2027x_pci_driver = { | |
121 | .name = DRV_NAME, | |
122 | .id_table = pdc2027x_pci_tbl, | |
123 | .probe = pdc2027x_init_one, | |
24dc5f33 | 124 | .remove = ata_pci_remove_one, |
669a5db4 JG |
125 | }; |
126 | ||
127 | static struct scsi_host_template pdc2027x_sht = { | |
128 | .module = THIS_MODULE, | |
129 | .name = DRV_NAME, | |
130 | .ioctl = ata_scsi_ioctl, | |
131 | .queuecommand = ata_scsi_queuecmd, | |
132 | .can_queue = ATA_DEF_QUEUE, | |
133 | .this_id = ATA_SHT_THIS_ID, | |
134 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
135 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
136 | .emulated = ATA_SHT_EMULATED, | |
137 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
138 | .proc_name = DRV_NAME, | |
139 | .dma_boundary = ATA_DMA_BOUNDARY, | |
140 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 141 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
142 | .bios_param = ata_std_bios_param, |
143 | }; | |
144 | ||
145 | static struct ata_port_operations pdc2027x_pata100_ops = { | |
146 | .port_disable = ata_port_disable, | |
147 | ||
148 | .tf_load = ata_tf_load, | |
149 | .tf_read = ata_tf_read, | |
150 | .check_status = ata_check_status, | |
151 | .exec_command = ata_exec_command, | |
152 | .dev_select = ata_std_dev_select, | |
153 | ||
154 | .check_atapi_dma = pdc2027x_check_atapi_dma, | |
155 | .bmdma_setup = ata_bmdma_setup, | |
156 | .bmdma_start = ata_bmdma_start, | |
157 | .bmdma_stop = ata_bmdma_stop, | |
158 | .bmdma_status = ata_bmdma_status, | |
159 | .qc_prep = ata_qc_prep, | |
160 | .qc_issue = ata_qc_issue_prot, | |
161 | .data_xfer = ata_mmio_data_xfer, | |
162 | ||
163 | .freeze = ata_bmdma_freeze, | |
164 | .thaw = ata_bmdma_thaw, | |
165 | .error_handler = pdc2027x_error_handler, | |
166 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
167 | ||
168 | .irq_handler = ata_interrupt, | |
169 | .irq_clear = ata_bmdma_irq_clear, | |
170 | ||
171 | .port_start = ata_port_start, | |
669a5db4 JG |
172 | }; |
173 | ||
174 | static struct ata_port_operations pdc2027x_pata133_ops = { | |
175 | .port_disable = ata_port_disable, | |
176 | .set_piomode = pdc2027x_set_piomode, | |
177 | .set_dmamode = pdc2027x_set_dmamode, | |
178 | .post_set_mode = pdc2027x_post_set_mode, | |
179 | ||
180 | .tf_load = ata_tf_load, | |
181 | .tf_read = ata_tf_read, | |
182 | .check_status = ata_check_status, | |
183 | .exec_command = ata_exec_command, | |
184 | .dev_select = ata_std_dev_select, | |
185 | ||
186 | .check_atapi_dma = pdc2027x_check_atapi_dma, | |
187 | .bmdma_setup = ata_bmdma_setup, | |
188 | .bmdma_start = ata_bmdma_start, | |
189 | .bmdma_stop = ata_bmdma_stop, | |
190 | .bmdma_status = ata_bmdma_status, | |
191 | .qc_prep = ata_qc_prep, | |
192 | .qc_issue = ata_qc_issue_prot, | |
193 | .data_xfer = ata_mmio_data_xfer, | |
194 | ||
195 | .freeze = ata_bmdma_freeze, | |
196 | .thaw = ata_bmdma_thaw, | |
197 | .error_handler = pdc2027x_error_handler, | |
198 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
199 | ||
200 | .irq_handler = ata_interrupt, | |
201 | .irq_clear = ata_bmdma_irq_clear, | |
202 | ||
203 | .port_start = ata_port_start, | |
669a5db4 JG |
204 | }; |
205 | ||
206 | static struct ata_port_info pdc2027x_port_info[] = { | |
207 | /* PDC_UDMA_100 */ | |
208 | { | |
209 | .sht = &pdc2027x_sht, | |
210 | .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS | | |
211 | ATA_FLAG_MMIO, | |
212 | .pio_mask = 0x1f, /* pio0-4 */ | |
213 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
214 | .udma_mask = ATA_UDMA5, /* udma0-5 */ | |
215 | .port_ops = &pdc2027x_pata100_ops, | |
216 | }, | |
217 | /* PDC_UDMA_133 */ | |
218 | { | |
219 | .sht = &pdc2027x_sht, | |
220 | .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS | | |
221 | ATA_FLAG_MMIO, | |
222 | .pio_mask = 0x1f, /* pio0-4 */ | |
223 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
224 | .udma_mask = ATA_UDMA6, /* udma0-6 */ | |
225 | .port_ops = &pdc2027x_pata133_ops, | |
226 | }, | |
227 | }; | |
228 | ||
229 | MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee"); | |
230 | MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277"); | |
231 | MODULE_LICENSE("GPL"); | |
232 | MODULE_VERSION(DRV_VERSION); | |
233 | MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl); | |
234 | ||
235 | /** | |
236 | * port_mmio - Get the MMIO address of PDC2027x extended registers | |
237 | * @ap: Port | |
238 | * @offset: offset from mmio base | |
239 | */ | |
7c250413 | 240 | static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) |
669a5db4 JG |
241 | { |
242 | return ap->host->mmio_base + ap->port_no * 0x100 + offset; | |
243 | } | |
244 | ||
245 | /** | |
246 | * dev_mmio - Get the MMIO address of PDC2027x extended registers | |
247 | * @ap: Port | |
248 | * @adev: device | |
249 | * @offset: offset from mmio base | |
250 | */ | |
7c250413 | 251 | static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset) |
669a5db4 JG |
252 | { |
253 | u8 adj = (adev->devno) ? 0x08 : 0x00; | |
254 | return port_mmio(ap, offset) + adj; | |
255 | } | |
256 | ||
257 | /** | |
258 | * pdc2027x_pata_cbl_detect - Probe host controller cable detect info | |
259 | * @ap: Port for which cable detect info is desired | |
260 | * | |
261 | * Read 80c cable indicator from Promise extended register. | |
262 | * This register is latched when the system is reset. | |
263 | * | |
264 | * LOCKING: | |
265 | * None (inherited from caller). | |
266 | */ | |
267 | static void pdc2027x_cbl_detect(struct ata_port *ap) | |
268 | { | |
269 | u32 cgcr; | |
270 | ||
271 | /* check cable detect results */ | |
272 | cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL)); | |
273 | if (cgcr & (1 << 26)) | |
274 | goto cbl40; | |
275 | ||
276 | PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no); | |
277 | ||
278 | ap->cbl = ATA_CBL_PATA80; | |
279 | return; | |
280 | ||
281 | cbl40: | |
282 | printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no); | |
283 | ap->cbl = ATA_CBL_PATA40; | |
284 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
285 | } | |
286 | ||
287 | /** | |
288 | * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled. | |
289 | * @ap: Port to check | |
290 | */ | |
291 | static inline int pdc2027x_port_enabled(struct ata_port *ap) | |
292 | { | |
293 | return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02; | |
294 | } | |
295 | ||
296 | /** | |
297 | * pdc2027x_prereset - prereset for PATA host controller | |
298 | * @ap: Target port | |
299 | * | |
300 | * Probeinit including cable detection. | |
301 | * | |
302 | * LOCKING: | |
303 | * None (inherited from caller). | |
304 | */ | |
305 | ||
306 | static int pdc2027x_prereset(struct ata_port *ap) | |
307 | { | |
308 | /* Check whether port enabled */ | |
c961922b AC |
309 | if (!pdc2027x_port_enabled(ap)) |
310 | return -ENOENT; | |
669a5db4 JG |
311 | pdc2027x_cbl_detect(ap); |
312 | return ata_std_prereset(ap); | |
313 | } | |
314 | ||
315 | /** | |
316 | * pdc2027x_error_handler - Perform reset on PATA port and classify | |
317 | * @ap: Port to reset | |
318 | * | |
319 | * Reset PATA phy and classify attached devices. | |
320 | * | |
321 | * LOCKING: | |
322 | * None (inherited from caller). | |
323 | */ | |
324 | ||
325 | static void pdc2027x_error_handler(struct ata_port *ap) | |
326 | { | |
327 | ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset); | |
328 | } | |
329 | ||
330 | /** | |
331 | * pdc2027x_set_piomode - Initialize host controller PATA PIO timings | |
332 | * @ap: Port to configure | |
333 | * @adev: um | |
334 | * @pio: PIO mode, 0 - 4 | |
335 | * | |
336 | * Set PIO mode for device. | |
337 | * | |
338 | * LOCKING: | |
339 | * None (inherited from caller). | |
340 | */ | |
341 | ||
342 | static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
343 | { | |
344 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
345 | u32 ctcr0, ctcr1; | |
346 | ||
347 | PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode); | |
348 | ||
349 | /* Sanity check */ | |
350 | if (pio > 4) { | |
351 | printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio); | |
352 | return; | |
353 | ||
354 | } | |
355 | ||
356 | /* Set the PIO timing registers using value table for 133MHz */ | |
357 | PDPRINTK("Set pio regs... \n"); | |
358 | ||
359 | ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0)); | |
360 | ctcr0 &= 0xffff0000; | |
361 | ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 | | |
362 | (pdc2027x_pio_timing_tbl[pio].value1 << 8); | |
363 | writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); | |
364 | ||
365 | ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1)); | |
366 | ctcr1 &= 0x00ffffff; | |
367 | ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24); | |
368 | writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); | |
369 | ||
370 | PDPRINTK("Set pio regs done\n"); | |
371 | ||
372 | PDPRINTK("Set to pio mode[%u] \n", pio); | |
373 | } | |
374 | ||
375 | /** | |
376 | * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings | |
377 | * @ap: Port to configure | |
378 | * @adev: um | |
379 | * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6 | |
380 | * | |
381 | * Set UDMA mode for device. | |
382 | * | |
383 | * LOCKING: | |
384 | * None (inherited from caller). | |
385 | */ | |
386 | static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
387 | { | |
388 | unsigned int dma_mode = adev->dma_mode; | |
389 | u32 ctcr0, ctcr1; | |
390 | ||
391 | if ((dma_mode >= XFER_UDMA_0) && | |
392 | (dma_mode <= XFER_UDMA_6)) { | |
393 | /* Set the UDMA timing registers with value table for 133MHz */ | |
394 | unsigned int udma_mode = dma_mode & 0x07; | |
395 | ||
396 | if (dma_mode == XFER_UDMA_2) { | |
397 | /* | |
398 | * Turn off tHOLD. | |
399 | * If tHOLD is '1', the hardware will add half clock for data hold time. | |
400 | * This code segment seems to be no effect. tHOLD will be overwritten below. | |
401 | */ | |
402 | ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1)); | |
403 | writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1)); | |
404 | } | |
405 | ||
406 | PDPRINTK("Set udma regs... \n"); | |
407 | ||
408 | ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1)); | |
409 | ctcr1 &= 0xff000000; | |
410 | ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 | | |
411 | (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) | | |
412 | (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16); | |
413 | writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); | |
414 | ||
415 | PDPRINTK("Set udma regs done\n"); | |
416 | ||
417 | PDPRINTK("Set to udma mode[%u] \n", udma_mode); | |
418 | ||
419 | } else if ((dma_mode >= XFER_MW_DMA_0) && | |
420 | (dma_mode <= XFER_MW_DMA_2)) { | |
421 | /* Set the MDMA timing registers with value table for 133MHz */ | |
422 | unsigned int mdma_mode = dma_mode & 0x07; | |
423 | ||
424 | PDPRINTK("Set mdma regs... \n"); | |
425 | ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0)); | |
426 | ||
427 | ctcr0 &= 0x0000ffff; | |
428 | ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) | | |
429 | (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24); | |
430 | ||
431 | writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); | |
432 | PDPRINTK("Set mdma regs done\n"); | |
433 | ||
434 | PDPRINTK("Set to mdma mode[%u] \n", mdma_mode); | |
435 | } else { | |
436 | printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode); | |
437 | } | |
438 | } | |
439 | ||
440 | /** | |
441 | * pdc2027x_post_set_mode - Set the timing registers back to correct values. | |
442 | * @ap: Port to configure | |
443 | * | |
444 | * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers | |
445 | * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL. | |
446 | * This function overwrites the possibly incorrect values set by the hardware to be correct. | |
447 | */ | |
448 | static void pdc2027x_post_set_mode(struct ata_port *ap) | |
449 | { | |
450 | int i; | |
451 | ||
452 | for (i = 0; i < ATA_MAX_DEVICES; i++) { | |
453 | struct ata_device *dev = &ap->device[i]; | |
454 | ||
455 | if (ata_dev_enabled(dev)) { | |
456 | ||
457 | pdc2027x_set_piomode(ap, dev); | |
458 | ||
459 | /* | |
460 | * Enable prefetch if the device support PIO only. | |
461 | */ | |
462 | if (dev->xfer_shift == ATA_SHIFT_PIO) { | |
463 | u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1)); | |
464 | ctcr1 |= (1 << 25); | |
465 | writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1)); | |
466 | ||
467 | PDPRINTK("Turn on prefetch\n"); | |
468 | } else { | |
469 | pdc2027x_set_dmamode(ap, dev); | |
470 | } | |
471 | } | |
472 | } | |
473 | } | |
474 | ||
475 | /** | |
476 | * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command | |
477 | * @qc: Metadata associated with taskfile to check | |
478 | * | |
479 | * LOCKING: | |
480 | * None (inherited from caller). | |
481 | * | |
482 | * RETURNS: 0 when ATAPI DMA can be used | |
483 | * 1 otherwise | |
484 | */ | |
485 | static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc) | |
486 | { | |
487 | struct scsi_cmnd *cmd = qc->scsicmd; | |
488 | u8 *scsicmd = cmd->cmnd; | |
489 | int rc = 1; /* atapi dma off by default */ | |
490 | ||
491 | /* | |
492 | * This workaround is from Promise's GPL driver. | |
493 | * If ATAPI DMA is used for commands not in the | |
494 | * following white list, say MODE_SENSE and REQUEST_SENSE, | |
495 | * pdc2027x might hit the irq lost problem. | |
496 | */ | |
497 | switch (scsicmd[0]) { | |
498 | case READ_10: | |
499 | case WRITE_10: | |
500 | case READ_12: | |
501 | case WRITE_12: | |
502 | case READ_6: | |
503 | case WRITE_6: | |
504 | case 0xad: /* READ_DVD_STRUCTURE */ | |
505 | case 0xbe: /* READ_CD */ | |
506 | /* ATAPI DMA is ok */ | |
507 | rc = 0; | |
508 | break; | |
509 | default: | |
510 | ; | |
511 | } | |
512 | ||
513 | return rc; | |
514 | } | |
515 | ||
516 | /** | |
517 | * pdc_read_counter - Read the ctr counter | |
518 | * @probe_ent: for the port address | |
519 | */ | |
520 | ||
521 | static long pdc_read_counter(struct ata_probe_ent *probe_ent) | |
522 | { | |
523 | long counter; | |
524 | int retry = 1; | |
525 | u32 bccrl, bccrh, bccrlv, bccrhv; | |
526 | ||
527 | retry: | |
528 | bccrl = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff; | |
529 | bccrh = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff; | |
530 | rmb(); | |
531 | ||
532 | /* Read the counter values again for verification */ | |
533 | bccrlv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff; | |
534 | bccrhv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff; | |
535 | rmb(); | |
536 | ||
537 | counter = (bccrh << 15) | bccrl; | |
538 | ||
539 | PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl); | |
540 | PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv); | |
541 | ||
542 | /* | |
543 | * The 30-bit decreasing counter are read by 2 pieces. | |
544 | * Incorrect value may be read when both bccrh and bccrl are changing. | |
545 | * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read. | |
546 | */ | |
547 | if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) { | |
548 | retry--; | |
549 | PDPRINTK("rereading counter\n"); | |
550 | goto retry; | |
551 | } | |
552 | ||
553 | return counter; | |
554 | } | |
555 | ||
556 | /** | |
557 | * adjust_pll - Adjust the PLL input clock in Hz. | |
558 | * | |
559 | * @pdc_controller: controller specific information | |
560 | * @probe_ent: For the port address | |
561 | * @pll_clock: The input of PLL in HZ | |
562 | */ | |
563 | static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx) | |
564 | { | |
565 | ||
566 | u16 pll_ctl; | |
567 | long pll_clock_khz = pll_clock / 1000; | |
568 | long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ; | |
569 | long ratio = pout_required / pll_clock_khz; | |
570 | int F, R; | |
571 | ||
572 | /* Sanity check */ | |
573 | if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) { | |
574 | printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz); | |
575 | return; | |
576 | } | |
577 | ||
578 | #ifdef PDC_DEBUG | |
579 | PDPRINTK("pout_required is %ld\n", pout_required); | |
580 | ||
581 | /* Show the current clock value of PLL control register | |
582 | * (maybe already configured by the firmware) | |
583 | */ | |
584 | pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL); | |
585 | ||
586 | PDPRINTK("pll_ctl[%X]\n", pll_ctl); | |
587 | #endif | |
588 | ||
589 | /* | |
590 | * Calculate the ratio of F, R and OD | |
591 | * POUT = (F + 2) / (( R + 2) * NO) | |
592 | */ | |
593 | if (ratio < 8600L) { /* 8.6x */ | |
594 | /* Using NO = 0x01, R = 0x0D */ | |
595 | R = 0x0d; | |
596 | } else if (ratio < 12900L) { /* 12.9x */ | |
597 | /* Using NO = 0x01, R = 0x08 */ | |
598 | R = 0x08; | |
599 | } else if (ratio < 16100L) { /* 16.1x */ | |
600 | /* Using NO = 0x01, R = 0x06 */ | |
601 | R = 0x06; | |
602 | } else if (ratio < 64000L) { /* 64x */ | |
603 | R = 0x00; | |
604 | } else { | |
605 | /* Invalid ratio */ | |
606 | printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio); | |
607 | return; | |
608 | } | |
609 | ||
610 | F = (ratio * (R+2)) / 1000 - 2; | |
611 | ||
612 | if (unlikely(F < 0 || F > 127)) { | |
613 | /* Invalid F */ | |
614 | printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F); | |
615 | return; | |
616 | } | |
617 | ||
618 | PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio); | |
619 | ||
620 | pll_ctl = (R << 8) | F; | |
621 | ||
622 | PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl); | |
623 | ||
624 | writew(pll_ctl, probe_ent->mmio_base + PDC_PLL_CTL); | |
625 | readw(probe_ent->mmio_base + PDC_PLL_CTL); /* flush */ | |
626 | ||
627 | /* Wait the PLL circuit to be stable */ | |
628 | mdelay(30); | |
629 | ||
630 | #ifdef PDC_DEBUG | |
631 | /* | |
632 | * Show the current clock value of PLL control register | |
633 | * (maybe configured by the firmware) | |
634 | */ | |
635 | pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL); | |
636 | ||
637 | PDPRINTK("pll_ctl[%X]\n", pll_ctl); | |
638 | #endif | |
639 | ||
640 | return; | |
641 | } | |
642 | ||
643 | /** | |
644 | * detect_pll_input_clock - Detect the PLL input clock in Hz. | |
645 | * @probe_ent: for the port address | |
646 | * Ex. 16949000 on 33MHz PCI bus for pdc20275. | |
647 | * Half of the PCI clock. | |
648 | */ | |
649 | static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent) | |
650 | { | |
651 | u32 scr; | |
652 | long start_count, end_count; | |
653 | long pll_clock; | |
654 | ||
655 | /* Read current counter value */ | |
656 | start_count = pdc_read_counter(probe_ent); | |
657 | ||
658 | /* Start the test mode */ | |
659 | scr = readl(probe_ent->mmio_base + PDC_SYS_CTL); | |
660 | PDPRINTK("scr[%X]\n", scr); | |
661 | writel(scr | (0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL); | |
662 | readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */ | |
663 | ||
664 | /* Let the counter run for 100 ms. */ | |
665 | mdelay(100); | |
666 | ||
667 | /* Read the counter values again */ | |
668 | end_count = pdc_read_counter(probe_ent); | |
669 | ||
670 | /* Stop the test mode */ | |
671 | scr = readl(probe_ent->mmio_base + PDC_SYS_CTL); | |
672 | PDPRINTK("scr[%X]\n", scr); | |
673 | writel(scr & ~(0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL); | |
674 | readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */ | |
675 | ||
676 | /* calculate the input clock in Hz */ | |
677 | pll_clock = (start_count - end_count) * 10; | |
678 | ||
679 | PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count); | |
680 | PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock); | |
681 | ||
682 | return pll_clock; | |
683 | } | |
684 | ||
685 | /** | |
686 | * pdc_hardware_init - Initialize the hardware. | |
687 | * @pdev: instance of pci_dev found | |
688 | * @pdc_controller: controller specific information | |
689 | * @pe: for the port address | |
690 | */ | |
691 | static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, unsigned int board_idx) | |
692 | { | |
693 | long pll_clock; | |
694 | ||
695 | /* | |
696 | * Detect PLL input clock rate. | |
697 | * On some system, where PCI bus is running at non-standard clock rate. | |
698 | * Ex. 25MHz or 40MHz, we have to adjust the cycle_time. | |
699 | * The pdc20275 controller employs PLL circuit to help correct timing registers setting. | |
700 | */ | |
701 | pll_clock = pdc_detect_pll_input_clock(pe); | |
702 | ||
703 | if (pll_clock < 0) /* counter overflow? Try again. */ | |
704 | pll_clock = pdc_detect_pll_input_clock(pe); | |
705 | ||
706 | dev_printk(KERN_INFO, &pdev->dev, "PLL input clock %ld kHz\n", pll_clock/1000); | |
707 | ||
708 | /* Adjust PLL control register */ | |
709 | pdc_adjust_pll(pe, pll_clock, board_idx); | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
714 | /** | |
715 | * pdc_ata_setup_port - setup the mmio address | |
716 | * @port: ata ioports to setup | |
717 | * @base: base address | |
718 | */ | |
719 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
720 | { | |
721 | port->cmd_addr = | |
722 | port->data_addr = base; | |
723 | port->feature_addr = | |
724 | port->error_addr = base + 0x05; | |
725 | port->nsect_addr = base + 0x0a; | |
726 | port->lbal_addr = base + 0x0f; | |
727 | port->lbam_addr = base + 0x10; | |
728 | port->lbah_addr = base + 0x15; | |
729 | port->device_addr = base + 0x1a; | |
730 | port->command_addr = | |
731 | port->status_addr = base + 0x1f; | |
732 | port->altstatus_addr = | |
733 | port->ctl_addr = base + 0x81a; | |
734 | } | |
735 | ||
736 | /** | |
737 | * pdc2027x_init_one - PCI probe function | |
738 | * Called when an instance of PCI adapter is inserted. | |
739 | * This function checks whether the hardware is supported, | |
740 | * initialize hardware and register an instance of ata_host to | |
741 | * libata by providing struct ata_probe_ent and ata_device_add(). | |
742 | * (implements struct pci_driver.probe() ) | |
743 | * | |
744 | * @pdev: instance of pci_dev found | |
745 | * @ent: matching entry in the id_tbl[] | |
746 | */ | |
747 | static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
748 | { | |
749 | static int printed_version; | |
750 | unsigned int board_idx = (unsigned int) ent->driver_data; | |
751 | ||
24dc5f33 | 752 | struct ata_probe_ent *probe_ent; |
669a5db4 | 753 | unsigned long base; |
7c250413 | 754 | void __iomem *mmio_base; |
669a5db4 JG |
755 | int rc; |
756 | ||
757 | if (!printed_version++) | |
758 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
759 | ||
24dc5f33 | 760 | rc = pcim_enable_device(pdev); |
669a5db4 JG |
761 | if (rc) |
762 | return rc; | |
763 | ||
764 | rc = pci_request_regions(pdev, DRV_NAME); | |
765 | if (rc) | |
24dc5f33 | 766 | return rc; |
669a5db4 JG |
767 | |
768 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
769 | if (rc) | |
24dc5f33 | 770 | return rc; |
669a5db4 JG |
771 | |
772 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
773 | if (rc) | |
24dc5f33 | 774 | return rc; |
669a5db4 JG |
775 | |
776 | /* Prepare the probe entry */ | |
24dc5f33 TH |
777 | probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL); |
778 | if (probe_ent == NULL) | |
779 | return -ENOMEM; | |
669a5db4 JG |
780 | |
781 | probe_ent->dev = pci_dev_to_dev(pdev); | |
782 | INIT_LIST_HEAD(&probe_ent->node); | |
783 | ||
24dc5f33 TH |
784 | mmio_base = pcim_iomap(pdev, 5, 0); |
785 | if (!mmio_base) | |
786 | return -ENOMEM; | |
669a5db4 JG |
787 | |
788 | base = (unsigned long) mmio_base; | |
789 | ||
790 | probe_ent->sht = pdc2027x_port_info[board_idx].sht; | |
791 | probe_ent->port_flags = pdc2027x_port_info[board_idx].flags; | |
792 | probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask; | |
793 | probe_ent->mwdma_mask = pdc2027x_port_info[board_idx].mwdma_mask; | |
794 | probe_ent->udma_mask = pdc2027x_port_info[board_idx].udma_mask; | |
795 | probe_ent->port_ops = pdc2027x_port_info[board_idx].port_ops; | |
796 | ||
797 | probe_ent->irq = pdev->irq; | |
798 | probe_ent->irq_flags = SA_SHIRQ; | |
799 | probe_ent->mmio_base = mmio_base; | |
800 | ||
801 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x17c0); | |
802 | probe_ent->port[0].bmdma_addr = base + 0x1000; | |
803 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x15c0); | |
804 | probe_ent->port[1].bmdma_addr = base + 0x1008; | |
805 | ||
806 | probe_ent->n_ports = 2; | |
807 | ||
808 | pci_set_master(pdev); | |
809 | //pci_enable_intx(pdev); | |
810 | ||
811 | /* initialize adapter */ | |
812 | if (pdc_hardware_init(pdev, probe_ent, board_idx) != 0) | |
24dc5f33 | 813 | return -EIO; |
669a5db4 | 814 | |
24dc5f33 TH |
815 | if (!ata_device_add(probe_ent)) |
816 | return -ENODEV; | |
669a5db4 | 817 | |
24dc5f33 | 818 | devm_kfree(&pdev->dev, probe_ent); |
669a5db4 | 819 | return 0; |
669a5db4 JG |
820 | } |
821 | ||
822 | /** | |
823 | * pdc2027x_init - Called after this module is loaded into the kernel. | |
824 | */ | |
825 | static int __init pdc2027x_init(void) | |
826 | { | |
72dc6794 | 827 | return pci_register_driver(&pdc2027x_pci_driver); |
669a5db4 JG |
828 | } |
829 | ||
830 | /** | |
831 | * pdc2027x_exit - Called before this module unloaded from the kernel | |
832 | */ | |
833 | static void __exit pdc2027x_exit(void) | |
834 | { | |
835 | pci_unregister_driver(&pdc2027x_pci_driver); | |
836 | } | |
837 | ||
838 | module_init(pdc2027x_init); | |
839 | module_exit(pdc2027x_exit); |