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669a5db4
JG		 1/*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 *
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
17 *
18 *
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under NDA.
23 *
24 */
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi.h>
33#include <scsi/scsi_host.h>
34#include <scsi/scsi_cmnd.h>
35#include <linux/libata.h>
669a5db4
JG		 36
37#define DRV_NAME "pata_pdc2027x"
2a3103ce 38#define DRV_VERSION "1.0"
669a5db4
JG		 39#undef PDC_DEBUG
40
41#ifdef PDC_DEBUG
42#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
43#else
44#define PDPRINTK(fmt, args...)
45#endif
46
47enum {
0d5ff566
TH		 48 PDC_MMIO_BAR = 5,
49
669a5db4
JG		 50 PDC_UDMA_100 = 0,
51 PDC_UDMA_133 = 1,
52
53 PDC_100_MHZ = 100000000,
54 PDC_133_MHZ = 133333333,
55
56 PDC_SYS_CTL = 0x1100,
57 PDC_ATA_CTL = 0x1104,
58 PDC_GLOBAL_CTL = 0x1108,
59 PDC_CTCR0 = 0x110C,
60 PDC_CTCR1 = 0x1110,
61 PDC_BYTE_COUNT = 0x1120,
62 PDC_PLL_CTL = 0x1202,
63};
64
65static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
669a5db4
JG		 66static void pdc2027x_error_handler(struct ata_port *ap);
67static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
669a5db4 69static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
9bedb799
AC		 70static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
71static int pdc2027x_cable_detect(struct ata_port *ap);
72static int pdc2027x_set_mode(struct ata_port *ap, struct ata_device **r_failed);
669a5db4
JG		 73
74/*
75 * ATA Timing Tables based on 133MHz controller clock.
76 * These tables are only used when the controller is in 133MHz clock.
77 * If the controller is in 100MHz clock, the ASIC hardware will
78 * set the timing registers automatically when "set feature" command
79 * is issued to the device. However, if the controller clock is 133MHz,
80 * the following tables must be used.
81 */
82static struct pdc2027x_pio_timing {
83 u8 value0, value1, value2;
84} pdc2027x_pio_timing_tbl [] = {
85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
90};
91
92static struct pdc2027x_mdma_timing {
93 u8 value0, value1;
94} pdc2027x_mdma_timing_tbl [] = {
95 { 0xdf, 0x5f }, /* MDMA mode 0 */
96 { 0x6b, 0x27 }, /* MDMA mode 1 */
97 { 0x69, 0x25 }, /* MDMA mode 2 */
98};
99
100static struct pdc2027x_udma_timing {
101 u8 value0, value1, value2;
102} pdc2027x_udma_timing_tbl [] = {
103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
110};
111
112static const struct pci_device_id pdc2027x_pci_tbl[] = {
2d2744fc
JG		 113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
120
669a5db4
JG		 121 { } /* terminate list */
122};
123
124static struct pci_driver pdc2027x_pci_driver = {
125 .name = DRV_NAME,
126 .id_table = pdc2027x_pci_tbl,
127 .probe = pdc2027x_init_one,
24dc5f33 128 .remove = ata_pci_remove_one,
669a5db4
JG		 129};
130
131static struct scsi_host_template pdc2027x_sht = {
132 .module = THIS_MODULE,
133 .name = DRV_NAME,
134 .ioctl = ata_scsi_ioctl,
135 .queuecommand = ata_scsi_queuecmd,
136 .can_queue = ATA_DEF_QUEUE,
137 .this_id = ATA_SHT_THIS_ID,
138 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 139 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
140 .emulated = ATA_SHT_EMULATED,
141 .use_clustering = ATA_SHT_USE_CLUSTERING,
142 .proc_name = DRV_NAME,
143 .dma_boundary = ATA_DMA_BOUNDARY,
144 .slave_configure = ata_scsi_slave_config,
afdfe899 145 .slave_destroy = ata_scsi_slave_destroy,
669a5db4
JG		 146 .bios_param = ata_std_bios_param,
147};
148
149static struct ata_port_operations pdc2027x_pata100_ops = {
150 .port_disable = ata_port_disable,
9bedb799 151 .mode_filter = ata_pci_default_filter,
669a5db4
JG		 152
153 .tf_load = ata_tf_load,
154 .tf_read = ata_tf_read,
155 .check_status = ata_check_status,
156 .exec_command = ata_exec_command,
157 .dev_select = ata_std_dev_select,
158
159 .check_atapi_dma = pdc2027x_check_atapi_dma,
160 .bmdma_setup = ata_bmdma_setup,
161 .bmdma_start = ata_bmdma_start,
162 .bmdma_stop = ata_bmdma_stop,
163 .bmdma_status = ata_bmdma_status,
164 .qc_prep = ata_qc_prep,
165 .qc_issue = ata_qc_issue_prot,
0d5ff566 166 .data_xfer = ata_data_xfer,
669a5db4
JG		 167
168 .freeze = ata_bmdma_freeze,
169 .thaw = ata_bmdma_thaw,
170 .error_handler = pdc2027x_error_handler,
171 .post_internal_cmd = ata_bmdma_post_internal_cmd,
9bedb799 172 .cable_detect = pdc2027x_cable_detect,
669a5db4 173
669a5db4 174 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 175 .irq_on = ata_irq_on,
176 .irq_ack = ata_irq_ack,
669a5db4
JG		 177
178 .port_start = ata_port_start,
669a5db4
JG		 179};
180
181static struct ata_port_operations pdc2027x_pata133_ops = {
182 .port_disable = ata_port_disable,
183 .set_piomode = pdc2027x_set_piomode,
184 .set_dmamode = pdc2027x_set_dmamode,
9bedb799
AC		 185 .set_mode = pdc2027x_set_mode,
186 .mode_filter = pdc2027x_mode_filter,
669a5db4
JG		 187
188 .tf_load = ata_tf_load,
189 .tf_read = ata_tf_read,
190 .check_status = ata_check_status,
191 .exec_command = ata_exec_command,
192 .dev_select = ata_std_dev_select,
193
194 .check_atapi_dma = pdc2027x_check_atapi_dma,
195 .bmdma_setup = ata_bmdma_setup,
196 .bmdma_start = ata_bmdma_start,
197 .bmdma_stop = ata_bmdma_stop,
198 .bmdma_status = ata_bmdma_status,
199 .qc_prep = ata_qc_prep,
200 .qc_issue = ata_qc_issue_prot,
0d5ff566 201 .data_xfer = ata_data_xfer,
669a5db4
JG		 202
203 .freeze = ata_bmdma_freeze,
204 .thaw = ata_bmdma_thaw,
205 .error_handler = pdc2027x_error_handler,
206 .post_internal_cmd = ata_bmdma_post_internal_cmd,
9bedb799 207 .cable_detect = pdc2027x_cable_detect,
669a5db4 208
669a5db4 209 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 210 .irq_on = ata_irq_on,
211 .irq_ack = ata_irq_ack,
669a5db4
JG		 212
213 .port_start = ata_port_start,
669a5db4
JG		 214};
215
216static struct ata_port_info pdc2027x_port_info[] = {
217 /* PDC_UDMA_100 */
218 {
669a5db4
JG		 219 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
220 ATA_FLAG_MMIO,
221 .pio_mask = 0x1f, /* pio0-4 */
222 .mwdma_mask = 0x07, /* mwdma0-2 */
223 .udma_mask = ATA_UDMA5, /* udma0-5 */
224 .port_ops = &pdc2027x_pata100_ops,
225 },
226 /* PDC_UDMA_133 */
227 {
669a5db4
JG		 228 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
229 ATA_FLAG_MMIO,
230 .pio_mask = 0x1f, /* pio0-4 */
231 .mwdma_mask = 0x07, /* mwdma0-2 */
232 .udma_mask = ATA_UDMA6, /* udma0-6 */
233 .port_ops = &pdc2027x_pata133_ops,
234 },
235};
236
237MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
238MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
239MODULE_LICENSE("GPL");
240MODULE_VERSION(DRV_VERSION);
241MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
242
243/**
244 * port_mmio - Get the MMIO address of PDC2027x extended registers
245 * @ap: Port
246 * @offset: offset from mmio base
247 */
7c250413 248static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
669a5db4 249{
0d5ff566 250 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
669a5db4
JG		 251}
252
253/**
254 * dev_mmio - Get the MMIO address of PDC2027x extended registers
255 * @ap: Port
256 * @adev: device
257 * @offset: offset from mmio base
258 */
7c250413 259static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
669a5db4
JG		 260{
261 u8 adj = (adev->devno) ? 0x08 : 0x00;
262 return port_mmio(ap, offset) + adj;
263}
264
265/**
9bedb799 266 * pdc2027x_pata_cable_detect - Probe host controller cable detect info
669a5db4
JG		 267 * @ap: Port for which cable detect info is desired
268 *
269 * Read 80c cable indicator from Promise extended register.
270 * This register is latched when the system is reset.
271 *
272 * LOCKING:
273 * None (inherited from caller).
274 */
9bedb799 275static int pdc2027x_cable_detect(struct ata_port *ap)
669a5db4
JG		 276{
277 u32 cgcr;
278
279 /* check cable detect results */
280 cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL));
281 if (cgcr & (1 << 26))
282 goto cbl40;
283
284 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
285
9bedb799 286 return ATA_CBL_PATA80;
669a5db4
JG		 287cbl40:
288 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
9bedb799 289 return ATA_CBL_PATA40;
669a5db4
JG		 290}
291
292/**
293 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
294 * @ap: Port to check
295 */
296static inline int pdc2027x_port_enabled(struct ata_port *ap)
297{
298 return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
299}
300
301/**
302 * pdc2027x_prereset - prereset for PATA host controller
303 * @ap: Target port
d4b2bab4 304 * @deadline: deadline jiffies for the operation
669a5db4
JG		 305 *
306 * Probeinit including cable detection.
307 *
308 * LOCKING:
309 * None (inherited from caller).
310 */
311
d4b2bab4 312static int pdc2027x_prereset(struct ata_port *ap, unsigned long deadline)
669a5db4
JG		 313{
314 /* Check whether port enabled */
c961922b
AC		 315 if (!pdc2027x_port_enabled(ap))
316 return -ENOENT;
d4b2bab4 317 return ata_std_prereset(ap, deadline);
669a5db4
JG		 318}
319
320/**
321 * pdc2027x_error_handler - Perform reset on PATA port and classify
322 * @ap: Port to reset
323 *
324 * Reset PATA phy and classify attached devices.
325 *
326 * LOCKING:
327 * None (inherited from caller).
328 */
329
330static void pdc2027x_error_handler(struct ata_port *ap)
331{
332 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
333}
334
9bedb799
AC		 335/**
336 * pdc2720x_mode_filter - mode selection filter
337 * @adev: ATA device
338 * @mask: list of modes proposed
339 *
340 * Block UDMA on devices that cause trouble with this controller.
341 */
342
343static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
344{
345 unsigned char model_num[ATA_ID_PROD_LEN + 1];
346 struct ata_device *pair = ata_dev_pair(adev);
347
348 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
349 return ata_pci_default_filter(adev, mask);
350
351 /* Check for slave of a Maxtor at UDMA6 */
352 ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
353 ATA_ID_PROD_LEN + 1);
354 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
355 if(strstr(model_num, "Maxtor") == 0 && pair->dma_mode == XFER_UDMA_6)
356 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
357
358 return ata_pci_default_filter(adev, mask);
359}
360
669a5db4
JG		 361/**
362 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
363 * @ap: Port to configure
364 * @adev: um
365 * @pio: PIO mode, 0 - 4
366 *
367 * Set PIO mode for device.
368 *
369 * LOCKING:
370 * None (inherited from caller).
371 */
372
373static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
374{
375 unsigned int pio = adev->pio_mode - XFER_PIO_0;
376 u32 ctcr0, ctcr1;
377
378 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
379
380 /* Sanity check */
381 if (pio > 4) {
382 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
383 return;
384
385 }
386
387 /* Set the PIO timing registers using value table for 133MHz */
388 PDPRINTK("Set pio regs... \n");
389
390 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
391 ctcr0 &= 0xffff0000;
392 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
393 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
394 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
395
396 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
397 ctcr1 &= 0x00ffffff;
398 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
399 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
400
401 PDPRINTK("Set pio regs done\n");
402
403 PDPRINTK("Set to pio mode[%u] \n", pio);
404}
405
406/**
407 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
408 * @ap: Port to configure
409 * @adev: um
410 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
411 *
412 * Set UDMA mode for device.
413 *
414 * LOCKING:
415 * None (inherited from caller).
416 */
417static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
418{
419 unsigned int dma_mode = adev->dma_mode;
420 u32 ctcr0, ctcr1;
421
422 if ((dma_mode >= XFER_UDMA_0) &&
423 (dma_mode <= XFER_UDMA_6)) {
424 /* Set the UDMA timing registers with value table for 133MHz */
425 unsigned int udma_mode = dma_mode & 0x07;
426
427 if (dma_mode == XFER_UDMA_2) {
428 /*
429 * Turn off tHOLD.
430 * If tHOLD is '1', the hardware will add half clock for data hold time.
431 * This code segment seems to be no effect. tHOLD will be overwritten below.
432 */
433 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
434 writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
435 }
436
437 PDPRINTK("Set udma regs... \n");
438
439 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
440 ctcr1 &= 0xff000000;
441 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
442 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
443 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
444 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
445
446 PDPRINTK("Set udma regs done\n");
447
448 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
449
450 } else if ((dma_mode >= XFER_MW_DMA_0) &&
451 (dma_mode <= XFER_MW_DMA_2)) {
452 /* Set the MDMA timing registers with value table for 133MHz */
453 unsigned int mdma_mode = dma_mode & 0x07;
454
455 PDPRINTK("Set mdma regs... \n");
456 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
457
458 ctcr0 &= 0x0000ffff;
459 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
460 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
461
462 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
463 PDPRINTK("Set mdma regs done\n");
464
465 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
466 } else {
467 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
468 }
469}
470
471/**
9bedb799 472 * pdc2027x_set_mode - Set the timing registers back to correct values.
669a5db4 473 * @ap: Port to configure
9bedb799 474 * @r_failed: Returned device for failure
669a5db4
JG		 475 *
476 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
477 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
478 * This function overwrites the possibly incorrect values set by the hardware to be correct.
479 */
9bedb799 480static int pdc2027x_set_mode(struct ata_port *ap, struct ata_device **r_failed)
669a5db4 481{
f58229f8
TH		 482 struct ata_device *dev;
483 int rc;
669a5db4 484
f58229f8
TH		 485 rc = ata_do_set_mode(ap, r_failed);
486 if (rc < 0)
487 return rc;
669a5db4 488
f58229f8 489 ata_link_for_each_dev(dev, &ap->link) {
669a5db4
JG		 490 if (ata_dev_enabled(dev)) {
491
492 pdc2027x_set_piomode(ap, dev);
493
494 /*
495 * Enable prefetch if the device support PIO only.
496 */
497 if (dev->xfer_shift == ATA_SHIFT_PIO) {
498 u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1));
499 ctcr1 |= (1 << 25);
500 writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
501
502 PDPRINTK("Turn on prefetch\n");
503 } else {
504 pdc2027x_set_dmamode(ap, dev);
505 }
506 }
507 }
9bedb799 508 return 0;
669a5db4
JG		 509}
510
511/**
512 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
513 * @qc: Metadata associated with taskfile to check
514 *
515 * LOCKING:
516 * None (inherited from caller).
517 *
518 * RETURNS: 0 when ATAPI DMA can be used
519 * 1 otherwise
520 */
521static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
522{
523 struct scsi_cmnd *cmd = qc->scsicmd;
524 u8 *scsicmd = cmd->cmnd;
525 int rc = 1; /* atapi dma off by default */
526
527 /*
528 * This workaround is from Promise's GPL driver.
529 * If ATAPI DMA is used for commands not in the
530 * following white list, say MODE_SENSE and REQUEST_SENSE,
531 * pdc2027x might hit the irq lost problem.
532 */
533 switch (scsicmd[0]) {
534 case READ_10:
535 case WRITE_10:
536 case READ_12:
537 case WRITE_12:
538 case READ_6:
539 case WRITE_6:
540 case 0xad: /* READ_DVD_STRUCTURE */
541 case 0xbe: /* READ_CD */
542 /* ATAPI DMA is ok */
543 rc = 0;
544 break;
545 default:
546 ;
547 }
548
549 return rc;
550}
551
552/**
553 * pdc_read_counter - Read the ctr counter
5d728824 554 * @host: target ATA host
669a5db4
JG		 555 */
556
5d728824 557static long pdc_read_counter(struct ata_host *host)
669a5db4 558{
5d728824 559 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
669a5db4
JG		 560 long counter;
561 int retry = 1;
562 u32 bccrl, bccrh, bccrlv, bccrhv;
563
564retry:
78c4af0b
MP		 565 bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
566 bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
669a5db4
JG		 567 rmb();
568
569 /* Read the counter values again for verification */
78c4af0b
MP		 570 bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
571 bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
669a5db4
JG		 572 rmb();
573
574 counter = (bccrh << 15) | bccrl;
575
576 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
577 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
578
579 /*
580 * The 30-bit decreasing counter are read by 2 pieces.
581 * Incorrect value may be read when both bccrh and bccrl are changing.
582 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
583 */
584 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
585 retry--;
586 PDPRINTK("rereading counter\n");
587 goto retry;
588 }
589
590 return counter;
591}
592
593/**
594 * adjust_pll - Adjust the PLL input clock in Hz.
595 *
596 * @pdc_controller: controller specific information
5d728824 597 * @host: target ATA host
669a5db4
JG		 598 * @pll_clock: The input of PLL in HZ
599 */
5d728824 600static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
669a5db4 601{
5d728824 602 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
669a5db4
JG		 603 u16 pll_ctl;
604 long pll_clock_khz = pll_clock / 1000;
605 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
606 long ratio = pout_required / pll_clock_khz;
607 int F, R;
608
609 /* Sanity check */
610 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
611 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
612 return;
613 }
614
615#ifdef PDC_DEBUG
616 PDPRINTK("pout_required is %ld\n", pout_required);
617
618 /* Show the current clock value of PLL control register
619 * (maybe already configured by the firmware)
620 */
0d5ff566 621 pll_ctl = readw(mmio_base + PDC_PLL_CTL);
669a5db4
JG		 622
623 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
624#endif
625
626 /*
627 * Calculate the ratio of F, R and OD
628 * POUT = (F + 2) / (( R + 2) * NO)
629 */
630 if (ratio < 8600L) { /* 8.6x */
631 /* Using NO = 0x01, R = 0x0D */
632 R = 0x0d;
633 } else if (ratio < 12900L) { /* 12.9x */
634 /* Using NO = 0x01, R = 0x08 */
635 R = 0x08;
636 } else if (ratio < 16100L) { /* 16.1x */
637 /* Using NO = 0x01, R = 0x06 */
638 R = 0x06;
639 } else if (ratio < 64000L) { /* 64x */
640 R = 0x00;
641 } else {
642 /* Invalid ratio */
643 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
644 return;
645 }
646
647 F = (ratio * (R+2)) / 1000 - 2;
648
649 if (unlikely(F < 0 || F > 127)) {
650 /* Invalid F */
651 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
652 return;
653 }
654
655 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
656
657 pll_ctl = (R << 8) | F;
658
659 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
660
0d5ff566
TH		 661 writew(pll_ctl, mmio_base + PDC_PLL_CTL);
662 readw(mmio_base + PDC_PLL_CTL); /* flush */
669a5db4
JG		 663
664 /* Wait the PLL circuit to be stable */
665 mdelay(30);
666
667#ifdef PDC_DEBUG
668 /*
669 * Show the current clock value of PLL control register
670 * (maybe configured by the firmware)
671 */
0d5ff566 672 pll_ctl = readw(mmio_base + PDC_PLL_CTL);
669a5db4
JG		 673
674 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
675#endif
676
677 return;
678}
679
680/**
681 * detect_pll_input_clock - Detect the PLL input clock in Hz.
5d728824 682 * @host: target ATA host
669a5db4
JG		 683 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
684 * Half of the PCI clock.
685 */
5d728824 686static long pdc_detect_pll_input_clock(struct ata_host *host)
669a5db4 687{
5d728824 688 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
669a5db4
JG		 689 u32 scr;
690 long start_count, end_count;
8c781bf7
AL		 691 struct timeval start_time, end_time;
692 long pll_clock, usec_elapsed;
669a5db4 693
669a5db4 694 /* Start the test mode */
0d5ff566 695 scr = readl(mmio_base + PDC_SYS_CTL);
669a5db4 696 PDPRINTK("scr[%X]\n", scr);
0d5ff566
TH		 697 writel(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
698 readl(mmio_base + PDC_SYS_CTL); /* flush */
669a5db4 699
78c4af0b
MP		 700 /* Read current counter value */
701 start_count = pdc_read_counter(host);
702 do_gettimeofday(&start_time);
703
669a5db4
JG		 704 /* Let the counter run for 100 ms. */
705 mdelay(100);
706
707 /* Read the counter values again */
5d728824 708 end_count = pdc_read_counter(host);
8c781bf7 709 do_gettimeofday(&end_time);
669a5db4
JG		 710
711 /* Stop the test mode */
0d5ff566 712 scr = readl(mmio_base + PDC_SYS_CTL);
669a5db4 713 PDPRINTK("scr[%X]\n", scr);
0d5ff566
TH		 714 writel(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
715 readl(mmio_base + PDC_SYS_CTL); /* flush */
669a5db4
JG		 716
717 /* calculate the input clock in Hz */
8c781bf7
AL		 718 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
719 (end_time.tv_usec - start_time.tv_usec);
720
78c4af0b 721 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
8c781bf7 722 (100000000 / usec_elapsed);
669a5db4
JG		 723
724 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
725 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
726
727 return pll_clock;
728}
729
730/**
731 * pdc_hardware_init - Initialize the hardware.
5d728824
TH		 732 * @host: target ATA host
733 * @board_idx: board identifier
669a5db4 734 */
5d728824 735static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
669a5db4
JG		 736{
737 long pll_clock;
738
739 /*
740 * Detect PLL input clock rate.
741 * On some system, where PCI bus is running at non-standard clock rate.
742 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
743 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
744 */
5d728824 745 pll_clock = pdc_detect_pll_input_clock(host);
669a5db4
JG		 746
747 if (pll_clock < 0) /* counter overflow? Try again. */
5d728824 748 pll_clock = pdc_detect_pll_input_clock(host);
669a5db4 749
5d728824 750 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
669a5db4
JG		 751
752 /* Adjust PLL control register */
5d728824 753 pdc_adjust_pll(host, pll_clock, board_idx);
669a5db4
JG		 754
755 return 0;
756}
757
758/**
759 * pdc_ata_setup_port - setup the mmio address
760 * @port: ata ioports to setup
761 * @base: base address
762 */
0d5ff566 763static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
669a5db4
JG		 764{
765 port->cmd_addr =
766 port->data_addr = base;
767 port->feature_addr =
768 port->error_addr = base + 0x05;
769 port->nsect_addr = base + 0x0a;
770 port->lbal_addr = base + 0x0f;
771 port->lbam_addr = base + 0x10;
772 port->lbah_addr = base + 0x15;
773 port->device_addr = base + 0x1a;
774 port->command_addr =
775 port->status_addr = base + 0x1f;
776 port->altstatus_addr =
777 port->ctl_addr = base + 0x81a;
778}
779
780/**
781 * pdc2027x_init_one - PCI probe function
782 * Called when an instance of PCI adapter is inserted.
783 * This function checks whether the hardware is supported,
784 * initialize hardware and register an instance of ata_host to
5d728824 785 * libata. (implements struct pci_driver.probe() )
669a5db4
JG		 786 *
787 * @pdev: instance of pci_dev found
788 * @ent: matching entry in the id_tbl[]
789 */
790static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
791{
792 static int printed_version;
793 unsigned int board_idx = (unsigned int) ent->driver_data;
5d728824
TH		 794 const struct ata_port_info *ppi[] =
795 { &pdc2027x_port_info[board_idx], NULL };
796 struct ata_host *host;
7c250413 797 void __iomem *mmio_base;
669a5db4
JG		 798 int rc;
799
800 if (!printed_version++)
801 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
802
5d728824
TH		 803 /* alloc host */
804 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
805 if (!host)
806 return -ENOMEM;
807
808 /* acquire resources and fill host */
24dc5f33 809 rc = pcim_enable_device(pdev);
669a5db4
JG		 810 if (rc)
811 return rc;
812
0d5ff566 813 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
669a5db4 814 if (rc)
24dc5f33 815 return rc;
5d728824 816 host->iomap = pcim_iomap_table(pdev);
669a5db4
JG		 817
818 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
819 if (rc)
24dc5f33 820 return rc;
669a5db4
JG		 821
822 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
823 if (rc)
24dc5f33 824 return rc;
669a5db4 825
5d728824 826 mmio_base = host->iomap[PDC_MMIO_BAR];
669a5db4 827
5d728824
TH		 828 pdc_ata_setup_port(&host->ports[0]->ioaddr, mmio_base + 0x17c0);
829 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x1000;
830 pdc_ata_setup_port(&host->ports[1]->ioaddr, mmio_base + 0x15c0);
831 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x1008;
0d5ff566 832
669a5db4
JG		 833 //pci_enable_intx(pdev);
834
835 /* initialize adapter */
5d728824 836 if (pdc_hardware_init(host, board_idx) != 0)
24dc5f33 837 return -EIO;
669a5db4 838
5d728824
TH		 839 pci_set_master(pdev);
840 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
841 &pdc2027x_sht);
669a5db4
JG		 842}
843
844/**
845 * pdc2027x_init - Called after this module is loaded into the kernel.
846 */
847static int __init pdc2027x_init(void)
848{
72dc6794 849 return pci_register_driver(&pdc2027x_pci_driver);
669a5db4
JG		 850}
851
852/**
853 * pdc2027x_exit - Called before this module unloaded from the kernel
854 */
855static void __exit pdc2027x_exit(void)
856{
857 pci_unregister_driver(&pdc2027x_pci_driver);
858}
859
860module_init(pdc2027x_init);
861module_exit(pdc2027x_exit);
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