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669a5db4 JG |
1 | /* |
2 | * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Ported to libata by: | |
10 | * Albert Lee <albertcc@tw.ibm.com> IBM Corporation | |
11 | * | |
12 | * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> | |
13 | * Portions Copyright (C) 1999 Promise Technology, Inc. | |
14 | * | |
15 | * Author: Frank Tiernan (frankt@promise.com) | |
16 | * Released under terms of General Public License | |
17 | * | |
18 | * | |
19 | * libata documentation is available via 'make {ps|pdf}docs', | |
20 | * as Documentation/DocBook/libata.* | |
21 | * | |
22 | * Hardware information only available under NDA. | |
23 | * | |
24 | */ | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/blkdev.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/device.h> | |
32 | #include <scsi/scsi.h> | |
33 | #include <scsi/scsi_host.h> | |
34 | #include <scsi/scsi_cmnd.h> | |
35 | #include <linux/libata.h> | |
36 | #include <asm/io.h> | |
37 | ||
38 | #define DRV_NAME "pata_pdc2027x" | |
c961922b | 39 | #define DRV_VERSION "0.74-ac5" |
669a5db4 JG |
40 | #undef PDC_DEBUG |
41 | ||
42 | #ifdef PDC_DEBUG | |
43 | #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) | |
44 | #else | |
45 | #define PDPRINTK(fmt, args...) | |
46 | #endif | |
47 | ||
48 | enum { | |
49 | PDC_UDMA_100 = 0, | |
50 | PDC_UDMA_133 = 1, | |
51 | ||
52 | PDC_100_MHZ = 100000000, | |
53 | PDC_133_MHZ = 133333333, | |
54 | ||
55 | PDC_SYS_CTL = 0x1100, | |
56 | PDC_ATA_CTL = 0x1104, | |
57 | PDC_GLOBAL_CTL = 0x1108, | |
58 | PDC_CTCR0 = 0x110C, | |
59 | PDC_CTCR1 = 0x1110, | |
60 | PDC_BYTE_COUNT = 0x1120, | |
61 | PDC_PLL_CTL = 0x1202, | |
62 | }; | |
63 | ||
64 | static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); | |
65 | static void pdc2027x_remove_one(struct pci_dev *pdev); | |
66 | static void pdc2027x_error_handler(struct ata_port *ap); | |
67 | static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev); | |
68 | static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
69 | static void pdc2027x_post_set_mode(struct ata_port *ap); | |
70 | static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc); | |
71 | ||
72 | /* | |
73 | * ATA Timing Tables based on 133MHz controller clock. | |
74 | * These tables are only used when the controller is in 133MHz clock. | |
75 | * If the controller is in 100MHz clock, the ASIC hardware will | |
76 | * set the timing registers automatically when "set feature" command | |
77 | * is issued to the device. However, if the controller clock is 133MHz, | |
78 | * the following tables must be used. | |
79 | */ | |
80 | static struct pdc2027x_pio_timing { | |
81 | u8 value0, value1, value2; | |
82 | } pdc2027x_pio_timing_tbl [] = { | |
83 | { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ | |
84 | { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */ | |
85 | { 0x23, 0x26, 0x64 }, /* PIO mode 2 */ | |
86 | { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */ | |
87 | { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ | |
88 | }; | |
89 | ||
90 | static struct pdc2027x_mdma_timing { | |
91 | u8 value0, value1; | |
92 | } pdc2027x_mdma_timing_tbl [] = { | |
93 | { 0xdf, 0x5f }, /* MDMA mode 0 */ | |
94 | { 0x6b, 0x27 }, /* MDMA mode 1 */ | |
95 | { 0x69, 0x25 }, /* MDMA mode 2 */ | |
96 | }; | |
97 | ||
98 | static struct pdc2027x_udma_timing { | |
99 | u8 value0, value1, value2; | |
100 | } pdc2027x_udma_timing_tbl [] = { | |
101 | { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ | |
102 | { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */ | |
103 | { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */ | |
104 | { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */ | |
105 | { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */ | |
106 | { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */ | |
107 | { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ | |
108 | }; | |
109 | ||
110 | static const struct pci_device_id pdc2027x_pci_tbl[] = { | |
2d2744fc JG |
111 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 }, |
112 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 }, | |
113 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 }, | |
114 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 }, | |
115 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 }, | |
116 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 }, | |
117 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 }, | |
118 | ||
669a5db4 JG |
119 | { } /* terminate list */ |
120 | }; | |
121 | ||
122 | static struct pci_driver pdc2027x_pci_driver = { | |
123 | .name = DRV_NAME, | |
124 | .id_table = pdc2027x_pci_tbl, | |
125 | .probe = pdc2027x_init_one, | |
126 | .remove = __devexit_p(pdc2027x_remove_one), | |
127 | }; | |
128 | ||
129 | static struct scsi_host_template pdc2027x_sht = { | |
130 | .module = THIS_MODULE, | |
131 | .name = DRV_NAME, | |
132 | .ioctl = ata_scsi_ioctl, | |
133 | .queuecommand = ata_scsi_queuecmd, | |
134 | .can_queue = ATA_DEF_QUEUE, | |
135 | .this_id = ATA_SHT_THIS_ID, | |
136 | .sg_tablesize = LIBATA_MAX_PRD, | |
137 | .max_sectors = ATA_MAX_SECTORS, | |
138 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
139 | .emulated = ATA_SHT_EMULATED, | |
140 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
141 | .proc_name = DRV_NAME, | |
142 | .dma_boundary = ATA_DMA_BOUNDARY, | |
143 | .slave_configure = ata_scsi_slave_config, | |
144 | .bios_param = ata_std_bios_param, | |
145 | }; | |
146 | ||
147 | static struct ata_port_operations pdc2027x_pata100_ops = { | |
148 | .port_disable = ata_port_disable, | |
149 | ||
150 | .tf_load = ata_tf_load, | |
151 | .tf_read = ata_tf_read, | |
152 | .check_status = ata_check_status, | |
153 | .exec_command = ata_exec_command, | |
154 | .dev_select = ata_std_dev_select, | |
155 | ||
156 | .check_atapi_dma = pdc2027x_check_atapi_dma, | |
157 | .bmdma_setup = ata_bmdma_setup, | |
158 | .bmdma_start = ata_bmdma_start, | |
159 | .bmdma_stop = ata_bmdma_stop, | |
160 | .bmdma_status = ata_bmdma_status, | |
161 | .qc_prep = ata_qc_prep, | |
162 | .qc_issue = ata_qc_issue_prot, | |
163 | .data_xfer = ata_mmio_data_xfer, | |
164 | ||
165 | .freeze = ata_bmdma_freeze, | |
166 | .thaw = ata_bmdma_thaw, | |
167 | .error_handler = pdc2027x_error_handler, | |
168 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
169 | ||
170 | .irq_handler = ata_interrupt, | |
171 | .irq_clear = ata_bmdma_irq_clear, | |
172 | ||
173 | .port_start = ata_port_start, | |
174 | .port_stop = ata_port_stop, | |
175 | .host_stop = ata_pci_host_stop, | |
176 | }; | |
177 | ||
178 | static struct ata_port_operations pdc2027x_pata133_ops = { | |
179 | .port_disable = ata_port_disable, | |
180 | .set_piomode = pdc2027x_set_piomode, | |
181 | .set_dmamode = pdc2027x_set_dmamode, | |
182 | .post_set_mode = pdc2027x_post_set_mode, | |
183 | ||
184 | .tf_load = ata_tf_load, | |
185 | .tf_read = ata_tf_read, | |
186 | .check_status = ata_check_status, | |
187 | .exec_command = ata_exec_command, | |
188 | .dev_select = ata_std_dev_select, | |
189 | ||
190 | .check_atapi_dma = pdc2027x_check_atapi_dma, | |
191 | .bmdma_setup = ata_bmdma_setup, | |
192 | .bmdma_start = ata_bmdma_start, | |
193 | .bmdma_stop = ata_bmdma_stop, | |
194 | .bmdma_status = ata_bmdma_status, | |
195 | .qc_prep = ata_qc_prep, | |
196 | .qc_issue = ata_qc_issue_prot, | |
197 | .data_xfer = ata_mmio_data_xfer, | |
198 | ||
199 | .freeze = ata_bmdma_freeze, | |
200 | .thaw = ata_bmdma_thaw, | |
201 | .error_handler = pdc2027x_error_handler, | |
202 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
203 | ||
204 | .irq_handler = ata_interrupt, | |
205 | .irq_clear = ata_bmdma_irq_clear, | |
206 | ||
207 | .port_start = ata_port_start, | |
208 | .port_stop = ata_port_stop, | |
209 | .host_stop = ata_pci_host_stop, | |
210 | }; | |
211 | ||
212 | static struct ata_port_info pdc2027x_port_info[] = { | |
213 | /* PDC_UDMA_100 */ | |
214 | { | |
215 | .sht = &pdc2027x_sht, | |
216 | .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS | | |
217 | ATA_FLAG_MMIO, | |
218 | .pio_mask = 0x1f, /* pio0-4 */ | |
219 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
220 | .udma_mask = ATA_UDMA5, /* udma0-5 */ | |
221 | .port_ops = &pdc2027x_pata100_ops, | |
222 | }, | |
223 | /* PDC_UDMA_133 */ | |
224 | { | |
225 | .sht = &pdc2027x_sht, | |
226 | .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS | | |
227 | ATA_FLAG_MMIO, | |
228 | .pio_mask = 0x1f, /* pio0-4 */ | |
229 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
230 | .udma_mask = ATA_UDMA6, /* udma0-6 */ | |
231 | .port_ops = &pdc2027x_pata133_ops, | |
232 | }, | |
233 | }; | |
234 | ||
235 | MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee"); | |
236 | MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277"); | |
237 | MODULE_LICENSE("GPL"); | |
238 | MODULE_VERSION(DRV_VERSION); | |
239 | MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl); | |
240 | ||
241 | /** | |
242 | * port_mmio - Get the MMIO address of PDC2027x extended registers | |
243 | * @ap: Port | |
244 | * @offset: offset from mmio base | |
245 | */ | |
7c250413 | 246 | static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) |
669a5db4 JG |
247 | { |
248 | return ap->host->mmio_base + ap->port_no * 0x100 + offset; | |
249 | } | |
250 | ||
251 | /** | |
252 | * dev_mmio - Get the MMIO address of PDC2027x extended registers | |
253 | * @ap: Port | |
254 | * @adev: device | |
255 | * @offset: offset from mmio base | |
256 | */ | |
7c250413 | 257 | static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset) |
669a5db4 JG |
258 | { |
259 | u8 adj = (adev->devno) ? 0x08 : 0x00; | |
260 | return port_mmio(ap, offset) + adj; | |
261 | } | |
262 | ||
263 | /** | |
264 | * pdc2027x_pata_cbl_detect - Probe host controller cable detect info | |
265 | * @ap: Port for which cable detect info is desired | |
266 | * | |
267 | * Read 80c cable indicator from Promise extended register. | |
268 | * This register is latched when the system is reset. | |
269 | * | |
270 | * LOCKING: | |
271 | * None (inherited from caller). | |
272 | */ | |
273 | static void pdc2027x_cbl_detect(struct ata_port *ap) | |
274 | { | |
275 | u32 cgcr; | |
276 | ||
277 | /* check cable detect results */ | |
278 | cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL)); | |
279 | if (cgcr & (1 << 26)) | |
280 | goto cbl40; | |
281 | ||
282 | PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no); | |
283 | ||
284 | ap->cbl = ATA_CBL_PATA80; | |
285 | return; | |
286 | ||
287 | cbl40: | |
288 | printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no); | |
289 | ap->cbl = ATA_CBL_PATA40; | |
290 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
291 | } | |
292 | ||
293 | /** | |
294 | * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled. | |
295 | * @ap: Port to check | |
296 | */ | |
297 | static inline int pdc2027x_port_enabled(struct ata_port *ap) | |
298 | { | |
299 | return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02; | |
300 | } | |
301 | ||
302 | /** | |
303 | * pdc2027x_prereset - prereset for PATA host controller | |
304 | * @ap: Target port | |
305 | * | |
306 | * Probeinit including cable detection. | |
307 | * | |
308 | * LOCKING: | |
309 | * None (inherited from caller). | |
310 | */ | |
311 | ||
312 | static int pdc2027x_prereset(struct ata_port *ap) | |
313 | { | |
314 | /* Check whether port enabled */ | |
c961922b AC |
315 | if (!pdc2027x_port_enabled(ap)) |
316 | return -ENOENT; | |
669a5db4 JG |
317 | pdc2027x_cbl_detect(ap); |
318 | return ata_std_prereset(ap); | |
319 | } | |
320 | ||
321 | /** | |
322 | * pdc2027x_error_handler - Perform reset on PATA port and classify | |
323 | * @ap: Port to reset | |
324 | * | |
325 | * Reset PATA phy and classify attached devices. | |
326 | * | |
327 | * LOCKING: | |
328 | * None (inherited from caller). | |
329 | */ | |
330 | ||
331 | static void pdc2027x_error_handler(struct ata_port *ap) | |
332 | { | |
333 | ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset); | |
334 | } | |
335 | ||
336 | /** | |
337 | * pdc2027x_set_piomode - Initialize host controller PATA PIO timings | |
338 | * @ap: Port to configure | |
339 | * @adev: um | |
340 | * @pio: PIO mode, 0 - 4 | |
341 | * | |
342 | * Set PIO mode for device. | |
343 | * | |
344 | * LOCKING: | |
345 | * None (inherited from caller). | |
346 | */ | |
347 | ||
348 | static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
349 | { | |
350 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
351 | u32 ctcr0, ctcr1; | |
352 | ||
353 | PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode); | |
354 | ||
355 | /* Sanity check */ | |
356 | if (pio > 4) { | |
357 | printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio); | |
358 | return; | |
359 | ||
360 | } | |
361 | ||
362 | /* Set the PIO timing registers using value table for 133MHz */ | |
363 | PDPRINTK("Set pio regs... \n"); | |
364 | ||
365 | ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0)); | |
366 | ctcr0 &= 0xffff0000; | |
367 | ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 | | |
368 | (pdc2027x_pio_timing_tbl[pio].value1 << 8); | |
369 | writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); | |
370 | ||
371 | ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1)); | |
372 | ctcr1 &= 0x00ffffff; | |
373 | ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24); | |
374 | writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); | |
375 | ||
376 | PDPRINTK("Set pio regs done\n"); | |
377 | ||
378 | PDPRINTK("Set to pio mode[%u] \n", pio); | |
379 | } | |
380 | ||
381 | /** | |
382 | * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings | |
383 | * @ap: Port to configure | |
384 | * @adev: um | |
385 | * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6 | |
386 | * | |
387 | * Set UDMA mode for device. | |
388 | * | |
389 | * LOCKING: | |
390 | * None (inherited from caller). | |
391 | */ | |
392 | static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
393 | { | |
394 | unsigned int dma_mode = adev->dma_mode; | |
395 | u32 ctcr0, ctcr1; | |
396 | ||
397 | if ((dma_mode >= XFER_UDMA_0) && | |
398 | (dma_mode <= XFER_UDMA_6)) { | |
399 | /* Set the UDMA timing registers with value table for 133MHz */ | |
400 | unsigned int udma_mode = dma_mode & 0x07; | |
401 | ||
402 | if (dma_mode == XFER_UDMA_2) { | |
403 | /* | |
404 | * Turn off tHOLD. | |
405 | * If tHOLD is '1', the hardware will add half clock for data hold time. | |
406 | * This code segment seems to be no effect. tHOLD will be overwritten below. | |
407 | */ | |
408 | ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1)); | |
409 | writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1)); | |
410 | } | |
411 | ||
412 | PDPRINTK("Set udma regs... \n"); | |
413 | ||
414 | ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1)); | |
415 | ctcr1 &= 0xff000000; | |
416 | ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 | | |
417 | (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) | | |
418 | (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16); | |
419 | writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); | |
420 | ||
421 | PDPRINTK("Set udma regs done\n"); | |
422 | ||
423 | PDPRINTK("Set to udma mode[%u] \n", udma_mode); | |
424 | ||
425 | } else if ((dma_mode >= XFER_MW_DMA_0) && | |
426 | (dma_mode <= XFER_MW_DMA_2)) { | |
427 | /* Set the MDMA timing registers with value table for 133MHz */ | |
428 | unsigned int mdma_mode = dma_mode & 0x07; | |
429 | ||
430 | PDPRINTK("Set mdma regs... \n"); | |
431 | ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0)); | |
432 | ||
433 | ctcr0 &= 0x0000ffff; | |
434 | ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) | | |
435 | (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24); | |
436 | ||
437 | writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); | |
438 | PDPRINTK("Set mdma regs done\n"); | |
439 | ||
440 | PDPRINTK("Set to mdma mode[%u] \n", mdma_mode); | |
441 | } else { | |
442 | printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode); | |
443 | } | |
444 | } | |
445 | ||
446 | /** | |
447 | * pdc2027x_post_set_mode - Set the timing registers back to correct values. | |
448 | * @ap: Port to configure | |
449 | * | |
450 | * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers | |
451 | * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL. | |
452 | * This function overwrites the possibly incorrect values set by the hardware to be correct. | |
453 | */ | |
454 | static void pdc2027x_post_set_mode(struct ata_port *ap) | |
455 | { | |
456 | int i; | |
457 | ||
458 | for (i = 0; i < ATA_MAX_DEVICES; i++) { | |
459 | struct ata_device *dev = &ap->device[i]; | |
460 | ||
461 | if (ata_dev_enabled(dev)) { | |
462 | ||
463 | pdc2027x_set_piomode(ap, dev); | |
464 | ||
465 | /* | |
466 | * Enable prefetch if the device support PIO only. | |
467 | */ | |
468 | if (dev->xfer_shift == ATA_SHIFT_PIO) { | |
469 | u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1)); | |
470 | ctcr1 |= (1 << 25); | |
471 | writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1)); | |
472 | ||
473 | PDPRINTK("Turn on prefetch\n"); | |
474 | } else { | |
475 | pdc2027x_set_dmamode(ap, dev); | |
476 | } | |
477 | } | |
478 | } | |
479 | } | |
480 | ||
481 | /** | |
482 | * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command | |
483 | * @qc: Metadata associated with taskfile to check | |
484 | * | |
485 | * LOCKING: | |
486 | * None (inherited from caller). | |
487 | * | |
488 | * RETURNS: 0 when ATAPI DMA can be used | |
489 | * 1 otherwise | |
490 | */ | |
491 | static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc) | |
492 | { | |
493 | struct scsi_cmnd *cmd = qc->scsicmd; | |
494 | u8 *scsicmd = cmd->cmnd; | |
495 | int rc = 1; /* atapi dma off by default */ | |
496 | ||
497 | /* | |
498 | * This workaround is from Promise's GPL driver. | |
499 | * If ATAPI DMA is used for commands not in the | |
500 | * following white list, say MODE_SENSE and REQUEST_SENSE, | |
501 | * pdc2027x might hit the irq lost problem. | |
502 | */ | |
503 | switch (scsicmd[0]) { | |
504 | case READ_10: | |
505 | case WRITE_10: | |
506 | case READ_12: | |
507 | case WRITE_12: | |
508 | case READ_6: | |
509 | case WRITE_6: | |
510 | case 0xad: /* READ_DVD_STRUCTURE */ | |
511 | case 0xbe: /* READ_CD */ | |
512 | /* ATAPI DMA is ok */ | |
513 | rc = 0; | |
514 | break; | |
515 | default: | |
516 | ; | |
517 | } | |
518 | ||
519 | return rc; | |
520 | } | |
521 | ||
522 | /** | |
523 | * pdc_read_counter - Read the ctr counter | |
524 | * @probe_ent: for the port address | |
525 | */ | |
526 | ||
527 | static long pdc_read_counter(struct ata_probe_ent *probe_ent) | |
528 | { | |
529 | long counter; | |
530 | int retry = 1; | |
531 | u32 bccrl, bccrh, bccrlv, bccrhv; | |
532 | ||
533 | retry: | |
534 | bccrl = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff; | |
535 | bccrh = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff; | |
536 | rmb(); | |
537 | ||
538 | /* Read the counter values again for verification */ | |
539 | bccrlv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff; | |
540 | bccrhv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff; | |
541 | rmb(); | |
542 | ||
543 | counter = (bccrh << 15) | bccrl; | |
544 | ||
545 | PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl); | |
546 | PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv); | |
547 | ||
548 | /* | |
549 | * The 30-bit decreasing counter are read by 2 pieces. | |
550 | * Incorrect value may be read when both bccrh and bccrl are changing. | |
551 | * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read. | |
552 | */ | |
553 | if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) { | |
554 | retry--; | |
555 | PDPRINTK("rereading counter\n"); | |
556 | goto retry; | |
557 | } | |
558 | ||
559 | return counter; | |
560 | } | |
561 | ||
562 | /** | |
563 | * adjust_pll - Adjust the PLL input clock in Hz. | |
564 | * | |
565 | * @pdc_controller: controller specific information | |
566 | * @probe_ent: For the port address | |
567 | * @pll_clock: The input of PLL in HZ | |
568 | */ | |
569 | static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx) | |
570 | { | |
571 | ||
572 | u16 pll_ctl; | |
573 | long pll_clock_khz = pll_clock / 1000; | |
574 | long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ; | |
575 | long ratio = pout_required / pll_clock_khz; | |
576 | int F, R; | |
577 | ||
578 | /* Sanity check */ | |
579 | if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) { | |
580 | printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz); | |
581 | return; | |
582 | } | |
583 | ||
584 | #ifdef PDC_DEBUG | |
585 | PDPRINTK("pout_required is %ld\n", pout_required); | |
586 | ||
587 | /* Show the current clock value of PLL control register | |
588 | * (maybe already configured by the firmware) | |
589 | */ | |
590 | pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL); | |
591 | ||
592 | PDPRINTK("pll_ctl[%X]\n", pll_ctl); | |
593 | #endif | |
594 | ||
595 | /* | |
596 | * Calculate the ratio of F, R and OD | |
597 | * POUT = (F + 2) / (( R + 2) * NO) | |
598 | */ | |
599 | if (ratio < 8600L) { /* 8.6x */ | |
600 | /* Using NO = 0x01, R = 0x0D */ | |
601 | R = 0x0d; | |
602 | } else if (ratio < 12900L) { /* 12.9x */ | |
603 | /* Using NO = 0x01, R = 0x08 */ | |
604 | R = 0x08; | |
605 | } else if (ratio < 16100L) { /* 16.1x */ | |
606 | /* Using NO = 0x01, R = 0x06 */ | |
607 | R = 0x06; | |
608 | } else if (ratio < 64000L) { /* 64x */ | |
609 | R = 0x00; | |
610 | } else { | |
611 | /* Invalid ratio */ | |
612 | printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio); | |
613 | return; | |
614 | } | |
615 | ||
616 | F = (ratio * (R+2)) / 1000 - 2; | |
617 | ||
618 | if (unlikely(F < 0 || F > 127)) { | |
619 | /* Invalid F */ | |
620 | printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F); | |
621 | return; | |
622 | } | |
623 | ||
624 | PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio); | |
625 | ||
626 | pll_ctl = (R << 8) | F; | |
627 | ||
628 | PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl); | |
629 | ||
630 | writew(pll_ctl, probe_ent->mmio_base + PDC_PLL_CTL); | |
631 | readw(probe_ent->mmio_base + PDC_PLL_CTL); /* flush */ | |
632 | ||
633 | /* Wait the PLL circuit to be stable */ | |
634 | mdelay(30); | |
635 | ||
636 | #ifdef PDC_DEBUG | |
637 | /* | |
638 | * Show the current clock value of PLL control register | |
639 | * (maybe configured by the firmware) | |
640 | */ | |
641 | pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL); | |
642 | ||
643 | PDPRINTK("pll_ctl[%X]\n", pll_ctl); | |
644 | #endif | |
645 | ||
646 | return; | |
647 | } | |
648 | ||
649 | /** | |
650 | * detect_pll_input_clock - Detect the PLL input clock in Hz. | |
651 | * @probe_ent: for the port address | |
652 | * Ex. 16949000 on 33MHz PCI bus for pdc20275. | |
653 | * Half of the PCI clock. | |
654 | */ | |
655 | static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent) | |
656 | { | |
657 | u32 scr; | |
658 | long start_count, end_count; | |
659 | long pll_clock; | |
660 | ||
661 | /* Read current counter value */ | |
662 | start_count = pdc_read_counter(probe_ent); | |
663 | ||
664 | /* Start the test mode */ | |
665 | scr = readl(probe_ent->mmio_base + PDC_SYS_CTL); | |
666 | PDPRINTK("scr[%X]\n", scr); | |
667 | writel(scr | (0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL); | |
668 | readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */ | |
669 | ||
670 | /* Let the counter run for 100 ms. */ | |
671 | mdelay(100); | |
672 | ||
673 | /* Read the counter values again */ | |
674 | end_count = pdc_read_counter(probe_ent); | |
675 | ||
676 | /* Stop the test mode */ | |
677 | scr = readl(probe_ent->mmio_base + PDC_SYS_CTL); | |
678 | PDPRINTK("scr[%X]\n", scr); | |
679 | writel(scr & ~(0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL); | |
680 | readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */ | |
681 | ||
682 | /* calculate the input clock in Hz */ | |
683 | pll_clock = (start_count - end_count) * 10; | |
684 | ||
685 | PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count); | |
686 | PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock); | |
687 | ||
688 | return pll_clock; | |
689 | } | |
690 | ||
691 | /** | |
692 | * pdc_hardware_init - Initialize the hardware. | |
693 | * @pdev: instance of pci_dev found | |
694 | * @pdc_controller: controller specific information | |
695 | * @pe: for the port address | |
696 | */ | |
697 | static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, unsigned int board_idx) | |
698 | { | |
699 | long pll_clock; | |
700 | ||
701 | /* | |
702 | * Detect PLL input clock rate. | |
703 | * On some system, where PCI bus is running at non-standard clock rate. | |
704 | * Ex. 25MHz or 40MHz, we have to adjust the cycle_time. | |
705 | * The pdc20275 controller employs PLL circuit to help correct timing registers setting. | |
706 | */ | |
707 | pll_clock = pdc_detect_pll_input_clock(pe); | |
708 | ||
709 | if (pll_clock < 0) /* counter overflow? Try again. */ | |
710 | pll_clock = pdc_detect_pll_input_clock(pe); | |
711 | ||
712 | dev_printk(KERN_INFO, &pdev->dev, "PLL input clock %ld kHz\n", pll_clock/1000); | |
713 | ||
714 | /* Adjust PLL control register */ | |
715 | pdc_adjust_pll(pe, pll_clock, board_idx); | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | /** | |
721 | * pdc_ata_setup_port - setup the mmio address | |
722 | * @port: ata ioports to setup | |
723 | * @base: base address | |
724 | */ | |
725 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
726 | { | |
727 | port->cmd_addr = | |
728 | port->data_addr = base; | |
729 | port->feature_addr = | |
730 | port->error_addr = base + 0x05; | |
731 | port->nsect_addr = base + 0x0a; | |
732 | port->lbal_addr = base + 0x0f; | |
733 | port->lbam_addr = base + 0x10; | |
734 | port->lbah_addr = base + 0x15; | |
735 | port->device_addr = base + 0x1a; | |
736 | port->command_addr = | |
737 | port->status_addr = base + 0x1f; | |
738 | port->altstatus_addr = | |
739 | port->ctl_addr = base + 0x81a; | |
740 | } | |
741 | ||
742 | /** | |
743 | * pdc2027x_init_one - PCI probe function | |
744 | * Called when an instance of PCI adapter is inserted. | |
745 | * This function checks whether the hardware is supported, | |
746 | * initialize hardware and register an instance of ata_host to | |
747 | * libata by providing struct ata_probe_ent and ata_device_add(). | |
748 | * (implements struct pci_driver.probe() ) | |
749 | * | |
750 | * @pdev: instance of pci_dev found | |
751 | * @ent: matching entry in the id_tbl[] | |
752 | */ | |
753 | static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
754 | { | |
755 | static int printed_version; | |
756 | unsigned int board_idx = (unsigned int) ent->driver_data; | |
757 | ||
758 | struct ata_probe_ent *probe_ent = NULL; | |
759 | unsigned long base; | |
7c250413 | 760 | void __iomem *mmio_base; |
669a5db4 JG |
761 | int rc; |
762 | ||
763 | if (!printed_version++) | |
764 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
765 | ||
766 | rc = pci_enable_device(pdev); | |
767 | if (rc) | |
768 | return rc; | |
769 | ||
770 | rc = pci_request_regions(pdev, DRV_NAME); | |
771 | if (rc) | |
772 | goto err_out; | |
773 | ||
774 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
775 | if (rc) | |
776 | goto err_out_regions; | |
777 | ||
778 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
779 | if (rc) | |
780 | goto err_out_regions; | |
781 | ||
782 | /* Prepare the probe entry */ | |
783 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); | |
784 | if (probe_ent == NULL) { | |
785 | rc = -ENOMEM; | |
786 | goto err_out_regions; | |
787 | } | |
788 | ||
789 | probe_ent->dev = pci_dev_to_dev(pdev); | |
790 | INIT_LIST_HEAD(&probe_ent->node); | |
791 | ||
792 | mmio_base = pci_iomap(pdev, 5, 0); | |
793 | if (!mmio_base) { | |
794 | rc = -ENOMEM; | |
795 | goto err_out_free_ent; | |
796 | } | |
797 | ||
798 | base = (unsigned long) mmio_base; | |
799 | ||
800 | probe_ent->sht = pdc2027x_port_info[board_idx].sht; | |
801 | probe_ent->port_flags = pdc2027x_port_info[board_idx].flags; | |
802 | probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask; | |
803 | probe_ent->mwdma_mask = pdc2027x_port_info[board_idx].mwdma_mask; | |
804 | probe_ent->udma_mask = pdc2027x_port_info[board_idx].udma_mask; | |
805 | probe_ent->port_ops = pdc2027x_port_info[board_idx].port_ops; | |
806 | ||
807 | probe_ent->irq = pdev->irq; | |
808 | probe_ent->irq_flags = SA_SHIRQ; | |
809 | probe_ent->mmio_base = mmio_base; | |
810 | ||
811 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x17c0); | |
812 | probe_ent->port[0].bmdma_addr = base + 0x1000; | |
813 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x15c0); | |
814 | probe_ent->port[1].bmdma_addr = base + 0x1008; | |
815 | ||
816 | probe_ent->n_ports = 2; | |
817 | ||
818 | pci_set_master(pdev); | |
819 | //pci_enable_intx(pdev); | |
820 | ||
821 | /* initialize adapter */ | |
822 | if (pdc_hardware_init(pdev, probe_ent, board_idx) != 0) | |
823 | goto err_out_free_ent; | |
824 | ||
825 | ata_device_add(probe_ent); | |
826 | kfree(probe_ent); | |
827 | ||
828 | return 0; | |
829 | ||
830 | err_out_free_ent: | |
831 | kfree(probe_ent); | |
832 | err_out_regions: | |
833 | pci_release_regions(pdev); | |
834 | err_out: | |
835 | pci_disable_device(pdev); | |
836 | return rc; | |
837 | } | |
838 | ||
839 | /** | |
840 | * pdc2027x_remove_one - Called to remove a single instance of the | |
841 | * adapter. | |
842 | * | |
843 | * @dev: The PCI device to remove. | |
844 | * FIXME: module load/unload not working yet | |
845 | */ | |
846 | static void __devexit pdc2027x_remove_one(struct pci_dev *pdev) | |
847 | { | |
848 | ata_pci_remove_one(pdev); | |
849 | } | |
850 | ||
851 | /** | |
852 | * pdc2027x_init - Called after this module is loaded into the kernel. | |
853 | */ | |
854 | static int __init pdc2027x_init(void) | |
855 | { | |
856 | return pci_module_init(&pdc2027x_pci_driver); | |
857 | } | |
858 | ||
859 | /** | |
860 | * pdc2027x_exit - Called before this module unloaded from the kernel | |
861 | */ | |
862 | static void __exit pdc2027x_exit(void) | |
863 | { | |
864 | pci_unregister_driver(&pdc2027x_pci_driver); | |
865 | } | |
866 | ||
867 | module_init(pdc2027x_init); | |
868 | module_exit(pdc2027x_exit); |