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Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * Based in part on linux/drivers/ide/pci/pdc202xx_old.c | |
7 | * | |
8 | * First cut with LBA48/ATAPI | |
9 | * | |
10 | * TODO: | |
11 | * Channel interlock/reset on both required ? | |
12 | */ | |
85cd7251 | 13 | |
669a5db4 JG |
14 | #include <linux/kernel.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/blkdev.h> | |
19 | #include <linux/delay.h> | |
20 | #include <scsi/scsi_host.h> | |
21 | #include <linux/libata.h> | |
22 | ||
23 | #define DRV_NAME "pata_pdc202xx_old" | |
cb48cab7 | 24 | #define DRV_VERSION "0.3.0" |
669a5db4 JG |
25 | |
26 | /** | |
27 | * pdc2024x_pre_reset - probe begin | |
28 | * @ap: ATA port | |
29 | * | |
30 | * Set up cable type and use generic probe init | |
31 | */ | |
85cd7251 | 32 | |
669a5db4 JG |
33 | static int pdc2024x_pre_reset(struct ata_port *ap) |
34 | { | |
35 | ap->cbl = ATA_CBL_PATA40; | |
36 | return ata_std_prereset(ap); | |
37 | } | |
38 | ||
39 | ||
40 | static void pdc2024x_error_handler(struct ata_port *ap) | |
41 | { | |
42 | ata_bmdma_drive_eh(ap, pdc2024x_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
43 | } | |
44 | ||
45 | ||
46 | static int pdc2026x_pre_reset(struct ata_port *ap) | |
47 | { | |
48 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
49 | u16 cis; | |
85cd7251 | 50 | |
669a5db4 JG |
51 | pci_read_config_word(pdev, 0x50, &cis); |
52 | if (cis & (1 << (10 + ap->port_no))) | |
53 | ap->cbl = ATA_CBL_PATA80; | |
54 | else | |
55 | ap->cbl = ATA_CBL_PATA40; | |
56 | ||
57 | return ata_std_prereset(ap); | |
58 | } | |
59 | ||
60 | static void pdc2026x_error_handler(struct ata_port *ap) | |
61 | { | |
62 | ata_bmdma_drive_eh(ap, pdc2026x_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
63 | } | |
64 | ||
65 | /** | |
ada406c8 | 66 | * pdc202xx_configure_piomode - set chip PIO timing |
669a5db4 JG |
67 | * @ap: ATA interface |
68 | * @adev: ATA device | |
69 | * @pio: PIO mode | |
70 | * | |
71 | * Called to do the PIO mode setup. Our timing registers are shared | |
72 | * so a configure_dmamode call will undo any work we do here and vice | |
73 | * versa | |
74 | */ | |
85cd7251 | 75 | |
ada406c8 | 76 | static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio) |
669a5db4 JG |
77 | { |
78 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
79 | int port = 0x60 + 4 * ap->port_no + 2 * adev->devno; | |
80 | static u16 pio_timing[5] = { | |
81 | 0x0913, 0x050C , 0x0308, 0x0206, 0x0104 | |
82 | }; | |
83 | u8 r_ap, r_bp; | |
84 | ||
85 | pci_read_config_byte(pdev, port, &r_ap); | |
86 | pci_read_config_byte(pdev, port + 1, &r_bp); | |
87 | r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */ | |
88 | r_bp &= ~0x07; | |
89 | r_ap |= (pio_timing[pio] >> 8); | |
90 | r_bp |= (pio_timing[pio] & 0xFF); | |
85cd7251 | 91 | |
669a5db4 JG |
92 | if (ata_pio_need_iordy(adev)) |
93 | r_ap |= 0x20; /* IORDY enable */ | |
94 | if (adev->class == ATA_DEV_ATA) | |
95 | r_ap |= 0x10; /* FIFO enable */ | |
96 | pci_write_config_byte(pdev, port, r_ap); | |
97 | pci_write_config_byte(pdev, port + 1, r_bp); | |
98 | } | |
99 | ||
100 | /** | |
ada406c8 | 101 | * pdc202xx_set_piomode - set initial PIO mode data |
669a5db4 JG |
102 | * @ap: ATA interface |
103 | * @adev: ATA device | |
104 | * | |
105 | * Called to do the PIO mode setup. Our timing registers are shared | |
106 | * but we want to set the PIO timing by default. | |
107 | */ | |
85cd7251 | 108 | |
ada406c8 | 109 | static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 | 110 | { |
ada406c8 | 111 | pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); |
669a5db4 JG |
112 | } |
113 | ||
114 | /** | |
ada406c8 | 115 | * pdc202xx_configure_dmamode - set DMA mode in chip |
669a5db4 JG |
116 | * @ap: ATA interface |
117 | * @adev: ATA device | |
118 | * | |
119 | * Load DMA cycle times into the chip ready for a DMA transfer | |
120 | * to occur. | |
121 | */ | |
85cd7251 | 122 | |
ada406c8 | 123 | static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
124 | { |
125 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
126 | int port = 0x60 + 4 * ap->port_no + 2 * adev->devno; | |
127 | static u8 udma_timing[6][2] = { | |
128 | { 0x60, 0x03 }, /* 33 Mhz Clock */ | |
129 | { 0x40, 0x02 }, | |
130 | { 0x20, 0x01 }, | |
131 | { 0x40, 0x02 }, /* 66 Mhz Clock */ | |
132 | { 0x20, 0x01 }, | |
85cd7251 | 133 | { 0x20, 0x01 } |
669a5db4 JG |
134 | }; |
135 | u8 r_bp, r_cp; | |
85cd7251 | 136 | |
669a5db4 JG |
137 | pci_read_config_byte(pdev, port + 1, &r_bp); |
138 | pci_read_config_byte(pdev, port + 2, &r_cp); | |
85cd7251 | 139 | |
669a5db4 JG |
140 | r_bp &= ~0xF0; |
141 | r_cp &= ~0x0F; | |
85cd7251 | 142 | |
669a5db4 JG |
143 | if (adev->dma_mode >= XFER_UDMA_0) { |
144 | int speed = adev->dma_mode - XFER_UDMA_0; | |
145 | r_bp |= udma_timing[speed][0]; | |
146 | r_cp |= udma_timing[speed][1]; | |
85cd7251 | 147 | |
669a5db4 JG |
148 | } else { |
149 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
150 | r_bp |= 0x60; | |
151 | r_cp |= (5 - speed); | |
152 | } | |
153 | pci_write_config_byte(pdev, port + 1, r_bp); | |
154 | pci_write_config_byte(pdev, port + 2, r_cp); | |
85cd7251 | 155 | |
669a5db4 JG |
156 | } |
157 | ||
158 | /** | |
159 | * pdc2026x_bmdma_start - DMA engine begin | |
160 | * @qc: ATA command | |
161 | * | |
162 | * In UDMA3 or higher we have to clock switch for the duration of the | |
163 | * DMA transfer sequence. | |
164 | */ | |
85cd7251 | 165 | |
669a5db4 JG |
166 | static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc) |
167 | { | |
168 | struct ata_port *ap = qc->ap; | |
169 | struct ata_device *adev = qc->dev; | |
170 | struct ata_taskfile *tf = &qc->tf; | |
171 | int sel66 = ap->port_no ? 0x08: 0x02; | |
172 | ||
0d5ff566 TH |
173 | void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; |
174 | void __iomem *clock = master + 0x11; | |
175 | void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); | |
85cd7251 | 176 | |
669a5db4 | 177 | u32 len; |
85cd7251 | 178 | |
669a5db4 JG |
179 | /* Check we keep host level locking here */ |
180 | if (adev->dma_mode >= XFER_UDMA_2) | |
0d5ff566 | 181 | iowrite8(ioread8(clock) | sel66, clock); |
669a5db4 | 182 | else |
0d5ff566 | 183 | iowrite8(ioread8(clock) & ~sel66, clock); |
669a5db4 | 184 | |
85cd7251 | 185 | /* The DMA clocks may have been trashed by a reset. FIXME: make conditional |
669a5db4 | 186 | and move to qc_issue ? */ |
ada406c8 | 187 | pdc202xx_set_dmamode(ap, qc->dev); |
669a5db4 JG |
188 | |
189 | /* Cases the state machine will not complete correctly without help */ | |
190 | if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATA_PROT_ATAPI_DMA) | |
191 | { | |
726f0785 | 192 | len = qc->nbytes; |
85cd7251 | 193 | |
669a5db4 JG |
194 | if (tf->flags & ATA_TFLAG_WRITE) |
195 | len |= 0x06000000; | |
196 | else | |
197 | len |= 0x05000000; | |
85cd7251 | 198 | |
0d5ff566 | 199 | iowrite32(len, atapi_reg); |
669a5db4 | 200 | } |
85cd7251 JG |
201 | |
202 | /* Activate DMA */ | |
669a5db4 JG |
203 | ata_bmdma_start(qc); |
204 | } | |
205 | ||
206 | /** | |
207 | * pdc2026x_bmdma_end - DMA engine stop | |
208 | * @qc: ATA command | |
209 | * | |
210 | * After a DMA completes we need to put the clock back to 33MHz for | |
211 | * PIO timings. | |
212 | */ | |
85cd7251 | 213 | |
669a5db4 JG |
214 | static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc) |
215 | { | |
216 | struct ata_port *ap = qc->ap; | |
217 | struct ata_device *adev = qc->dev; | |
218 | struct ata_taskfile *tf = &qc->tf; | |
85cd7251 | 219 | |
669a5db4 JG |
220 | int sel66 = ap->port_no ? 0x08: 0x02; |
221 | /* The clock bits are in the same register for both channels */ | |
0d5ff566 TH |
222 | void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; |
223 | void __iomem *clock = master + 0x11; | |
224 | void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); | |
85cd7251 | 225 | |
669a5db4 JG |
226 | /* Cases the state machine will not complete correctly */ |
227 | if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) { | |
0d5ff566 TH |
228 | iowrite32(0, atapi_reg); |
229 | iowrite8(ioread8(clock) & ~sel66, clock); | |
669a5db4 JG |
230 | } |
231 | /* Check we keep host level locking here */ | |
232 | /* Flip back to 33Mhz for PIO */ | |
233 | if (adev->dma_mode >= XFER_UDMA_2) | |
0d5ff566 | 234 | iowrite8(ioread8(clock) & ~sel66, clock); |
669a5db4 JG |
235 | |
236 | ata_bmdma_stop(qc); | |
237 | } | |
238 | ||
239 | /** | |
240 | * pdc2026x_dev_config - device setup hook | |
241 | * @ap: ATA port | |
242 | * @adev: newly found device | |
243 | * | |
244 | * Perform chip specific early setup. We need to lock the transfer | |
245 | * sizes to 8bit to avoid making the state engine on the 2026x cards | |
246 | * barf. | |
247 | */ | |
85cd7251 | 248 | |
669a5db4 JG |
249 | static void pdc2026x_dev_config(struct ata_port *ap, struct ata_device *adev) |
250 | { | |
251 | adev->max_sectors = 256; | |
252 | } | |
253 | ||
ada406c8 | 254 | static struct scsi_host_template pdc202xx_sht = { |
669a5db4 JG |
255 | .module = THIS_MODULE, |
256 | .name = DRV_NAME, | |
257 | .ioctl = ata_scsi_ioctl, | |
258 | .queuecommand = ata_scsi_queuecmd, | |
259 | .can_queue = ATA_DEF_QUEUE, | |
260 | .this_id = ATA_SHT_THIS_ID, | |
261 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
262 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
263 | .emulated = ATA_SHT_EMULATED, | |
264 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
265 | .proc_name = DRV_NAME, | |
266 | .dma_boundary = ATA_DMA_BOUNDARY, | |
267 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 268 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 | 269 | .bios_param = ata_std_bios_param, |
438ac6d5 | 270 | #ifdef CONFIG_PM |
62d64ae0 AC |
271 | .resume = ata_scsi_device_resume, |
272 | .suspend = ata_scsi_device_suspend, | |
438ac6d5 | 273 | #endif |
669a5db4 JG |
274 | }; |
275 | ||
276 | static struct ata_port_operations pdc2024x_port_ops = { | |
277 | .port_disable = ata_port_disable, | |
ada406c8 AC |
278 | .set_piomode = pdc202xx_set_piomode, |
279 | .set_dmamode = pdc202xx_set_dmamode, | |
669a5db4 JG |
280 | .mode_filter = ata_pci_default_filter, |
281 | .tf_load = ata_tf_load, | |
282 | .tf_read = ata_tf_read, | |
283 | .check_status = ata_check_status, | |
284 | .exec_command = ata_exec_command, | |
285 | .dev_select = ata_std_dev_select, | |
286 | ||
287 | .freeze = ata_bmdma_freeze, | |
288 | .thaw = ata_bmdma_thaw, | |
289 | .error_handler = pdc2024x_error_handler, | |
290 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
291 | ||
292 | .bmdma_setup = ata_bmdma_setup, | |
293 | .bmdma_start = ata_bmdma_start, | |
294 | .bmdma_stop = ata_bmdma_stop, | |
295 | .bmdma_status = ata_bmdma_status, | |
296 | ||
297 | .qc_prep = ata_qc_prep, | |
298 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 299 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
300 | |
301 | .irq_handler = ata_interrupt, | |
302 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
303 | .irq_on = ata_irq_on, |
304 | .irq_ack = ata_irq_ack, | |
85cd7251 | 305 | |
669a5db4 | 306 | .port_start = ata_port_start, |
85cd7251 | 307 | }; |
669a5db4 JG |
308 | |
309 | static struct ata_port_operations pdc2026x_port_ops = { | |
310 | .port_disable = ata_port_disable, | |
ada406c8 AC |
311 | .set_piomode = pdc202xx_set_piomode, |
312 | .set_dmamode = pdc202xx_set_dmamode, | |
669a5db4 JG |
313 | .mode_filter = ata_pci_default_filter, |
314 | .tf_load = ata_tf_load, | |
315 | .tf_read = ata_tf_read, | |
316 | .check_status = ata_check_status, | |
317 | .exec_command = ata_exec_command, | |
318 | .dev_select = ata_std_dev_select, | |
319 | .dev_config = pdc2026x_dev_config, | |
320 | ||
321 | .freeze = ata_bmdma_freeze, | |
322 | .thaw = ata_bmdma_thaw, | |
323 | .error_handler = pdc2026x_error_handler, | |
324 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
325 | ||
326 | .bmdma_setup = ata_bmdma_setup, | |
327 | .bmdma_start = pdc2026x_bmdma_start, | |
328 | .bmdma_stop = pdc2026x_bmdma_stop, | |
329 | .bmdma_status = ata_bmdma_status, | |
330 | ||
331 | .qc_prep = ata_qc_prep, | |
332 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 333 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
334 | |
335 | .irq_handler = ata_interrupt, | |
336 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
337 | .irq_on = ata_irq_on, |
338 | .irq_ack = ata_irq_ack, | |
85cd7251 | 339 | |
669a5db4 | 340 | .port_start = ata_port_start, |
85cd7251 | 341 | }; |
669a5db4 | 342 | |
ada406c8 | 343 | static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
669a5db4 JG |
344 | { |
345 | static struct ata_port_info info[3] = { | |
346 | { | |
ada406c8 | 347 | .sht = &pdc202xx_sht, |
669a5db4 JG |
348 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, |
349 | .pio_mask = 0x1f, | |
350 | .mwdma_mask = 0x07, | |
351 | .udma_mask = ATA_UDMA2, | |
352 | .port_ops = &pdc2024x_port_ops | |
85cd7251 | 353 | }, |
669a5db4 | 354 | { |
ada406c8 | 355 | .sht = &pdc202xx_sht, |
669a5db4 JG |
356 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, |
357 | .pio_mask = 0x1f, | |
358 | .mwdma_mask = 0x07, | |
359 | .udma_mask = ATA_UDMA4, | |
360 | .port_ops = &pdc2026x_port_ops | |
361 | }, | |
362 | { | |
ada406c8 | 363 | .sht = &pdc202xx_sht, |
669a5db4 JG |
364 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, |
365 | .pio_mask = 0x1f, | |
366 | .mwdma_mask = 0x07, | |
367 | .udma_mask = ATA_UDMA5, | |
368 | .port_ops = &pdc2026x_port_ops | |
369 | } | |
85cd7251 | 370 | |
669a5db4 JG |
371 | }; |
372 | static struct ata_port_info *port_info[2]; | |
373 | ||
374 | port_info[0] = port_info[1] = &info[id->driver_data]; | |
85cd7251 | 375 | |
669a5db4 JG |
376 | if (dev->device == PCI_DEVICE_ID_PROMISE_20265) { |
377 | struct pci_dev *bridge = dev->bus->self; | |
378 | /* Don't grab anything behind a Promise I2O RAID */ | |
379 | if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) { | |
380 | if( bridge->device == PCI_DEVICE_ID_INTEL_I960) | |
381 | return -ENODEV; | |
382 | if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM) | |
383 | return -ENODEV; | |
384 | } | |
385 | } | |
386 | return ata_pci_init_one(dev, port_info, 2); | |
387 | } | |
388 | ||
ada406c8 | 389 | static const struct pci_device_id pdc202xx[] = { |
2d2744fc JG |
390 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, |
391 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, | |
392 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, | |
393 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, | |
394 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, | |
395 | ||
396 | { }, | |
669a5db4 JG |
397 | }; |
398 | ||
ada406c8 | 399 | static struct pci_driver pdc202xx_pci_driver = { |
2d2744fc | 400 | .name = DRV_NAME, |
ada406c8 AC |
401 | .id_table = pdc202xx, |
402 | .probe = pdc202xx_init_one, | |
62d64ae0 | 403 | .remove = ata_pci_remove_one, |
438ac6d5 | 404 | #ifdef CONFIG_PM |
62d64ae0 AC |
405 | .suspend = ata_pci_device_suspend, |
406 | .resume = ata_pci_device_resume, | |
438ac6d5 | 407 | #endif |
669a5db4 JG |
408 | }; |
409 | ||
ada406c8 | 410 | static int __init pdc202xx_init(void) |
669a5db4 | 411 | { |
ada406c8 | 412 | return pci_register_driver(&pdc202xx_pci_driver); |
669a5db4 JG |
413 | } |
414 | ||
ada406c8 | 415 | static void __exit pdc202xx_exit(void) |
669a5db4 | 416 | { |
ada406c8 | 417 | pci_unregister_driver(&pdc202xx_pci_driver); |
669a5db4 JG |
418 | } |
419 | ||
669a5db4 JG |
420 | MODULE_AUTHOR("Alan Cox"); |
421 | MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267"); | |
422 | MODULE_LICENSE("GPL"); | |
ada406c8 | 423 | MODULE_DEVICE_TABLE(pci, pdc202xx); |
669a5db4 JG |
424 | MODULE_VERSION(DRV_VERSION); |
425 | ||
ada406c8 AC |
426 | module_init(pdc202xx_init); |
427 | module_exit(pdc202xx_exit); |