[mirror_ubuntu-bionic-kernel.git] / drivers / ata / pata_pdc202xx_old.c

/*
 * pata_pdc202xx_old.c 	- Promise PDC202xx PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *			  (C) 2007 Bartlomiej Zolnierkiewicz
 *
 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
 *
 * First cut with LBA48/ATAPI
 *
 * TODO:
 *	Channel interlock/reset on both required
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_pdc202xx_old"
#define DRV_VERSION "0.4.0"

/**
 *	pdc2024x_pre_reset		-	probe begin
 *	@ap: ATA port
 *
 *	Set up cable type and use generic probe init
 */

static int pdc2024x_pre_reset(struct ata_port *ap)
{
	ap->cbl = ATA_CBL_PATA40;
	return ata_std_prereset(ap);
}


static void pdc2024x_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, pdc2024x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}


static int pdc2026x_pre_reset(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 cis;

	pci_read_config_word(pdev, 0x50, &cis);
	if (cis & (1 << (10 + ap->port_no)))
		ap->cbl = ATA_CBL_PATA80;
	else
		ap->cbl = ATA_CBL_PATA40;

	return ata_std_prereset(ap);
}

static void pdc2026x_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, pdc2026x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	pdc202xx_configure_piomode	-	set chip PIO timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@pio: PIO mode
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	so a configure_dmamode call will undo any work we do here and vice
 *	versa
 */

static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
	static u16 pio_timing[5] = {
		0x0913, 0x050C , 0x0308, 0x0206, 0x0104
	};
	u8 r_ap, r_bp;

	pci_read_config_byte(pdev, port, &r_ap);
	pci_read_config_byte(pdev, port + 1, &r_bp);
	r_ap &= ~0x3F;	/* Preserve ERRDY_EN, SYNC_IN */
	r_bp &= ~0x1F;
	r_ap |= (pio_timing[pio] >> 8);
	r_bp |= (pio_timing[pio] & 0xFF);

	if (ata_pio_need_iordy(adev))
		r_ap |= 0x20;	/* IORDY enable */
	if (adev->class == ATA_DEV_ATA)
		r_ap |= 0x10;	/* FIFO enable */
	pci_write_config_byte(pdev, port, r_ap);
	pci_write_config_byte(pdev, port + 1, r_bp);
}

/**
 *	pdc202xx_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	but we want to set the PIO timing by default.
 */

static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
}

/**
 *	pdc202xx_configure_dmamode	-	set DMA mode in chip
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Load DMA cycle times into the chip ready for a DMA transfer
 *	to occur.
 */

static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
	static u8 udma_timing[6][2] = {
		{ 0x60, 0x03 },	/* 33 Mhz Clock */
		{ 0x40, 0x02 },
		{ 0x20, 0x01 },
		{ 0x40, 0x02 },	/* 66 Mhz Clock */
		{ 0x20, 0x01 },
		{ 0x20, 0x01 }
	};
	static u8 mdma_timing[3][2] = {
		{ 0x60, 0x03 },
		{ 0x60, 0x04 },
		{ 0xe0, 0x0f },
	};
	u8 r_bp, r_cp;

	pci_read_config_byte(pdev, port + 1, &r_bp);
	pci_read_config_byte(pdev, port + 2, &r_cp);

	r_bp &= ~0xE0;
	r_cp &= ~0x0F;

	if (adev->dma_mode >= XFER_UDMA_0) {
		int speed = adev->dma_mode - XFER_UDMA_0;
		r_bp |= udma_timing[speed][0];
		r_cp |= udma_timing[speed][1];

	} else {
		int speed = adev->dma_mode - XFER_MW_DMA_0;
		r_bp |= mdma_timing[speed][0];
		r_cp |= mdma_timing[speed][1];
	}
	pci_write_config_byte(pdev, port + 1, r_bp);
	pci_write_config_byte(pdev, port + 2, r_cp);

}

/**
 *	pdc2026x_bmdma_start		-	DMA engine begin
 *	@qc: ATA command
 *
 *	In UDMA3 or higher we have to clock switch for the duration of the
 *	DMA transfer sequence.
 */

static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_taskfile *tf = &qc->tf;
	int sel66 = ap->port_no ? 0x08: 0x02;

	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	void __iomem *clock = master + 0x11;
	void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);

	u32 len;

	/* Check we keep host level locking here */
	if (adev->dma_mode >= XFER_UDMA_2)
		iowrite8(ioread8(clock) | sel66, clock);
	else
		iowrite8(ioread8(clock) & ~sel66, clock);

	/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
	   and move to qc_issue ? */
	pdc202xx_set_dmamode(ap, qc->dev);

	/* Cases the state machine will not complete correctly without help */
	if ((tf->flags & ATA_TFLAG_LBA48) ||  tf->protocol == ATA_PROT_ATAPI_DMA)
	{
		len = qc->nbytes;

		if (tf->flags & ATA_TFLAG_WRITE)
			len |= 0x06000000;
		else
			len |= 0x05000000;

		iowrite32(len, atapi_reg);
	}

	/* Activate DMA */
	ata_bmdma_start(qc);
}

/**
 *	pdc2026x_bmdma_end		-	DMA engine stop
 *	@qc: ATA command
 *
 *	After a DMA completes we need to put the clock back to 33MHz for
 *	PIO timings.
 */

static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_taskfile *tf = &qc->tf;

	int sel66 = ap->port_no ? 0x08: 0x02;
	/* The clock bits are in the same register for both channels */
	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	void __iomem *clock = master + 0x11;
	void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);

	/* Cases the state machine will not complete correctly */
	if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) {
		iowrite32(0, atapi_reg);
		iowrite8(ioread8(clock) & ~sel66, clock);
	}
	/* Check we keep host level locking here */
	/* Flip back to 33Mhz for PIO */
	if (adev->dma_mode >= XFER_UDMA_2)
		iowrite8(ioread8(clock) & ~sel66, clock);

	ata_bmdma_stop(qc);
}

/**
 *	pdc2026x_dev_config	-	device setup hook
 *	@ap: ATA port
 *	@adev: newly found device
 *
 *	Perform chip specific early setup. We need to lock the transfer
 *	sizes to 8bit to avoid making the state engine on the 2026x cards
 *	barf.
 */

static void pdc2026x_dev_config(struct ata_port *ap, struct ata_device *adev)
{
	adev->max_sectors = 256;
}

static struct scsi_host_template pdc202xx_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
#ifdef CONFIG_PM
	.resume			= ata_scsi_device_resume,
	.suspend		= ata_scsi_device_suspend,
#endif
};

static struct ata_port_operations pdc2024x_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= pdc202xx_set_piomode,
	.set_dmamode	= pdc202xx_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= pdc2024x_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,
	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static struct ata_port_operations pdc2026x_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= pdc202xx_set_piomode,
	.set_dmamode	= pdc202xx_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,
	.dev_config	= pdc2026x_dev_config,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= pdc2026x_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= pdc2026x_bmdma_start,
	.bmdma_stop	= pdc2026x_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,
	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static struct ata_port_info info[3] = {
		{
			.sht = &pdc202xx_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA2,
			.port_ops = &pdc2024x_port_ops
		},
		{
			.sht = &pdc202xx_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,
			.port_ops = &pdc2026x_port_ops
		},
		{
			.sht = &pdc202xx_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,
			.port_ops = &pdc2026x_port_ops
		}

	};
	static struct ata_port_info *port_info[2];

	port_info[0] = port_info[1] = &info[id->driver_data];

	if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
		struct pci_dev *bridge = dev->bus->self;
		/* Don't grab anything behind a Promise I2O RAID */
		if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
			if( bridge->device == PCI_DEVICE_ID_INTEL_I960)
				return -ENODEV;
			if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
				return -ENODEV;
		}
	}
	return ata_pci_init_one(dev, port_info, 2);
}

static const struct pci_device_id pdc202xx[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },

	{ },
};

static struct pci_driver pdc202xx_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= pdc202xx,
	.probe 		= pdc202xx_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

static int __init pdc202xx_init(void)
{
	return pci_register_driver(&pdc202xx_pci_driver);
}

static void __exit pdc202xx_exit(void)
{
	pci_unregister_driver(&pdc202xx_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, pdc202xx);
MODULE_VERSION(DRV_VERSION);

module_init(pdc202xx_init);
module_exit(pdc202xx_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
63ed7101	5	* (C) 2007 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
	8	*
	9	* First cut with LBA48/ATAPI
	10	*
	11	* TODO:
63ed7101	12	* Channel interlock/reset on both required
669a5db4	13	*/
85cd7251	14
669a5db4 JG	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/pci.h>
	18	#include <linux/init.h>
	19	#include <linux/blkdev.h>
	20	#include <linux/delay.h>
	21	#include <scsi/scsi_host.h>
	22	#include <linux/libata.h>
	23
	24	#define DRV_NAME "pata_pdc202xx_old"
63ed7101	25	#define DRV_VERSION "0.4.0"
669a5db4 JG	26
	27	/**
	28	* pdc2024x_pre_reset - probe begin
	29	* @ap: ATA port
	30	*
	31	* Set up cable type and use generic probe init
	32	*/
85cd7251	33
669a5db4 JG	34	static int pdc2024x_pre_reset(struct ata_port *ap)
	35	{
	36	ap->cbl = ATA_CBL_PATA40;
	37	return ata_std_prereset(ap);
	38	}
	39
	40
	41	static void pdc2024x_error_handler(struct ata_port *ap)
	42	{
	43	ata_bmdma_drive_eh(ap, pdc2024x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	44	}
	45
	46
	47	static int pdc2026x_pre_reset(struct ata_port *ap)
	48	{
	49	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	50	u16 cis;
85cd7251	51
669a5db4 JG	52	pci_read_config_word(pdev, 0x50, &cis);
	53	if (cis & (1 << (10 + ap->port_no)))
	54	ap->cbl = ATA_CBL_PATA80;
	55	else
	56	ap->cbl = ATA_CBL_PATA40;
	57
	58	return ata_std_prereset(ap);
	59	}
	60
	61	static void pdc2026x_error_handler(struct ata_port *ap)
	62	{
	63	ata_bmdma_drive_eh(ap, pdc2026x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	64	}
	65
	66	/**
ada406c8	67	* pdc202xx_configure_piomode - set chip PIO timing
669a5db4 JG	68	* @ap: ATA interface
	69	* @adev: ATA device
	70	* @pio: PIO mode
	71	*
	72	* Called to do the PIO mode setup. Our timing registers are shared
	73	* so a configure_dmamode call will undo any work we do here and vice
	74	* versa
	75	*/
85cd7251	76
ada406c8	77	static void pdc202xx_configure_piomode(struct ata_port ap, struct ata_device adev, int pio)
669a5db4 JG	78	{
669a5db4 JG	79	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
63ed7101	80	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
669a5db4 JG	81	static u16 pio_timing[5] = {
	82	0x0913, 0x050C , 0x0308, 0x0206, 0x0104
	83	};
	84	u8 r_ap, r_bp;
	85
	86	pci_read_config_byte(pdev, port, &r_ap);
	87	pci_read_config_byte(pdev, port + 1, &r_bp);
	88	r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
63ed7101	89	r_bp &= ~0x1F;
669a5db4 JG	90	r_ap \|= (pio_timing[pio] >> 8);
669a5db4 JG	91	r_bp \|= (pio_timing[pio] & 0xFF);
85cd7251	92
669a5db4 JG	93	if (ata_pio_need_iordy(adev))
	94	r_ap \|= 0x20; /* IORDY enable */
	95	if (adev->class == ATA_DEV_ATA)
	96	r_ap \|= 0x10; /* FIFO enable */
	97	pci_write_config_byte(pdev, port, r_ap);
	98	pci_write_config_byte(pdev, port + 1, r_bp);
	99	}
	100
	101	/**
ada406c8	102	* pdc202xx_set_piomode - set initial PIO mode data
669a5db4 JG	103	* @ap: ATA interface
	104	* @adev: ATA device
	105	*
	106	* Called to do the PIO mode setup. Our timing registers are shared
	107	* but we want to set the PIO timing by default.
	108	*/
85cd7251	109
ada406c8	110	static void pdc202xx_set_piomode(struct ata_port ap, struct ata_device adev)
669a5db4	111	{
ada406c8	112	pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
669a5db4 JG	113	}
	114
	115	/**
ada406c8	116	* pdc202xx_configure_dmamode - set DMA mode in chip
669a5db4 JG	117	* @ap: ATA interface
	118	* @adev: ATA device
	119	*
	120	* Load DMA cycle times into the chip ready for a DMA transfer
	121	* to occur.
	122	*/
85cd7251	123
ada406c8	124	static void pdc202xx_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	125	{
669a5db4 JG	126	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
63ed7101	127	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
669a5db4 JG	128	static u8 udma_timing[6][2] = {
	129	{ 0x60, 0x03 }, /* 33 Mhz Clock */
	130	{ 0x40, 0x02 },
	131	{ 0x20, 0x01 },
	132	{ 0x40, 0x02 }, /* 66 Mhz Clock */
	133	{ 0x20, 0x01 },
85cd7251	134	{ 0x20, 0x01 }
669a5db4	135	};
63ed7101 BZ	136	static u8 mdma_timing[3][2] = {
	137	{ 0x60, 0x03 },
	138	{ 0x60, 0x04 },
	139	{ 0xe0, 0x0f },
	140	};
669a5db4	141	u8 r_bp, r_cp;
85cd7251	142
669a5db4 JG	143	pci_read_config_byte(pdev, port + 1, &r_bp);
669a5db4 JG	144	pci_read_config_byte(pdev, port + 2, &r_cp);
85cd7251	145
63ed7101	146	r_bp &= ~0xE0;
669a5db4	147	r_cp &= ~0x0F;
85cd7251	148
669a5db4 JG	149	if (adev->dma_mode >= XFER_UDMA_0) {
	150	int speed = adev->dma_mode - XFER_UDMA_0;
	151	r_bp \|= udma_timing[speed][0];
	152	r_cp \|= udma_timing[speed][1];
85cd7251	153
669a5db4 JG	154	} else {
669a5db4 JG	155	int speed = adev->dma_mode - XFER_MW_DMA_0;
63ed7101 BZ	156	r_bp \|= mdma_timing[speed][0];
63ed7101 BZ	157	r_cp \|= mdma_timing[speed][1];
669a5db4 JG	158	}
	159	pci_write_config_byte(pdev, port + 1, r_bp);
	160	pci_write_config_byte(pdev, port + 2, r_cp);
85cd7251	161
669a5db4 JG	162	}
	163
	164	/**
	165	* pdc2026x_bmdma_start - DMA engine begin
	166	* @qc: ATA command
	167	*
	168	* In UDMA3 or higher we have to clock switch for the duration of the
	169	* DMA transfer sequence.
	170	*/
85cd7251	171
669a5db4 JG	172	static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
	173	{
	174	struct ata_port *ap = qc->ap;
	175	struct ata_device *adev = qc->dev;
	176	struct ata_taskfile *tf = &qc->tf;
	177	int sel66 = ap->port_no ? 0x08: 0x02;
	178
0d5ff566 TH	179	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	180	void __iomem *clock = master + 0x11;
	181	void __iomem atapi_reg = master + 0x20 + (4 ap->port_no);
85cd7251	182
669a5db4	183	u32 len;
85cd7251	184
669a5db4 JG	185	/* Check we keep host level locking here */
669a5db4 JG	186	if (adev->dma_mode >= XFER_UDMA_2)
0d5ff566	187	iowrite8(ioread8(clock) \| sel66, clock);
669a5db4	188	else
0d5ff566	189	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	190
85cd7251	191	/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
669a5db4	192	and move to qc_issue ? */
ada406c8	193	pdc202xx_set_dmamode(ap, qc->dev);
669a5db4 JG	194
	195	/* Cases the state machine will not complete correctly without help */
	196	if ((tf->flags & ATA_TFLAG_LBA48) \|\| tf->protocol == ATA_PROT_ATAPI_DMA)
	197	{
726f0785	198	len = qc->nbytes;
85cd7251	199
669a5db4 JG	200	if (tf->flags & ATA_TFLAG_WRITE)
	201	len \|= 0x06000000;
	202	else
	203	len \|= 0x05000000;
85cd7251	204
0d5ff566	205	iowrite32(len, atapi_reg);
669a5db4	206	}
85cd7251 JG	207
85cd7251 JG	208	/* Activate DMA */
669a5db4 JG	209	ata_bmdma_start(qc);
	210	}
	211
	212	/**
	213	* pdc2026x_bmdma_end - DMA engine stop
	214	* @qc: ATA command
	215	*
	216	* After a DMA completes we need to put the clock back to 33MHz for
	217	* PIO timings.
	218	*/
85cd7251	219
669a5db4 JG	220	static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
	221	{
	222	struct ata_port *ap = qc->ap;
	223	struct ata_device *adev = qc->dev;
	224	struct ata_taskfile *tf = &qc->tf;
85cd7251	225
669a5db4 JG	226	int sel66 = ap->port_no ? 0x08: 0x02;
669a5db4 JG	227	/* The clock bits are in the same register for both channels */
0d5ff566 TH	228	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	229	void __iomem *clock = master + 0x11;
	230	void __iomem atapi_reg = master + 0x20 + (4 ap->port_no);
85cd7251	231
669a5db4 JG	232	/* Cases the state machine will not complete correctly */
669a5db4 JG	233	if (tf->protocol == ATA_PROT_ATAPI_DMA \|\| ( tf->flags & ATA_TFLAG_LBA48)) {
0d5ff566 TH	234	iowrite32(0, atapi_reg);
0d5ff566 TH	235	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4 JG	236	}
	237	/* Check we keep host level locking here */
	238	/* Flip back to 33Mhz for PIO */
	239	if (adev->dma_mode >= XFER_UDMA_2)
0d5ff566	240	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4 JG	241
	242	ata_bmdma_stop(qc);
	243	}
	244
	245	/**
	246	* pdc2026x_dev_config - device setup hook
	247	* @ap: ATA port
	248	* @adev: newly found device
	249	*
	250	* Perform chip specific early setup. We need to lock the transfer
	251	* sizes to 8bit to avoid making the state engine on the 2026x cards
	252	* barf.
	253	*/
85cd7251	254
669a5db4 JG	255	static void pdc2026x_dev_config(struct ata_port ap, struct ata_device adev)
	256	{
	257	adev->max_sectors = 256;
	258	}
	259
ada406c8	260	static struct scsi_host_template pdc202xx_sht = {
669a5db4 JG	261	.module = THIS_MODULE,
	262	.name = DRV_NAME,
	263	.ioctl = ata_scsi_ioctl,
	264	.queuecommand = ata_scsi_queuecmd,
	265	.can_queue = ATA_DEF_QUEUE,
	266	.this_id = ATA_SHT_THIS_ID,
	267	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	268	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	269	.emulated = ATA_SHT_EMULATED,
	270	.use_clustering = ATA_SHT_USE_CLUSTERING,
	271	.proc_name = DRV_NAME,
	272	.dma_boundary = ATA_DMA_BOUNDARY,
	273	.slave_configure = ata_scsi_slave_config,
afdfe899	274	.slave_destroy = ata_scsi_slave_destroy,
669a5db4	275	.bios_param = ata_std_bios_param,
438ac6d5	276	#ifdef CONFIG_PM
62d64ae0 AC	277	.resume = ata_scsi_device_resume,
62d64ae0 AC	278	.suspend = ata_scsi_device_suspend,
438ac6d5	279	#endif
669a5db4 JG	280	};
	281
	282	static struct ata_port_operations pdc2024x_port_ops = {
	283	.port_disable = ata_port_disable,
ada406c8 AC	284	.set_piomode = pdc202xx_set_piomode,
ada406c8 AC	285	.set_dmamode = pdc202xx_set_dmamode,
669a5db4 JG	286	.mode_filter = ata_pci_default_filter,
	287	.tf_load = ata_tf_load,
	288	.tf_read = ata_tf_read,
	289	.check_status = ata_check_status,
	290	.exec_command = ata_exec_command,
	291	.dev_select = ata_std_dev_select,
	292
	293	.freeze = ata_bmdma_freeze,
	294	.thaw = ata_bmdma_thaw,
	295	.error_handler = pdc2024x_error_handler,
	296	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	297
	298	.bmdma_setup = ata_bmdma_setup,
	299	.bmdma_start = ata_bmdma_start,
	300	.bmdma_stop = ata_bmdma_stop,
	301	.bmdma_status = ata_bmdma_status,
	302
	303	.qc_prep = ata_qc_prep,
	304	.qc_issue = ata_qc_issue_prot,
0d5ff566	305	.data_xfer = ata_data_xfer,
669a5db4 JG	306
	307	.irq_handler = ata_interrupt,
	308	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	309	.irq_on = ata_irq_on,
246ce3b6 AI	310	.irq_ack = ata_irq_ack,
85cd7251	311
669a5db4	312	.port_start = ata_port_start,
85cd7251	313	};
669a5db4 JG	314
	315	static struct ata_port_operations pdc2026x_port_ops = {
	316	.port_disable = ata_port_disable,
ada406c8 AC	317	.set_piomode = pdc202xx_set_piomode,
ada406c8 AC	318	.set_dmamode = pdc202xx_set_dmamode,
669a5db4 JG	319	.mode_filter = ata_pci_default_filter,
	320	.tf_load = ata_tf_load,
	321	.tf_read = ata_tf_read,
	322	.check_status = ata_check_status,
	323	.exec_command = ata_exec_command,
	324	.dev_select = ata_std_dev_select,
	325	.dev_config = pdc2026x_dev_config,
	326
	327	.freeze = ata_bmdma_freeze,
	328	.thaw = ata_bmdma_thaw,
	329	.error_handler = pdc2026x_error_handler,
	330	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	331
	332	.bmdma_setup = ata_bmdma_setup,
	333	.bmdma_start = pdc2026x_bmdma_start,
	334	.bmdma_stop = pdc2026x_bmdma_stop,
	335	.bmdma_status = ata_bmdma_status,
	336
	337	.qc_prep = ata_qc_prep,
	338	.qc_issue = ata_qc_issue_prot,
0d5ff566	339	.data_xfer = ata_data_xfer,
669a5db4 JG	340
	341	.irq_handler = ata_interrupt,
	342	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	343	.irq_on = ata_irq_on,
246ce3b6 AI	344	.irq_ack = ata_irq_ack,
85cd7251	345
669a5db4	346	.port_start = ata_port_start,
85cd7251	347	};
669a5db4	348
ada406c8	349	static int pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	350	{
	351	static struct ata_port_info info[3] = {
	352	{
ada406c8	353	.sht = &pdc202xx_sht,
669a5db4 JG	354	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	355	.pio_mask = 0x1f,
	356	.mwdma_mask = 0x07,
	357	.udma_mask = ATA_UDMA2,
	358	.port_ops = &pdc2024x_port_ops
85cd7251	359	},
669a5db4	360	{
ada406c8	361	.sht = &pdc202xx_sht,
669a5db4 JG	362	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	363	.pio_mask = 0x1f,
	364	.mwdma_mask = 0x07,
	365	.udma_mask = ATA_UDMA4,
	366	.port_ops = &pdc2026x_port_ops
	367	},
	368	{
ada406c8	369	.sht = &pdc202xx_sht,
669a5db4 JG	370	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	371	.pio_mask = 0x1f,
	372	.mwdma_mask = 0x07,
	373	.udma_mask = ATA_UDMA5,
	374	.port_ops = &pdc2026x_port_ops
	375	}
85cd7251	376
669a5db4 JG	377	};
	378	static struct ata_port_info *port_info[2];
	379
	380	port_info[0] = port_info[1] = &info[id->driver_data];
85cd7251	381
669a5db4 JG	382	if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
	383	struct pci_dev *bridge = dev->bus->self;
	384	/* Don't grab anything behind a Promise I2O RAID */
	385	if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
	386	if( bridge->device == PCI_DEVICE_ID_INTEL_I960)
	387	return -ENODEV;
	388	if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
	389	return -ENODEV;
	390	}
	391	}
	392	return ata_pci_init_one(dev, port_info, 2);
	393	}
	394
ada406c8	395	static const struct pci_device_id pdc202xx[] = {
2d2744fc JG	396	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	397	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	398	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	399	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	400	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
	401
	402	{ },
669a5db4 JG	403	};
669a5db4 JG	404
ada406c8	405	static struct pci_driver pdc202xx_pci_driver = {
2d2744fc	406	.name = DRV_NAME,
ada406c8 AC	407	.id_table = pdc202xx,
ada406c8 AC	408	.probe = pdc202xx_init_one,
62d64ae0	409	.remove = ata_pci_remove_one,
438ac6d5	410	#ifdef CONFIG_PM
62d64ae0 AC	411	.suspend = ata_pci_device_suspend,
62d64ae0 AC	412	.resume = ata_pci_device_resume,
438ac6d5	413	#endif
669a5db4 JG	414	};
669a5db4 JG	415
ada406c8	416	static int __init pdc202xx_init(void)
669a5db4	417	{
ada406c8	418	return pci_register_driver(&pdc202xx_pci_driver);
669a5db4 JG	419	}
669a5db4 JG	420
ada406c8	421	static void __exit pdc202xx_exit(void)
669a5db4	422	{
ada406c8	423	pci_unregister_driver(&pdc202xx_pci_driver);
669a5db4 JG	424	}
669a5db4 JG	425
669a5db4 JG	426	MODULE_AUTHOR("Alan Cox");
	427	MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
	428	MODULE_LICENSE("GPL");
ada406c8	429	MODULE_DEVICE_TABLE(pci, pdc202xx);
669a5db4 JG	430	MODULE_VERSION(DRV_VERSION);
669a5db4 JG	431
ada406c8 AC	432	module_init(pdc202xx_init);
ada406c8 AC	433	module_exit(pdc202xx_exit);