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Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
63ed7101 | 5 | * (C) 2007 Bartlomiej Zolnierkiewicz |
669a5db4 JG |
6 | * |
7 | * Based in part on linux/drivers/ide/pci/pdc202xx_old.c | |
8 | * | |
9 | * First cut with LBA48/ATAPI | |
10 | * | |
11 | * TODO: | |
63ed7101 | 12 | * Channel interlock/reset on both required |
669a5db4 | 13 | */ |
85cd7251 | 14 | |
669a5db4 JG |
15 | #include <linux/kernel.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/blkdev.h> | |
20 | #include <linux/delay.h> | |
21 | #include <scsi/scsi_host.h> | |
22 | #include <linux/libata.h> | |
23 | ||
24 | #define DRV_NAME "pata_pdc202xx_old" | |
a0fcdc02 | 25 | #define DRV_VERSION "0.4.2" |
669a5db4 | 26 | |
a0fcdc02 | 27 | static int pdc2026x_cable_detect(struct ata_port *ap) |
669a5db4 JG |
28 | { |
29 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
30 | u16 cis; | |
85cd7251 | 31 | |
669a5db4 JG |
32 | pci_read_config_word(pdev, 0x50, &cis); |
33 | if (cis & (1 << (10 + ap->port_no))) | |
a0ac38f1 AC |
34 | return ATA_CBL_PATA40; |
35 | return ATA_CBL_PATA80; | |
669a5db4 JG |
36 | } |
37 | ||
38 | /** | |
ada406c8 | 39 | * pdc202xx_configure_piomode - set chip PIO timing |
669a5db4 JG |
40 | * @ap: ATA interface |
41 | * @adev: ATA device | |
42 | * @pio: PIO mode | |
43 | * | |
44 | * Called to do the PIO mode setup. Our timing registers are shared | |
45 | * so a configure_dmamode call will undo any work we do here and vice | |
46 | * versa | |
47 | */ | |
85cd7251 | 48 | |
ada406c8 | 49 | static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio) |
669a5db4 JG |
50 | { |
51 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
63ed7101 | 52 | int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; |
669a5db4 JG |
53 | static u16 pio_timing[5] = { |
54 | 0x0913, 0x050C , 0x0308, 0x0206, 0x0104 | |
55 | }; | |
56 | u8 r_ap, r_bp; | |
57 | ||
58 | pci_read_config_byte(pdev, port, &r_ap); | |
59 | pci_read_config_byte(pdev, port + 1, &r_bp); | |
60 | r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */ | |
63ed7101 | 61 | r_bp &= ~0x1F; |
669a5db4 JG |
62 | r_ap |= (pio_timing[pio] >> 8); |
63 | r_bp |= (pio_timing[pio] & 0xFF); | |
85cd7251 | 64 | |
669a5db4 JG |
65 | if (ata_pio_need_iordy(adev)) |
66 | r_ap |= 0x20; /* IORDY enable */ | |
67 | if (adev->class == ATA_DEV_ATA) | |
68 | r_ap |= 0x10; /* FIFO enable */ | |
69 | pci_write_config_byte(pdev, port, r_ap); | |
70 | pci_write_config_byte(pdev, port + 1, r_bp); | |
71 | } | |
72 | ||
73 | /** | |
ada406c8 | 74 | * pdc202xx_set_piomode - set initial PIO mode data |
669a5db4 JG |
75 | * @ap: ATA interface |
76 | * @adev: ATA device | |
77 | * | |
78 | * Called to do the PIO mode setup. Our timing registers are shared | |
79 | * but we want to set the PIO timing by default. | |
80 | */ | |
85cd7251 | 81 | |
ada406c8 | 82 | static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 | 83 | { |
ada406c8 | 84 | pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); |
669a5db4 JG |
85 | } |
86 | ||
87 | /** | |
ada406c8 | 88 | * pdc202xx_configure_dmamode - set DMA mode in chip |
669a5db4 JG |
89 | * @ap: ATA interface |
90 | * @adev: ATA device | |
91 | * | |
92 | * Load DMA cycle times into the chip ready for a DMA transfer | |
93 | * to occur. | |
94 | */ | |
85cd7251 | 95 | |
ada406c8 | 96 | static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
97 | { |
98 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
63ed7101 | 99 | int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; |
669a5db4 JG |
100 | static u8 udma_timing[6][2] = { |
101 | { 0x60, 0x03 }, /* 33 Mhz Clock */ | |
102 | { 0x40, 0x02 }, | |
103 | { 0x20, 0x01 }, | |
104 | { 0x40, 0x02 }, /* 66 Mhz Clock */ | |
105 | { 0x20, 0x01 }, | |
85cd7251 | 106 | { 0x20, 0x01 } |
669a5db4 | 107 | }; |
63ed7101 BZ |
108 | static u8 mdma_timing[3][2] = { |
109 | { 0x60, 0x03 }, | |
110 | { 0x60, 0x04 }, | |
111 | { 0xe0, 0x0f }, | |
112 | }; | |
669a5db4 | 113 | u8 r_bp, r_cp; |
85cd7251 | 114 | |
669a5db4 JG |
115 | pci_read_config_byte(pdev, port + 1, &r_bp); |
116 | pci_read_config_byte(pdev, port + 2, &r_cp); | |
85cd7251 | 117 | |
63ed7101 | 118 | r_bp &= ~0xE0; |
669a5db4 | 119 | r_cp &= ~0x0F; |
85cd7251 | 120 | |
669a5db4 JG |
121 | if (adev->dma_mode >= XFER_UDMA_0) { |
122 | int speed = adev->dma_mode - XFER_UDMA_0; | |
123 | r_bp |= udma_timing[speed][0]; | |
124 | r_cp |= udma_timing[speed][1]; | |
85cd7251 | 125 | |
669a5db4 JG |
126 | } else { |
127 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
63ed7101 BZ |
128 | r_bp |= mdma_timing[speed][0]; |
129 | r_cp |= mdma_timing[speed][1]; | |
669a5db4 JG |
130 | } |
131 | pci_write_config_byte(pdev, port + 1, r_bp); | |
132 | pci_write_config_byte(pdev, port + 2, r_cp); | |
85cd7251 | 133 | |
669a5db4 JG |
134 | } |
135 | ||
136 | /** | |
137 | * pdc2026x_bmdma_start - DMA engine begin | |
138 | * @qc: ATA command | |
139 | * | |
140 | * In UDMA3 or higher we have to clock switch for the duration of the | |
141 | * DMA transfer sequence. | |
142 | */ | |
85cd7251 | 143 | |
669a5db4 JG |
144 | static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc) |
145 | { | |
146 | struct ata_port *ap = qc->ap; | |
147 | struct ata_device *adev = qc->dev; | |
148 | struct ata_taskfile *tf = &qc->tf; | |
149 | int sel66 = ap->port_no ? 0x08: 0x02; | |
150 | ||
0d5ff566 TH |
151 | void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; |
152 | void __iomem *clock = master + 0x11; | |
153 | void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); | |
85cd7251 | 154 | |
669a5db4 | 155 | u32 len; |
85cd7251 | 156 | |
669a5db4 JG |
157 | /* Check we keep host level locking here */ |
158 | if (adev->dma_mode >= XFER_UDMA_2) | |
0d5ff566 | 159 | iowrite8(ioread8(clock) | sel66, clock); |
669a5db4 | 160 | else |
0d5ff566 | 161 | iowrite8(ioread8(clock) & ~sel66, clock); |
669a5db4 | 162 | |
85cd7251 | 163 | /* The DMA clocks may have been trashed by a reset. FIXME: make conditional |
669a5db4 | 164 | and move to qc_issue ? */ |
ada406c8 | 165 | pdc202xx_set_dmamode(ap, qc->dev); |
669a5db4 JG |
166 | |
167 | /* Cases the state machine will not complete correctly without help */ | |
168 | if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATA_PROT_ATAPI_DMA) | |
169 | { | |
5e518810 | 170 | len = qc->nbytes / 2; |
85cd7251 | 171 | |
669a5db4 JG |
172 | if (tf->flags & ATA_TFLAG_WRITE) |
173 | len |= 0x06000000; | |
174 | else | |
175 | len |= 0x05000000; | |
85cd7251 | 176 | |
0d5ff566 | 177 | iowrite32(len, atapi_reg); |
669a5db4 | 178 | } |
85cd7251 JG |
179 | |
180 | /* Activate DMA */ | |
669a5db4 JG |
181 | ata_bmdma_start(qc); |
182 | } | |
183 | ||
184 | /** | |
185 | * pdc2026x_bmdma_end - DMA engine stop | |
186 | * @qc: ATA command | |
187 | * | |
188 | * After a DMA completes we need to put the clock back to 33MHz for | |
189 | * PIO timings. | |
190 | */ | |
85cd7251 | 191 | |
669a5db4 JG |
192 | static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc) |
193 | { | |
194 | struct ata_port *ap = qc->ap; | |
195 | struct ata_device *adev = qc->dev; | |
196 | struct ata_taskfile *tf = &qc->tf; | |
85cd7251 | 197 | |
669a5db4 JG |
198 | int sel66 = ap->port_no ? 0x08: 0x02; |
199 | /* The clock bits are in the same register for both channels */ | |
0d5ff566 TH |
200 | void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; |
201 | void __iomem *clock = master + 0x11; | |
202 | void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); | |
85cd7251 | 203 | |
669a5db4 JG |
204 | /* Cases the state machine will not complete correctly */ |
205 | if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) { | |
0d5ff566 TH |
206 | iowrite32(0, atapi_reg); |
207 | iowrite8(ioread8(clock) & ~sel66, clock); | |
669a5db4 JG |
208 | } |
209 | /* Check we keep host level locking here */ | |
210 | /* Flip back to 33Mhz for PIO */ | |
211 | if (adev->dma_mode >= XFER_UDMA_2) | |
0d5ff566 | 212 | iowrite8(ioread8(clock) & ~sel66, clock); |
669a5db4 JG |
213 | |
214 | ata_bmdma_stop(qc); | |
215 | } | |
216 | ||
217 | /** | |
218 | * pdc2026x_dev_config - device setup hook | |
669a5db4 JG |
219 | * @adev: newly found device |
220 | * | |
221 | * Perform chip specific early setup. We need to lock the transfer | |
222 | * sizes to 8bit to avoid making the state engine on the 2026x cards | |
223 | * barf. | |
224 | */ | |
85cd7251 | 225 | |
cd0d3bbc | 226 | static void pdc2026x_dev_config(struct ata_device *adev) |
669a5db4 JG |
227 | { |
228 | adev->max_sectors = 256; | |
229 | } | |
230 | ||
ada406c8 | 231 | static struct scsi_host_template pdc202xx_sht = { |
669a5db4 JG |
232 | .module = THIS_MODULE, |
233 | .name = DRV_NAME, | |
234 | .ioctl = ata_scsi_ioctl, | |
235 | .queuecommand = ata_scsi_queuecmd, | |
236 | .can_queue = ATA_DEF_QUEUE, | |
237 | .this_id = ATA_SHT_THIS_ID, | |
238 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
239 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
240 | .emulated = ATA_SHT_EMULATED, | |
241 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
242 | .proc_name = DRV_NAME, | |
243 | .dma_boundary = ATA_DMA_BOUNDARY, | |
244 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 245 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
246 | .bios_param = ata_std_bios_param, |
247 | }; | |
248 | ||
249 | static struct ata_port_operations pdc2024x_port_ops = { | |
ada406c8 AC |
250 | .set_piomode = pdc202xx_set_piomode, |
251 | .set_dmamode = pdc202xx_set_dmamode, | |
669a5db4 JG |
252 | .mode_filter = ata_pci_default_filter, |
253 | .tf_load = ata_tf_load, | |
254 | .tf_read = ata_tf_read, | |
255 | .check_status = ata_check_status, | |
256 | .exec_command = ata_exec_command, | |
257 | .dev_select = ata_std_dev_select, | |
258 | ||
259 | .freeze = ata_bmdma_freeze, | |
260 | .thaw = ata_bmdma_thaw, | |
a0fcdc02 | 261 | .error_handler = ata_bmdma_error_handler, |
669a5db4 | 262 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a0fcdc02 | 263 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
264 | |
265 | .bmdma_setup = ata_bmdma_setup, | |
266 | .bmdma_start = ata_bmdma_start, | |
267 | .bmdma_stop = ata_bmdma_stop, | |
268 | .bmdma_status = ata_bmdma_status, | |
269 | ||
270 | .qc_prep = ata_qc_prep, | |
271 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 272 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
273 | |
274 | .irq_handler = ata_interrupt, | |
275 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 | 276 | .irq_on = ata_irq_on, |
85cd7251 | 277 | |
669a5db4 | 278 | .port_start = ata_port_start, |
85cd7251 | 279 | }; |
669a5db4 JG |
280 | |
281 | static struct ata_port_operations pdc2026x_port_ops = { | |
ada406c8 AC |
282 | .set_piomode = pdc202xx_set_piomode, |
283 | .set_dmamode = pdc202xx_set_dmamode, | |
669a5db4 JG |
284 | .mode_filter = ata_pci_default_filter, |
285 | .tf_load = ata_tf_load, | |
286 | .tf_read = ata_tf_read, | |
287 | .check_status = ata_check_status, | |
288 | .exec_command = ata_exec_command, | |
289 | .dev_select = ata_std_dev_select, | |
290 | .dev_config = pdc2026x_dev_config, | |
291 | ||
292 | .freeze = ata_bmdma_freeze, | |
293 | .thaw = ata_bmdma_thaw, | |
a0fcdc02 | 294 | .error_handler = ata_bmdma_error_handler, |
669a5db4 | 295 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a0fcdc02 | 296 | .cable_detect = pdc2026x_cable_detect, |
669a5db4 JG |
297 | |
298 | .bmdma_setup = ata_bmdma_setup, | |
299 | .bmdma_start = pdc2026x_bmdma_start, | |
300 | .bmdma_stop = pdc2026x_bmdma_stop, | |
301 | .bmdma_status = ata_bmdma_status, | |
302 | ||
303 | .qc_prep = ata_qc_prep, | |
304 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 305 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
306 | |
307 | .irq_handler = ata_interrupt, | |
308 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 | 309 | .irq_on = ata_irq_on, |
85cd7251 | 310 | |
669a5db4 | 311 | .port_start = ata_port_start, |
85cd7251 | 312 | }; |
669a5db4 | 313 | |
ada406c8 | 314 | static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
669a5db4 | 315 | { |
1626aeb8 | 316 | static const struct ata_port_info info[3] = { |
669a5db4 | 317 | { |
ada406c8 | 318 | .sht = &pdc202xx_sht, |
1d2808fd | 319 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
320 | .pio_mask = 0x1f, |
321 | .mwdma_mask = 0x07, | |
322 | .udma_mask = ATA_UDMA2, | |
323 | .port_ops = &pdc2024x_port_ops | |
85cd7251 | 324 | }, |
669a5db4 | 325 | { |
ada406c8 | 326 | .sht = &pdc202xx_sht, |
1d2808fd | 327 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
328 | .pio_mask = 0x1f, |
329 | .mwdma_mask = 0x07, | |
330 | .udma_mask = ATA_UDMA4, | |
331 | .port_ops = &pdc2026x_port_ops | |
332 | }, | |
333 | { | |
ada406c8 | 334 | .sht = &pdc202xx_sht, |
1d2808fd | 335 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
336 | .pio_mask = 0x1f, |
337 | .mwdma_mask = 0x07, | |
338 | .udma_mask = ATA_UDMA5, | |
339 | .port_ops = &pdc2026x_port_ops | |
340 | } | |
85cd7251 | 341 | |
669a5db4 | 342 | }; |
1626aeb8 | 343 | const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL }; |
85cd7251 | 344 | |
669a5db4 JG |
345 | if (dev->device == PCI_DEVICE_ID_PROMISE_20265) { |
346 | struct pci_dev *bridge = dev->bus->self; | |
347 | /* Don't grab anything behind a Promise I2O RAID */ | |
348 | if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) { | |
349 | if( bridge->device == PCI_DEVICE_ID_INTEL_I960) | |
350 | return -ENODEV; | |
351 | if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM) | |
352 | return -ENODEV; | |
353 | } | |
354 | } | |
1626aeb8 | 355 | return ata_pci_init_one(dev, ppi); |
669a5db4 JG |
356 | } |
357 | ||
ada406c8 | 358 | static const struct pci_device_id pdc202xx[] = { |
2d2744fc JG |
359 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, |
360 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, | |
361 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, | |
362 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, | |
363 | { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, | |
364 | ||
365 | { }, | |
669a5db4 JG |
366 | }; |
367 | ||
ada406c8 | 368 | static struct pci_driver pdc202xx_pci_driver = { |
2d2744fc | 369 | .name = DRV_NAME, |
ada406c8 AC |
370 | .id_table = pdc202xx, |
371 | .probe = pdc202xx_init_one, | |
62d64ae0 | 372 | .remove = ata_pci_remove_one, |
438ac6d5 | 373 | #ifdef CONFIG_PM |
62d64ae0 AC |
374 | .suspend = ata_pci_device_suspend, |
375 | .resume = ata_pci_device_resume, | |
438ac6d5 | 376 | #endif |
669a5db4 JG |
377 | }; |
378 | ||
ada406c8 | 379 | static int __init pdc202xx_init(void) |
669a5db4 | 380 | { |
ada406c8 | 381 | return pci_register_driver(&pdc202xx_pci_driver); |
669a5db4 JG |
382 | } |
383 | ||
ada406c8 | 384 | static void __exit pdc202xx_exit(void) |
669a5db4 | 385 | { |
ada406c8 | 386 | pci_unregister_driver(&pdc202xx_pci_driver); |
669a5db4 JG |
387 | } |
388 | ||
669a5db4 JG |
389 | MODULE_AUTHOR("Alan Cox"); |
390 | MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267"); | |
391 | MODULE_LICENSE("GPL"); | |
ada406c8 | 392 | MODULE_DEVICE_TABLE(pci, pdc202xx); |
669a5db4 JG |
393 | MODULE_VERSION(DRV_VERSION); |
394 | ||
ada406c8 AC |
395 | module_init(pdc202xx_init); |
396 | module_exit(pdc202xx_exit); |