[mirror_ubuntu-artful-kernel.git] / drivers / ata / pata_radisys.c

/*
 *    pata_radisys.c - Intel PATA/SATA controllers
 *
 *	(C) 2006 Red Hat <alan@lxorguk.ukuu.org.uk>
 *
 *    Some parts based on ata_piix.c by Jeff Garzik and others.
 *
 *    A PIIX relative, this device has a single ATA channel and no
 *    slave timings, SITRE or PPE. In that sense it is a close relative
 *    of the original PIIX. It does however support UDMA 33/66 per channel
 *    although no other modes/timings. Also lacking is 32bit I/O on the ATA
 *    port.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_radisys"
#define DRV_VERSION	"0.4.4"

/**
 *	radisys_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: ATA port
 *	@adev: Device whose timings we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void radisys_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	u16 idetm_data;
	int control = 0;

	/*
	 *	See Intel Document 298600-004 for the timing programing rules
	 *	for PIIX/ICH. Note that the early PIIX does not have the slave
	 *	timing port at 0x44. The Radisys is a relative of the PIIX
	 *	but not the same so be careful.
	 */

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },	/* Check me */
			    { 0, 0 },
			    { 1, 1 },
			    { 2, 2 },
			    { 3, 3 }, };

	if (pio > 0)
		control |= 1;	/* TIME1 enable */
	if (ata_pio_need_iordy(adev))
		control |= 2;	/* IE IORDY */

	pci_read_config_word(dev, 0x40, &idetm_data);

	/* Enable IE and TIME as appropriate. Clear the other
	   drive timing bits */
	idetm_data &= 0xCCCC;
	idetm_data |= (control << (4 * adev->devno));
	idetm_data |= (timings[pio][0] << 12) |
			(timings[pio][1] << 8);
	pci_write_config_word(dev, 0x40, idetm_data);

	/* Track which port is configured */
	ap->private_data = adev;
}

/**
 *	radisys_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device to program
 *
 *	Set MWDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void radisys_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	u16 idetm_data;
	u8 udma_enable;

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 1 },
			    { 2, 2 },
			    { 3, 3 }, };

	/*
	 * MWDMA is driven by the PIO timings. We must also enable
	 * IORDY unconditionally.
	 */

	pci_read_config_word(dev, 0x40, &idetm_data);
	pci_read_config_byte(dev, 0x48, &udma_enable);

	if (adev->dma_mode < XFER_UDMA_0) {
		unsigned int mwdma	= adev->dma_mode - XFER_MW_DMA_0;
		const unsigned int needed_pio[3] = {
			XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
		};
		int pio = needed_pio[mwdma] - XFER_PIO_0;
		int control = 3;	/* IORDY|TIME0 */

		/* If the drive MWDMA is faster than it can do PIO then
		   we must force PIO0 for PIO cycles. */

		if (adev->pio_mode < needed_pio[mwdma])
			control = 1;

		/* Mask out the relevant control and timing bits we will load. Also
		   clear the other drive TIME register as a precaution */

		idetm_data &= 0xCCCC;
		idetm_data |= control << (4 * adev->devno);
		idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);

		udma_enable &= ~(1 << adev->devno);
	} else {
		u8 udma_mode;

		/* UDMA66 on: UDMA 33 and 66 are switchable via register 0x4A */

		pci_read_config_byte(dev, 0x4A, &udma_mode);

		if (adev->xfer_mode == XFER_UDMA_2)
			udma_mode &= ~(2 << (adev->devno * 4));
		else /* UDMA 4 */
			udma_mode |= (2 << (adev->devno * 4));

		pci_write_config_byte(dev, 0x4A, udma_mode);

		udma_enable |= (1 << adev->devno);
	}
	pci_write_config_word(dev, 0x40, idetm_data);
	pci_write_config_byte(dev, 0x48, udma_enable);

	/* Track which port is configured */
	ap->private_data = adev;
}

/**
 *	radisys_qc_issue	-	command issue
 *	@qc: command pending
 *
 *	Called when the libata layer is about to issue a command. We wrap
 *	this interface so that we can load the correct ATA timings if
 *	necessary. Our logic also clears TIME0/TIME1 for the other device so
 *	that, even if we get this wrong, cycles to the other device will
 *	be made PIO0.
 */

static unsigned int radisys_qc_issue(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;

	if (adev != ap->private_data) {
		/* UDMA timing is not shared */
		if (adev->dma_mode < XFER_UDMA_0) {
			if (adev->dma_mode)
				radisys_set_dmamode(ap, adev);
			else if (adev->pio_mode)
				radisys_set_piomode(ap, adev);
		}
	}
	return ata_bmdma_qc_issue(qc);
}


static struct scsi_host_template radisys_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations radisys_pata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.qc_issue		= radisys_qc_issue,
	.cable_detect		= ata_cable_unknown,
	.set_piomode		= radisys_set_piomode,
	.set_dmamode		= radisys_set_dmamode,
};


/**
 *	radisys_init_one - Register PIIX ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in radisys_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.  We probe for combined mode (sigh),
 *	and then hand over control to libata, for it to do the rest.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int radisys_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static const struct ata_port_info info = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA12_ONLY,
		.udma_mask	= ATA_UDMA24_ONLY,
		.port_ops	= &radisys_pata_ops,
	};
	const struct ata_port_info *ppi[] = { &info, NULL };

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	return ata_pci_bmdma_init_one(pdev, ppi, &radisys_sht, NULL, 0);
}

static const struct pci_device_id radisys_pci_tbl[] = {
	{ PCI_VDEVICE(RADISYS, 0x8201), },

	{ }	/* terminate list */
};

static struct pci_driver radisys_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= radisys_pci_tbl,
	.probe			= radisys_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
};

module_pci_driver(radisys_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for Radisys R82600 controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, radisys_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_radisys.c - Intel PATA/SATA controllers
	3	*
ab771630	4	* (C) 2006 Red Hat <alan@lxorguk.ukuu.org.uk>
669a5db4 JG	5	*
	6	* Some parts based on ata_piix.c by Jeff Garzik and others.
	7	*
	8	* A PIIX relative, this device has a single ATA channel and no
	9	* slave timings, SITRE or PPE. In that sense it is a close relative
	10	* of the original PIIX. It does however support UDMA 33/66 per channel
	11	* although no other modes/timings. Also lacking is 32bit I/O on the ATA
	12	* port.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/pci.h>
669a5db4 JG	18	#include <linux/blkdev.h>
	19	#include <linux/delay.h>
	20	#include <linux/device.h>
	21	#include <scsi/scsi_host.h>
	22	#include <linux/libata.h>
	23	#include <linux/ata.h>
	24
	25	#define DRV_NAME "pata_radisys"
d36a7648	26	#define DRV_VERSION "0.4.4"
669a5db4 JG	27
	28	/**
	29	* radisys_set_piomode - Initialize host controller PATA PIO timings
d36a7648 AC	30	* @ap: ATA port
d36a7648 AC	31	* @adev: Device whose timings we are configuring
669a5db4 JG	32	*
	33	* Set PIO mode for device, in host controller PCI config space.
	34	*
	35	* LOCKING:
	36	* None (inherited from caller).
	37	*/
	38
	39	static void radisys_set_piomode (struct ata_port ap, struct ata_device adev)
	40	{
	41	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	42	struct pci_dev *dev = to_pci_dev(ap->host->dev);
	43	u16 idetm_data;
	44	int control = 0;
	45
	46	/*
	47	* See Intel Document 298600-004 for the timing programing rules
	48	* for PIIX/ICH. Note that the early PIIX does not have the slave
	49	* timing port at 0x44. The Radisys is a relative of the PIIX
	50	* but not the same so be careful.
	51	*/
	52
	53	static const /* ISP RTC */
	54	u8 timings[][2] = { { 0, 0 }, /* Check me */
	55	{ 0, 0 },
	56	{ 1, 1 },
	57	{ 2, 2 },
	58	{ 3, 3 }, };
	59
	60	if (pio > 0)
	61	control \|= 1; /* TIME1 enable */
	62	if (ata_pio_need_iordy(adev))
	63	control \|= 2; /* IE IORDY */
	64
	65	pci_read_config_word(dev, 0x40, &idetm_data);
	66
	67	/* Enable IE and TIME as appropriate. Clear the other
	68	drive timing bits */
	69	idetm_data &= 0xCCCC;
	70	idetm_data \|= (control << (4 * adev->devno));
	71	idetm_data \|= (timings[pio][0] << 12) \|
	72	(timings[pio][1] << 8);
	73	pci_write_config_word(dev, 0x40, idetm_data);
	74
	75	/* Track which port is configured */
	76	ap->private_data = adev;
	77	}
	78
	79	/**
	80	* radisys_set_dmamode - Initialize host controller PATA DMA timings
	81	* @ap: Port whose timings we are configuring
	82	* @adev: Device to program
669a5db4 JG	83	*
	84	* Set MWDMA mode for device, in host controller PCI config space.
	85	*
	86	* LOCKING:
	87	* None (inherited from caller).
	88	*/
	89
	90	static void radisys_set_dmamode (struct ata_port ap, struct ata_device adev)
	91	{
	92	struct pci_dev *dev = to_pci_dev(ap->host->dev);
	93	u16 idetm_data;
	94	u8 udma_enable;
85cd7251	95
669a5db4 JG	96	static const /* ISP RTC */
	97	u8 timings[][2] = { { 0, 0 },
	98	{ 0, 0 },
	99	{ 1, 1 },
	100	{ 2, 2 },
	101	{ 3, 3 }, };
	102
	103	/*
	104	* MWDMA is driven by the PIO timings. We must also enable
	105	* IORDY unconditionally.
	106	*/
	107
	108	pci_read_config_word(dev, 0x40, &idetm_data);
	109	pci_read_config_byte(dev, 0x48, &udma_enable);
	110
	111	if (adev->dma_mode < XFER_UDMA_0) {
	112	unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
	113	const unsigned int needed_pio[3] = {
	114	XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
	115	};
	116	int pio = needed_pio[mwdma] - XFER_PIO_0;
	117	int control = 3; /* IORDY\|TIME0 */
	118
	119	/* If the drive MWDMA is faster than it can do PIO then
	120	we must force PIO0 for PIO cycles. */
	121
	122	if (adev->pio_mode < needed_pio[mwdma])
	123	control = 1;
	124
	125	/* Mask out the relevant control and timing bits we will load. Also
	126	clear the other drive TIME register as a precaution */
85cd7251	127
669a5db4 JG	128	idetm_data &= 0xCCCC;
	129	idetm_data \|= control << (4 * adev->devno);
	130	idetm_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
	131
	132	udma_enable &= ~(1 << adev->devno);
	133	} else {
	134	u8 udma_mode;
85cd7251	135
669a5db4	136	/* UDMA66 on: UDMA 33 and 66 are switchable via register 0x4A */
85cd7251	137
669a5db4	138	pci_read_config_byte(dev, 0x4A, &udma_mode);
85cd7251	139
669a5db4	140	if (adev->xfer_mode == XFER_UDMA_2)
dd4a43c9	141	udma_mode &= ~(2 << (adev->devno * 4));
669a5db4	142	else /* UDMA 4 */
dd4a43c9	143	udma_mode \|= (2 << (adev->devno * 4));
85cd7251	144
669a5db4	145	pci_write_config_byte(dev, 0x4A, udma_mode);
85cd7251	146
669a5db4 JG	147	udma_enable \|= (1 << adev->devno);
	148	}
	149	pci_write_config_word(dev, 0x40, idetm_data);
	150	pci_write_config_byte(dev, 0x48, udma_enable);
	151
	152	/* Track which port is configured */
	153	ap->private_data = adev;
	154	}
	155
	156	/**
9363c382	157	* radisys_qc_issue - command issue
669a5db4 JG	158	* @qc: command pending
	159	*
	160	* Called when the libata layer is about to issue a command. We wrap
	161	* this interface so that we can load the correct ATA timings if
3a4fa0a2	162	* necessary. Our logic also clears TIME0/TIME1 for the other device so
669a5db4 JG	163	* that, even if we get this wrong, cycles to the other device will
	164	* be made PIO0.
	165	*/
	166
9363c382	167	static unsigned int radisys_qc_issue(struct ata_queued_cmd *qc)
669a5db4 JG	168	{
	169	struct ata_port *ap = qc->ap;
	170	struct ata_device *adev = qc->dev;
	171
	172	if (adev != ap->private_data) {
	173	/* UDMA timing is not shared */
	174	if (adev->dma_mode < XFER_UDMA_0) {
	175	if (adev->dma_mode)
	176	radisys_set_dmamode(ap, adev);
	177	else if (adev->pio_mode)
	178	radisys_set_piomode(ap, adev);
	179	}
	180	}
360ff783	181	return ata_bmdma_qc_issue(qc);
669a5db4 JG	182	}
	183
	184
	185	static struct scsi_host_template radisys_sht = {
68d1d07b	186	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	187	};
669a5db4 JG	188
029cfd6b TH	189	static struct ata_port_operations radisys_pata_ops = {
029cfd6b TH	190	.inherits = &ata_bmdma_port_ops,
9363c382	191	.qc_issue = radisys_qc_issue,
029cfd6b	192	.cable_detect = ata_cable_unknown,
669a5db4 JG	193	.set_piomode = radisys_set_piomode,
669a5db4 JG	194	.set_dmamode = radisys_set_dmamode,
669a5db4 JG	195	};
	196
	197
	198	/**
	199	* radisys_init_one - Register PIIX ATA PCI device with kernel services
	200	* @pdev: PCI device to register
	201	* @ent: Entry in radisys_pci_tbl matching with @pdev
	202	*
	203	* Called from kernel PCI layer. We probe for combined mode (sigh),
	204	* and then hand over control to libata, for it to do the rest.
	205	*
	206	* LOCKING:
	207	* Inherited from PCI layer (may sleep).
	208	*
	209	* RETURNS:
	210	* Zero on success, or -ERRNO value.
	211	*/
	212
	213	static int radisys_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	214	{
1626aeb8	215	static const struct ata_port_info info = {
1d2808fd	216	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98	217	.pio_mask = ATA_PIO4,
aef37d8d	218	.mwdma_mask = ATA_MWDMA12_ONLY,
14bdef98	219	.udma_mask = ATA_UDMA24_ONLY,
669a5db4 JG	220	.port_ops = &radisys_pata_ops,
669a5db4 JG	221	};
1626aeb8	222	const struct ata_port_info *ppi[] = { &info, NULL };
669a5db4	223
06296a1e	224	ata_print_version_once(&pdev->dev, DRV_VERSION);
669a5db4	225
1c5afdf7	226	return ata_pci_bmdma_init_one(pdev, ppi, &radisys_sht, NULL, 0);
669a5db4 JG	227	}
	228
	229	static const struct pci_device_id radisys_pci_tbl[] = {
2d2744fc JG	230	{ PCI_VDEVICE(RADISYS, 0x8201), },
2d2744fc JG	231
669a5db4 JG	232	{ } /* terminate list */
	233	};
	234
	235	static struct pci_driver radisys_pci_driver = {
	236	.name = DRV_NAME,
	237	.id_table = radisys_pci_tbl,
	238	.probe = radisys_init_one,
	239	.remove = ata_pci_remove_one,
58eb8cd5	240	#ifdef CONFIG_PM_SLEEP
30ced0f0 AC	241	.suspend = ata_pci_device_suspend,
30ced0f0 AC	242	.resume = ata_pci_device_resume,
438ac6d5	243	#endif
669a5db4 JG	244	};
669a5db4 JG	245
2fc75da0	246	module_pci_driver(radisys_pci_driver);
669a5db4 JG	247
	248	MODULE_AUTHOR("Alan Cox");
	249	MODULE_DESCRIPTION("SCSI low-level driver for Radisys R82600 controllers");
	250	MODULE_LICENSE("GPL");
	251	MODULE_DEVICE_TABLE(pci, radisys_pci_tbl);
	252	MODULE_VERSION(DRV_VERSION);