]>
Commit | Line | Data |
---|---|---|
a619f981 AI |
1 | /* |
2 | * Support for IDE interfaces on Celleb platform | |
3 | * | |
4 | * (C) Copyright 2006 TOSHIBA CORPORATION | |
5 | * | |
6 | * This code is based on drivers/ata/ata_piix.c: | |
7 | * Copyright 2003-2005 Red Hat Inc | |
8 | * Copyright 2003-2005 Jeff Garzik | |
9 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
10 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
ab771630 | 11 | * Copyright (C) 2003 Red Hat Inc |
a619f981 AI |
12 | * |
13 | * and drivers/ata/ahci.c: | |
14 | * Copyright 2004-2005 Red Hat, Inc. | |
15 | * | |
16 | * and drivers/ata/libata-core.c: | |
17 | * Copyright 2003-2004 Red Hat, Inc. All rights reserved. | |
18 | * Copyright 2003-2004 Jeff Garzik | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License along | |
31 | * with this program; if not, write to the Free Software Foundation, Inc., | |
32 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/device.h> | |
42 | #include <scsi/scsi_host.h> | |
43 | #include <linux/libata.h> | |
44 | ||
45 | #define DRV_NAME "pata_scc" | |
2a3103ce | 46 | #define DRV_VERSION "0.3" |
a619f981 AI |
47 | |
48 | #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 | |
49 | ||
50 | /* PCI BARs */ | |
51 | #define SCC_CTRL_BAR 0 | |
52 | #define SCC_BMID_BAR 1 | |
53 | ||
54 | /* offset of CTRL registers */ | |
55 | #define SCC_CTL_PIOSHT 0x000 | |
56 | #define SCC_CTL_PIOCT 0x004 | |
57 | #define SCC_CTL_MDMACT 0x008 | |
58 | #define SCC_CTL_MCRCST 0x00C | |
59 | #define SCC_CTL_SDMACT 0x010 | |
60 | #define SCC_CTL_SCRCST 0x014 | |
61 | #define SCC_CTL_UDENVT 0x018 | |
62 | #define SCC_CTL_TDVHSEL 0x020 | |
63 | #define SCC_CTL_MODEREG 0x024 | |
64 | #define SCC_CTL_ECMODE 0xF00 | |
65 | #define SCC_CTL_MAEA0 0xF50 | |
66 | #define SCC_CTL_MAEC0 0xF54 | |
67 | #define SCC_CTL_CCKCTRL 0xFF0 | |
68 | ||
69 | /* offset of BMID registers */ | |
70 | #define SCC_DMA_CMD 0x000 | |
71 | #define SCC_DMA_STATUS 0x004 | |
72 | #define SCC_DMA_TABLE_OFS 0x008 | |
73 | #define SCC_DMA_INTMASK 0x010 | |
74 | #define SCC_DMA_INTST 0x014 | |
75 | #define SCC_DMA_PTERADD 0x018 | |
76 | #define SCC_REG_CMD_ADDR 0x020 | |
77 | #define SCC_REG_DATA 0x000 | |
78 | #define SCC_REG_ERR 0x004 | |
79 | #define SCC_REG_FEATURE 0x004 | |
80 | #define SCC_REG_NSECT 0x008 | |
81 | #define SCC_REG_LBAL 0x00C | |
82 | #define SCC_REG_LBAM 0x010 | |
83 | #define SCC_REG_LBAH 0x014 | |
84 | #define SCC_REG_DEVICE 0x018 | |
85 | #define SCC_REG_STATUS 0x01C | |
86 | #define SCC_REG_CMD 0x01C | |
87 | #define SCC_REG_ALTSTATUS 0x020 | |
88 | ||
89 | /* register value */ | |
90 | #define TDVHSEL_MASTER 0x00000001 | |
91 | #define TDVHSEL_SLAVE 0x00000004 | |
92 | ||
93 | #define MODE_JCUSFEN 0x00000080 | |
94 | ||
95 | #define ECMODE_VALUE 0x01 | |
96 | ||
97 | #define CCKCTRL_ATARESET 0x00040000 | |
98 | #define CCKCTRL_BUFCNT 0x00020000 | |
99 | #define CCKCTRL_CRST 0x00010000 | |
100 | #define CCKCTRL_OCLKEN 0x00000100 | |
101 | #define CCKCTRL_ATACLKOEN 0x00000002 | |
102 | #define CCKCTRL_LCLKEN 0x00000001 | |
103 | ||
104 | #define QCHCD_IOS_SS 0x00000001 | |
105 | ||
106 | #define QCHSD_STPDIAG 0x00020000 | |
107 | ||
108 | #define INTMASK_MSK 0xD1000012 | |
109 | #define INTSTS_SERROR 0x80000000 | |
110 | #define INTSTS_PRERR 0x40000000 | |
111 | #define INTSTS_RERR 0x10000000 | |
112 | #define INTSTS_ICERR 0x01000000 | |
113 | #define INTSTS_BMSINT 0x00000010 | |
114 | #define INTSTS_BMHE 0x00000008 | |
115 | #define INTSTS_IOIRQS 0x00000004 | |
116 | #define INTSTS_INTRQ 0x00000002 | |
117 | #define INTSTS_ACTEINT 0x00000001 | |
118 | ||
119 | ||
120 | /* PIO transfer mode table */ | |
121 | /* JCHST */ | |
122 | static const unsigned long JCHSTtbl[2][7] = { | |
123 | {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */ | |
124 | {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */ | |
125 | }; | |
126 | ||
127 | /* JCHHT */ | |
128 | static const unsigned long JCHHTtbl[2][7] = { | |
129 | {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */ | |
130 | {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */ | |
131 | }; | |
132 | ||
133 | /* JCHCT */ | |
134 | static const unsigned long JCHCTtbl[2][7] = { | |
135 | {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */ | |
136 | {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */ | |
137 | }; | |
138 | ||
139 | /* DMA transfer mode table */ | |
140 | /* JCHDCTM/JCHDCTS */ | |
141 | static const unsigned long JCHDCTxtbl[2][7] = { | |
142 | {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */ | |
143 | {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */ | |
144 | }; | |
145 | ||
146 | /* JCSTWTM/JCSTWTS */ | |
147 | static const unsigned long JCSTWTxtbl[2][7] = { | |
148 | {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */ | |
149 | {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
150 | }; | |
151 | ||
152 | /* JCTSS */ | |
153 | static const unsigned long JCTSStbl[2][7] = { | |
154 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */ | |
155 | {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */ | |
156 | }; | |
157 | ||
158 | /* JCENVT */ | |
159 | static const unsigned long JCENVTtbl[2][7] = { | |
160 | {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */ | |
161 | {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ | |
162 | }; | |
163 | ||
164 | /* JCACTSELS/JCACTSELM */ | |
165 | static const unsigned long JCACTSELtbl[2][7] = { | |
166 | {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */ | |
167 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */ | |
168 | }; | |
169 | ||
170 | static const struct pci_device_id scc_pci_tbl[] = { | |
171 | {PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA, | |
172 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
173 | { } /* terminate list */ | |
174 | }; | |
175 | ||
176 | /** | |
177 | * scc_set_piomode - Initialize host controller PATA PIO timings | |
178 | * @ap: Port whose timings we are configuring | |
179 | * @adev: um | |
180 | * | |
181 | * Set PIO mode for device. | |
182 | * | |
183 | * LOCKING: | |
184 | * None (inherited from caller). | |
185 | */ | |
186 | ||
187 | static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
188 | { | |
189 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
190 | void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR]; | |
191 | void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL; | |
192 | void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT; | |
193 | void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT; | |
194 | unsigned long reg; | |
195 | int offset; | |
196 | ||
197 | reg = in_be32(cckctrl_port); | |
198 | if (reg & CCKCTRL_ATACLKOEN) | |
199 | offset = 1; /* 133MHz */ | |
200 | else | |
201 | offset = 0; /* 100MHz */ | |
202 | ||
203 | reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio]; | |
204 | out_be32(piosht_port, reg); | |
205 | reg = JCHCTtbl[offset][pio]; | |
206 | out_be32(pioct_port, reg); | |
207 | } | |
208 | ||
209 | /** | |
210 | * scc_set_dmamode - Initialize host controller PATA DMA timings | |
211 | * @ap: Port whose timings we are configuring | |
212 | * @adev: um | |
a619f981 AI |
213 | * |
214 | * Set UDMA mode for device. | |
215 | * | |
216 | * LOCKING: | |
217 | * None (inherited from caller). | |
218 | */ | |
219 | ||
220 | static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
221 | { | |
222 | unsigned int udma = adev->dma_mode; | |
223 | unsigned int is_slave = (adev->devno != 0); | |
224 | u8 speed = udma; | |
225 | void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR]; | |
226 | void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL; | |
227 | void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT; | |
228 | void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST; | |
229 | void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT; | |
230 | void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST; | |
231 | void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT; | |
232 | void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL; | |
233 | int offset, idx; | |
234 | ||
a84471fe | 235 | if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN) |
a619f981 AI |
236 | offset = 1; /* 133MHz */ |
237 | else | |
238 | offset = 0; /* 100MHz */ | |
239 | ||
240 | if (speed >= XFER_UDMA_0) | |
241 | idx = speed - XFER_UDMA_0; | |
242 | else | |
243 | return; | |
244 | ||
245 | if (is_slave) { | |
246 | out_be32(sdmact_port, JCHDCTxtbl[offset][idx]); | |
247 | out_be32(scrcst_port, JCSTWTxtbl[offset][idx]); | |
248 | out_be32(tdvhsel_port, | |
249 | (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2)); | |
250 | } else { | |
251 | out_be32(mdmact_port, JCHDCTxtbl[offset][idx]); | |
252 | out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]); | |
253 | out_be32(tdvhsel_port, | |
254 | (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]); | |
255 | } | |
256 | out_be32(udenvt_port, | |
257 | JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]); | |
258 | } | |
259 | ||
dcd03447 AI |
260 | unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask) |
261 | { | |
262 | /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */ | |
263 | if (adev->class == ATA_DEV_ATAPI && | |
264 | (mask & (0xE0 << ATA_SHIFT_UDMA))) { | |
265 | printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME); | |
266 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); | |
267 | } | |
c7087652 | 268 | return mask; |
dcd03447 AI |
269 | } |
270 | ||
a619f981 AI |
271 | /** |
272 | * scc_tf_load - send taskfile registers to host controller | |
273 | * @ap: Port to which output is sent | |
274 | * @tf: ATA taskfile register set | |
275 | * | |
9363c382 | 276 | * Note: Original code is ata_sff_tf_load(). |
a619f981 AI |
277 | */ |
278 | ||
279 | static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf) | |
280 | { | |
281 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
282 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
283 | ||
284 | if (tf->ctl != ap->last_ctl) { | |
285 | out_be32(ioaddr->ctl_addr, tf->ctl); | |
286 | ap->last_ctl = tf->ctl; | |
287 | ata_wait_idle(ap); | |
288 | } | |
289 | ||
290 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
291 | out_be32(ioaddr->feature_addr, tf->hob_feature); | |
292 | out_be32(ioaddr->nsect_addr, tf->hob_nsect); | |
293 | out_be32(ioaddr->lbal_addr, tf->hob_lbal); | |
294 | out_be32(ioaddr->lbam_addr, tf->hob_lbam); | |
295 | out_be32(ioaddr->lbah_addr, tf->hob_lbah); | |
296 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
297 | tf->hob_feature, | |
298 | tf->hob_nsect, | |
299 | tf->hob_lbal, | |
300 | tf->hob_lbam, | |
301 | tf->hob_lbah); | |
302 | } | |
303 | ||
304 | if (is_addr) { | |
305 | out_be32(ioaddr->feature_addr, tf->feature); | |
306 | out_be32(ioaddr->nsect_addr, tf->nsect); | |
307 | out_be32(ioaddr->lbal_addr, tf->lbal); | |
308 | out_be32(ioaddr->lbam_addr, tf->lbam); | |
309 | out_be32(ioaddr->lbah_addr, tf->lbah); | |
310 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
311 | tf->feature, | |
312 | tf->nsect, | |
313 | tf->lbal, | |
314 | tf->lbam, | |
315 | tf->lbah); | |
316 | } | |
317 | ||
318 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
319 | out_be32(ioaddr->device_addr, tf->device); | |
320 | VPRINTK("device 0x%X\n", tf->device); | |
321 | } | |
322 | ||
323 | ata_wait_idle(ap); | |
324 | } | |
325 | ||
326 | /** | |
327 | * scc_check_status - Read device status reg & clear interrupt | |
328 | * @ap: port where the device is | |
329 | * | |
330 | * Note: Original code is ata_check_status(). | |
331 | */ | |
332 | ||
333 | static u8 scc_check_status (struct ata_port *ap) | |
334 | { | |
335 | return in_be32(ap->ioaddr.status_addr); | |
336 | } | |
337 | ||
338 | /** | |
339 | * scc_tf_read - input device's ATA taskfile shadow registers | |
340 | * @ap: Port from which input is read | |
341 | * @tf: ATA taskfile register set for storing input | |
342 | * | |
9363c382 | 343 | * Note: Original code is ata_sff_tf_read(). |
a619f981 AI |
344 | */ |
345 | ||
346 | static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf) | |
347 | { | |
348 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
349 | ||
350 | tf->command = scc_check_status(ap); | |
351 | tf->feature = in_be32(ioaddr->error_addr); | |
352 | tf->nsect = in_be32(ioaddr->nsect_addr); | |
353 | tf->lbal = in_be32(ioaddr->lbal_addr); | |
354 | tf->lbam = in_be32(ioaddr->lbam_addr); | |
355 | tf->lbah = in_be32(ioaddr->lbah_addr); | |
356 | tf->device = in_be32(ioaddr->device_addr); | |
357 | ||
358 | if (tf->flags & ATA_TFLAG_LBA48) { | |
359 | out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB); | |
360 | tf->hob_feature = in_be32(ioaddr->error_addr); | |
361 | tf->hob_nsect = in_be32(ioaddr->nsect_addr); | |
362 | tf->hob_lbal = in_be32(ioaddr->lbal_addr); | |
363 | tf->hob_lbam = in_be32(ioaddr->lbam_addr); | |
364 | tf->hob_lbah = in_be32(ioaddr->lbah_addr); | |
fe36cb53 PV |
365 | out_be32(ioaddr->ctl_addr, tf->ctl); |
366 | ap->last_ctl = tf->ctl; | |
a619f981 AI |
367 | } |
368 | } | |
369 | ||
370 | /** | |
371 | * scc_exec_command - issue ATA command to host controller | |
372 | * @ap: port to which command is being issued | |
373 | * @tf: ATA taskfile register set | |
374 | * | |
9363c382 | 375 | * Note: Original code is ata_sff_exec_command(). |
a619f981 AI |
376 | */ |
377 | ||
378 | static void scc_exec_command (struct ata_port *ap, | |
379 | const struct ata_taskfile *tf) | |
380 | { | |
878d4fed | 381 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); |
a619f981 AI |
382 | |
383 | out_be32(ap->ioaddr.command_addr, tf->command); | |
9363c382 | 384 | ata_sff_pause(ap); |
a619f981 AI |
385 | } |
386 | ||
387 | /** | |
388 | * scc_check_altstatus - Read device alternate status reg | |
389 | * @ap: port where the device is | |
390 | */ | |
391 | ||
392 | static u8 scc_check_altstatus (struct ata_port *ap) | |
393 | { | |
394 | return in_be32(ap->ioaddr.altstatus_addr); | |
395 | } | |
396 | ||
397 | /** | |
9363c382 | 398 | * scc_dev_select - Select device 0/1 on ATA bus |
a619f981 AI |
399 | * @ap: ATA channel to manipulate |
400 | * @device: ATA device (numbered from zero) to select | |
401 | * | |
9363c382 | 402 | * Note: Original code is ata_sff_dev_select(). |
a619f981 AI |
403 | */ |
404 | ||
9363c382 | 405 | static void scc_dev_select (struct ata_port *ap, unsigned int device) |
a619f981 AI |
406 | { |
407 | u8 tmp; | |
408 | ||
409 | if (device == 0) | |
410 | tmp = ATA_DEVICE_OBS; | |
411 | else | |
412 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
413 | ||
414 | out_be32(ap->ioaddr.device_addr, tmp); | |
9363c382 | 415 | ata_sff_pause(ap); |
a619f981 AI |
416 | } |
417 | ||
41dec29b SS |
418 | /** |
419 | * scc_set_devctl - Write device control reg | |
420 | * @ap: port where the device is | |
421 | * @ctl: value to write | |
422 | */ | |
423 | ||
424 | static void scc_set_devctl(struct ata_port *ap, u8 ctl) | |
425 | { | |
426 | out_be32(ap->ioaddr.ctl_addr, ctl); | |
427 | } | |
428 | ||
a619f981 AI |
429 | /** |
430 | * scc_bmdma_setup - Set up PCI IDE BMDMA transaction | |
431 | * @qc: Info associated with this ATA transaction. | |
432 | * | |
433 | * Note: Original code is ata_bmdma_setup(). | |
434 | */ | |
435 | ||
436 | static void scc_bmdma_setup (struct ata_queued_cmd *qc) | |
437 | { | |
438 | struct ata_port *ap = qc->ap; | |
439 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
440 | u8 dmactl; | |
441 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
442 | ||
443 | /* load PRD table addr */ | |
444 | out_be32(mmio + SCC_DMA_TABLE_OFS, ap->prd_dma); | |
445 | ||
446 | /* specify data direction, triple-check start bit is clear */ | |
447 | dmactl = in_be32(mmio + SCC_DMA_CMD); | |
448 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
449 | if (!rw) | |
450 | dmactl |= ATA_DMA_WR; | |
451 | out_be32(mmio + SCC_DMA_CMD, dmactl); | |
452 | ||
453 | /* issue r/w command */ | |
5682ed33 | 454 | ap->ops->sff_exec_command(ap, &qc->tf); |
a619f981 AI |
455 | } |
456 | ||
457 | /** | |
458 | * scc_bmdma_start - Start a PCI IDE BMDMA transaction | |
459 | * @qc: Info associated with this ATA transaction. | |
460 | * | |
461 | * Note: Original code is ata_bmdma_start(). | |
462 | */ | |
463 | ||
464 | static void scc_bmdma_start (struct ata_queued_cmd *qc) | |
465 | { | |
466 | struct ata_port *ap = qc->ap; | |
467 | u8 dmactl; | |
468 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
469 | ||
470 | /* start host DMA transaction */ | |
471 | dmactl = in_be32(mmio + SCC_DMA_CMD); | |
472 | out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START); | |
473 | } | |
474 | ||
475 | /** | |
476 | * scc_devchk - PATA device presence detection | |
477 | * @ap: ATA channel to examine | |
478 | * @device: Device to examine (starting at zero) | |
479 | * | |
480 | * Note: Original code is ata_devchk(). | |
481 | */ | |
482 | ||
483 | static unsigned int scc_devchk (struct ata_port *ap, | |
484 | unsigned int device) | |
485 | { | |
486 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
487 | u8 nsect, lbal; | |
488 | ||
5682ed33 | 489 | ap->ops->sff_dev_select(ap, device); |
a619f981 AI |
490 | |
491 | out_be32(ioaddr->nsect_addr, 0x55); | |
492 | out_be32(ioaddr->lbal_addr, 0xaa); | |
493 | ||
494 | out_be32(ioaddr->nsect_addr, 0xaa); | |
495 | out_be32(ioaddr->lbal_addr, 0x55); | |
496 | ||
497 | out_be32(ioaddr->nsect_addr, 0x55); | |
498 | out_be32(ioaddr->lbal_addr, 0xaa); | |
499 | ||
500 | nsect = in_be32(ioaddr->nsect_addr); | |
501 | lbal = in_be32(ioaddr->lbal_addr); | |
502 | ||
503 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
504 | return 1; /* we found a device */ | |
505 | ||
506 | return 0; /* nothing found */ | |
507 | } | |
508 | ||
509 | /** | |
705e76be | 510 | * scc_wait_after_reset - wait for devices to become ready after reset |
a619f981 | 511 | * |
705e76be | 512 | * Note: Original code is ata_sff_wait_after_reset |
a619f981 AI |
513 | */ |
514 | ||
fe6005b8 SS |
515 | static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask, |
516 | unsigned long deadline) | |
a619f981 | 517 | { |
705e76be | 518 | struct ata_port *ap = link->ap; |
a619f981 AI |
519 | struct ata_ioports *ioaddr = &ap->ioaddr; |
520 | unsigned int dev0 = devmask & (1 << 0); | |
521 | unsigned int dev1 = devmask & (1 << 1); | |
705e76be TH |
522 | int rc, ret = 0; |
523 | ||
524 | /* Spec mandates ">= 2ms" before checking status. We wait | |
525 | * 150ms, because that was the magic delay used for ATAPI | |
526 | * devices in Hale Landis's ATADRVR, for the period of time | |
527 | * between when the ATA command register is written, and then | |
528 | * status is checked. Because waiting for "a while" before | |
529 | * checking status is fine, post SRST, we perform this magic | |
530 | * delay here as well. | |
531 | * | |
532 | * Old drivers/ide uses the 2mS rule and then waits for ready. | |
533 | */ | |
534 | msleep(150); | |
a619f981 | 535 | |
705e76be TH |
536 | /* always check readiness of the master device */ |
537 | rc = ata_sff_wait_ready(link, deadline); | |
538 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
539 | * and TF status is 0xff, bail out on it too. | |
a619f981 | 540 | */ |
705e76be TH |
541 | if (rc) |
542 | return rc; | |
a619f981 | 543 | |
705e76be TH |
544 | /* if device 1 was found in ata_devchk, wait for register |
545 | * access briefly, then wait for BSY to clear. | |
a619f981 | 546 | */ |
705e76be TH |
547 | if (dev1) { |
548 | int i; | |
a619f981 | 549 | |
5682ed33 | 550 | ap->ops->sff_dev_select(ap, 1); |
705e76be TH |
551 | |
552 | /* Wait for register access. Some ATAPI devices fail | |
553 | * to set nsect/lbal after reset, so don't waste too | |
554 | * much time on it. We're gonna wait for !BSY anyway. | |
555 | */ | |
556 | for (i = 0; i < 2; i++) { | |
557 | u8 nsect, lbal; | |
558 | ||
559 | nsect = in_be32(ioaddr->nsect_addr); | |
560 | lbal = in_be32(ioaddr->lbal_addr); | |
561 | if ((nsect == 1) && (lbal == 1)) | |
562 | break; | |
563 | msleep(50); /* give drive a breather */ | |
564 | } | |
565 | ||
566 | rc = ata_sff_wait_ready(link, deadline); | |
567 | if (rc) { | |
568 | if (rc != -ENODEV) | |
569 | return rc; | |
570 | ret = rc; | |
571 | } | |
7e068376 | 572 | } |
a619f981 AI |
573 | |
574 | /* is all this really necessary? */ | |
5682ed33 | 575 | ap->ops->sff_dev_select(ap, 0); |
a619f981 | 576 | if (dev1) |
5682ed33 | 577 | ap->ops->sff_dev_select(ap, 1); |
a619f981 | 578 | if (dev0) |
5682ed33 | 579 | ap->ops->sff_dev_select(ap, 0); |
7e068376 | 580 | |
705e76be | 581 | return ret; |
a619f981 AI |
582 | } |
583 | ||
584 | /** | |
585 | * scc_bus_softreset - PATA device software reset | |
586 | * | |
587 | * Note: Original code is ata_bus_softreset(). | |
588 | */ | |
589 | ||
7e068376 TB |
590 | static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask, |
591 | unsigned long deadline) | |
a619f981 AI |
592 | { |
593 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
594 | ||
878d4fed | 595 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
a619f981 AI |
596 | |
597 | /* software reset. causes dev0 to be selected */ | |
598 | out_be32(ioaddr->ctl_addr, ap->ctl); | |
599 | udelay(20); | |
600 | out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST); | |
601 | udelay(20); | |
602 | out_be32(ioaddr->ctl_addr, ap->ctl); | |
603 | ||
e50e3ce5 | 604 | scc_wait_after_reset(&ap->link, devmask, deadline); |
a619f981 AI |
605 | |
606 | return 0; | |
607 | } | |
608 | ||
609 | /** | |
9363c382 | 610 | * scc_softreset - reset host port via ATA SRST |
a619f981 AI |
611 | * @ap: port to reset |
612 | * @classes: resulting classes of attached devices | |
7e068376 | 613 | * @deadline: deadline jiffies for the operation |
a619f981 | 614 | * |
9363c382 | 615 | * Note: Original code is ata_sff_softreset(). |
a619f981 AI |
616 | */ |
617 | ||
9363c382 TH |
618 | static int scc_softreset(struct ata_link *link, unsigned int *classes, |
619 | unsigned long deadline) | |
a619f981 | 620 | { |
b90fe23b | 621 | struct ata_port *ap = link->ap; |
a619f981 AI |
622 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; |
623 | unsigned int devmask = 0, err_mask; | |
624 | u8 err; | |
625 | ||
626 | DPRINTK("ENTER\n"); | |
627 | ||
a619f981 AI |
628 | /* determine if device 0/1 are present */ |
629 | if (scc_devchk(ap, 0)) | |
630 | devmask |= (1 << 0); | |
631 | if (slave_possible && scc_devchk(ap, 1)) | |
632 | devmask |= (1 << 1); | |
633 | ||
634 | /* select device 0 again */ | |
5682ed33 | 635 | ap->ops->sff_dev_select(ap, 0); |
a619f981 AI |
636 | |
637 | /* issue bus reset */ | |
638 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
7e068376 | 639 | err_mask = scc_bus_softreset(ap, devmask, deadline); |
a619f981 AI |
640 | if (err_mask) { |
641 | ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n", | |
642 | err_mask); | |
643 | return -EIO; | |
644 | } | |
645 | ||
646 | /* determine by signature whether we have ATA or ATAPI devices */ | |
9363c382 | 647 | classes[0] = ata_sff_dev_classify(&ap->link.device[0], |
3f19859e | 648 | devmask & (1 << 0), &err); |
a619f981 | 649 | if (slave_possible && err != 0x81) |
9363c382 | 650 | classes[1] = ata_sff_dev_classify(&ap->link.device[1], |
3f19859e | 651 | devmask & (1 << 1), &err); |
a619f981 | 652 | |
a619f981 AI |
653 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); |
654 | return 0; | |
655 | } | |
656 | ||
657 | /** | |
658 | * scc_bmdma_stop - Stop PCI IDE BMDMA transfer | |
659 | * @qc: Command we are ending DMA for | |
660 | */ | |
661 | ||
662 | static void scc_bmdma_stop (struct ata_queued_cmd *qc) | |
663 | { | |
664 | struct ata_port *ap = qc->ap; | |
665 | void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR]; | |
666 | void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR]; | |
667 | u32 reg; | |
668 | ||
669 | while (1) { | |
670 | reg = in_be32(bmid_base + SCC_DMA_INTST); | |
671 | ||
672 | if (reg & INTSTS_SERROR) { | |
673 | printk(KERN_WARNING "%s: SERROR\n", DRV_NAME); | |
674 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT); | |
675 | out_be32(bmid_base + SCC_DMA_CMD, | |
676 | in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); | |
677 | continue; | |
678 | } | |
679 | ||
680 | if (reg & INTSTS_PRERR) { | |
681 | u32 maea0, maec0; | |
682 | maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0); | |
683 | maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0); | |
684 | printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0); | |
685 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT); | |
686 | out_be32(bmid_base + SCC_DMA_CMD, | |
687 | in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); | |
688 | continue; | |
689 | } | |
690 | ||
691 | if (reg & INTSTS_RERR) { | |
692 | printk(KERN_WARNING "%s: Response Error\n", DRV_NAME); | |
693 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT); | |
694 | out_be32(bmid_base + SCC_DMA_CMD, | |
695 | in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); | |
696 | continue; | |
697 | } | |
698 | ||
699 | if (reg & INTSTS_ICERR) { | |
700 | out_be32(bmid_base + SCC_DMA_CMD, | |
701 | in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); | |
702 | printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME); | |
703 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT); | |
704 | continue; | |
705 | } | |
706 | ||
707 | if (reg & INTSTS_BMSINT) { | |
708 | unsigned int classes; | |
341c2c95 | 709 | unsigned long deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT); |
a619f981 AI |
710 | printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME); |
711 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT); | |
712 | /* TBD: SW reset */ | |
9363c382 | 713 | scc_softreset(&ap->link, &classes, deadline); |
a619f981 AI |
714 | continue; |
715 | } | |
716 | ||
717 | if (reg & INTSTS_BMHE) { | |
718 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE); | |
719 | continue; | |
720 | } | |
721 | ||
722 | if (reg & INTSTS_ACTEINT) { | |
723 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT); | |
724 | continue; | |
725 | } | |
726 | ||
727 | if (reg & INTSTS_IOIRQS) { | |
728 | out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS); | |
729 | continue; | |
730 | } | |
731 | break; | |
732 | } | |
733 | ||
734 | /* clear start/stop bit */ | |
735 | out_be32(bmid_base + SCC_DMA_CMD, | |
736 | in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); | |
737 | ||
738 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
a57c1bad | 739 | ata_sff_dma_pause(ap); /* dummy read */ |
a619f981 AI |
740 | } |
741 | ||
742 | /** | |
743 | * scc_bmdma_status - Read PCI IDE BMDMA status | |
744 | * @ap: Port associated with this ATA transaction. | |
745 | */ | |
746 | ||
747 | static u8 scc_bmdma_status (struct ata_port *ap) | |
748 | { | |
a619f981 | 749 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
fae57d34 AI |
750 | u8 host_stat = in_be32(mmio + SCC_DMA_STATUS); |
751 | u32 int_status = in_be32(mmio + SCC_DMA_INTST); | |
b90fe23b | 752 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); |
fae57d34 AI |
753 | static int retry = 0; |
754 | ||
755 | /* return if IOS_SS is cleared */ | |
756 | if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START)) | |
757 | return host_stat; | |
758 | ||
759 | /* errata A252,A308 workaround: Step4 */ | |
a57c1bad AC |
760 | if ((scc_check_altstatus(ap) & ATA_ERR) |
761 | && (int_status & INTSTS_INTRQ)) | |
fae57d34 AI |
762 | return (host_stat | ATA_DMA_INTR); |
763 | ||
764 | /* errata A308 workaround Step5 */ | |
765 | if (int_status & INTSTS_IOIRQS) { | |
766 | host_stat |= ATA_DMA_INTR; | |
767 | ||
768 | /* We don't check ATAPI DMA because it is limited to UDMA4 */ | |
769 | if ((qc->tf.protocol == ATA_PROT_DMA && | |
770 | qc->dev->xfer_mode > XFER_UDMA_4)) { | |
771 | if (!(int_status & INTSTS_ACTEINT)) { | |
dcd03447 AI |
772 | printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n", |
773 | ap->print_id); | |
fae57d34 AI |
774 | host_stat |= ATA_DMA_ERR; |
775 | if (retry++) | |
dcd03447 | 776 | ap->udma_mask &= ~(1 << qc->dev->xfer_mode); |
fae57d34 AI |
777 | } else |
778 | retry = 0; | |
779 | } | |
a619f981 AI |
780 | } |
781 | ||
782 | return host_stat; | |
783 | } | |
784 | ||
785 | /** | |
786 | * scc_data_xfer - Transfer data by PIO | |
55dba312 | 787 | * @dev: device for this I/O |
a619f981 AI |
788 | * @buf: data buffer |
789 | * @buflen: buffer length | |
55dba312 | 790 | * @rw: read/write |
a619f981 | 791 | * |
9363c382 | 792 | * Note: Original code is ata_sff_data_xfer(). |
a619f981 AI |
793 | */ |
794 | ||
55dba312 TH |
795 | static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf, |
796 | unsigned int buflen, int rw) | |
a619f981 | 797 | { |
55dba312 | 798 | struct ata_port *ap = dev->link->ap; |
a619f981 AI |
799 | unsigned int words = buflen >> 1; |
800 | unsigned int i; | |
826cd156 | 801 | __le16 *buf16 = (__le16 *) buf; |
a619f981 AI |
802 | void __iomem *mmio = ap->ioaddr.data_addr; |
803 | ||
804 | /* Transfer multiple of 2 bytes */ | |
55dba312 | 805 | if (rw == READ) |
a619f981 | 806 | for (i = 0; i < words; i++) |
826cd156 | 807 | buf16[i] = cpu_to_le16(in_be32(mmio)); |
55dba312 TH |
808 | else |
809 | for (i = 0; i < words; i++) | |
826cd156 | 810 | out_be32(mmio, le16_to_cpu(buf16[i])); |
a619f981 AI |
811 | |
812 | /* Transfer trailing 1 byte, if any. */ | |
813 | if (unlikely(buflen & 0x01)) { | |
826cd156 | 814 | __le16 align_buf[1] = { 0 }; |
a619f981 AI |
815 | unsigned char *trailing_buf = buf + buflen - 1; |
816 | ||
55dba312 | 817 | if (rw == READ) { |
826cd156 | 818 | align_buf[0] = cpu_to_le16(in_be32(mmio)); |
a619f981 | 819 | memcpy(trailing_buf, align_buf, 1); |
55dba312 TH |
820 | } else { |
821 | memcpy(align_buf, trailing_buf, 1); | |
826cd156 | 822 | out_be32(mmio, le16_to_cpu(align_buf[0])); |
a619f981 | 823 | } |
55dba312 | 824 | words++; |
a619f981 | 825 | } |
55dba312 TH |
826 | |
827 | return words << 1; | |
a619f981 AI |
828 | } |
829 | ||
a619f981 AI |
830 | /** |
831 | * scc_pata_prereset - prepare for reset | |
832 | * @ap: ATA port to be reset | |
7e068376 | 833 | * @deadline: deadline jiffies for the operation |
a619f981 AI |
834 | */ |
835 | ||
b90fe23b | 836 | static int scc_pata_prereset(struct ata_link *link, unsigned long deadline) |
a619f981 | 837 | { |
b90fe23b | 838 | link->ap->cbl = ATA_CBL_PATA80; |
9363c382 | 839 | return ata_sff_prereset(link, deadline); |
a619f981 AI |
840 | } |
841 | ||
842 | /** | |
9363c382 | 843 | * scc_postreset - standard postreset callback |
a619f981 AI |
844 | * @ap: the target ata_port |
845 | * @classes: classes of attached devices | |
846 | * | |
9363c382 | 847 | * Note: Original code is ata_sff_postreset(). |
a619f981 AI |
848 | */ |
849 | ||
9363c382 | 850 | static void scc_postreset(struct ata_link *link, unsigned int *classes) |
a619f981 | 851 | { |
b90fe23b SS |
852 | struct ata_port *ap = link->ap; |
853 | ||
a619f981 AI |
854 | DPRINTK("ENTER\n"); |
855 | ||
a619f981 AI |
856 | /* is double-select really necessary? */ |
857 | if (classes[0] != ATA_DEV_NONE) | |
5682ed33 | 858 | ap->ops->sff_dev_select(ap, 1); |
a619f981 | 859 | if (classes[1] != ATA_DEV_NONE) |
5682ed33 | 860 | ap->ops->sff_dev_select(ap, 0); |
a619f981 AI |
861 | |
862 | /* bail out if no device is present */ | |
863 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
864 | DPRINTK("EXIT, no device\n"); | |
865 | return; | |
866 | } | |
867 | ||
868 | /* set up device control */ | |
ec86c81d | 869 | out_be32(ap->ioaddr.ctl_addr, ap->ctl); |
a619f981 AI |
870 | |
871 | DPRINTK("EXIT\n"); | |
872 | } | |
873 | ||
a619f981 | 874 | /** |
9363c382 | 875 | * scc_irq_clear - Clear PCI IDE BMDMA interrupt. |
a619f981 AI |
876 | * @ap: Port associated with this ATA transaction. |
877 | * | |
9363c382 | 878 | * Note: Original code is ata_sff_irq_clear(). |
a619f981 AI |
879 | */ |
880 | ||
9363c382 | 881 | static void scc_irq_clear (struct ata_port *ap) |
a619f981 AI |
882 | { |
883 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
884 | ||
885 | if (!mmio) | |
886 | return; | |
887 | ||
888 | out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS)); | |
889 | } | |
890 | ||
891 | /** | |
892 | * scc_port_start - Set port up for dma. | |
893 | * @ap: Port to initialize | |
894 | * | |
c7087652 | 895 | * Allocate space for PRD table using ata_bmdma_port_start(). |
a619f981 AI |
896 | * Set PRD table address for PTERADD. (PRD Transfer End Read) |
897 | */ | |
898 | ||
899 | static int scc_port_start (struct ata_port *ap) | |
900 | { | |
901 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
902 | int rc; | |
903 | ||
c7087652 | 904 | rc = ata_bmdma_port_start(ap); |
a619f981 AI |
905 | if (rc) |
906 | return rc; | |
907 | ||
908 | out_be32(mmio + SCC_DMA_PTERADD, ap->prd_dma); | |
909 | return 0; | |
910 | } | |
911 | ||
912 | /** | |
913 | * scc_port_stop - Undo scc_port_start() | |
914 | * @ap: Port to shut down | |
915 | * | |
916 | * Reset PTERADD. | |
917 | */ | |
918 | ||
919 | static void scc_port_stop (struct ata_port *ap) | |
920 | { | |
921 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
922 | ||
923 | out_be32(mmio + SCC_DMA_PTERADD, 0); | |
924 | } | |
925 | ||
926 | static struct scsi_host_template scc_sht = { | |
68d1d07b | 927 | ATA_BMDMA_SHT(DRV_NAME), |
a619f981 AI |
928 | }; |
929 | ||
c1796d98 | 930 | static struct ata_port_operations scc_pata_ops = { |
029cfd6b TH |
931 | .inherits = &ata_bmdma_port_ops, |
932 | ||
a619f981 AI |
933 | .set_piomode = scc_set_piomode, |
934 | .set_dmamode = scc_set_dmamode, | |
dcd03447 | 935 | .mode_filter = scc_mode_filter, |
a619f981 | 936 | |
5682ed33 TH |
937 | .sff_tf_load = scc_tf_load, |
938 | .sff_tf_read = scc_tf_read, | |
939 | .sff_exec_command = scc_exec_command, | |
940 | .sff_check_status = scc_check_status, | |
941 | .sff_check_altstatus = scc_check_altstatus, | |
942 | .sff_dev_select = scc_dev_select, | |
41dec29b | 943 | .sff_set_devctl = scc_set_devctl, |
a619f981 AI |
944 | |
945 | .bmdma_setup = scc_bmdma_setup, | |
946 | .bmdma_start = scc_bmdma_start, | |
947 | .bmdma_stop = scc_bmdma_stop, | |
948 | .bmdma_status = scc_bmdma_status, | |
5682ed33 | 949 | .sff_data_xfer = scc_data_xfer, |
a619f981 | 950 | |
a1efdaba | 951 | .prereset = scc_pata_prereset, |
9363c382 TH |
952 | .softreset = scc_softreset, |
953 | .postreset = scc_postreset, | |
a619f981 | 954 | |
5682ed33 | 955 | .sff_irq_clear = scc_irq_clear, |
a619f981 AI |
956 | |
957 | .port_start = scc_port_start, | |
958 | .port_stop = scc_port_stop, | |
959 | }; | |
960 | ||
961 | static struct ata_port_info scc_port_info[] = { | |
962 | { | |
a619f981 | 963 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY, |
14bdef98 EIB |
964 | .pio_mask = ATA_PIO4, |
965 | /* No MWDMA */ | |
a619f981 AI |
966 | .udma_mask = ATA_UDMA6, |
967 | .port_ops = &scc_pata_ops, | |
968 | }, | |
969 | }; | |
970 | ||
971 | /** | |
972 | * scc_reset_controller - initialize SCC PATA controller. | |
973 | */ | |
974 | ||
5d728824 | 975 | static int scc_reset_controller(struct ata_host *host) |
a619f981 | 976 | { |
5d728824 TH |
977 | void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR]; |
978 | void __iomem *bmid_base = host->iomap[SCC_BMID_BAR]; | |
a619f981 AI |
979 | void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL; |
980 | void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG; | |
981 | void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE; | |
982 | void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK; | |
983 | void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS; | |
984 | u32 reg = 0; | |
985 | ||
986 | out_be32(cckctrl_port, reg); | |
987 | reg |= CCKCTRL_ATACLKOEN; | |
988 | out_be32(cckctrl_port, reg); | |
989 | reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN; | |
990 | out_be32(cckctrl_port, reg); | |
991 | reg |= CCKCTRL_CRST; | |
992 | out_be32(cckctrl_port, reg); | |
993 | ||
994 | for (;;) { | |
995 | reg = in_be32(cckctrl_port); | |
996 | if (reg & CCKCTRL_CRST) | |
997 | break; | |
998 | udelay(5000); | |
999 | } | |
1000 | ||
1001 | reg |= CCKCTRL_ATARESET; | |
1002 | out_be32(cckctrl_port, reg); | |
1003 | out_be32(ecmode_port, ECMODE_VALUE); | |
1004 | out_be32(mode_port, MODE_JCUSFEN); | |
1005 | out_be32(intmask_port, INTMASK_MSK); | |
1006 | ||
1007 | if (in_be32(dmastatus_port) & QCHSD_STPDIAG) { | |
1008 | printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME); | |
1009 | return -EIO; | |
1010 | } | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | ||
1015 | /** | |
1016 | * scc_setup_ports - initialize ioaddr with SCC PATA port offsets. | |
1017 | * @ioaddr: IO address structure to be initialized | |
1018 | * @base: base address of BMID region | |
1019 | */ | |
1020 | ||
1021 | static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base) | |
1022 | { | |
1023 | ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR; | |
1024 | ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS; | |
1025 | ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS; | |
1026 | ioaddr->bmdma_addr = base; | |
1027 | ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA; | |
1028 | ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR; | |
1029 | ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE; | |
1030 | ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT; | |
1031 | ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL; | |
1032 | ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM; | |
1033 | ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH; | |
1034 | ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE; | |
1035 | ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS; | |
1036 | ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD; | |
1037 | } | |
1038 | ||
5d728824 | 1039 | static int scc_host_init(struct ata_host *host) |
a619f981 | 1040 | { |
5d728824 | 1041 | struct pci_dev *pdev = to_pci_dev(host->dev); |
a619f981 AI |
1042 | int rc; |
1043 | ||
5d728824 | 1044 | rc = scc_reset_controller(host); |
a619f981 AI |
1045 | if (rc) |
1046 | return rc; | |
1047 | ||
a619f981 AI |
1048 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
1049 | if (rc) | |
1050 | return rc; | |
1051 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
1052 | if (rc) | |
1053 | return rc; | |
1054 | ||
5d728824 | 1055 | scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]); |
a619f981 AI |
1056 | |
1057 | pci_set_master(pdev); | |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | /** | |
1063 | * scc_init_one - Register SCC PATA device with kernel services | |
1064 | * @pdev: PCI device to register | |
1065 | * @ent: Entry in scc_pci_tbl matching with @pdev | |
1066 | * | |
1067 | * LOCKING: | |
1068 | * Inherited from PCI layer (may sleep). | |
1069 | * | |
1070 | * RETURNS: | |
1071 | * Zero on success, or -ERRNO value. | |
1072 | */ | |
1073 | ||
1074 | static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1075 | { | |
1076 | static int printed_version; | |
1077 | unsigned int board_idx = (unsigned int) ent->driver_data; | |
5d728824 | 1078 | const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL }; |
0397bad5 | 1079 | struct ata_host *host; |
a619f981 AI |
1080 | int rc; |
1081 | ||
1082 | if (!printed_version++) | |
1083 | dev_printk(KERN_DEBUG, &pdev->dev, | |
1084 | "version " DRV_VERSION "\n"); | |
1085 | ||
0397bad5 | 1086 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1); |
5d728824 TH |
1087 | if (!host) |
1088 | return -ENOMEM; | |
1089 | ||
a619f981 AI |
1090 | rc = pcim_enable_device(pdev); |
1091 | if (rc) | |
1092 | return rc; | |
1093 | ||
1094 | rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME); | |
1095 | if (rc == -EBUSY) | |
1096 | pcim_pin_device(pdev); | |
1097 | if (rc) | |
1098 | return rc; | |
5d728824 | 1099 | host->iomap = pcim_iomap_table(pdev); |
a619f981 | 1100 | |
cbcdd875 TH |
1101 | ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl"); |
1102 | ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid"); | |
1103 | ||
5d728824 | 1104 | rc = scc_host_init(host); |
a619f981 AI |
1105 | if (rc) |
1106 | return rc; | |
1107 | ||
9363c382 TH |
1108 | return ata_host_activate(host, pdev->irq, ata_sff_interrupt, |
1109 | IRQF_SHARED, &scc_sht); | |
a619f981 AI |
1110 | } |
1111 | ||
1112 | static struct pci_driver scc_pci_driver = { | |
1113 | .name = DRV_NAME, | |
1114 | .id_table = scc_pci_tbl, | |
1115 | .probe = scc_init_one, | |
1116 | .remove = ata_pci_remove_one, | |
1117 | #ifdef CONFIG_PM | |
1118 | .suspend = ata_pci_device_suspend, | |
1119 | .resume = ata_pci_device_resume, | |
1120 | #endif | |
1121 | }; | |
1122 | ||
1123 | static int __init scc_init (void) | |
1124 | { | |
1125 | int rc; | |
1126 | ||
1127 | DPRINTK("pci_register_driver\n"); | |
1128 | rc = pci_register_driver(&scc_pci_driver); | |
1129 | if (rc) | |
1130 | return rc; | |
1131 | ||
1132 | DPRINTK("done\n"); | |
1133 | return 0; | |
1134 | } | |
1135 | ||
1136 | static void __exit scc_exit (void) | |
1137 | { | |
1138 | pci_unregister_driver(&scc_pci_driver); | |
1139 | } | |
1140 | ||
1141 | module_init(scc_init); | |
1142 | module_exit(scc_exit); | |
1143 | ||
1144 | MODULE_AUTHOR("Toshiba corp"); | |
1145 | MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller"); | |
1146 | MODULE_LICENSE("GPL"); | |
1147 | MODULE_DEVICE_TABLE(pci, scc_pci_tbl); | |
1148 | MODULE_VERSION(DRV_VERSION); |