[mirror_ubuntu-artful-kernel.git] / drivers / ata / pata_serverworks.c

/*
 * pata_serverworks.c 	- Serverworks PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * based upon
 *
 * serverworks.c
 *
 * Copyright (C) 1998-2000 Michel Aubry
 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 * Portions copyright (c) 2001 Sun Microsystems
 *
 *
 * RCC/ServerWorks IDE driver for Linux
 *
 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
 *         supports UDMA mode 2 (33 MB/s)
 *
 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
 *         all revisions support UDMA mode 4 (66 MB/s)
 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
 *
 *         *** The CSB5 does not provide ANY register ***
 *         *** to detect 80-conductor cable presence. ***
 *
 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
 *
 * Documentation:
 *	Available under NDA only. Errata info very hard to get.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_serverworks"
#define DRV_VERSION "0.4.3"

#define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
#define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */

/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
 * can overrun their FIFOs when used with the CSB5 */

static const char *csb_bad_ata100[] = {
	"ST320011A",
	"ST340016A",
	"ST360021A",
	"ST380021A",
	NULL
};

/**
 *	dell_cable	-	Dell serverworks cable detection
 *	@ap: ATA port to do cable detect
 *
 *	Dell hide the 40/80 pin select for their interfaces in the top two
 *	bits of the subsystem ID.
 */

static int dell_cable(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	sun_cable	-	Sun Cobalt 'Alpine' cable detection
 *	@ap: ATA port to do cable select
 *
 *	Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
 *	subsystem ID the same as dell. We could use one function but we may
 *	need to extend the Dell one in future
 */

static int sun_cable(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	osb4_cable	-	OSB4 cable detect
 *	@ap: ATA port to check
 *
 *	The OSB4 isn't UDMA66 capable so this is easy
 */

static int osb4_cable(struct ata_port *ap) {
	return ATA_CBL_PATA40;
}

/**
 *	csb_cable	-	CSB5/6 cable detect
 *	@ap: ATA port to check
 *
 *	Serverworks default arrangement is to use the drive side detection
 *	only.
 */

static int csb_cable(struct ata_port *ap) {
	return ATA_CBL_PATA_UNK;
}

struct sv_cable_table {
	int device;
	int subvendor;
	int (*cable_detect)(struct ata_port *ap);
};

/*
 *	Note that we don't copy the old serverworks code because the old
 *	code contains obvious mistakes
 */

static struct sv_cable_table cable_detect[] = {
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN,  sun_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
	{ }
};

/**
 *	serverworks_cable_detect	-	cable detection
 *	@ap: ATA port
 *	@deadline: deadline jiffies for the operation
 *
 *	Perform cable detection according to the device and subvendor
 *	identifications
 */

static int serverworks_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct sv_cable_table *cb = cable_detect;

	while(cb->device) {
		if (cb->device == pdev->device &&
		    (cb->subvendor == pdev->subsystem_vendor ||
		      cb->subvendor == PCI_ANY_ID)) {
			return cb->cable_detect(ap);
		}
		cb++;
	}

	BUG();
	return -1;	/* kill compiler warning */
}

/**
 *	serverworks_is_csb	-	Check for CSB or OSB
 *	@pdev: PCI device to check
 *
 *	Returns true if the device being checked is known to be a CSB
 *	series device.
 */

static u8 serverworks_is_csb(struct pci_dev *pdev)
{
	switch (pdev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			return 1;
		default:
			break;
	}
	return 0;
}

/**
 *	serverworks_osb4_filter	-	mode selection filter
 *	@adev: ATA device
 *	@mask: Mask of proposed modes
 *
 *	Filter the offered modes for the device to apply controller
 *	specific rules. OSB4 requires no UDMA for disks due to a FIFO
 *	bug we hit.
 */

static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA)
		mask &= ~ATA_MASK_UDMA;
	return ata_pci_default_filter(adev, mask);
}


/**
 *	serverworks_csb_filter	-	mode selection filter
 *	@adev: ATA device
 *	@mask: Mask of proposed modes
 *
 *	Check the blacklist and disable UDMA5 if matched
 */

static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
{
	const char *p;
	char model_num[ATA_ID_PROD_LEN + 1];
	int i;

	/* Disk, UDMA */
	if (adev->class != ATA_DEV_ATA)
		return ata_pci_default_filter(adev, mask);

	/* Actually do need to check */
	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
		if (!strcmp(p, model_num))
			mask &= ~(0xE0 << ATA_SHIFT_UDMA);
	}
	return ata_pci_default_filter(adev, mask);
}

/**
 *	serverworks_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the OSB4/CSB5 timing registers for PIO. The PIO register
 *	load is done as a simple lookup.
 */
static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	int offset = 1 + 2 * ap->port_no - adev->devno;
	int devbits = (2 * ap->port_no + adev->devno) * 4;
	u16 csb5_pio;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int pio = adev->pio_mode - XFER_PIO_0;

	pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);

	/* The OSB4 just requires the timing but the CSB series want the
	   mode number as well */
	if (serverworks_is_csb(pdev)) {
		pci_read_config_word(pdev, 0x4A, &csb5_pio);
		csb5_pio &= ~(0x0F << devbits);
		pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits));
	}
}

/**
 *	serverworks_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
 *	chipset. The MWDMA mode values are pulled from a lookup table
 *	while the chipset uses mode number for UDMA.
 */

static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
	int offset = 1 + 2 * ap->port_no - adev->devno;
	int devbits = 2 * ap->port_no + adev->devno;
	u8 ultra;
	u8 ultra_cfg;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	pci_read_config_byte(pdev, 0x54, &ultra_cfg);
	pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
	ultra &= ~(0x0F << (adev->devno * 4));

	if (adev->dma_mode >= XFER_UDMA_0) {
		pci_write_config_byte(pdev, 0x44 + offset,  0x20);

		ultra |= (adev->dma_mode - XFER_UDMA_0)
					<< (adev->devno * 4);
		ultra_cfg |=  (1 << devbits);
	} else {
		pci_write_config_byte(pdev, 0x44 + offset,
			dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
		ultra_cfg &= ~(1 << devbits);
	}
	pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
	pci_write_config_byte(pdev, 0x54, ultra_cfg);
}

static struct scsi_host_template serverworks_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations serverworks_osb4_port_ops = {
	.set_piomode	= serverworks_set_piomode,
	.set_dmamode	= serverworks_set_dmamode,
	.mode_filter	= serverworks_osb4_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= serverworks_cable_detect,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,

	.port_start	= ata_sff_port_start,
};

static struct ata_port_operations serverworks_csb_port_ops = {
	.set_piomode	= serverworks_set_piomode,
	.set_dmamode	= serverworks_set_dmamode,
	.mode_filter	= serverworks_csb_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= serverworks_cable_detect,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,

	.port_start	= ata_sff_port_start,
};

static int serverworks_fixup_osb4(struct pci_dev *pdev)
{
	u32 reg;
	struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
		  PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
	if (isa_dev) {
		pci_read_config_dword(isa_dev, 0x64, &reg);
		reg &= ~0x00002000; /* disable 600ns interrupt mask */
		if (!(reg & 0x00004000))
			printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
		reg |=  0x00004000; /* enable UDMA/33 support */
		pci_write_config_dword(isa_dev, 0x64, reg);
		pci_dev_put(isa_dev);
		return 0;
	}
	printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n");
	return -ENODEV;
}

static int serverworks_fixup_csb(struct pci_dev *pdev)
{
	u8 btr;

	/* Third Channel Test */
	if (!(PCI_FUNC(pdev->devfn) & 1)) {
		struct pci_dev * findev = NULL;
		u32 reg4c = 0;
		findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
			PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
		if (findev) {
			pci_read_config_dword(findev, 0x4C, &reg4c);
			reg4c &= ~0x000007FF;
			reg4c |=  0x00000040;
			reg4c |=  0x00000020;
			pci_write_config_dword(findev, 0x4C, reg4c);
			pci_dev_put(findev);
		}
	} else {
		struct pci_dev * findev = NULL;
		u8 reg41 = 0;

		findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
				PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
		if (findev) {
			pci_read_config_byte(findev, 0x41, &reg41);
			reg41 &= ~0x40;
			pci_write_config_byte(findev, 0x41, reg41);
			pci_dev_put(findev);
		}
	}
	/* setup the UDMA Control register
	 *
	 * 1. clear bit 6 to enable DMA
	 * 2. enable DMA modes with bits 0-1
	 * 	00 : legacy
	 * 	01 : udma2
	 * 	10 : udma2/udma4
	 * 	11 : udma2/udma4/udma5
	 */
	pci_read_config_byte(pdev, 0x5A, &btr);
	btr &= ~0x40;
	if (!(PCI_FUNC(pdev->devfn) & 1))
		btr |= 0x2;
	else
		btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
	pci_write_config_byte(pdev, 0x5A, btr);

	return btr;
}

static void serverworks_fixup_ht1000(struct pci_dev *pdev)
{
	u8 btr;
	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	pci_read_config_byte(pdev, 0x5A, &btr);
	btr &= ~0x40;
	btr |= 0x3;
	pci_write_config_byte(pdev, 0x5A, btr);
}


static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info[4] = {
		{ /* OSB4 */
			.sht = &serverworks_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = 0x07,
			.port_ops = &serverworks_osb4_port_ops
		}, { /* OSB4 no UDMA */
			.sht = &serverworks_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = 0x00,
			.port_ops = &serverworks_osb4_port_ops
		}, { /* CSB5 */
			.sht = &serverworks_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,
			.port_ops = &serverworks_csb_port_ops
		}, { /* CSB5 - later revisions*/
			.sht = &serverworks_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,
			.port_ops = &serverworks_csb_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
	int rc;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* Force master latency timer to 64 PCI clocks */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);

	/* OSB4 : South Bridge and IDE */
	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		/* Select non UDMA capable OSB4 if we can't do fixups */
		if ( serverworks_fixup_osb4(pdev) < 0)
			ppi[0] = &info[1];
	}
	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
		 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
		 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {

		 /* If the returned btr is the newer revision then
		    select the right info block */
		 if (serverworks_fixup_csb(pdev) == 3)
		 	ppi[0] = &info[3];

		/* Is this the 3rd channel CSB6 IDE ? */
		if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
			ppi[1] = &ata_dummy_port_info;
	}
	/* setup HT1000E */
	else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
		serverworks_fixup_ht1000(pdev);

	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
		ata_pci_clear_simplex(pdev);

	return ata_pci_init_one(pdev, ppi);
}

#ifdef CONFIG_PM
static int serverworks_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	/* Force master latency timer to 64 PCI clocks */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);

	switch (pdev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
			serverworks_fixup_osb4(pdev);
			break;
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
			ata_pci_clear_simplex(pdev);
			/* fall through */
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
			serverworks_fixup_csb(pdev);
			break;
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			serverworks_fixup_ht1000(pdev);
			break;
	}

	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id serverworks[] = {
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},

	{ },
};

static struct pci_driver serverworks_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= serverworks,
	.probe 		= serverworks_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= serverworks_reinit_one,
#endif
};

static int __init serverworks_init(void)
{
	return pci_register_driver(&serverworks_pci_driver);
}

static void __exit serverworks_exit(void)
{
	pci_unregister_driver(&serverworks_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, serverworks);
MODULE_VERSION(DRV_VERSION);

module_init(serverworks_init);
module_exit(serverworks_exit);
Commit	Line	Data
669a5db4	1	/*
a0fcdc02	2	* pata_serverworks.c - Serverworks PATA for new ATA layer
669a5db4 JG	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* based upon
	7	*
	8	* serverworks.c
85cd7251	9	*
669a5db4 JG	10	* Copyright (C) 1998-2000 Michel Aubry
	11	* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
	12	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	13	* Portions copyright (c) 2001 Sun Microsystems
	14	*
	15	*
	16	* RCC/ServerWorks IDE driver for Linux
	17	*
	18	* OSB4: `Open South Bridge' IDE Interface (fn 1)
	19	* supports UDMA mode 2 (33 MB/s)
	20	*
	21	* CSB5: `Champion South Bridge' IDE Interface (fn 1)
	22	* all revisions support UDMA mode 4 (66 MB/s)
	23	* revision A2.0 and up support UDMA mode 5 (100 MB/s)
	24	*
	25	* * The CSB5 does not provide ANY register *
	26	* * to detect 80-conductor cable presence. *
	27	*
	28	* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
	29	*
	30	* Documentation:
	31	* Available under NDA only. Errata info very hard to get.
	32	*/
	33
	34	#include <linux/kernel.h>
	35	#include <linux/module.h>
	36	#include <linux/pci.h>
	37	#include <linux/init.h>
	38	#include <linux/blkdev.h>
	39	#include <linux/delay.h>
	40	#include <scsi/scsi_host.h>
	41	#include <linux/libata.h>
	42
	43	#define DRV_NAME "pata_serverworks"
0f069788	44	#define DRV_VERSION "0.4.3"
669a5db4 JG	45
	46	#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
	47	#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
	48
	49	/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
	50	* can overrun their FIFOs when used with the CSB5 */
	51
	52	static const char *csb_bad_ata100[] = {
	53	"ST320011A",
	54	"ST340016A",
	55	"ST360021A",
	56	"ST380021A",
	57	NULL
	58	};
	59
	60	/**
	61	* dell_cable - Dell serverworks cable detection
	62	* @ap: ATA port to do cable detect
	63	*
	64	* Dell hide the 40/80 pin select for their interfaces in the top two
85cd7251	65	* bits of the subsystem ID.
669a5db4	66	*/
85cd7251	67
669a5db4 JG	68	static int dell_cable(struct ata_port *ap) {
669a5db4 JG	69	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	70
669a5db4 JG	71	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
	72	return ATA_CBL_PATA80;
	73	return ATA_CBL_PATA40;
	74	}
	75
	76	/**
	77	* sun_cable - Sun Cobalt 'Alpine' cable detection
	78	* @ap: ATA port to do cable select
	79	*
	80	* Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
	81	* subsystem ID the same as dell. We could use one function but we may
	82	* need to extend the Dell one in future
	83	*/
85cd7251	84
669a5db4 JG	85	static int sun_cable(struct ata_port *ap) {
669a5db4 JG	86	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	87
669a5db4 JG	88	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
	89	return ATA_CBL_PATA80;
	90	return ATA_CBL_PATA40;
	91	}
	92
	93	/**
	94	* osb4_cable - OSB4 cable detect
	95	* @ap: ATA port to check
	96	*
	97	* The OSB4 isn't UDMA66 capable so this is easy
	98	*/
	99
	100	static int osb4_cable(struct ata_port *ap) {
	101	return ATA_CBL_PATA40;
	102	}
	103
	104	/**
0f069788	105	* csb_cable - CSB5/6 cable detect
669a5db4 JG	106	* @ap: ATA port to check
	107	*
	108	* Serverworks default arrangement is to use the drive side detection
	109	* only.
	110	*/
	111
	112	static int csb_cable(struct ata_port *ap) {
0f069788	113	return ATA_CBL_PATA_UNK;
669a5db4 JG	114	}
	115
	116	struct sv_cable_table {
	117	int device;
	118	int subvendor;
	119	int (cable_detect)(struct ata_port ap);
	120	};
	121
	122	/*
	123	* Note that we don't copy the old serverworks code because the old
	124	* code contains obvious mistakes
	125	*/
85cd7251	126
669a5db4 JG	127	static struct sv_cable_table cable_detect[] = {
	128	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
	129	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
	130	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable },
68d0d7ab	131	{ PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable },
669a5db4 JG	132	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
	133	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
	134	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
	135	{ PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
	136	{ }
	137	};
	138
	139	/**
a0fcdc02	140	* serverworks_cable_detect - cable detection
669a5db4	141	* @ap: ATA port
d4b2bab4	142	* @deadline: deadline jiffies for the operation
669a5db4	143	*
85cd7251	144	* Perform cable detection according to the device and subvendor
669a5db4 JG	145	* identifications
669a5db4 JG	146	*/
85cd7251	147
d4b2bab4 TH	148	static int serverworks_cable_detect(struct ata_port *ap)
d4b2bab4 TH	149	{
669a5db4 JG	150	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	151	struct sv_cable_table *cb = cable_detect;
	152
	153	while(cb->device) {
85cd7251	154	if (cb->device == pdev->device &&
669a5db4 JG	155	(cb->subvendor == pdev->subsystem_vendor \|\|
669a5db4 JG	156	cb->subvendor == PCI_ANY_ID)) {
a0fcdc02	157	return cb->cable_detect(ap);
669a5db4 JG	158	}
	159	cb++;
	160	}
	161
	162	BUG();
	163	return -1; /* kill compiler warning */
	164	}
	165
669a5db4 JG	166	/**
	167	* serverworks_is_csb - Check for CSB or OSB
	168	* @pdev: PCI device to check
	169	*
	170	* Returns true if the device being checked is known to be a CSB
	171	* series device.
	172	*/
85cd7251	173
669a5db4 JG	174	static u8 serverworks_is_csb(struct pci_dev *pdev)
	175	{
	176	switch (pdev->device) {
	177	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	178	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	179	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
	180	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
	181	return 1;
	182	default:
	183	break;
	184	}
	185	return 0;
	186	}
	187
	188	/**
	189	* serverworks_osb4_filter - mode selection filter
669a5db4	190	* @adev: ATA device
a76b62ca	191	* @mask: Mask of proposed modes
669a5db4 JG	192	*
	193	* Filter the offered modes for the device to apply controller
	194	* specific rules. OSB4 requires no UDMA for disks due to a FIFO
	195	* bug we hit.
	196	*/
85cd7251	197
a76b62ca	198	static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	199	{
	200	if (adev->class == ATA_DEV_ATA)
	201	mask &= ~ATA_MASK_UDMA;
a76b62ca	202	return ata_pci_default_filter(adev, mask);
669a5db4 JG	203	}
	204
	205
	206	/**
	207	* serverworks_csb_filter - mode selection filter
669a5db4	208	* @adev: ATA device
a76b62ca	209	* @mask: Mask of proposed modes
669a5db4 JG	210	*
	211	* Check the blacklist and disable UDMA5 if matched
	212	*/
	213
a76b62ca	214	static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	215	{
669a5db4 JG	216	const char *p;
8bfa79fc TH	217	char model_num[ATA_ID_PROD_LEN + 1];
8bfa79fc TH	218	int i;
669a5db4	219
85cd7251	220	/* Disk, UDMA */
669a5db4	221	if (adev->class != ATA_DEV_ATA)
a76b62ca	222	return ata_pci_default_filter(adev, mask);
669a5db4 JG	223
669a5db4 JG	224	/* Actually do need to check */
8bfa79fc	225	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
85cd7251	226
8bfa79fc TH	227	for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
8bfa79fc TH	228	if (!strcmp(p, model_num))
6ddd6861	229	mask &= ~(0xE0 << ATA_SHIFT_UDMA);
669a5db4	230	}
a76b62ca	231	return ata_pci_default_filter(adev, mask);
669a5db4 JG	232	}
669a5db4 JG	233
669a5db4 JG	234	/**
	235	* serverworks_set_piomode - set initial PIO mode data
	236	* @ap: ATA interface
	237	* @adev: ATA device
	238	*
	239	* Program the OSB4/CSB5 timing registers for PIO. The PIO register
	240	* load is done as a simple lookup.
	241	*/
	242	static void serverworks_set_piomode(struct ata_port ap, struct ata_device adev)
	243	{
	244	static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
0f069788	245	int offset = 1 + 2 * ap->port_no - adev->devno;
669a5db4 JG	246	int devbits = (2 * ap->port_no + adev->devno) * 4;
	247	u16 csb5_pio;
	248	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	249	int pio = adev->pio_mode - XFER_PIO_0;
	250
	251	pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
85cd7251	252
669a5db4 JG	253	/* The OSB4 just requires the timing but the CSB series want the
	254	mode number as well */
	255	if (serverworks_is_csb(pdev)) {
	256	pci_read_config_word(pdev, 0x4A, &csb5_pio);
	257	csb5_pio &= ~(0x0F << devbits);
	258	pci_write_config_byte(pdev, 0x4A, csb5_pio \| (pio << devbits));
	259	}
	260	}
	261
	262	/**
	263	* serverworks_set_dmamode - set initial DMA mode data
	264	* @ap: ATA interface
	265	* @adev: ATA device
	266	*
	267	* Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
	268	* chipset. The MWDMA mode values are pulled from a lookup table
	269	* while the chipset uses mode number for UDMA.
	270	*/
	271
	272	static void serverworks_set_dmamode(struct ata_port ap, struct ata_device adev)
	273	{
	274	static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
	275	int offset = 1 + 2 * ap->port_no - adev->devno;
36beb823	276	int devbits = 2 * ap->port_no + adev->devno;
669a5db4 JG	277	u8 ultra;
	278	u8 ultra_cfg;
	279	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	280
	281	pci_read_config_byte(pdev, 0x54, &ultra_cfg);
36beb823 AC	282	pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
36beb823 AC	283	ultra &= ~(0x0F << (adev->devno * 4));
669a5db4 JG	284
	285	if (adev->dma_mode >= XFER_UDMA_0) {
	286	pci_write_config_byte(pdev, 0x44 + offset, 0x20);
	287
669a5db4	288	ultra \|= (adev->dma_mode - XFER_UDMA_0)
36beb823	289	<< (adev->devno * 4);
669a5db4 JG	290	ultra_cfg \|= (1 << devbits);
669a5db4 JG	291	} else {
85cd7251	292	pci_write_config_byte(pdev, 0x44 + offset,
669a5db4 JG	293	dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
	294	ultra_cfg &= ~(1 << devbits);
	295	}
36beb823	296	pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
669a5db4 JG	297	pci_write_config_byte(pdev, 0x54, ultra_cfg);
	298	}
	299
	300	static struct scsi_host_template serverworks_sht = {
68d1d07b	301	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	302	};
	303
	304	static struct ata_port_operations serverworks_osb4_port_ops = {
669a5db4 JG	305	.set_piomode = serverworks_set_piomode,
	306	.set_dmamode = serverworks_set_dmamode,
	307	.mode_filter = serverworks_osb4_filter,
85cd7251	308
669a5db4 JG	309	.tf_load = ata_tf_load,
	310	.tf_read = ata_tf_read,
	311	.check_status = ata_check_status,
	312	.exec_command = ata_exec_command,
	313	.dev_select = ata_std_dev_select,
	314
	315	.freeze = ata_bmdma_freeze,
	316	.thaw = ata_bmdma_thaw,
a0fcdc02	317	.error_handler = ata_bmdma_error_handler,
669a5db4	318	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	319	.cable_detect = serverworks_cable_detect,
669a5db4 JG	320
	321	.bmdma_setup = ata_bmdma_setup,
	322	.bmdma_start = ata_bmdma_start,
	323	.bmdma_stop = ata_bmdma_stop,
	324	.bmdma_status = ata_bmdma_status,
	325
	326	.qc_prep = ata_qc_prep,
	327	.qc_issue = ata_qc_issue_prot,
bda30288	328
0d5ff566	329	.data_xfer = ata_data_xfer,
85cd7251	330
669a5db4	331	.irq_handler = ata_interrupt,
efbf3f14	332	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	333	.irq_on = ata_irq_on,
efbf3f14	334
81ad1837	335	.port_start = ata_sff_port_start,
85cd7251	336	};
669a5db4 JG	337
669a5db4 JG	338	static struct ata_port_operations serverworks_csb_port_ops = {
669a5db4 JG	339	.set_piomode = serverworks_set_piomode,
	340	.set_dmamode = serverworks_set_dmamode,
	341	.mode_filter = serverworks_csb_filter,
85cd7251	342
669a5db4 JG	343	.tf_load = ata_tf_load,
	344	.tf_read = ata_tf_read,
	345	.check_status = ata_check_status,
	346	.exec_command = ata_exec_command,
	347	.dev_select = ata_std_dev_select,
	348
	349	.freeze = ata_bmdma_freeze,
	350	.thaw = ata_bmdma_thaw,
a0fcdc02	351	.error_handler = ata_bmdma_error_handler,
669a5db4	352	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	353	.cable_detect = serverworks_cable_detect,
669a5db4 JG	354
	355	.bmdma_setup = ata_bmdma_setup,
	356	.bmdma_start = ata_bmdma_start,
	357	.bmdma_stop = ata_bmdma_stop,
	358	.bmdma_status = ata_bmdma_status,
	359
	360	.qc_prep = ata_qc_prep,
	361	.qc_issue = ata_qc_issue_prot,
bda30288	362
0d5ff566	363	.data_xfer = ata_data_xfer,
85cd7251	364
669a5db4	365	.irq_handler = ata_interrupt,
efbf3f14	366	.irq_clear = ata_bmdma_irq_clear,
246ce3b6	367	.irq_on = ata_irq_on,
efbf3f14	368
81ad1837	369	.port_start = ata_sff_port_start,
85cd7251	370	};
669a5db4 JG	371
	372	static int serverworks_fixup_osb4(struct pci_dev *pdev)
	373	{
	374	u32 reg;
	375	struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	376	PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
	377	if (isa_dev) {
	378	pci_read_config_dword(isa_dev, 0x64, &reg);
	379	reg &= ~0x00002000; /* disable 600ns interrupt mask */
	380	if (!(reg & 0x00004000))
	381	printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
	382	reg \|= 0x00004000; /* enable UDMA/33 support */
	383	pci_write_config_dword(isa_dev, 0x64, reg);
	384	pci_dev_put(isa_dev);
	385	return 0;
	386	}
	387	printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n");
	388	return -ENODEV;
	389	}
	390
	391	static int serverworks_fixup_csb(struct pci_dev *pdev)
	392	{
669a5db4	393	u8 btr;
85cd7251	394
669a5db4 JG	395	/* Third Channel Test */
	396	if (!(PCI_FUNC(pdev->devfn) & 1)) {
	397	struct pci_dev * findev = NULL;
	398	u32 reg4c = 0;
	399	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	400	PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
	401	if (findev) {
	402	pci_read_config_dword(findev, 0x4C, &reg4c);
	403	reg4c &= ~0x000007FF;
	404	reg4c \|= 0x00000040;
	405	reg4c \|= 0x00000020;
	406	pci_write_config_dword(findev, 0x4C, reg4c);
	407	pci_dev_put(findev);
	408	}
	409	} else {
	410	struct pci_dev * findev = NULL;
	411	u8 reg41 = 0;
	412
	413	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	414	PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
	415	if (findev) {
	416	pci_read_config_byte(findev, 0x41, &reg41);
	417	reg41 &= ~0x40;
	418	pci_write_config_byte(findev, 0x41, reg41);
	419	pci_dev_put(findev);
	420	}
	421	}
	422	/* setup the UDMA Control register
	423	*
	424	* 1. clear bit 6 to enable DMA
	425	* 2. enable DMA modes with bits 0-1
	426	* 00 : legacy
	427	* 01 : udma2
	428	* 10 : udma2/udma4
	429	* 11 : udma2/udma4/udma5
	430	*/
	431	pci_read_config_byte(pdev, 0x5A, &btr);
	432	btr &= ~0x40;
	433	if (!(PCI_FUNC(pdev->devfn) & 1))
	434	btr \|= 0x2;
	435	else
44c10138	436	btr \|= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
669a5db4	437	pci_write_config_byte(pdev, 0x5A, btr);
85cd7251	438
669a5db4 JG	439	return btr;
	440	}
	441
	442	static void serverworks_fixup_ht1000(struct pci_dev *pdev)
	443	{
	444	u8 btr;
	445	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	446	pci_read_config_byte(pdev, 0x5A, &btr);
	447	btr &= ~0x40;
	448	btr \|= 0x3;
	449	pci_write_config_byte(pdev, 0x5A, btr);
	450	}
	451
	452
	453	static int serverworks_init_one(struct pci_dev pdev, const struct pci_device_id id)
	454	{
1626aeb8	455	static const struct ata_port_info info[4] = {
669a5db4 JG	456	{ /* OSB4 */
669a5db4 JG	457	.sht = &serverworks_sht,
1d2808fd	458	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	459	.pio_mask = 0x1f,
	460	.mwdma_mask = 0x07,
	461	.udma_mask = 0x07,
	462	.port_ops = &serverworks_osb4_port_ops
	463	}, { /* OSB4 no UDMA */
	464	.sht = &serverworks_sht,
1d2808fd	465	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	466	.pio_mask = 0x1f,
	467	.mwdma_mask = 0x07,
	468	.udma_mask = 0x00,
	469	.port_ops = &serverworks_osb4_port_ops
	470	}, { /* CSB5 */
	471	.sht = &serverworks_sht,
1d2808fd	472	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	473	.pio_mask = 0x1f,
669a5db4 JG	474	.mwdma_mask = 0x07,
bf6263a8	475	.udma_mask = ATA_UDMA4,
669a5db4 JG	476	.port_ops = &serverworks_csb_port_ops
	477	}, { /* CSB5 - later revisions*/
	478	.sht = &serverworks_sht,
1d2808fd	479	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	480	.pio_mask = 0x1f,
669a5db4 JG	481	.mwdma_mask = 0x07,
bf6263a8	482	.udma_mask = ATA_UDMA5,
669a5db4 JG	483	.port_ops = &serverworks_csb_port_ops
	484	}
	485	};
1626aeb8	486	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
f08048e9 TH	487	int rc;
	488
	489	rc = pcim_enable_device(pdev);
	490	if (rc)
	491	return rc;
85cd7251	492
669a5db4 JG	493	/* Force master latency timer to 64 PCI clocks */
	494	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
	495
	496	/* OSB4 : South Bridge and IDE */
	497	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
	498	/* Select non UDMA capable OSB4 if we can't do fixups */
	499	if ( serverworks_fixup_osb4(pdev) < 0)
1626aeb8	500	ppi[0] = &info[1];
669a5db4 JG	501	}
	502	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	503	else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) \|\|
	504	(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	505	(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
85cd7251	506
669a5db4 JG	507	/* If the returned btr is the newer revision then
	508	select the right info block */
	509	if (serverworks_fixup_csb(pdev) == 3)
1626aeb8	510	ppi[0] = &info[3];
85cd7251	511
669a5db4 JG	512	/* Is this the 3rd channel CSB6 IDE ? */
669a5db4 JG	513	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
1626aeb8	514	ppi[1] = &ata_dummy_port_info;
669a5db4 JG	515	}
	516	/* setup HT1000E */
	517	else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
	518	serverworks_fixup_ht1000(pdev);
85cd7251	519
669a5db4 JG	520	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
669a5db4 JG	521	ata_pci_clear_simplex(pdev);
85cd7251	522
1626aeb8	523	return ata_pci_init_one(pdev, ppi);
669a5db4 JG	524	}
669a5db4 JG	525
438ac6d5	526	#ifdef CONFIG_PM
38e0d56e AC	527	static int serverworks_reinit_one(struct pci_dev *pdev)
38e0d56e AC	528	{
f08048e9 TH	529	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	530	int rc;
	531
	532	rc = ata_pci_device_do_resume(pdev);
	533	if (rc)
	534	return rc;
	535
38e0d56e AC	536	/* Force master latency timer to 64 PCI clocks */
38e0d56e AC	537	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
f20b16ff	538
f08048e9	539	switch (pdev->device) {
38e0d56e AC	540	case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
	541	serverworks_fixup_osb4(pdev);
	542	break;
	543	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	544	ata_pci_clear_simplex(pdev);
	545	/* fall through */
	546	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	547	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
	548	serverworks_fixup_csb(pdev);
	549	break;
	550	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
	551	serverworks_fixup_ht1000(pdev);
	552	break;
	553	}
f08048e9 TH	554
	555	ata_host_resume(host);
	556	return 0;
38e0d56e	557	}
438ac6d5	558	#endif
38e0d56e	559
2d2744fc JG	560	static const struct pci_device_id serverworks[] = {
	561	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
	562	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
	563	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
	564	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
	565	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
	566
	567	{ },
669a5db4 JG	568	};
	569
	570	static struct pci_driver serverworks_pci_driver = {
	571	.name = DRV_NAME,
	572	.id_table = serverworks,
	573	.probe = serverworks_init_one,
38e0d56e	574	.remove = ata_pci_remove_one,
438ac6d5	575	#ifdef CONFIG_PM
38e0d56e AC	576	.suspend = ata_pci_device_suspend,
38e0d56e AC	577	.resume = serverworks_reinit_one,
438ac6d5	578	#endif
669a5db4 JG	579	};
	580
	581	static int __init serverworks_init(void)
	582	{
	583	return pci_register_driver(&serverworks_pci_driver);
	584	}
	585
669a5db4 JG	586	static void __exit serverworks_exit(void)
	587	{
	588	pci_unregister_driver(&serverworks_pci_driver);
	589	}
	590
669a5db4 JG	591	MODULE_AUTHOR("Alan Cox");
	592	MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
	593	MODULE_LICENSE("GPL");
	594	MODULE_DEVICE_TABLE(pci, serverworks);
	595	MODULE_VERSION(DRV_VERSION);
	596
	597	module_init(serverworks_init);
	598	module_exit(serverworks_exit);