]>
Commit | Line | Data |
---|---|---|
669a5db4 JG |
1 | /* |
2 | * pata_sil680.c - SIL680 PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * based upon | |
7 | * | |
8 | * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003 | |
9 | * | |
10 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
11 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
12 | * | |
13 | * May be copied or modified under the terms of the GNU General Public License | |
14 | * | |
15 | * Documentation publically available. | |
16 | * | |
17 | * If you have strange problems with nVidia chipset systems please | |
18 | * see the SI support documentation and update your system BIOS | |
19 | * if neccessary | |
20 | * | |
21 | * TODO | |
22 | * If we know all our devices are LBA28 (or LBA28 sized) we could use | |
23 | * the command fifo mode. | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/blkdev.h> | |
31 | #include <linux/delay.h> | |
32 | #include <scsi/scsi_host.h> | |
33 | #include <linux/libata.h> | |
34 | ||
35 | #define DRV_NAME "pata_sil680" | |
2a3103ce | 36 | #define DRV_VERSION "0.4.7" |
669a5db4 | 37 | |
79b0bde1 JG |
38 | #define SIL680_MMIO_BAR 5 |
39 | ||
669a5db4 JG |
40 | /** |
41 | * sil680_selreg - return register base | |
42 | * @hwif: interface | |
43 | * @r: config offset | |
44 | * | |
45 | * Turn a config register offset into the right address in either | |
46 | * PCI space or MMIO space to access the control register in question | |
47 | * Thankfully this is a configuration operation so isnt performance | |
48 | * criticial. | |
49 | */ | |
50 | ||
51 | static unsigned long sil680_selreg(struct ata_port *ap, int r) | |
52 | { | |
53 | unsigned long base = 0xA0 + r; | |
54 | base += (ap->port_no << 4); | |
55 | return base; | |
56 | } | |
57 | ||
58 | /** | |
59 | * sil680_seldev - return register base | |
60 | * @hwif: interface | |
61 | * @r: config offset | |
62 | * | |
63 | * Turn a config register offset into the right address in either | |
64 | * PCI space or MMIO space to access the control register in question | |
65 | * including accounting for the unit shift. | |
66 | */ | |
67 | ||
68 | static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r) | |
69 | { | |
70 | unsigned long base = 0xA0 + r; | |
71 | base += (ap->port_no << 4); | |
72 | base |= adev->devno ? 2 : 0; | |
73 | return base; | |
74 | } | |
75 | ||
76 | ||
77 | /** | |
78 | * sil680_cable_detect - cable detection | |
79 | * @ap: ATA port | |
80 | * | |
81 | * Perform cable detection. The SIL680 stores this in PCI config | |
82 | * space for us. | |
83 | */ | |
84 | ||
85 | static int sil680_cable_detect(struct ata_port *ap) { | |
86 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
87 | unsigned long addr = sil680_selreg(ap, 0); | |
88 | u8 ata66; | |
89 | pci_read_config_byte(pdev, addr, &ata66); | |
90 | if (ata66 & 1) | |
91 | return ATA_CBL_PATA80; | |
92 | else | |
93 | return ATA_CBL_PATA40; | |
94 | } | |
95 | ||
669a5db4 JG |
96 | /** |
97 | * sil680_bus_reset - reset the SIL680 bus | |
98 | * @ap: ATA port to reset | |
d4b2bab4 | 99 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
100 | * |
101 | * Perform the SIL680 housekeeping when doing an ATA bus reset | |
102 | */ | |
103 | ||
d4b2bab4 TH |
104 | static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes, |
105 | unsigned long deadline) | |
669a5db4 JG |
106 | { |
107 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
108 | unsigned long addr = sil680_selreg(ap, 0); | |
109 | u8 reset; | |
110 | ||
111 | pci_read_config_byte(pdev, addr, &reset); | |
112 | pci_write_config_byte(pdev, addr, reset | 0x03); | |
113 | udelay(25); | |
114 | pci_write_config_byte(pdev, addr, reset); | |
d4b2bab4 | 115 | return ata_std_softreset(ap, classes, deadline); |
669a5db4 JG |
116 | } |
117 | ||
118 | static void sil680_error_handler(struct ata_port *ap) | |
119 | { | |
a0fcdc02 | 120 | ata_bmdma_drive_eh(ap, ata_std_prereset, sil680_bus_reset, NULL, ata_std_postreset); |
669a5db4 JG |
121 | } |
122 | ||
123 | /** | |
124 | * sil680_set_piomode - set initial PIO mode data | |
125 | * @ap: ATA interface | |
126 | * @adev: ATA device | |
127 | * | |
128 | * Program the SIL680 registers for PIO mode. Note that the task speed | |
129 | * registers are shared between the devices so we must pick the lowest | |
130 | * mode for command work. | |
131 | */ | |
132 | ||
133 | static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
134 | { | |
135 | static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 }; | |
5dcade90 | 136 | static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 }; |
669a5db4 JG |
137 | |
138 | unsigned long tfaddr = sil680_selreg(ap, 0x02); | |
139 | unsigned long addr = sil680_seldev(ap, adev, 0x04); | |
cb0e34ba | 140 | unsigned long addr_mask = 0x80 + 4 * ap->port_no; |
669a5db4 JG |
141 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
142 | int pio = adev->pio_mode - XFER_PIO_0; | |
143 | int lowest_pio = pio; | |
cb0e34ba | 144 | int port_shift = 4 * adev->devno; |
669a5db4 | 145 | u16 reg; |
cb0e34ba | 146 | u8 mode; |
669a5db4 JG |
147 | |
148 | struct ata_device *pair = ata_dev_pair(adev); | |
149 | ||
150 | if (pair != NULL && adev->pio_mode > pair->pio_mode) | |
151 | lowest_pio = pair->pio_mode - XFER_PIO_0; | |
152 | ||
153 | pci_write_config_word(pdev, addr, speed_p[pio]); | |
154 | pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]); | |
155 | ||
156 | pci_read_config_word(pdev, tfaddr-2, ®); | |
cb0e34ba | 157 | pci_read_config_byte(pdev, addr_mask, &mode); |
a84471fe | 158 | |
669a5db4 | 159 | reg &= ~0x0200; /* Clear IORDY */ |
cb0e34ba | 160 | mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */ |
a84471fe | 161 | |
cb0e34ba | 162 | if (ata_pio_need_iordy(adev)) { |
669a5db4 | 163 | reg |= 0x0200; /* Enable IORDY */ |
cb0e34ba AC |
164 | mode |= 1 << port_shift; |
165 | } | |
669a5db4 | 166 | pci_write_config_word(pdev, tfaddr-2, reg); |
cb0e34ba | 167 | pci_write_config_byte(pdev, addr_mask, mode); |
669a5db4 JG |
168 | } |
169 | ||
170 | /** | |
171 | * sil680_set_dmamode - set initial DMA mode data | |
172 | * @ap: ATA interface | |
173 | * @adev: ATA device | |
174 | * | |
175 | * Program the MWDMA/UDMA modes for the sil680 k | |
176 | * chipset. The MWDMA mode values are pulled from a lookup table | |
177 | * while the chipset uses mode number for UDMA. | |
178 | */ | |
179 | ||
180 | static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
181 | { | |
182 | static u8 ultra_table[2][7] = { | |
183 | { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */ | |
184 | { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */ | |
185 | }; | |
186 | static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 }; | |
187 | ||
188 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
189 | unsigned long ma = sil680_seldev(ap, adev, 0x08); | |
190 | unsigned long ua = sil680_seldev(ap, adev, 0x0C); | |
191 | unsigned long addr_mask = 0x80 + 4 * ap->port_no; | |
192 | int port_shift = adev->devno * 4; | |
193 | u8 scsc, mode; | |
194 | u16 multi, ultra; | |
195 | ||
196 | pci_read_config_byte(pdev, 0x8A, &scsc); | |
197 | pci_read_config_byte(pdev, addr_mask, &mode); | |
198 | pci_read_config_word(pdev, ma, &multi); | |
199 | pci_read_config_word(pdev, ua, &ultra); | |
200 | ||
201 | /* Mask timing bits */ | |
202 | ultra &= ~0x3F; | |
203 | mode &= ~(0x03 << port_shift); | |
204 | ||
205 | /* Extract scsc */ | |
206 | scsc = (scsc & 0x30) ? 1: 0; | |
207 | ||
208 | if (adev->dma_mode >= XFER_UDMA_0) { | |
209 | multi = 0x10C1; | |
210 | ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0]; | |
211 | mode |= (0x03 << port_shift); | |
212 | } else { | |
213 | multi = dma_table[adev->dma_mode - XFER_MW_DMA_0]; | |
214 | mode |= (0x02 << port_shift); | |
215 | } | |
216 | pci_write_config_byte(pdev, addr_mask, mode); | |
217 | pci_write_config_word(pdev, ma, multi); | |
218 | pci_write_config_word(pdev, ua, ultra); | |
219 | } | |
220 | ||
221 | static struct scsi_host_template sil680_sht = { | |
222 | .module = THIS_MODULE, | |
223 | .name = DRV_NAME, | |
224 | .ioctl = ata_scsi_ioctl, | |
225 | .queuecommand = ata_scsi_queuecmd, | |
226 | .can_queue = ATA_DEF_QUEUE, | |
227 | .this_id = ATA_SHT_THIS_ID, | |
228 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
229 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
230 | .emulated = ATA_SHT_EMULATED, | |
231 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
232 | .proc_name = DRV_NAME, | |
233 | .dma_boundary = ATA_DMA_BOUNDARY, | |
234 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 235 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
236 | .bios_param = ata_std_bios_param, |
237 | }; | |
238 | ||
239 | static struct ata_port_operations sil680_port_ops = { | |
240 | .port_disable = ata_port_disable, | |
241 | .set_piomode = sil680_set_piomode, | |
242 | .set_dmamode = sil680_set_dmamode, | |
243 | .mode_filter = ata_pci_default_filter, | |
244 | .tf_load = ata_tf_load, | |
245 | .tf_read = ata_tf_read, | |
246 | .check_status = ata_check_status, | |
247 | .exec_command = ata_exec_command, | |
248 | .dev_select = ata_std_dev_select, | |
249 | ||
250 | .freeze = ata_bmdma_freeze, | |
251 | .thaw = ata_bmdma_thaw, | |
252 | .error_handler = sil680_error_handler, | |
253 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
a0fcdc02 | 254 | .cable_detect = sil680_cable_detect, |
669a5db4 JG |
255 | |
256 | .bmdma_setup = ata_bmdma_setup, | |
257 | .bmdma_start = ata_bmdma_start, | |
258 | .bmdma_stop = ata_bmdma_stop, | |
259 | .bmdma_status = ata_bmdma_status, | |
260 | ||
261 | .qc_prep = ata_qc_prep, | |
262 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 263 | |
0d5ff566 | 264 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
265 | |
266 | .irq_handler = ata_interrupt, | |
267 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
268 | .irq_on = ata_irq_on, |
269 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
270 | |
271 | .port_start = ata_port_start, | |
669a5db4 JG |
272 | }; |
273 | ||
8550c163 AC |
274 | /** |
275 | * sil680_init_chip - chip setup | |
276 | * @pdev: PCI device | |
277 | * | |
278 | * Perform all the chip setup which must be done both when the device | |
279 | * is powered up on boot and when we resume in case we resumed from RAM. | |
280 | * Returns the final clock settings. | |
281 | */ | |
f20b16ff | 282 | |
8550c163 | 283 | static u8 sil680_init_chip(struct pci_dev *pdev) |
669a5db4 | 284 | { |
669a5db4 JG |
285 | u32 class_rev = 0; |
286 | u8 tmpbyte = 0; | |
287 | ||
669a5db4 JG |
288 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev); |
289 | class_rev &= 0xff; | |
290 | /* FIXME: double check */ | |
291 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255); | |
292 | ||
293 | pci_write_config_byte(pdev, 0x80, 0x00); | |
294 | pci_write_config_byte(pdev, 0x84, 0x00); | |
295 | ||
296 | pci_read_config_byte(pdev, 0x8A, &tmpbyte); | |
297 | ||
79b0bde1 JG |
298 | dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", |
299 | tmpbyte & 1, tmpbyte & 0x30); | |
669a5db4 JG |
300 | |
301 | switch(tmpbyte & 0x30) { | |
302 | case 0x00: | |
303 | /* 133 clock attempt to force it on */ | |
304 | pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10); | |
305 | break; | |
306 | case 0x30: | |
307 | /* if clocking is disabled */ | |
308 | /* 133 clock attempt to force it on */ | |
309 | pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20); | |
310 | break; | |
311 | case 0x10: | |
312 | /* 133 already */ | |
313 | break; | |
314 | case 0x20: | |
315 | /* BIOS set PCI x2 clocking */ | |
316 | break; | |
317 | } | |
318 | ||
319 | pci_read_config_byte(pdev, 0x8A, &tmpbyte); | |
79b0bde1 JG |
320 | dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", |
321 | tmpbyte & 1, tmpbyte & 0x30); | |
669a5db4 JG |
322 | |
323 | pci_write_config_byte(pdev, 0xA1, 0x72); | |
324 | pci_write_config_word(pdev, 0xA2, 0x328A); | |
325 | pci_write_config_dword(pdev, 0xA4, 0x62DD62DD); | |
326 | pci_write_config_dword(pdev, 0xA8, 0x43924392); | |
327 | pci_write_config_dword(pdev, 0xAC, 0x40094009); | |
328 | pci_write_config_byte(pdev, 0xB1, 0x72); | |
329 | pci_write_config_word(pdev, 0xB2, 0x328A); | |
330 | pci_write_config_dword(pdev, 0xB4, 0x62DD62DD); | |
331 | pci_write_config_dword(pdev, 0xB8, 0x43924392); | |
332 | pci_write_config_dword(pdev, 0xBC, 0x40094009); | |
333 | ||
334 | switch(tmpbyte & 0x30) { | |
335 | case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break; | |
336 | case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break; | |
337 | case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break; | |
338 | /* This last case is _NOT_ ok */ | |
339 | case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n"); | |
8550c163 AC |
340 | } |
341 | return tmpbyte & 0x30; | |
342 | } | |
343 | ||
79b0bde1 JG |
344 | static int __devinit sil680_init_one(struct pci_dev *pdev, |
345 | const struct pci_device_id *id) | |
8550c163 | 346 | { |
1626aeb8 | 347 | static const struct ata_port_info info = { |
8550c163 | 348 | .sht = &sil680_sht, |
1d2808fd | 349 | .flags = ATA_FLAG_SLAVE_POSS, |
8550c163 AC |
350 | .pio_mask = 0x1f, |
351 | .mwdma_mask = 0x07, | |
bf6263a8 | 352 | .udma_mask = ATA_UDMA6, |
8550c163 AC |
353 | .port_ops = &sil680_port_ops |
354 | }; | |
1626aeb8 | 355 | static const struct ata_port_info info_slow = { |
8550c163 | 356 | .sht = &sil680_sht, |
1d2808fd | 357 | .flags = ATA_FLAG_SLAVE_POSS, |
8550c163 AC |
358 | .pio_mask = 0x1f, |
359 | .mwdma_mask = 0x07, | |
bf6263a8 | 360 | .udma_mask = ATA_UDMA5, |
8550c163 AC |
361 | .port_ops = &sil680_port_ops |
362 | }; | |
1626aeb8 | 363 | const struct ata_port_info *ppi[] = { &info, NULL }; |
8550c163 AC |
364 | static int printed_version; |
365 | ||
366 | if (!printed_version++) | |
367 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
368 | ||
369 | switch(sil680_init_chip(pdev)) | |
370 | { | |
371 | case 0: | |
1626aeb8 | 372 | ppi[0] = &info_slow; |
8550c163 AC |
373 | break; |
374 | case 0x30: | |
375 | return -ENODEV; | |
669a5db4 | 376 | } |
1626aeb8 | 377 | return ata_pci_init_one(pdev, ppi); |
669a5db4 JG |
378 | } |
379 | ||
438ac6d5 | 380 | #ifdef CONFIG_PM |
8550c163 AC |
381 | static int sil680_reinit_one(struct pci_dev *pdev) |
382 | { | |
383 | sil680_init_chip(pdev); | |
384 | return ata_pci_device_resume(pdev); | |
385 | } | |
438ac6d5 | 386 | #endif |
8550c163 | 387 | |
669a5db4 | 388 | static const struct pci_device_id sil680[] = { |
2d2744fc JG |
389 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), }, |
390 | ||
391 | { }, | |
669a5db4 JG |
392 | }; |
393 | ||
394 | static struct pci_driver sil680_pci_driver = { | |
2d2744fc | 395 | .name = DRV_NAME, |
669a5db4 JG |
396 | .id_table = sil680, |
397 | .probe = sil680_init_one, | |
8550c163 | 398 | .remove = ata_pci_remove_one, |
438ac6d5 | 399 | #ifdef CONFIG_PM |
8550c163 AC |
400 | .suspend = ata_pci_device_suspend, |
401 | .resume = sil680_reinit_one, | |
438ac6d5 | 402 | #endif |
669a5db4 JG |
403 | }; |
404 | ||
405 | static int __init sil680_init(void) | |
406 | { | |
407 | return pci_register_driver(&sil680_pci_driver); | |
408 | } | |
409 | ||
669a5db4 JG |
410 | static void __exit sil680_exit(void) |
411 | { | |
412 | pci_unregister_driver(&sil680_pci_driver); | |
413 | } | |
414 | ||
669a5db4 JG |
415 | MODULE_AUTHOR("Alan Cox"); |
416 | MODULE_DESCRIPTION("low-level driver for SI680 PATA"); | |
417 | MODULE_LICENSE("GPL"); | |
418 | MODULE_DEVICE_TABLE(pci, sil680); | |
419 | MODULE_VERSION(DRV_VERSION); | |
420 | ||
421 | module_init(sil680_init); | |
422 | module_exit(sil680_exit); |