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669a5db4 JG |
1 | /* |
2 | * pata_sil680.c - SIL680 PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * based upon | |
7 | * | |
8 | * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003 | |
9 | * | |
10 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> | |
11 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
12 | * | |
13 | * May be copied or modified under the terms of the GNU General Public License | |
14 | * | |
15 | * Documentation publically available. | |
16 | * | |
17 | * If you have strange problems with nVidia chipset systems please | |
18 | * see the SI support documentation and update your system BIOS | |
19 | * if neccessary | |
20 | * | |
21 | * TODO | |
22 | * If we know all our devices are LBA28 (or LBA28 sized) we could use | |
23 | * the command fifo mode. | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/blkdev.h> | |
31 | #include <linux/delay.h> | |
32 | #include <scsi/scsi_host.h> | |
33 | #include <linux/libata.h> | |
34 | ||
35 | #define DRV_NAME "pata_sil680" | |
2a3103ce | 36 | #define DRV_VERSION "0.4.7" |
669a5db4 | 37 | |
79b0bde1 JG |
38 | #define SIL680_MMIO_BAR 5 |
39 | ||
669a5db4 JG |
40 | /** |
41 | * sil680_selreg - return register base | |
42 | * @hwif: interface | |
43 | * @r: config offset | |
44 | * | |
45 | * Turn a config register offset into the right address in either | |
46 | * PCI space or MMIO space to access the control register in question | |
47 | * Thankfully this is a configuration operation so isnt performance | |
48 | * criticial. | |
49 | */ | |
50 | ||
51 | static unsigned long sil680_selreg(struct ata_port *ap, int r) | |
52 | { | |
53 | unsigned long base = 0xA0 + r; | |
54 | base += (ap->port_no << 4); | |
55 | return base; | |
56 | } | |
57 | ||
58 | /** | |
59 | * sil680_seldev - return register base | |
60 | * @hwif: interface | |
61 | * @r: config offset | |
62 | * | |
63 | * Turn a config register offset into the right address in either | |
64 | * PCI space or MMIO space to access the control register in question | |
65 | * including accounting for the unit shift. | |
66 | */ | |
67 | ||
68 | static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r) | |
69 | { | |
70 | unsigned long base = 0xA0 + r; | |
71 | base += (ap->port_no << 4); | |
72 | base |= adev->devno ? 2 : 0; | |
73 | return base; | |
74 | } | |
75 | ||
76 | ||
77 | /** | |
78 | * sil680_cable_detect - cable detection | |
79 | * @ap: ATA port | |
80 | * | |
81 | * Perform cable detection. The SIL680 stores this in PCI config | |
82 | * space for us. | |
83 | */ | |
84 | ||
85 | static int sil680_cable_detect(struct ata_port *ap) { | |
86 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
87 | unsigned long addr = sil680_selreg(ap, 0); | |
88 | u8 ata66; | |
89 | pci_read_config_byte(pdev, addr, &ata66); | |
90 | if (ata66 & 1) | |
91 | return ATA_CBL_PATA80; | |
92 | else | |
93 | return ATA_CBL_PATA40; | |
94 | } | |
95 | ||
669a5db4 JG |
96 | /** |
97 | * sil680_bus_reset - reset the SIL680 bus | |
cc0680a5 | 98 | * @link: ATA link to reset |
d4b2bab4 | 99 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
100 | * |
101 | * Perform the SIL680 housekeeping when doing an ATA bus reset | |
102 | */ | |
103 | ||
cc0680a5 | 104 | static int sil680_bus_reset(struct ata_link *link, unsigned int *classes, |
d4b2bab4 | 105 | unsigned long deadline) |
669a5db4 | 106 | { |
cc0680a5 | 107 | struct ata_port *ap = link->ap; |
669a5db4 JG |
108 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
109 | unsigned long addr = sil680_selreg(ap, 0); | |
110 | u8 reset; | |
111 | ||
112 | pci_read_config_byte(pdev, addr, &reset); | |
113 | pci_write_config_byte(pdev, addr, reset | 0x03); | |
114 | udelay(25); | |
115 | pci_write_config_byte(pdev, addr, reset); | |
cc0680a5 | 116 | return ata_std_softreset(link, classes, deadline); |
669a5db4 JG |
117 | } |
118 | ||
119 | static void sil680_error_handler(struct ata_port *ap) | |
120 | { | |
a0fcdc02 | 121 | ata_bmdma_drive_eh(ap, ata_std_prereset, sil680_bus_reset, NULL, ata_std_postreset); |
669a5db4 JG |
122 | } |
123 | ||
124 | /** | |
125 | * sil680_set_piomode - set initial PIO mode data | |
126 | * @ap: ATA interface | |
127 | * @adev: ATA device | |
128 | * | |
129 | * Program the SIL680 registers for PIO mode. Note that the task speed | |
130 | * registers are shared between the devices so we must pick the lowest | |
131 | * mode for command work. | |
132 | */ | |
133 | ||
134 | static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
135 | { | |
136 | static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 }; | |
5dcade90 | 137 | static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 }; |
669a5db4 JG |
138 | |
139 | unsigned long tfaddr = sil680_selreg(ap, 0x02); | |
140 | unsigned long addr = sil680_seldev(ap, adev, 0x04); | |
cb0e34ba | 141 | unsigned long addr_mask = 0x80 + 4 * ap->port_no; |
669a5db4 JG |
142 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
143 | int pio = adev->pio_mode - XFER_PIO_0; | |
144 | int lowest_pio = pio; | |
cb0e34ba | 145 | int port_shift = 4 * adev->devno; |
669a5db4 | 146 | u16 reg; |
cb0e34ba | 147 | u8 mode; |
669a5db4 JG |
148 | |
149 | struct ata_device *pair = ata_dev_pair(adev); | |
150 | ||
151 | if (pair != NULL && adev->pio_mode > pair->pio_mode) | |
152 | lowest_pio = pair->pio_mode - XFER_PIO_0; | |
153 | ||
154 | pci_write_config_word(pdev, addr, speed_p[pio]); | |
155 | pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]); | |
156 | ||
157 | pci_read_config_word(pdev, tfaddr-2, ®); | |
cb0e34ba | 158 | pci_read_config_byte(pdev, addr_mask, &mode); |
a84471fe | 159 | |
669a5db4 | 160 | reg &= ~0x0200; /* Clear IORDY */ |
cb0e34ba | 161 | mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */ |
a84471fe | 162 | |
cb0e34ba | 163 | if (ata_pio_need_iordy(adev)) { |
669a5db4 | 164 | reg |= 0x0200; /* Enable IORDY */ |
cb0e34ba AC |
165 | mode |= 1 << port_shift; |
166 | } | |
669a5db4 | 167 | pci_write_config_word(pdev, tfaddr-2, reg); |
cb0e34ba | 168 | pci_write_config_byte(pdev, addr_mask, mode); |
669a5db4 JG |
169 | } |
170 | ||
171 | /** | |
172 | * sil680_set_dmamode - set initial DMA mode data | |
173 | * @ap: ATA interface | |
174 | * @adev: ATA device | |
175 | * | |
176 | * Program the MWDMA/UDMA modes for the sil680 k | |
177 | * chipset. The MWDMA mode values are pulled from a lookup table | |
178 | * while the chipset uses mode number for UDMA. | |
179 | */ | |
180 | ||
181 | static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
182 | { | |
183 | static u8 ultra_table[2][7] = { | |
184 | { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */ | |
185 | { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */ | |
186 | }; | |
187 | static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 }; | |
188 | ||
189 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
190 | unsigned long ma = sil680_seldev(ap, adev, 0x08); | |
191 | unsigned long ua = sil680_seldev(ap, adev, 0x0C); | |
192 | unsigned long addr_mask = 0x80 + 4 * ap->port_no; | |
193 | int port_shift = adev->devno * 4; | |
194 | u8 scsc, mode; | |
195 | u16 multi, ultra; | |
196 | ||
197 | pci_read_config_byte(pdev, 0x8A, &scsc); | |
198 | pci_read_config_byte(pdev, addr_mask, &mode); | |
199 | pci_read_config_word(pdev, ma, &multi); | |
200 | pci_read_config_word(pdev, ua, &ultra); | |
201 | ||
202 | /* Mask timing bits */ | |
203 | ultra &= ~0x3F; | |
204 | mode &= ~(0x03 << port_shift); | |
205 | ||
206 | /* Extract scsc */ | |
207 | scsc = (scsc & 0x30) ? 1: 0; | |
208 | ||
209 | if (adev->dma_mode >= XFER_UDMA_0) { | |
210 | multi = 0x10C1; | |
211 | ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0]; | |
212 | mode |= (0x03 << port_shift); | |
213 | } else { | |
214 | multi = dma_table[adev->dma_mode - XFER_MW_DMA_0]; | |
215 | mode |= (0x02 << port_shift); | |
216 | } | |
217 | pci_write_config_byte(pdev, addr_mask, mode); | |
218 | pci_write_config_word(pdev, ma, multi); | |
219 | pci_write_config_word(pdev, ua, ultra); | |
220 | } | |
221 | ||
222 | static struct scsi_host_template sil680_sht = { | |
223 | .module = THIS_MODULE, | |
224 | .name = DRV_NAME, | |
225 | .ioctl = ata_scsi_ioctl, | |
226 | .queuecommand = ata_scsi_queuecmd, | |
227 | .can_queue = ATA_DEF_QUEUE, | |
228 | .this_id = ATA_SHT_THIS_ID, | |
229 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
230 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
231 | .emulated = ATA_SHT_EMULATED, | |
232 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
233 | .proc_name = DRV_NAME, | |
234 | .dma_boundary = ATA_DMA_BOUNDARY, | |
235 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 236 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
237 | .bios_param = ata_std_bios_param, |
238 | }; | |
239 | ||
240 | static struct ata_port_operations sil680_port_ops = { | |
669a5db4 JG |
241 | .set_piomode = sil680_set_piomode, |
242 | .set_dmamode = sil680_set_dmamode, | |
243 | .mode_filter = ata_pci_default_filter, | |
244 | .tf_load = ata_tf_load, | |
245 | .tf_read = ata_tf_read, | |
246 | .check_status = ata_check_status, | |
247 | .exec_command = ata_exec_command, | |
248 | .dev_select = ata_std_dev_select, | |
249 | ||
250 | .freeze = ata_bmdma_freeze, | |
251 | .thaw = ata_bmdma_thaw, | |
252 | .error_handler = sil680_error_handler, | |
253 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
a0fcdc02 | 254 | .cable_detect = sil680_cable_detect, |
669a5db4 JG |
255 | |
256 | .bmdma_setup = ata_bmdma_setup, | |
257 | .bmdma_start = ata_bmdma_start, | |
258 | .bmdma_stop = ata_bmdma_stop, | |
259 | .bmdma_status = ata_bmdma_status, | |
260 | ||
261 | .qc_prep = ata_qc_prep, | |
262 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 263 | |
0d5ff566 | 264 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
265 | |
266 | .irq_handler = ata_interrupt, | |
267 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 | 268 | .irq_on = ata_irq_on, |
669a5db4 | 269 | |
81ad1837 | 270 | .port_start = ata_sff_port_start, |
669a5db4 JG |
271 | }; |
272 | ||
8550c163 AC |
273 | /** |
274 | * sil680_init_chip - chip setup | |
275 | * @pdev: PCI device | |
276 | * | |
277 | * Perform all the chip setup which must be done both when the device | |
278 | * is powered up on boot and when we resume in case we resumed from RAM. | |
279 | * Returns the final clock settings. | |
280 | */ | |
f20b16ff | 281 | |
8550c163 | 282 | static u8 sil680_init_chip(struct pci_dev *pdev) |
669a5db4 | 283 | { |
669a5db4 JG |
284 | u32 class_rev = 0; |
285 | u8 tmpbyte = 0; | |
286 | ||
669a5db4 JG |
287 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev); |
288 | class_rev &= 0xff; | |
289 | /* FIXME: double check */ | |
290 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255); | |
291 | ||
292 | pci_write_config_byte(pdev, 0x80, 0x00); | |
293 | pci_write_config_byte(pdev, 0x84, 0x00); | |
294 | ||
295 | pci_read_config_byte(pdev, 0x8A, &tmpbyte); | |
296 | ||
79b0bde1 JG |
297 | dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", |
298 | tmpbyte & 1, tmpbyte & 0x30); | |
669a5db4 JG |
299 | |
300 | switch(tmpbyte & 0x30) { | |
301 | case 0x00: | |
302 | /* 133 clock attempt to force it on */ | |
303 | pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10); | |
304 | break; | |
305 | case 0x30: | |
306 | /* if clocking is disabled */ | |
307 | /* 133 clock attempt to force it on */ | |
308 | pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20); | |
309 | break; | |
310 | case 0x10: | |
311 | /* 133 already */ | |
312 | break; | |
313 | case 0x20: | |
314 | /* BIOS set PCI x2 clocking */ | |
315 | break; | |
316 | } | |
317 | ||
318 | pci_read_config_byte(pdev, 0x8A, &tmpbyte); | |
79b0bde1 JG |
319 | dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", |
320 | tmpbyte & 1, tmpbyte & 0x30); | |
669a5db4 JG |
321 | |
322 | pci_write_config_byte(pdev, 0xA1, 0x72); | |
323 | pci_write_config_word(pdev, 0xA2, 0x328A); | |
324 | pci_write_config_dword(pdev, 0xA4, 0x62DD62DD); | |
325 | pci_write_config_dword(pdev, 0xA8, 0x43924392); | |
326 | pci_write_config_dword(pdev, 0xAC, 0x40094009); | |
327 | pci_write_config_byte(pdev, 0xB1, 0x72); | |
328 | pci_write_config_word(pdev, 0xB2, 0x328A); | |
329 | pci_write_config_dword(pdev, 0xB4, 0x62DD62DD); | |
330 | pci_write_config_dword(pdev, 0xB8, 0x43924392); | |
331 | pci_write_config_dword(pdev, 0xBC, 0x40094009); | |
332 | ||
333 | switch(tmpbyte & 0x30) { | |
334 | case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break; | |
335 | case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break; | |
336 | case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break; | |
337 | /* This last case is _NOT_ ok */ | |
338 | case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n"); | |
8550c163 AC |
339 | } |
340 | return tmpbyte & 0x30; | |
341 | } | |
342 | ||
79b0bde1 JG |
343 | static int __devinit sil680_init_one(struct pci_dev *pdev, |
344 | const struct pci_device_id *id) | |
8550c163 | 345 | { |
1626aeb8 | 346 | static const struct ata_port_info info = { |
8550c163 | 347 | .sht = &sil680_sht, |
1d2808fd | 348 | .flags = ATA_FLAG_SLAVE_POSS, |
8550c163 AC |
349 | .pio_mask = 0x1f, |
350 | .mwdma_mask = 0x07, | |
bf6263a8 | 351 | .udma_mask = ATA_UDMA6, |
8550c163 AC |
352 | .port_ops = &sil680_port_ops |
353 | }; | |
1626aeb8 | 354 | static const struct ata_port_info info_slow = { |
8550c163 | 355 | .sht = &sil680_sht, |
1d2808fd | 356 | .flags = ATA_FLAG_SLAVE_POSS, |
8550c163 AC |
357 | .pio_mask = 0x1f, |
358 | .mwdma_mask = 0x07, | |
bf6263a8 | 359 | .udma_mask = ATA_UDMA5, |
8550c163 AC |
360 | .port_ops = &sil680_port_ops |
361 | }; | |
1626aeb8 | 362 | const struct ata_port_info *ppi[] = { &info, NULL }; |
8550c163 AC |
363 | static int printed_version; |
364 | ||
365 | if (!printed_version++) | |
366 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
367 | ||
368 | switch(sil680_init_chip(pdev)) | |
369 | { | |
370 | case 0: | |
1626aeb8 | 371 | ppi[0] = &info_slow; |
8550c163 AC |
372 | break; |
373 | case 0x30: | |
374 | return -ENODEV; | |
669a5db4 | 375 | } |
1626aeb8 | 376 | return ata_pci_init_one(pdev, ppi); |
669a5db4 JG |
377 | } |
378 | ||
438ac6d5 | 379 | #ifdef CONFIG_PM |
8550c163 AC |
380 | static int sil680_reinit_one(struct pci_dev *pdev) |
381 | { | |
382 | sil680_init_chip(pdev); | |
383 | return ata_pci_device_resume(pdev); | |
384 | } | |
438ac6d5 | 385 | #endif |
8550c163 | 386 | |
669a5db4 | 387 | static const struct pci_device_id sil680[] = { |
2d2744fc JG |
388 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), }, |
389 | ||
390 | { }, | |
669a5db4 JG |
391 | }; |
392 | ||
393 | static struct pci_driver sil680_pci_driver = { | |
2d2744fc | 394 | .name = DRV_NAME, |
669a5db4 JG |
395 | .id_table = sil680, |
396 | .probe = sil680_init_one, | |
8550c163 | 397 | .remove = ata_pci_remove_one, |
438ac6d5 | 398 | #ifdef CONFIG_PM |
8550c163 AC |
399 | .suspend = ata_pci_device_suspend, |
400 | .resume = sil680_reinit_one, | |
438ac6d5 | 401 | #endif |
669a5db4 JG |
402 | }; |
403 | ||
404 | static int __init sil680_init(void) | |
405 | { | |
406 | return pci_register_driver(&sil680_pci_driver); | |
407 | } | |
408 | ||
669a5db4 JG |
409 | static void __exit sil680_exit(void) |
410 | { | |
411 | pci_unregister_driver(&sil680_pci_driver); | |
412 | } | |
413 | ||
669a5db4 JG |
414 | MODULE_AUTHOR("Alan Cox"); |
415 | MODULE_DESCRIPTION("low-level driver for SI680 PATA"); | |
416 | MODULE_LICENSE("GPL"); | |
417 | MODULE_DEVICE_TABLE(pci, sil680); | |
418 | MODULE_VERSION(DRV_VERSION); | |
419 | ||
420 | module_init(sil680_init); | |
421 | module_exit(sil680_exit); |