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Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * pata_sis.c - SiS ATA driver | |
3 | * | |
ab771630 | 4 | * (C) 2005 Red Hat |
4761c06c | 5 | * (C) 2007 Bartlomiej Zolnierkiewicz |
669a5db4 JG |
6 | * |
7 | * Based upon linux/drivers/ide/pci/sis5513.c | |
8 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
9 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer | |
10 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> | |
11 | * SiS Taiwan : for direct support and hardware. | |
12 | * Daniela Engert : for initial ATA100 advices and numerous others. | |
13 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : | |
14 | * for checking code correctness, providing patches. | |
15 | * Original tests and design on the SiS620 chipset. | |
16 | * ATA100 tests and design on the SiS735 chipset. | |
17 | * ATA16/33 support from specs | |
18 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> | |
19 | * | |
20 | * | |
21 | * TODO | |
22 | * Check MWDMA on drives that don't support MWDMA speed pio cycles ? | |
23 | * More Testing | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/blkdev.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/device.h> | |
33 | #include <scsi/scsi_host.h> | |
34 | #include <linux/libata.h> | |
35 | #include <linux/ata.h> | |
4bb64fb9 | 36 | #include "sis.h" |
669a5db4 JG |
37 | |
38 | #define DRV_NAME "pata_sis" | |
4761c06c | 39 | #define DRV_VERSION "0.5.2" |
669a5db4 JG |
40 | |
41 | struct sis_chipset { | |
1626aeb8 TH |
42 | u16 device; /* PCI host ID */ |
43 | const struct ata_port_info *info; /* Info block */ | |
669a5db4 JG |
44 | /* Probably add family, cable detect type etc here to clean |
45 | up code later */ | |
46 | }; | |
47 | ||
7dcbc1f2 JJ |
48 | struct sis_laptop { |
49 | u16 device; | |
50 | u16 subvendor; | |
51 | u16 subdevice; | |
52 | }; | |
53 | ||
54 | static const struct sis_laptop sis_laptop[] = { | |
55 | /* devid, subvendor, subdev */ | |
56 | { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ | |
4f2d47cf | 57 | { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ |
1f71d067 | 58 | { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ |
edb80471 | 59 | { 0x5513, 0x1039, 0x5513 }, /* Targa Visionary 1000 */ |
7dcbc1f2 JJ |
60 | /* end marker */ |
61 | { 0, } | |
62 | }; | |
63 | ||
64 | static int sis_short_ata40(struct pci_dev *dev) | |
65 | { | |
66 | const struct sis_laptop *lap = &sis_laptop[0]; | |
67 | ||
68 | while (lap->device) { | |
69 | if (lap->device == dev->device && | |
70 | lap->subvendor == dev->subsystem_vendor && | |
71 | lap->subdevice == dev->subsystem_device) | |
72 | return 1; | |
73 | lap++; | |
74 | } | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
669a5db4 | 79 | /** |
dd668d15 | 80 | * sis_old_port_base - return PCI configuration base for dev |
669a5db4 JG |
81 | * @adev: device |
82 | * | |
83 | * Returns the base of the PCI configuration registers for this port | |
84 | * number. | |
85 | */ | |
86 | ||
dd668d15 | 87 | static int sis_old_port_base(struct ata_device *adev) |
669a5db4 | 88 | { |
9af5c9c9 | 89 | return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); |
669a5db4 JG |
90 | } |
91 | ||
92 | /** | |
2e413f51 | 93 | * sis_133_cable_detect - check for 40/80 pin |
669a5db4 | 94 | * @ap: Port |
d4b2bab4 | 95 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
96 | * |
97 | * Perform cable detection for the later UDMA133 capable | |
98 | * SiS chipset. | |
99 | */ | |
100 | ||
2e413f51 | 101 | static int sis_133_cable_detect(struct ata_port *ap) |
669a5db4 | 102 | { |
669a5db4 JG |
103 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
104 | u16 tmp; | |
105 | ||
669a5db4 JG |
106 | /* The top bit of this register is the cable detect bit */ |
107 | pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); | |
7dcbc1f2 | 108 | if ((tmp & 0x8000) && !sis_short_ata40(pdev)) |
2e413f51 AC |
109 | return ATA_CBL_PATA40; |
110 | return ATA_CBL_PATA80; | |
669a5db4 JG |
111 | } |
112 | ||
113 | /** | |
2e413f51 | 114 | * sis_66_cable_detect - check for 40/80 pin |
669a5db4 | 115 | * @ap: Port |
d4b2bab4 | 116 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
117 | * |
118 | * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 | |
119 | * SiS IDE controllers. | |
120 | */ | |
121 | ||
2e413f51 | 122 | static int sis_66_cable_detect(struct ata_port *ap) |
669a5db4 | 123 | { |
669a5db4 JG |
124 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
125 | u8 tmp; | |
126 | ||
669a5db4 JG |
127 | /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ |
128 | pci_read_config_byte(pdev, 0x48, &tmp); | |
129 | tmp >>= ap->port_no; | |
7dcbc1f2 | 130 | if ((tmp & 0x10) && !sis_short_ata40(pdev)) |
2e413f51 AC |
131 | return ATA_CBL_PATA40; |
132 | return ATA_CBL_PATA80; | |
669a5db4 JG |
133 | } |
134 | ||
669a5db4 JG |
135 | |
136 | /** | |
2e413f51 | 137 | * sis_pre_reset - probe begin |
cc0680a5 | 138 | * @link: ATA link |
d4b2bab4 | 139 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
140 | * |
141 | * Set up cable type and use generic probe init | |
142 | */ | |
143 | ||
cc0680a5 | 144 | static int sis_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 JG |
145 | { |
146 | static const struct pci_bits sis_enable_bits[] = { | |
147 | { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ | |
148 | { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ | |
149 | }; | |
85cd7251 | 150 | |
cc0680a5 | 151 | struct ata_port *ap = link->ap; |
669a5db4 JG |
152 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
153 | ||
2e413f51 AC |
154 | if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) |
155 | return -ENOENT; | |
d4b2bab4 | 156 | |
15ce0943 AC |
157 | /* Clear the FIFO settings. We can't enable the FIFO until |
158 | we know we are poking at a disk */ | |
159 | pci_write_config_byte(pdev, 0x4B, 0); | |
9363c382 | 160 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
161 | } |
162 | ||
163 | ||
669a5db4 JG |
164 | /** |
165 | * sis_set_fifo - Set RWP fifo bits for this device | |
166 | * @ap: Port | |
167 | * @adev: Device | |
168 | * | |
169 | * SIS chipsets implement prefetch/postwrite bits for each device | |
170 | * on both channels. This functionality is not ATAPI compatible and | |
171 | * must be configured according to the class of device present | |
172 | */ | |
173 | ||
174 | static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) | |
175 | { | |
176 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
177 | u8 fifoctrl; | |
178 | u8 mask = 0x11; | |
179 | ||
180 | mask <<= (2 * ap->port_no); | |
181 | mask <<= adev->devno; | |
182 | ||
183 | /* This holds various bits including the FIFO control */ | |
184 | pci_read_config_byte(pdev, 0x4B, &fifoctrl); | |
185 | fifoctrl &= ~mask; | |
186 | ||
187 | /* Enable for ATA (disk) only */ | |
188 | if (adev->class == ATA_DEV_ATA) | |
189 | fifoctrl |= mask; | |
190 | pci_write_config_byte(pdev, 0x4B, fifoctrl); | |
191 | } | |
192 | ||
193 | /** | |
194 | * sis_old_set_piomode - Initialize host controller PATA PIO timings | |
195 | * @ap: Port whose timings we are configuring | |
196 | * @adev: Device we are configuring for. | |
197 | * | |
198 | * Set PIO mode for device, in host controller PCI config space. This | |
199 | * function handles PIO set up for all chips that are pre ATA100 and | |
200 | * also early ATA100 devices. | |
201 | * | |
202 | * LOCKING: | |
203 | * None (inherited from caller). | |
204 | */ | |
205 | ||
206 | static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
207 | { | |
208 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
dd668d15 | 209 | int port = sis_old_port_base(adev); |
669a5db4 JG |
210 | u8 t1, t2; |
211 | int speed = adev->pio_mode - XFER_PIO_0; | |
212 | ||
213 | const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; | |
214 | const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; | |
215 | ||
216 | sis_set_fifo(ap, adev); | |
217 | ||
218 | pci_read_config_byte(pdev, port, &t1); | |
219 | pci_read_config_byte(pdev, port + 1, &t2); | |
220 | ||
221 | t1 &= ~0x0F; /* Clear active/recovery timings */ | |
222 | t2 &= ~0x07; | |
223 | ||
224 | t1 |= active[speed]; | |
225 | t2 |= recovery[speed]; | |
226 | ||
227 | pci_write_config_byte(pdev, port, t1); | |
228 | pci_write_config_byte(pdev, port + 1, t2); | |
229 | } | |
230 | ||
231 | /** | |
4761c06c | 232 | * sis_100_set_piomode - Initialize host controller PATA PIO timings |
669a5db4 JG |
233 | * @ap: Port whose timings we are configuring |
234 | * @adev: Device we are configuring for. | |
235 | * | |
236 | * Set PIO mode for device, in host controller PCI config space. This | |
237 | * function handles PIO set up for ATA100 devices and early ATA133. | |
238 | * | |
239 | * LOCKING: | |
240 | * None (inherited from caller). | |
241 | */ | |
242 | ||
243 | static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
244 | { | |
245 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
dd668d15 | 246 | int port = sis_old_port_base(adev); |
669a5db4 JG |
247 | int speed = adev->pio_mode - XFER_PIO_0; |
248 | ||
249 | const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; | |
250 | ||
251 | sis_set_fifo(ap, adev); | |
252 | ||
253 | pci_write_config_byte(pdev, port, actrec[speed]); | |
254 | } | |
255 | ||
256 | /** | |
4761c06c | 257 | * sis_133_set_piomode - Initialize host controller PATA PIO timings |
669a5db4 JG |
258 | * @ap: Port whose timings we are configuring |
259 | * @adev: Device we are configuring for. | |
260 | * | |
261 | * Set PIO mode for device, in host controller PCI config space. This | |
262 | * function handles PIO set up for the later ATA133 devices. | |
263 | * | |
264 | * LOCKING: | |
265 | * None (inherited from caller). | |
266 | */ | |
267 | ||
268 | static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
269 | { | |
270 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
271 | int port = 0x40; | |
272 | u32 t1; | |
273 | u32 reg54; | |
274 | int speed = adev->pio_mode - XFER_PIO_0; | |
275 | ||
276 | const u32 timing133[] = { | |
277 | 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ | |
278 | 0x0C266000, | |
279 | 0x04263000, | |
280 | 0x0C0A3000, | |
281 | 0x05093000 | |
282 | }; | |
283 | const u32 timing100[] = { | |
284 | 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ | |
285 | 0x091C4000, | |
286 | 0x031C2000, | |
287 | 0x09072000, | |
288 | 0x04062000 | |
289 | }; | |
290 | ||
291 | sis_set_fifo(ap, adev); | |
292 | ||
293 | /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ | |
294 | pci_read_config_dword(pdev, 0x54, ®54); | |
295 | if (reg54 & 0x40000000) | |
296 | port = 0x70; | |
297 | port += 8 * ap->port_no + 4 * adev->devno; | |
298 | ||
299 | pci_read_config_dword(pdev, port, &t1); | |
300 | t1 &= 0xC0C00FFF; /* Mask out timing */ | |
301 | ||
302 | if (t1 & 0x08) /* 100 or 133 ? */ | |
303 | t1 |= timing133[speed]; | |
304 | else | |
305 | t1 |= timing100[speed]; | |
306 | pci_write_config_byte(pdev, port, t1); | |
307 | } | |
308 | ||
309 | /** | |
310 | * sis_old_set_dmamode - Initialize host controller PATA DMA timings | |
311 | * @ap: Port whose timings we are configuring | |
312 | * @adev: Device to program | |
313 | * | |
314 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
315 | * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike | |
316 | * the old ide/pci driver. | |
317 | * | |
318 | * LOCKING: | |
319 | * None (inherited from caller). | |
320 | */ | |
321 | ||
322 | static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
323 | { | |
324 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
325 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 | 326 | int drive_pci = sis_old_port_base(adev); |
669a5db4 JG |
327 | u16 timing; |
328 | ||
4761c06c | 329 | const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
669a5db4 JG |
330 | const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; |
331 | ||
332 | pci_read_config_word(pdev, drive_pci, &timing); | |
333 | ||
334 | if (adev->dma_mode < XFER_UDMA_0) { | |
335 | /* bits 3-0 hold recovery timing bits 8-10 active timing and | |
1967b7ff | 336 | the higher bits are dependant on the device */ |
4761c06c | 337 | timing &= ~0x870F; |
669a5db4 | 338 | timing |= mwdma_bits[speed]; |
669a5db4 JG |
339 | } else { |
340 | /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ | |
341 | speed = adev->dma_mode - XFER_UDMA_0; | |
342 | timing &= ~0x6000; | |
343 | timing |= udma_bits[speed]; | |
344 | } | |
4761c06c | 345 | pci_write_config_word(pdev, drive_pci, timing); |
669a5db4 JG |
346 | } |
347 | ||
348 | /** | |
349 | * sis_66_set_dmamode - Initialize host controller PATA DMA timings | |
350 | * @ap: Port whose timings we are configuring | |
351 | * @adev: Device to program | |
352 | * | |
353 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
354 | * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike | |
355 | * the old ide/pci driver. | |
356 | * | |
357 | * LOCKING: | |
358 | * None (inherited from caller). | |
359 | */ | |
360 | ||
361 | static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
362 | { | |
363 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
364 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 | 365 | int drive_pci = sis_old_port_base(adev); |
669a5db4 JG |
366 | u16 timing; |
367 | ||
edeb614c | 368 | /* MWDMA 0-2 and UDMA 0-5 */ |
4761c06c | 369 | const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
edeb614c | 370 | const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; |
669a5db4 JG |
371 | |
372 | pci_read_config_word(pdev, drive_pci, &timing); | |
373 | ||
374 | if (adev->dma_mode < XFER_UDMA_0) { | |
375 | /* bits 3-0 hold recovery timing bits 8-10 active timing and | |
1967b7ff | 376 | the higher bits are dependant on the device, bit 15 udma */ |
dd668d15 | 377 | timing &= ~0x870F; |
669a5db4 JG |
378 | timing |= mwdma_bits[speed]; |
379 | } else { | |
380 | /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ | |
381 | speed = adev->dma_mode - XFER_UDMA_0; | |
dd668d15 | 382 | timing &= ~0xF000; |
669a5db4 JG |
383 | timing |= udma_bits[speed]; |
384 | } | |
385 | pci_write_config_word(pdev, drive_pci, timing); | |
386 | } | |
387 | ||
388 | /** | |
389 | * sis_100_set_dmamode - Initialize host controller PATA DMA timings | |
390 | * @ap: Port whose timings we are configuring | |
391 | * @adev: Device to program | |
392 | * | |
393 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
394 | * Handles UDMA66 and early UDMA100 devices. | |
395 | * | |
396 | * LOCKING: | |
397 | * None (inherited from caller). | |
398 | */ | |
399 | ||
400 | static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
401 | { | |
402 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
403 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 AC |
404 | int drive_pci = sis_old_port_base(adev); |
405 | u8 timing; | |
669a5db4 | 406 | |
dd668d15 | 407 | const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; |
669a5db4 | 408 | |
dd668d15 | 409 | pci_read_config_byte(pdev, drive_pci + 1, &timing); |
669a5db4 JG |
410 | |
411 | if (adev->dma_mode < XFER_UDMA_0) { | |
412 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ | |
413 | } else { | |
dd668d15 | 414 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
669a5db4 | 415 | speed = adev->dma_mode - XFER_UDMA_0; |
dd668d15 | 416 | timing &= ~0x8F; |
669a5db4 JG |
417 | timing |= udma_bits[speed]; |
418 | } | |
dd668d15 | 419 | pci_write_config_byte(pdev, drive_pci + 1, timing); |
669a5db4 JG |
420 | } |
421 | ||
422 | /** | |
423 | * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings | |
424 | * @ap: Port whose timings we are configuring | |
425 | * @adev: Device to program | |
426 | * | |
427 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
4761c06c | 428 | * Handles early SiS 961 bridges. |
669a5db4 JG |
429 | * |
430 | * LOCKING: | |
431 | * None (inherited from caller). | |
432 | */ | |
433 | ||
434 | static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
435 | { | |
436 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
437 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 AC |
438 | int drive_pci = sis_old_port_base(adev); |
439 | u8 timing; | |
440 | /* Low 4 bits are timing */ | |
441 | static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; | |
669a5db4 | 442 | |
dd668d15 | 443 | pci_read_config_byte(pdev, drive_pci + 1, &timing); |
669a5db4 JG |
444 | |
445 | if (adev->dma_mode < XFER_UDMA_0) { | |
446 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ | |
447 | } else { | |
dd668d15 | 448 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
669a5db4 | 449 | speed = adev->dma_mode - XFER_UDMA_0; |
dd668d15 | 450 | timing &= ~0x8F; |
669a5db4 JG |
451 | timing |= udma_bits[speed]; |
452 | } | |
dd668d15 | 453 | pci_write_config_byte(pdev, drive_pci + 1, timing); |
669a5db4 JG |
454 | } |
455 | ||
456 | /** | |
457 | * sis_133_set_dmamode - Initialize host controller PATA DMA timings | |
458 | * @ap: Port whose timings we are configuring | |
459 | * @adev: Device to program | |
460 | * | |
461 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
669a5db4 JG |
462 | * |
463 | * LOCKING: | |
464 | * None (inherited from caller). | |
465 | */ | |
466 | ||
467 | static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
468 | { | |
469 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
470 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
471 | int port = 0x40; | |
472 | u32 t1; | |
473 | u32 reg54; | |
474 | ||
475 | /* bits 4- cycle time 8 - cvs time */ | |
2e413f51 AC |
476 | static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; |
477 | static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; | |
669a5db4 JG |
478 | |
479 | /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ | |
480 | pci_read_config_dword(pdev, 0x54, ®54); | |
481 | if (reg54 & 0x40000000) | |
482 | port = 0x70; | |
483 | port += (8 * ap->port_no) + (4 * adev->devno); | |
484 | ||
485 | pci_read_config_dword(pdev, port, &t1); | |
486 | ||
487 | if (adev->dma_mode < XFER_UDMA_0) { | |
488 | t1 &= ~0x00000004; | |
489 | /* FIXME: need data sheet to add MWDMA here. Also lacking on | |
490 | ide/pci driver */ | |
491 | } else { | |
492 | speed = adev->dma_mode - XFER_UDMA_0; | |
493 | /* if & 8 no UDMA133 - need info for ... */ | |
494 | t1 &= ~0x00000FF0; | |
495 | t1 |= 0x00000004; | |
496 | if (t1 & 0x08) | |
497 | t1 |= timing_u133[speed]; | |
498 | else | |
499 | t1 |= timing_u100[speed]; | |
500 | } | |
501 | pci_write_config_dword(pdev, port, t1); | |
502 | } | |
503 | ||
504 | static struct scsi_host_template sis_sht = { | |
68d1d07b | 505 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
506 | }; |
507 | ||
029cfd6b TH |
508 | static struct ata_port_operations sis_133_for_sata_ops = { |
509 | .inherits = &ata_bmdma_port_ops, | |
669a5db4 JG |
510 | .set_piomode = sis_133_set_piomode, |
511 | .set_dmamode = sis_133_set_dmamode, | |
2e413f51 | 512 | .cable_detect = sis_133_cable_detect, |
029cfd6b | 513 | }; |
669a5db4 | 514 | |
029cfd6b TH |
515 | static struct ata_port_operations sis_base_ops = { |
516 | .inherits = &ata_bmdma_port_ops, | |
a1efdaba | 517 | .prereset = sis_pre_reset, |
669a5db4 JG |
518 | }; |
519 | ||
029cfd6b TH |
520 | static struct ata_port_operations sis_133_ops = { |
521 | .inherits = &sis_base_ops, | |
a3cabb27 UK |
522 | .set_piomode = sis_133_set_piomode, |
523 | .set_dmamode = sis_133_set_dmamode, | |
a3cabb27 | 524 | .cable_detect = sis_133_cable_detect, |
a3cabb27 UK |
525 | }; |
526 | ||
029cfd6b TH |
527 | static struct ata_port_operations sis_133_early_ops = { |
528 | .inherits = &sis_base_ops, | |
669a5db4 JG |
529 | .set_piomode = sis_100_set_piomode, |
530 | .set_dmamode = sis_133_early_set_dmamode, | |
2e413f51 | 531 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
532 | }; |
533 | ||
029cfd6b TH |
534 | static struct ata_port_operations sis_100_ops = { |
535 | .inherits = &sis_base_ops, | |
669a5db4 JG |
536 | .set_piomode = sis_100_set_piomode, |
537 | .set_dmamode = sis_100_set_dmamode, | |
2e413f51 | 538 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
539 | }; |
540 | ||
029cfd6b TH |
541 | static struct ata_port_operations sis_66_ops = { |
542 | .inherits = &sis_base_ops, | |
669a5db4 JG |
543 | .set_piomode = sis_old_set_piomode, |
544 | .set_dmamode = sis_66_set_dmamode, | |
2e413f51 | 545 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
546 | }; |
547 | ||
029cfd6b TH |
548 | static struct ata_port_operations sis_old_ops = { |
549 | .inherits = &sis_base_ops, | |
669a5db4 JG |
550 | .set_piomode = sis_old_set_piomode, |
551 | .set_dmamode = sis_old_set_dmamode, | |
2e413f51 | 552 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
553 | }; |
554 | ||
1626aeb8 | 555 | static const struct ata_port_info sis_info = { |
1d2808fd | 556 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
557 | .pio_mask = 0x1f, /* pio0-4 */ |
558 | .mwdma_mask = 0x07, | |
559 | .udma_mask = 0, | |
560 | .port_ops = &sis_old_ops, | |
561 | }; | |
1626aeb8 | 562 | static const struct ata_port_info sis_info33 = { |
1d2808fd | 563 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
564 | .pio_mask = 0x1f, /* pio0-4 */ |
565 | .mwdma_mask = 0x07, | |
566 | .udma_mask = ATA_UDMA2, /* UDMA 33 */ | |
567 | .port_ops = &sis_old_ops, | |
568 | }; | |
1626aeb8 | 569 | static const struct ata_port_info sis_info66 = { |
1d2808fd | 570 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
571 | .pio_mask = 0x1f, /* pio0-4 */ |
572 | .udma_mask = ATA_UDMA4, /* UDMA 66 */ | |
573 | .port_ops = &sis_66_ops, | |
574 | }; | |
1626aeb8 | 575 | static const struct ata_port_info sis_info100 = { |
1d2808fd | 576 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
577 | .pio_mask = 0x1f, /* pio0-4 */ |
578 | .udma_mask = ATA_UDMA5, | |
579 | .port_ops = &sis_100_ops, | |
580 | }; | |
1626aeb8 | 581 | static const struct ata_port_info sis_info100_early = { |
1d2808fd | 582 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
583 | .udma_mask = ATA_UDMA5, |
584 | .pio_mask = 0x1f, /* pio0-4 */ | |
585 | .port_ops = &sis_66_ops, | |
586 | }; | |
a3cabb27 | 587 | static const struct ata_port_info sis_info133 = { |
1d2808fd | 588 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
589 | .pio_mask = 0x1f, /* pio0-4 */ |
590 | .udma_mask = ATA_UDMA6, | |
591 | .port_ops = &sis_133_ops, | |
592 | }; | |
a3cabb27 | 593 | const struct ata_port_info sis_info133_for_sata = { |
a3cabb27 UK |
594 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, |
595 | .pio_mask = 0x1f, /* pio0-4 */ | |
596 | .udma_mask = ATA_UDMA6, | |
597 | .port_ops = &sis_133_for_sata_ops, | |
598 | }; | |
1626aeb8 | 599 | static const struct ata_port_info sis_info133_early = { |
1d2808fd | 600 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
601 | .pio_mask = 0x1f, /* pio0-4 */ |
602 | .udma_mask = ATA_UDMA6, | |
603 | .port_ops = &sis_133_early_ops, | |
604 | }; | |
605 | ||
9b14dec5 | 606 | /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ |
a3cabb27 | 607 | EXPORT_SYMBOL_GPL(sis_info133_for_sata); |
669a5db4 JG |
608 | |
609 | static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) | |
610 | { | |
611 | u16 regw; | |
612 | u8 reg; | |
613 | ||
614 | if (sis->info == &sis_info133) { | |
615 | pci_read_config_word(pdev, 0x50, ®w); | |
616 | if (regw & 0x08) | |
617 | pci_write_config_word(pdev, 0x50, regw & ~0x08); | |
618 | pci_read_config_word(pdev, 0x52, ®w); | |
619 | if (regw & 0x08) | |
620 | pci_write_config_word(pdev, 0x52, regw & ~0x08); | |
621 | return; | |
622 | } | |
623 | ||
624 | if (sis->info == &sis_info133_early || sis->info == &sis_info100) { | |
625 | /* Fix up latency */ | |
626 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); | |
627 | /* Set compatibility bit */ | |
628 | pci_read_config_byte(pdev, 0x49, ®); | |
629 | if (!(reg & 0x01)) | |
630 | pci_write_config_byte(pdev, 0x49, reg | 0x01); | |
631 | return; | |
632 | } | |
633 | ||
634 | if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { | |
635 | /* Fix up latency */ | |
636 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); | |
637 | /* Set compatibility bit */ | |
638 | pci_read_config_byte(pdev, 0x52, ®); | |
639 | if (!(reg & 0x04)) | |
640 | pci_write_config_byte(pdev, 0x52, reg | 0x04); | |
641 | return; | |
642 | } | |
643 | ||
644 | if (sis->info == &sis_info33) { | |
645 | pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); | |
646 | if (( reg & 0x0F ) != 0x00) | |
647 | pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); | |
648 | /* Fall through to ATA16 fixup below */ | |
649 | } | |
650 | ||
651 | if (sis->info == &sis_info || sis->info == &sis_info33) { | |
652 | /* force per drive recovery and active timings | |
653 | needed on ATA_33 and below chips */ | |
654 | pci_read_config_byte(pdev, 0x52, ®); | |
655 | if (!(reg & 0x08)) | |
656 | pci_write_config_byte(pdev, 0x52, reg|0x08); | |
657 | return; | |
658 | } | |
659 | ||
660 | BUG(); | |
661 | } | |
662 | ||
663 | /** | |
664 | * sis_init_one - Register SiS ATA PCI device with kernel services | |
665 | * @pdev: PCI device to register | |
666 | * @ent: Entry in sis_pci_tbl matching with @pdev | |
667 | * | |
668 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
669 | * and then hand over control to libata, for it to do the rest. | |
670 | * | |
671 | * LOCKING: | |
672 | * Inherited from PCI layer (may sleep). | |
673 | * | |
674 | * RETURNS: | |
675 | * Zero on success, or -ERRNO value. | |
676 | */ | |
677 | ||
678 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
679 | { | |
680 | static int printed_version; | |
887125e3 | 681 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
669a5db4 JG |
682 | struct pci_dev *host = NULL; |
683 | struct sis_chipset *chipset = NULL; | |
f3769e9d | 684 | struct sis_chipset *sets; |
f08048e9 | 685 | int rc; |
669a5db4 JG |
686 | |
687 | static struct sis_chipset sis_chipsets[] = { | |
f20b16ff | 688 | |
af323a2f AC |
689 | { 0x0968, &sis_info133 }, |
690 | { 0x0966, &sis_info133 }, | |
691 | { 0x0965, &sis_info133 }, | |
669a5db4 JG |
692 | { 0x0745, &sis_info100 }, |
693 | { 0x0735, &sis_info100 }, | |
694 | { 0x0733, &sis_info100 }, | |
695 | { 0x0635, &sis_info100 }, | |
696 | { 0x0633, &sis_info100 }, | |
697 | ||
698 | { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ | |
699 | { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ | |
700 | ||
701 | { 0x0640, &sis_info66 }, | |
702 | { 0x0630, &sis_info66 }, | |
703 | { 0x0620, &sis_info66 }, | |
704 | { 0x0540, &sis_info66 }, | |
705 | { 0x0530, &sis_info66 }, | |
706 | ||
707 | { 0x5600, &sis_info33 }, | |
708 | { 0x5598, &sis_info33 }, | |
709 | { 0x5597, &sis_info33 }, | |
710 | { 0x5591, &sis_info33 }, | |
711 | { 0x5582, &sis_info33 }, | |
712 | { 0x5581, &sis_info33 }, | |
713 | ||
714 | { 0x5596, &sis_info }, | |
715 | { 0x5571, &sis_info }, | |
716 | { 0x5517, &sis_info }, | |
717 | { 0x5511, &sis_info }, | |
718 | ||
719 | {0} | |
720 | }; | |
721 | static struct sis_chipset sis133_early = { | |
722 | 0x0, &sis_info133_early | |
723 | }; | |
724 | static struct sis_chipset sis133 = { | |
725 | 0x0, &sis_info133 | |
726 | }; | |
727 | static struct sis_chipset sis100_early = { | |
728 | 0x0, &sis_info100_early | |
729 | }; | |
730 | static struct sis_chipset sis100 = { | |
731 | 0x0, &sis_info100 | |
732 | }; | |
733 | ||
734 | if (!printed_version++) | |
735 | dev_printk(KERN_DEBUG, &pdev->dev, | |
736 | "version " DRV_VERSION "\n"); | |
737 | ||
f08048e9 TH |
738 | rc = pcim_enable_device(pdev); |
739 | if (rc) | |
740 | return rc; | |
669a5db4 | 741 | |
f08048e9 | 742 | /* We have to find the bridge first */ |
f3769e9d AC |
743 | for (sets = &sis_chipsets[0]; sets->device; sets++) { |
744 | host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); | |
669a5db4 | 745 | if (host != NULL) { |
f3769e9d AC |
746 | chipset = sets; /* Match found */ |
747 | if (sets->device == 0x630) { /* SIS630 */ | |
44c10138 | 748 | if (host->revision >= 0x30) /* 630 ET */ |
669a5db4 JG |
749 | chipset = &sis100_early; |
750 | } | |
751 | break; | |
752 | } | |
753 | } | |
754 | ||
755 | /* Look for concealed bridges */ | |
f3769e9d | 756 | if (chipset == NULL) { |
669a5db4 JG |
757 | /* Second check */ |
758 | u32 idemisc; | |
759 | u16 trueid; | |
760 | ||
761 | /* Disable ID masking and register remapping then | |
762 | see what the real ID is */ | |
763 | ||
764 | pci_read_config_dword(pdev, 0x54, &idemisc); | |
765 | pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); | |
766 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); | |
767 | pci_write_config_dword(pdev, 0x54, idemisc); | |
768 | ||
769 | switch(trueid) { | |
770 | case 0x5518: /* SIS 962/963 */ | |
771 | chipset = &sis133; | |
772 | if ((idemisc & 0x40000000) == 0) { | |
773 | pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); | |
774 | printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); | |
775 | } | |
776 | break; | |
777 | case 0x0180: /* SIS 965/965L */ | |
778 | chipset = &sis133; | |
779 | break; | |
780 | case 0x1180: /* SIS 966/966L */ | |
781 | chipset = &sis133; | |
782 | break; | |
783 | } | |
784 | } | |
785 | ||
786 | /* Further check */ | |
787 | if (chipset == NULL) { | |
788 | struct pci_dev *lpc_bridge; | |
789 | u16 trueid; | |
790 | u8 prefctl; | |
791 | u8 idecfg; | |
669a5db4 JG |
792 | |
793 | /* Try the second unmasking technique */ | |
794 | pci_read_config_byte(pdev, 0x4a, &idecfg); | |
795 | pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); | |
796 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); | |
797 | pci_write_config_byte(pdev, 0x4a, idecfg); | |
798 | ||
799 | switch(trueid) { | |
800 | case 0x5517: | |
801 | lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ | |
802 | if (lpc_bridge == NULL) | |
803 | break; | |
669a5db4 JG |
804 | pci_read_config_byte(pdev, 0x49, &prefctl); |
805 | pci_dev_put(lpc_bridge); | |
806 | ||
44c10138 | 807 | if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { |
669a5db4 JG |
808 | chipset = &sis133_early; |
809 | break; | |
810 | } | |
811 | chipset = &sis100; | |
812 | break; | |
813 | } | |
814 | } | |
815 | pci_dev_put(host); | |
816 | ||
817 | /* No chipset info, no support */ | |
818 | if (chipset == NULL) | |
819 | return -ENODEV; | |
820 | ||
887125e3 | 821 | ppi[0] = chipset->info; |
669a5db4 JG |
822 | |
823 | sis_fixup(pdev, chipset); | |
824 | ||
9363c382 | 825 | return ata_pci_sff_init_one(pdev, ppi, &sis_sht, chipset); |
669a5db4 JG |
826 | } |
827 | ||
828 | static const struct pci_device_id sis_pci_tbl[] = { | |
2d2744fc JG |
829 | { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ |
830 | { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ | |
a3cabb27 | 831 | { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ |
2d2744fc | 832 | |
669a5db4 JG |
833 | { } |
834 | }; | |
835 | ||
836 | static struct pci_driver sis_pci_driver = { | |
837 | .name = DRV_NAME, | |
838 | .id_table = sis_pci_tbl, | |
839 | .probe = sis_init_one, | |
840 | .remove = ata_pci_remove_one, | |
438ac6d5 | 841 | #ifdef CONFIG_PM |
62d64ae0 AC |
842 | .suspend = ata_pci_device_suspend, |
843 | .resume = ata_pci_device_resume, | |
438ac6d5 | 844 | #endif |
669a5db4 JG |
845 | }; |
846 | ||
847 | static int __init sis_init(void) | |
848 | { | |
849 | return pci_register_driver(&sis_pci_driver); | |
850 | } | |
851 | ||
852 | static void __exit sis_exit(void) | |
853 | { | |
854 | pci_unregister_driver(&sis_pci_driver); | |
855 | } | |
856 | ||
669a5db4 JG |
857 | module_init(sis_init); |
858 | module_exit(sis_exit); | |
859 | ||
860 | MODULE_AUTHOR("Alan Cox"); | |
861 | MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); | |
862 | MODULE_LICENSE("GPL"); | |
863 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
864 | MODULE_VERSION(DRV_VERSION); | |
865 |