[mirror_ubuntu-artful-kernel.git] / drivers / ata / pata_sl82c105.c

/*
 * pata_sl82c105.c 	- SL82C105 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * Based in part on linux/drivers/ide/pci/sl82c105.c
 * 		SL82C105/Winbond 553 IDE driver
 *
 * and in part on the documentation and errata sheet
 *
 *
 * Note: The controller like many controllers has shared timings for
 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
 * in the dma_stop function. Thus we actually don't need a set_dmamode
 * method as the PIO method is always called and will set the right PIO
 * timing parameters.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_sl82c105"
#define DRV_VERSION "0.3.3"

enum {
	/*
	 * SL82C105 PCI config register 0x40 bits.
	 */
	CTRL_IDE_IRQB	=	(1 << 30),
	CTRL_IDE_IRQA   =	(1 << 28),
	CTRL_LEGIRQ     =	(1 << 11),
	CTRL_P1F16      =	(1 << 5),
	CTRL_P1EN       =	(1 << 4),
	CTRL_P0F16      =	(1 << 1),
	CTRL_P0EN       =	(1 << 0)
};

/**
 *	sl82c105_pre_reset		-	probe begin
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Set up cable type and use generic probe init
 */

static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits sl82c105_enable_bits[] = {
		{ 0x40, 1, 0x01, 0x01 },
		{ 0x40, 1, 0x10, 0x10 }
	};
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
		return -ENOENT;
	return ata_std_prereset(link, deadline);
}


/**
 *	sl82c105_configure_piomode	-	set chip PIO timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@pio: PIO mode
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	so a configure_dmamode call will undo any work we do here and vice
 *	versa
 */

static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static u16 pio_timing[5] = {
		0x50D, 0x407, 0x304, 0x242, 0x240
	};
	u16 dummy;
	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);

	pci_write_config_word(pdev, timing, pio_timing[pio]);
	/* Can we lose this oddity of the old driver */
	pci_read_config_word(pdev, timing, &dummy);
}

/**
 *	sl82c105_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	but we want to set the PIO timing by default.
 */

static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
}

/**
 *	sl82c105_configure_dmamode	-	set DMA mode in chip
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Load DMA cycle times into the chip ready for a DMA transfer
 *	to occur.
 */

static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static u16 dma_timing[3] = {
		0x707, 0x201, 0x200
	};
	u16 dummy;
	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
	int dma = adev->dma_mode - XFER_MW_DMA_0;

	pci_write_config_word(pdev, timing, dma_timing[dma]);
	/* Can we lose this oddity of the old driver */
	pci_read_config_word(pdev, timing, &dummy);
}

/**
 *	sl82c105_reset_engine	-	Reset the DMA engine
 *	@ap: ATA interface
 *
 *	The sl82c105 has some serious problems with the DMA engine
 *	when transfers don't run as expected or ATAPI is used. The
 *	recommended fix is to reset the engine each use using a chip
 *	test register.
 */

static void sl82c105_reset_engine(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 val;

	pci_read_config_word(pdev, 0x7E, &val);
	pci_write_config_word(pdev, 0x7E, val | 4);
	pci_write_config_word(pdev, 0x7E, val & ~4);
}

/**
 *	sl82c105_bmdma_start		-	DMA engine begin
 *	@qc: ATA command
 *
 *	Reset the DMA engine each use as recommended by the errata
 *	document.
 *
 *	FIXME: if we switch clock at BMDMA start/end we might get better
 *	PIO performance on DMA capable devices.
 */

static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;

	udelay(100);
	sl82c105_reset_engine(ap);
	udelay(100);

	/* Set the clocks for DMA */
	sl82c105_configure_dmamode(ap, qc->dev);
	/* Activate DMA */
	ata_bmdma_start(qc);
}

/**
 *	sl82c105_bmdma_end		-	DMA engine stop
 *	@qc: ATA command
 *
 *	Reset the DMA engine each use as recommended by the errata
 *	document.
 *
 *	This function is also called to turn off DMA when a timeout occurs
 *	during DMA operation. In both cases we need to reset the engine,
 *	so no actual eng_timeout handler is required.
 *
 *	We assume bmdma_stop is always called if bmdma_start as called. If
 *	not then we may need to wrap qc_issue.
 */

static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;

	ata_bmdma_stop(qc);
	sl82c105_reset_engine(ap);
	udelay(100);

	/* This will redo the initial setup of the DMA device to matching
	   PIO timings */
	sl82c105_set_piomode(ap, qc->dev);
}

/**
 *	sl82c105_qc_defer	-	implement serialization
 *	@qc: command
 *
 *	We must issue one command per host not per channel because
 *	of the reset bug.
 *
 *	Q: is the scsi host lock sufficient ?
 */

static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
{
	struct ata_host *host = qc->ap->host;
	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
	int rc;

	/* First apply the usual rules */	
	rc = ata_std_qc_defer(qc);
	if (rc != 0)
		return rc;

	/* Now apply serialization rules. Only allow a command if the
	   other channel state machine is idle */
	if (alt && alt->qc_active)
		return	ATA_DEFER_PORT;
	return 0;
}

static struct scsi_host_template sl82c105_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations sl82c105_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.qc_defer	= sl82c105_qc_defer,
	.bmdma_start 	= sl82c105_bmdma_start,
	.bmdma_stop	= sl82c105_bmdma_stop,
	.cable_detect	= ata_cable_40wire,
	.set_piomode	= sl82c105_set_piomode,
	.prereset	= sl82c105_pre_reset,
};

/**
 *	sl82c105_bridge_revision	-	find bridge version
 *	@pdev: PCI device for the ATA function
 *
 *	Locates the PCI bridge associated with the ATA function and
 *	providing it is a Winbond 553 reports the revision. If it cannot
 *	find a revision or the right device it returns -1
 */

static int sl82c105_bridge_revision(struct pci_dev *pdev)
{
	struct pci_dev *bridge;

	/*
	 * The bridge should be part of the same device, but function 0.
	 */
	bridge = pci_get_slot(pdev->bus,
			       PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
	if (!bridge)
		return -1;

	/*
	 * Make sure it is a Winbond 553 and is an ISA bridge.
	 */
	if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
	    bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
	    bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
	    	pci_dev_put(bridge);
		return -1;
	}
	/*
	 * We need to find function 0's revision, not function 1
	 */
	pci_dev_put(bridge);
	return bridge->revision;
}


static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_dma = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &sl82c105_port_ops
	};
	static const struct ata_port_info info_early = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.port_ops = &sl82c105_port_ops
	};
	/* for now use only the first port */
	const struct ata_port_info *ppi[] = { &info_early,
					       NULL };
	u32 val;
	int rev;
	int rc;

	rc = pcim_enable_device(dev);
	if (rc)
		return rc;

	rev = sl82c105_bridge_revision(dev);

	if (rev == -1)
		dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
	else if (rev <= 5)
		dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
	else
		ppi[0] = &info_dma;

	pci_read_config_dword(dev, 0x40, &val);
	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
	pci_write_config_dword(dev, 0x40, val);

	return ata_pci_init_one(dev, ppi, &sl82c105_sht, NULL);
}

static const struct pci_device_id sl82c105[] = {
	{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },

	{ },
};

static struct pci_driver sl82c105_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= sl82c105,
	.probe 		= sl82c105_init_one,
	.remove		= ata_pci_remove_one
};

static int __init sl82c105_init(void)
{
	return pci_register_driver(&sl82c105_pci_driver);
}

static void __exit sl82c105_exit(void)
{
	pci_unregister_driver(&sl82c105_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Sl82c105");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sl82c105);
MODULE_VERSION(DRV_VERSION);

module_init(sl82c105_init);
module_exit(sl82c105_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_sl82c105.c - SL82C105 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* Based in part on linux/drivers/ide/pci/sl82c105.c
	7	* SL82C105/Winbond 553 IDE driver
	8	*
	9	* and in part on the documentation and errata sheet
16728da9 AC	10	*
	11	*
	12	* Note: The controller like many controllers has shared timings for
	13	* PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
	14	* in the dma_stop function. Thus we actually don't need a set_dmamode
	15	* method as the PIO method is always called and will set the right PIO
	16	* timing parameters.
669a5db4	17	*/
85cd7251	18
669a5db4 JG	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/pci.h>
	22	#include <linux/init.h>
	23	#include <linux/blkdev.h>
	24	#include <linux/delay.h>
	25	#include <scsi/scsi_host.h>
	26	#include <linux/libata.h>
	27
	28	#define DRV_NAME "pata_sl82c105"
92ba5d02	29	#define DRV_VERSION "0.3.3"
669a5db4 JG	30
	31	enum {
	32	/*
	33	* SL82C105 PCI config register 0x40 bits.
	34	*/
	35	CTRL_IDE_IRQB = (1 << 30),
	36	CTRL_IDE_IRQA = (1 << 28),
	37	CTRL_LEGIRQ = (1 << 11),
	38	CTRL_P1F16 = (1 << 5),
	39	CTRL_P1EN = (1 << 4),
	40	CTRL_P0F16 = (1 << 1),
	41	CTRL_P0EN = (1 << 0)
	42	};
	43
	44	/**
	45	* sl82c105_pre_reset - probe begin
cc0680a5	46	* @link: ATA link
d4b2bab4	47	* @deadline: deadline jiffies for the operation
669a5db4 JG	48	*
	49	* Set up cable type and use generic probe init
	50	*/
85cd7251	51
cc0680a5	52	static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4 JG	53	{
	54	static const struct pci_bits sl82c105_enable_bits[] = {
	55	{ 0x40, 1, 0x01, 0x01 },
	56	{ 0x40, 1, 0x10, 0x10 }
	57	};
cc0680a5	58	struct ata_port *ap = link->ap;
669a5db4 JG	59	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4 JG	60
c961922b AC	61	if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
c961922b AC	62	return -ENOENT;
cc0680a5	63	return ata_std_prereset(link, deadline);
669a5db4 JG	64	}
	65
	66
669a5db4 JG	67	/**
	68	* sl82c105_configure_piomode - set chip PIO timing
	69	* @ap: ATA interface
	70	* @adev: ATA device
	71	* @pio: PIO mode
	72	*
	73	* Called to do the PIO mode setup. Our timing registers are shared
	74	* so a configure_dmamode call will undo any work we do here and vice
	75	* versa
	76	*/
85cd7251	77
669a5db4 JG	78	static void sl82c105_configure_piomode(struct ata_port ap, struct ata_device adev, int pio)
	79	{
	80	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	81	static u16 pio_timing[5] = {
	82	0x50D, 0x407, 0x304, 0x242, 0x240
	83	};
	84	u16 dummy;
	85	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
85cd7251	86
669a5db4 JG	87	pci_write_config_word(pdev, timing, pio_timing[pio]);
	88	/* Can we lose this oddity of the old driver */
	89	pci_read_config_word(pdev, timing, &dummy);
	90	}
	91
	92	/**
	93	* sl82c105_set_piomode - set initial PIO mode data
	94	* @ap: ATA interface
	95	* @adev: ATA device
	96	*
	97	* Called to do the PIO mode setup. Our timing registers are shared
	98	* but we want to set the PIO timing by default.
	99	*/
85cd7251	100
669a5db4 JG	101	static void sl82c105_set_piomode(struct ata_port ap, struct ata_device adev)
	102	{
	103	sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
	104	}
	105
	106	/**
	107	* sl82c105_configure_dmamode - set DMA mode in chip
	108	* @ap: ATA interface
	109	* @adev: ATA device
	110	*
	111	* Load DMA cycle times into the chip ready for a DMA transfer
	112	* to occur.
	113	*/
85cd7251	114
669a5db4 JG	115	static void sl82c105_configure_dmamode(struct ata_port ap, struct ata_device adev)
	116	{
	117	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	118	static u16 dma_timing[3] = {
	119	0x707, 0x201, 0x200
	120	};
	121	u16 dummy;
	122	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
	123	int dma = adev->dma_mode - XFER_MW_DMA_0;
85cd7251	124
669a5db4 JG	125	pci_write_config_word(pdev, timing, dma_timing[dma]);
	126	/* Can we lose this oddity of the old driver */
	127	pci_read_config_word(pdev, timing, &dummy);
	128	}
	129
669a5db4 JG	130	/**
	131	* sl82c105_reset_engine - Reset the DMA engine
	132	* @ap: ATA interface
	133	*
	134	* The sl82c105 has some serious problems with the DMA engine
85cd7251	135	* when transfers don't run as expected or ATAPI is used. The
669a5db4 JG	136	* recommended fix is to reset the engine each use using a chip
	137	* test register.
	138	*/
85cd7251	139
669a5db4 JG	140	static void sl82c105_reset_engine(struct ata_port *ap)
	141	{
	142	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	143	u16 val;
85cd7251	144
669a5db4 JG	145	pci_read_config_word(pdev, 0x7E, &val);
	146	pci_write_config_word(pdev, 0x7E, val \| 4);
	147	pci_write_config_word(pdev, 0x7E, val & ~4);
	148	}
	149
	150	/**
	151	* sl82c105_bmdma_start - DMA engine begin
	152	* @qc: ATA command
	153	*
	154	* Reset the DMA engine each use as recommended by the errata
85cd7251	155	* document.
669a5db4 JG	156	*
	157	* FIXME: if we switch clock at BMDMA start/end we might get better
	158	* PIO performance on DMA capable devices.
	159	*/
85cd7251	160
669a5db4 JG	161	static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
	162	{
	163	struct ata_port *ap = qc->ap;
	164
8361cd79	165	udelay(100);
669a5db4	166	sl82c105_reset_engine(ap);
8361cd79	167	udelay(100);
85cd7251	168
669a5db4 JG	169	/* Set the clocks for DMA */
669a5db4 JG	170	sl82c105_configure_dmamode(ap, qc->dev);
85cd7251	171	/* Activate DMA */
669a5db4 JG	172	ata_bmdma_start(qc);
	173	}
	174
	175	/**
	176	* sl82c105_bmdma_end - DMA engine stop
	177	* @qc: ATA command
	178	*
	179	* Reset the DMA engine each use as recommended by the errata
	180	* document.
	181	*
	182	* This function is also called to turn off DMA when a timeout occurs
	183	* during DMA operation. In both cases we need to reset the engine,
	184	* so no actual eng_timeout handler is required.
	185	*
	186	* We assume bmdma_stop is always called if bmdma_start as called. If
	187	* not then we may need to wrap qc_issue.
	188	*/
85cd7251	189
669a5db4 JG	190	static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
	191	{
	192	struct ata_port *ap = qc->ap;
	193
	194	ata_bmdma_stop(qc);
	195	sl82c105_reset_engine(ap);
8361cd79	196	udelay(100);
85cd7251	197
669a5db4 JG	198	/* This will redo the initial setup of the DMA device to matching
669a5db4 JG	199	PIO timings */
16728da9	200	sl82c105_set_piomode(ap, qc->dev);
669a5db4 JG	201	}
669a5db4 JG	202
92ba5d02 AC	203	/**
	204	* sl82c105_qc_defer - implement serialization
	205	* @qc: command
	206	*
	207	* We must issue one command per host not per channel because
	208	* of the reset bug.
	209	*
	210	* Q: is the scsi host lock sufficient ?
	211	*/
	212
	213	static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
	214	{
	215	struct ata_host *host = qc->ap->host;
	216	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
	217	int rc;
	218
	219	/* First apply the usual rules */
	220	rc = ata_std_qc_defer(qc);
	221	if (rc != 0)
	222	return rc;
	223
	224	/* Now apply serialization rules. Only allow a command if the
	225	other channel state machine is idle */
	226	if (alt && alt->qc_active)
	227	return ATA_DEFER_PORT;
	228	return 0;
	229	}
	230
669a5db4	231	static struct scsi_host_template sl82c105_sht = {
68d1d07b	232	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	233	};
	234
	235	static struct ata_port_operations sl82c105_port_ops = {
029cfd6b TH	236	.inherits = &ata_bmdma_port_ops,
029cfd6b TH	237	.qc_defer = sl82c105_qc_defer,
669a5db4 JG	238	.bmdma_start = sl82c105_bmdma_start,
669a5db4 JG	239	.bmdma_stop = sl82c105_bmdma_stop,
029cfd6b TH	240	.cable_detect = ata_cable_40wire,
029cfd6b TH	241	.set_piomode = sl82c105_set_piomode,
a1efdaba	242	.prereset = sl82c105_pre_reset,
85cd7251	243	};
669a5db4 JG	244
	245	/**
	246	* sl82c105_bridge_revision - find bridge version
	247	* @pdev: PCI device for the ATA function
	248	*
	249	* Locates the PCI bridge associated with the ATA function and
	250	* providing it is a Winbond 553 reports the revision. If it cannot
	251	* find a revision or the right device it returns -1
	252	*/
85cd7251	253
669a5db4 JG	254	static int sl82c105_bridge_revision(struct pci_dev *pdev)
	255	{
	256	struct pci_dev *bridge;
669a5db4 JG	257
	258	/*
	259	* The bridge should be part of the same device, but function 0.
	260	*/
	261	bridge = pci_get_slot(pdev->bus,
	262	PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
	263	if (!bridge)
	264	return -1;
	265
	266	/*
	267	* Make sure it is a Winbond 553 and is an ISA bridge.
	268	*/
	269	if (bridge->vendor != PCI_VENDOR_ID_WINBOND \|\|
	270	bridge->device != PCI_DEVICE_ID_WINBOND_83C553 \|\|
	271	bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
	272	pci_dev_put(bridge);
	273	return -1;
	274	}
	275	/*
	276	* We need to find function 0's revision, not function 1
	277	*/
669a5db4	278	pci_dev_put(bridge);
44c10138	279	return bridge->revision;
669a5db4 JG	280	}
669a5db4 JG	281
85cd7251	282
669a5db4 JG	283	static int sl82c105_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	284	{
1626aeb8	285	static const struct ata_port_info info_dma = {
1d2808fd	286	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	287	.pio_mask = 0x1f,
	288	.mwdma_mask = 0x07,
	289	.port_ops = &sl82c105_port_ops
	290	};
1626aeb8	291	static const struct ata_port_info info_early = {
1d2808fd	292	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	293	.pio_mask = 0x1f,
	294	.port_ops = &sl82c105_port_ops
	295	};
1626aeb8 TH	296	/* for now use only the first port */
1626aeb8 TH	297	const struct ata_port_info *ppi[] = { &info_early,
92ba5d02	298	NULL };
669a5db4 JG	299	u32 val;
669a5db4 JG	300	int rev;
f08048e9 TH	301	int rc;
	302
	303	rc = pcim_enable_device(dev);
	304	if (rc)
	305	return rc;
669a5db4 JG	306
669a5db4 JG	307	rev = sl82c105_bridge_revision(dev);
85cd7251	308
669a5db4 JG	309	if (rev == -1)
	310	dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
	311	else if (rev <= 5)
	312	dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
1626aeb8 TH	313	else
1626aeb8 TH	314	ppi[0] = &info_dma;
85cd7251	315
669a5db4 JG	316	pci_read_config_dword(dev, 0x40, &val);
	317	val \|= CTRL_P0EN \| CTRL_P0F16 \| CTRL_P1F16;
	318	pci_write_config_dword(dev, 0x40, val);
	319
887125e3	320	return ata_pci_init_one(dev, ppi, &sl82c105_sht, NULL);
669a5db4 JG	321	}
669a5db4 JG	322
2d2744fc JG	323	static const struct pci_device_id sl82c105[] = {
	324	{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
	325
	326	{ },
669a5db4 JG	327	};
	328
	329	static struct pci_driver sl82c105_pci_driver = {
	330	.name = DRV_NAME,
	331	.id_table = sl82c105,
	332	.probe = sl82c105_init_one,
	333	.remove = ata_pci_remove_one
	334	};
	335
	336	static int __init sl82c105_init(void)
	337	{
	338	return pci_register_driver(&sl82c105_pci_driver);
	339	}
	340
669a5db4 JG	341	static void __exit sl82c105_exit(void)
	342	{
	343	pci_unregister_driver(&sl82c105_pci_driver);
	344	}
	345
669a5db4 JG	346	MODULE_AUTHOR("Alan Cox");
	347	MODULE_DESCRIPTION("low-level driver for Sl82c105");
	348	MODULE_LICENSE("GPL");
	349	MODULE_DEVICE_TABLE(pci, sl82c105);
	350	MODULE_VERSION(DRV_VERSION);
	351
	352	module_init(sl82c105_init);
	353	module_exit(sl82c105_exit);