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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/hpa/linux...
[mirror_ubuntu-artful-kernel.git] / drivers / ata / pata_via.c
CommitLineData
669a5db4
JG		 1/*
2 * pata_via.c - VIA PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Documentation
7 * Most chipset documentation available under NDA only
8 *
9 * VIA version guide
10 * VIA VT82C561 - early design, uses ata_generic currently
11 * VIA VT82C576 - MWDMA, 33Mhz
12 * VIA VT82C586 - MWDMA, 33Mhz
13 * VIA VT82C586a - Added UDMA to 33Mhz
14 * VIA VT82C586b - UDMA33
15 * VIA VT82C596a - Nonfunctional UDMA66
16 * VIA VT82C596b - Working UDMA66
17 * VIA VT82C686 - Nonfunctional UDMA66
18 * VIA VT82C686a - Working UDMA66
19 * VIA VT82C686b - Updated to UDMA100
20 * VIA VT8231 - UDMA100
21 * VIA VT8233 - UDMA100
22 * VIA VT8233a - UDMA133
23 * VIA VT8233c - UDMA100
24 * VIA VT8235 - UDMA133
25 * VIA VT8237 - UDMA133
05c39e50 26 * VIA VT8237S - UDMA133
75f609d2 27 * VIA VT8251 - UDMA133
669a5db4
JG		 28 *
29 * Most registers remain compatible across chips. Others start reserved
30 * and acquire sensible semantics if set to 1 (eg cable detect). A few
31 * exceptions exist, notably around the FIFO settings.
32 *
33 * One additional quirk of the VIA design is that like ALi they use few
34 * PCI IDs for a lot of chips.
35 *
36 * Based heavily on:
37 *
38 * Version 3.38
39 *
40 * VIA IDE driver for Linux. Supported southbridges:
41 *
42 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
43 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
44 * vt8235, vt8237
45 *
46 * Copyright (c) 2000-2002 Vojtech Pavlik
47 *
48 * Based on the work of:
49 * Michel Aubry
50 * Jeff Garzik
51 * Andre Hedrick
52
53 */
54
55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <scsi/scsi_host.h>
62#include <linux/libata.h>
cf5792d2 63#include <linux/dmi.h>
669a5db4
JG		 64
65#define DRV_NAME "pata_via"
9edbdbea 66#define DRV_VERSION "0.3.2"
669a5db4
JG		 67
68/*
69 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
70 * driver.
71 */
72
73enum {
74 VIA_UDMA = 0x007,
75 VIA_UDMA_NONE = 0x000,
76 VIA_UDMA_33 = 0x001,
77 VIA_UDMA_66 = 0x002,
78 VIA_UDMA_100 = 0x003,
79 VIA_UDMA_133 = 0x004,
80 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
81 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
82 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
83 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
84 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
85 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
86 VIA_NO_ENABLES = 0x400, /* Has no enablebits */
87};
88
89/*
90 * VIA SouthBridge chips.
91 */
92
93static const struct via_isa_bridge {
94 const char *name;
95 u16 id;
96 u8 rev_min;
97 u8 rev_max;
98 u16 flags;
99} via_isa_bridges[] = {
e0b874df 100 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
75f609d2 101 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
669a5db4
JG		 102 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
103 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
104 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
105 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
106 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
107 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
108 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
109 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
110 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
111 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
112 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
113 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
114 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
115 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
116 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
117 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
118 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
119 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
120 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
121 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
122 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
123 { NULL }
124};
125
cf5792d2
AC		 126
127/*
128 * Cable special cases
129 */
130
131static struct dmi_system_id cable_dmi_table[] = {
132 {
133 .ident = "Acer Ferrari 3400",
134 .matches = {
135 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
136 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
137 },
138 },
139 { }
140};
141
142static int via_cable_override(struct pci_dev *pdev)
143{
144 /* Systems by DMI */
145 if (dmi_check_system(cable_dmi_table))
146 return 1;
9edbdbea
AC		 147 /* Arima W730-K8/Targa Visionary 811/... */
148 if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)
149 return 1;
cf5792d2
AC		 150 return 0;
151}
152
153
669a5db4
JG		 154/**
155 * via_cable_detect - cable detection
156 * @ap: ATA port
157 *
158 * Perform cable detection. Actually for the VIA case the BIOS
159 * already did this for us. We read the values provided by the
160 * BIOS. If you are using an 8235 in a non-PC configuration you
161 * may need to update this code.
162 *
163 * Hotplug also impacts on this.
164 */
165
166static int via_cable_detect(struct ata_port *ap) {
97cb81c3 167 const struct via_isa_bridge *config = ap->host->private_data;
669a5db4
JG		 168 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
169 u32 ata66;
170
cf5792d2
AC		 171 if (via_cable_override(pdev))
172 return ATA_CBL_PATA40_SHORT;
173
97cb81c3
AC		 174 /* Early chips are 40 wire */
175 if ((config->flags & VIA_UDMA) < VIA_UDMA_66)
176 return ATA_CBL_PATA40;
177 /* UDMA 66 chips have only drive side logic */
178 else if((config->flags & VIA_UDMA) < VIA_UDMA_100)
179 return ATA_CBL_PATA_UNK;
180 /* UDMA 100 or later */
669a5db4
JG		 181 pci_read_config_dword(pdev, 0x50, &ata66);
182 /* Check both the drive cable reporting bits, we might not have
183 two drives */
184 if (ata66 & (0x10100000 >> (16 * ap->port_no)))
185 return ATA_CBL_PATA80;
97cb81c3 186 return ATA_CBL_PATA40;
669a5db4
JG		 187}
188
d4b2bab4 189static int via_pre_reset(struct ata_port *ap, unsigned long deadline)
669a5db4
JG		 190{
191 const struct via_isa_bridge *config = ap->host->private_data;
192
193 if (!(config->flags & VIA_NO_ENABLES)) {
194 static const struct pci_bits via_enable_bits[] = {
195 { 0x40, 1, 0x02, 0x02 },
196 { 0x40, 1, 0x01, 0x01 }
197 };
669a5db4 198 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
c961922b
AC		 199 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
200 return -ENOENT;
669a5db4 201 }
d4b2bab4
TH		 202
203 return ata_std_prereset(ap, deadline);
669a5db4
JG		 204}
205
206
207/**
208 * via_error_handler - reset for VIA chips
209 * @ap: ATA port
210 *
211 * Handle the reset callback for the later chips with cable detect
212 */
213
214static void via_error_handler(struct ata_port *ap)
215{
216 ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
217}
218
219/**
220 * via_do_set_mode - set initial PIO mode data
221 * @ap: ATA interface
222 * @adev: ATA device
223 * @mode: ATA mode being programmed
224 * @tdiv: Clocks per PCI clock
225 * @set_ast: Set to program address setup
226 * @udma_type: UDMA mode/format of registers
227 *
228 * Program the VIA registers for DMA and PIO modes. Uses the ata timing
229 * support in order to compute modes.
230 *
231 * FIXME: Hotplug will require we serialize multiple mode changes
232 * on the two channels.
233 */
234
235static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
236{
237 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
238 struct ata_device *peer = ata_dev_pair(adev);
239 struct ata_timing t, p;
240 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
241 unsigned long T = 1000000000 / via_clock;
242 unsigned long UT = T/tdiv;
243 int ut;
244 int offset = 3 - (2*ap->port_no) - adev->devno;
245
246
247 /* Calculate the timing values we require */
248 ata_timing_compute(adev, mode, &t, T, UT);
249
250 /* We share 8bit timing so we must merge the constraints */
251 if (peer) {
252 if (peer->pio_mode) {
253 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
254 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
255 }
256 }
257
258 /* Address setup is programmable but breaks on UDMA133 setups */
259 if (set_ast) {
260 u8 setup; /* 2 bits per drive */
261 int shift = 2 * offset;
262
263 pci_read_config_byte(pdev, 0x4C, &setup);
264 setup &= ~(3 << shift);
265 setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
266 pci_write_config_byte(pdev, 0x4C, setup);
267 }
268
269 /* Load the PIO mode bits */
270 pci_write_config_byte(pdev, 0x4F - ap->port_no,
271 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1));
272 pci_write_config_byte(pdev, 0x48 + offset,
273 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1));
274
275 /* Load the UDMA bits according to type */
276 switch(udma_type) {
277 default:
278 /* BUG() ? */
279 /* fall through */
280 case 33:
281 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03;
282 break;
283 case 66:
284 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f;
285 break;
286 case 100:
287 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
288 break;
289 case 133:
290 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
291 break;
292 }
293 /* Set UDMA unless device is not UDMA capable */
294 if (udma_type)
295 pci_write_config_byte(pdev, 0x50 + offset, ut);
296}
297
298static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
299{
300 const struct via_isa_bridge *config = ap->host->private_data;
301 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
302 int mode = config->flags & VIA_UDMA;
303 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
304 static u8 udma[5] = { 0, 33, 66, 100, 133 };
305
306 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
307}
308
309static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
310{
311 const struct via_isa_bridge *config = ap->host->private_data;
312 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
313 int mode = config->flags & VIA_UDMA;
314 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
315 static u8 udma[5] = { 0, 33, 66, 100, 133 };
316
317 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
318}
319
320static struct scsi_host_template via_sht = {
321 .module = THIS_MODULE,
322 .name = DRV_NAME,
323 .ioctl = ata_scsi_ioctl,
324 .queuecommand = ata_scsi_queuecmd,
325 .can_queue = ATA_DEF_QUEUE,
326 .this_id = ATA_SHT_THIS_ID,
327 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 328 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
329 .emulated = ATA_SHT_EMULATED,
330 .use_clustering = ATA_SHT_USE_CLUSTERING,
331 .proc_name = DRV_NAME,
332 .dma_boundary = ATA_DMA_BOUNDARY,
333 .slave_configure = ata_scsi_slave_config,
afdfe899 334 .slave_destroy = ata_scsi_slave_destroy,
669a5db4
JG		 335 .bios_param = ata_std_bios_param,
336};
337
338static struct ata_port_operations via_port_ops = {
339 .port_disable = ata_port_disable,
340 .set_piomode = via_set_piomode,
341 .set_dmamode = via_set_dmamode,
342 .mode_filter = ata_pci_default_filter,
343
344 .tf_load = ata_tf_load,
345 .tf_read = ata_tf_read,
346 .check_status = ata_check_status,
347 .exec_command = ata_exec_command,
348 .dev_select = ata_std_dev_select,
349
350 .freeze = ata_bmdma_freeze,
351 .thaw = ata_bmdma_thaw,
352 .error_handler = via_error_handler,
353 .post_internal_cmd = ata_bmdma_post_internal_cmd,
97cb81c3 354 .cable_detect = via_cable_detect,
669a5db4
JG		 355
356 .bmdma_setup = ata_bmdma_setup,
357 .bmdma_start = ata_bmdma_start,
358 .bmdma_stop = ata_bmdma_stop,
359 .bmdma_status = ata_bmdma_status,
360
361 .qc_prep = ata_qc_prep,
362 .qc_issue = ata_qc_issue_prot,
bda30288 363
0d5ff566 364 .data_xfer = ata_data_xfer,
669a5db4
JG		 365
366 .irq_handler = ata_interrupt,
367 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 368 .irq_on = ata_irq_on,
369 .irq_ack = ata_irq_ack,
669a5db4
JG		 370
371 .port_start = ata_port_start,
669a5db4
JG		 372};
373
374static struct ata_port_operations via_port_ops_noirq = {
375 .port_disable = ata_port_disable,
376 .set_piomode = via_set_piomode,
377 .set_dmamode = via_set_dmamode,
378 .mode_filter = ata_pci_default_filter,
379
380 .tf_load = ata_tf_load,
381 .tf_read = ata_tf_read,
382 .check_status = ata_check_status,
383 .exec_command = ata_exec_command,
384 .dev_select = ata_std_dev_select,
385
386 .freeze = ata_bmdma_freeze,
387 .thaw = ata_bmdma_thaw,
388 .error_handler = via_error_handler,
389 .post_internal_cmd = ata_bmdma_post_internal_cmd,
97cb81c3 390 .cable_detect = via_cable_detect,
669a5db4
JG		 391
392 .bmdma_setup = ata_bmdma_setup,
393 .bmdma_start = ata_bmdma_start,
394 .bmdma_stop = ata_bmdma_stop,
395 .bmdma_status = ata_bmdma_status,
396
397 .qc_prep = ata_qc_prep,
398 .qc_issue = ata_qc_issue_prot,
bda30288 399
0d5ff566 400 .data_xfer = ata_data_xfer_noirq,
669a5db4
JG		 401
402 .irq_handler = ata_interrupt,
403 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 404 .irq_on = ata_irq_on,
405 .irq_ack = ata_irq_ack,
669a5db4
JG		 406
407 .port_start = ata_port_start,
669a5db4
JG		 408};
409
627d2d32
AC		 410/**
411 * via_config_fifo - set up the FIFO
412 * @pdev: PCI device
413 * @flags: configuration flags
414 *
415 * Set the FIFO properties for this device if neccessary. Used both on
416 * set up and on and the resume path
417 */
418
419static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
420{
421 u8 enable;
f20b16ff 422
627d2d32
AC		 423 /* 0x40 low bits indicate enabled channels */
424 pci_read_config_byte(pdev, 0x40 , &enable);
425 enable &= 3;
f20b16ff 426
627d2d32 427 if (flags & VIA_SET_FIFO) {
73720861 428 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
627d2d32
AC		 429 u8 fifo;
430
431 pci_read_config_byte(pdev, 0x43, &fifo);
432
433 /* Clear PREQ# until DDACK# for errata */
434 if (flags & VIA_BAD_PREQ)
435 fifo &= 0x7F;
436 else
437 fifo &= 0x9f;
438 /* Turn on FIFO for enabled channels */
439 fifo |= fifo_setting[enable];
440 pci_write_config_byte(pdev, 0x43, fifo);
441 }
442}
443
669a5db4
JG		 444/**
445 * via_init_one - discovery callback
627d2d32 446 * @pdev: PCI device
669a5db4
JG		 447 * @id: PCI table info
448 *
449 * A VIA IDE interface has been discovered. Figure out what revision
450 * and perform configuration work before handing it to the ATA layer
451 */
452
453static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
454{
455 /* Early VIA without UDMA support */
1626aeb8 456 static const struct ata_port_info via_mwdma_info = {
669a5db4 457 .sht = &via_sht,
464cf177 458 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 459 .pio_mask = 0x1f,
460 .mwdma_mask = 0x07,
461 .port_ops = &via_port_ops
462 };
463 /* Ditto with IRQ masking required */
1626aeb8 464 static const struct ata_port_info via_mwdma_info_borked = {
669a5db4 465 .sht = &via_sht,
464cf177 466 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 467 .pio_mask = 0x1f,
468 .mwdma_mask = 0x07,
469 .port_ops = &via_port_ops_noirq,
470 };
471 /* VIA UDMA 33 devices (and borked 66) */
1626aeb8 472 static const struct ata_port_info via_udma33_info = {
669a5db4 473 .sht = &via_sht,
464cf177 474 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 475 .pio_mask = 0x1f,
476 .mwdma_mask = 0x07,
bf6263a8 477 .udma_mask = ATA_UDMA2,
669a5db4
JG		 478 .port_ops = &via_port_ops
479 };
480 /* VIA UDMA 66 devices */
1626aeb8 481 static const struct ata_port_info via_udma66_info = {
669a5db4 482 .sht = &via_sht,
464cf177 483 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 484 .pio_mask = 0x1f,
485 .mwdma_mask = 0x07,
bf6263a8 486 .udma_mask = ATA_UDMA4,
669a5db4
JG		 487 .port_ops = &via_port_ops
488 };
489 /* VIA UDMA 100 devices */
1626aeb8 490 static const struct ata_port_info via_udma100_info = {
669a5db4 491 .sht = &via_sht,
464cf177 492 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 493 .pio_mask = 0x1f,
494 .mwdma_mask = 0x07,
bf6263a8 495 .udma_mask = ATA_UDMA5,
669a5db4
JG		 496 .port_ops = &via_port_ops
497 };
498 /* UDMA133 with bad AST (All current 133) */
1626aeb8 499 static const struct ata_port_info via_udma133_info = {
669a5db4 500 .sht = &via_sht,
464cf177 501 .flags = ATA_FLAG_SLAVE_POSS,
669a5db4
JG		 502 .pio_mask = 0x1f,
503 .mwdma_mask = 0x07,
bf6263a8 504 .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */
669a5db4
JG		 505 .port_ops = &via_port_ops
506 };
1626aeb8
TH		 507 struct ata_port_info type;
508 const struct ata_port_info *ppi[] = { &type, NULL };
669a5db4
JG		 509 struct pci_dev *isa = NULL;
510 const struct via_isa_bridge *config;
511 static int printed_version;
669a5db4
JG		 512 u8 enable;
513 u32 timing;
514
515 if (!printed_version++)
516 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
517
518 /* To find out how the IDE will behave and what features we
519 actually have to look at the bridge not the IDE controller */
520 for (config = via_isa_bridges; config->id; config++)
521 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
522 !!(config->flags & VIA_BAD_ID),
523 config->id, NULL))) {
524
44c10138
AK		 525 if (isa->revision >= config->rev_min &&
526 isa->revision <= config->rev_max)
669a5db4
JG		 527 break;
528 pci_dev_put(isa);
529 }
530
531 if (!config->id) {
532 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
533 return -ENODEV;
534 }
535 pci_dev_put(isa);
536
537 /* 0x40 low bits indicate enabled channels */
538 pci_read_config_byte(pdev, 0x40 , &enable);
539 enable &= 3;
540 if (enable == 0) {
541 return -ENODEV;
542 }
543
544 /* Initialise the FIFO for the enabled channels. */
627d2d32 545 via_config_fifo(pdev, config->flags);
f20b16ff 546
669a5db4
JG		 547 /* Clock set up */
548 switch(config->flags & VIA_UDMA) {
549 case VIA_UDMA_NONE:
550 if (config->flags & VIA_NO_UNMASK)
1626aeb8 551 type = via_mwdma_info_borked;
669a5db4 552 else
1626aeb8 553 type = via_mwdma_info;
669a5db4
JG		 554 break;
555 case VIA_UDMA_33:
1626aeb8 556 type = via_udma33_info;
669a5db4
JG		 557 break;
558 case VIA_UDMA_66:
1626aeb8 559 type = via_udma66_info;
669a5db4
JG		 560 /* The 66 MHz devices require we enable the clock */
561 pci_read_config_dword(pdev, 0x50, &timing);
562 timing |= 0x80008;
563 pci_write_config_dword(pdev, 0x50, timing);
564 break;
565 case VIA_UDMA_100:
1626aeb8 566 type = via_udma100_info;
669a5db4
JG		 567 break;
568 case VIA_UDMA_133:
1626aeb8 569 type = via_udma133_info;
669a5db4
JG		 570 break;
571 default:
572 WARN_ON(1);
573 return -ENODEV;
574 }
575
576 if (config->flags & VIA_BAD_CLK66) {
577 /* Disable the 66MHz clock on problem devices */
578 pci_read_config_dword(pdev, 0x50, &timing);
579 timing &= ~0x80008;
580 pci_write_config_dword(pdev, 0x50, timing);
581 }
582
583 /* We have established the device type, now fire it up */
1626aeb8 584 type.private_data = (void *)config;
669a5db4 585
1626aeb8 586 return ata_pci_init_one(pdev, ppi);
669a5db4
JG		 587}
588
438ac6d5 589#ifdef CONFIG_PM
627d2d32
AC		 590/**
591 * via_reinit_one - reinit after resume
592 * @pdev; PCI device
593 *
594 * Called when the VIA PATA device is resumed. We must then
595 * reconfigure the fifo and other setup we may have altered. In
596 * addition the kernel needs to have the resume methods on PCI
597 * quirk supported.
598 */
599
600static int via_reinit_one(struct pci_dev *pdev)
601{
602 u32 timing;
603 struct ata_host *host = dev_get_drvdata(&pdev->dev);
604 const struct via_isa_bridge *config = host->private_data;
f20b16ff 605
627d2d32
AC		 606 via_config_fifo(pdev, config->flags);
607
608 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
609 /* The 66 MHz devices require we enable the clock */
610 pci_read_config_dword(pdev, 0x50, &timing);
611 timing |= 0x80008;
612 pci_write_config_dword(pdev, 0x50, timing);
613 }
614 if (config->flags & VIA_BAD_CLK66) {
615 /* Disable the 66MHz clock on problem devices */
616 pci_read_config_dword(pdev, 0x50, &timing);
617 timing &= ~0x80008;
618 pci_write_config_dword(pdev, 0x50, timing);
619 }
f20b16ff 620 return ata_pci_device_resume(pdev);
627d2d32 621}
438ac6d5 622#endif
627d2d32 623
669a5db4 624static const struct pci_device_id via[] = {
52df0ee0
JG		 625 { PCI_VDEVICE(VIA, 0x0571), },
626 { PCI_VDEVICE(VIA, 0x0581), },
627 { PCI_VDEVICE(VIA, 0x1571), },
628 { PCI_VDEVICE(VIA, 0x3164), },
629 { PCI_VDEVICE(VIA, 0x5324), },
2d2744fc
JG		 630
631 { },
669a5db4
JG		 632};
633
634static struct pci_driver via_pci_driver = {
2d2744fc 635 .name = DRV_NAME,
669a5db4
JG		 636 .id_table = via,
637 .probe = via_init_one,
627d2d32 638 .remove = ata_pci_remove_one,
438ac6d5 639#ifdef CONFIG_PM
627d2d32
AC		 640 .suspend = ata_pci_device_suspend,
641 .resume = via_reinit_one,
438ac6d5 642#endif
669a5db4
JG		 643};
644
645static int __init via_init(void)
646{
647 return pci_register_driver(&via_pci_driver);
648}
649
669a5db4
JG		 650static void __exit via_exit(void)
651{
652 pci_unregister_driver(&via_pci_driver);
653}
654
669a5db4
JG		 655MODULE_AUTHOR("Alan Cox");
656MODULE_DESCRIPTION("low-level driver for VIA PATA");
657MODULE_LICENSE("GPL");
658MODULE_DEVICE_TABLE(pci, via);
659MODULE_VERSION(DRV_VERSION);
660
661module_init(via_init);
662module_exit(via_exit);
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