[mirror_ubuntu-zesty-kernel.git] / drivers / ata / pata_via.c

/*
 * pata_via.c 	- VIA PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 *  Documentation
 *	Most chipset documentation available under NDA only
 *
 *  VIA version guide
 *	VIA VT82C561	-	early design, uses ata_generic currently
 *	VIA VT82C576	-	MWDMA, 33Mhz
 *	VIA VT82C586	-	MWDMA, 33Mhz
 *	VIA VT82C586a	-	Added UDMA to 33Mhz
 *	VIA VT82C586b	-	UDMA33
 *	VIA VT82C596a	-	Nonfunctional UDMA66
 *	VIA VT82C596b	-	Working UDMA66
 *	VIA VT82C686	-	Nonfunctional UDMA66
 *	VIA VT82C686a	-	Working UDMA66
 *	VIA VT82C686b	-	Updated to UDMA100
 *	VIA VT8231	-	UDMA100
 *	VIA VT8233	-	UDMA100
 *	VIA VT8233a	-	UDMA133
 *	VIA VT8233c	-	UDMA100
 *	VIA VT8235	-	UDMA133
 *	VIA VT8237	-	UDMA133
 *	VIA VT8251	-	UDMA133
 *
 *	Most registers remain compatible across chips. Others start reserved
 *	and acquire sensible semantics if set to 1 (eg cable detect). A few
 *	exceptions exist, notably around the FIFO settings.
 *
 *	One additional quirk of the VIA design is that like ALi they use few
 *	PCI IDs for a lot of chips.
 *
 *	Based heavily on:
 *
 * Version 3.38
 *
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick

 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_via"
#define DRV_VERSION "0.2.0"

/*
 *	The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
 *	driver.
 */

enum {
	VIA_UDMA	= 0x007,
	VIA_UDMA_NONE	= 0x000,
	VIA_UDMA_33	= 0x001,
	VIA_UDMA_66	= 0x002,
	VIA_UDMA_100	= 0x003,
	VIA_UDMA_133	= 0x004,
	VIA_BAD_PREQ	= 0x010, /* Crashes if PREQ# till DDACK# set */
	VIA_BAD_CLK66	= 0x020, /* 66 MHz clock doesn't work correctly */
	VIA_SET_FIFO	= 0x040, /* Needs to have FIFO split set */
	VIA_NO_UNMASK	= 0x080, /* Doesn't work with IRQ unmasking on */
	VIA_BAD_ID	= 0x100, /* Has wrong vendor ID (0x1107) */
	VIA_BAD_AST	= 0x200, /* Don't touch Address Setup Timing */
	VIA_NO_ENABLES	= 0x400, /* Has no enablebits */
};

/*
 * VIA SouthBridge chips.
 */

static const struct via_isa_bridge {
	const char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u16 flags;
} via_isa_bridges[] = {
	{ "vt8237s",	PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, VIA_UDMA_100 },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, VIA_UDMA_100 },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, VIA_UDMA_100 },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, VIA_UDMA_100 },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, VIA_UDMA_66 },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, VIA_UDMA_66 },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ NULL }
};

/**
 *	via_cable_detect	-	cable detection
 *	@ap: ATA port
 *
 *	Perform cable detection. Actually for the VIA case the BIOS
 *	already did this for us. We read the values provided by the
 *	BIOS. If you are using an 8235 in a non-PC configuration you
 *	may need to update this code.
 *
 *	Hotplug also impacts on this.
 */

static int via_cable_detect(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 ata66;

	pci_read_config_dword(pdev, 0x50, &ata66);
	/* Check both the drive cable reporting bits, we might not have
	   two drives */
	if (ata66 & (0x10100000 >> (16 * ap->port_no)))
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static int via_pre_reset(struct ata_port *ap)
{
	const struct via_isa_bridge *config = ap->host->private_data;

	if (!(config->flags & VIA_NO_ENABLES)) {
		static const struct pci_bits via_enable_bits[] = {
			{ 0x40, 1, 0x02, 0x02 },
			{ 0x40, 1, 0x01, 0x01 }
		};

		struct pci_dev *pdev = to_pci_dev(ap->host->dev);

		if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
			return -ENOENT;
	}

	if ((config->flags & VIA_UDMA) >= VIA_UDMA_100)
		ap->cbl = via_cable_detect(ap);
	/* The UDMA66 series has no cable detect so do drive side detect */
	else if ((config->flags & VIA_UDMA) < VIA_UDMA_66)
		ap->cbl = ATA_CBL_PATA40;
	else
		ap->cbl = ATA_CBL_PATA_UNK;
		

	return ata_std_prereset(ap);
}


/**
 *	via_error_handler		-	reset for VIA chips
 *	@ap: ATA port
 *
 *	Handle the reset callback for the later chips with cable detect
 */

static void via_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	via_do_set_mode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: ATA mode being programmed
 *	@tdiv: Clocks per PCI clock
 *	@set_ast: Set to program address setup
 *	@udma_type: UDMA mode/format of registers
 *
 *	Program the VIA registers for DMA and PIO modes. Uses the ata timing
 *	support in order to compute modes.
 *
 *	FIXME: Hotplug will require we serialize multiple mode changes
 *	on the two channels.
 */

static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_device *peer = ata_dev_pair(adev);
	struct ata_timing t, p;
	static int via_clock = 33333;	/* Bus clock in kHZ - ought to be tunable one day */
	unsigned long T =  1000000000 / via_clock;
	unsigned long UT = T/tdiv;
	int ut;
	int offset = 3 - (2*ap->port_no) - adev->devno;


	/* Calculate the timing values we require */
	ata_timing_compute(adev, mode, &t, T, UT);

	/* We share 8bit timing so we must merge the constraints */
	if (peer) {
		if (peer->pio_mode) {
			ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
			ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
		}
	}

	/* Address setup is programmable but breaks on UDMA133 setups */
	if (set_ast) {
		u8 setup;	/* 2 bits per drive */
		int shift = 2 * offset;

		pci_read_config_byte(pdev, 0x4C, &setup);
		setup &= ~(3 << shift);
		setup |= FIT(t.setup, 1, 4) << shift;	/* 1,4 or 1,4 - 1  FIXME */
		pci_write_config_byte(pdev, 0x4C, setup);
	}

	/* Load the PIO mode bits */
	pci_write_config_byte(pdev, 0x4F - ap->port_no,
		((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1));
	pci_write_config_byte(pdev, 0x48 + offset,
		((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1));

	/* Load the UDMA bits according to type */
	switch(udma_type) {
		default:
			/* BUG() ? */
			/* fall through */
		case 33:
			ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03;
			break;
		case 66:
			ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f;
			break;
		case 100:
			ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
			break;
		case 133:
			ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
			break;
	}
	/* Set UDMA unless device is not UDMA capable */
	if (udma_type)
		pci_write_config_byte(pdev, 0x50 + offset, ut);
}

static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	const struct via_isa_bridge *config = ap->host->private_data;
	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
	int mode = config->flags & VIA_UDMA;
	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
	static u8 udma[5] = { 0, 33, 66, 100, 133 };

	via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
}

static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	const struct via_isa_bridge *config = ap->host->private_data;
	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
	int mode = config->flags & VIA_UDMA;
	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
	static u8 udma[5] = { 0, 33, 66, 100, 133 };

	via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
}

static struct scsi_host_template via_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
	.resume			= ata_scsi_device_resume,
	.suspend		= ata_scsi_device_suspend,
};

static struct ata_port_operations via_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= via_set_piomode,
	.set_dmamode	= via_set_dmamode,
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= via_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_pio_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
	.port_stop	= ata_port_stop,
	.host_stop	= ata_host_stop
};

static struct ata_port_operations via_port_ops_noirq = {
	.port_disable	= ata_port_disable,
	.set_piomode	= via_set_piomode,
	.set_dmamode	= via_set_dmamode,
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= via_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_pio_data_xfer_noirq,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
	.port_stop	= ata_port_stop,
	.host_stop	= ata_host_stop
};

/**
 *	via_config_fifo		-	set up the FIFO
 *	@pdev: PCI device
 *	@flags: configuration flags
 *
 *	Set the FIFO properties for this device if neccessary. Used both on
 *	set up and on and the resume path
 */

static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
{
	u8 enable;
	
	/* 0x40 low bits indicate enabled channels */
	pci_read_config_byte(pdev, 0x40 , &enable);
	enable &= 3;
	
	if (flags & VIA_SET_FIFO) {
		static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
		u8 fifo;

		pci_read_config_byte(pdev, 0x43, &fifo);

		/* Clear PREQ# until DDACK# for errata */
		if (flags & VIA_BAD_PREQ)
			fifo &= 0x7F;
		else
			fifo &= 0x9f;
		/* Turn on FIFO for enabled channels */
		fifo |= fifo_setting[enable];
		pci_write_config_byte(pdev, 0x43, fifo);
	}
}

/**
 *	via_init_one		-	discovery callback
 *	@pdev: PCI device
 *	@id: PCI table info
 *
 *	A VIA IDE interface has been discovered. Figure out what revision
 *	and perform configuration work before handing it to the ATA layer
 */

static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	/* Early VIA without UDMA support */
	static struct ata_port_info via_mwdma_info = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &via_port_ops
	};
	/* Ditto with IRQ masking required */
	static struct ata_port_info via_mwdma_info_borked = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &via_port_ops_noirq,
	};
	/* VIA UDMA 33 devices (and borked 66) */
	static struct ata_port_info via_udma33_info = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x7,
		.port_ops = &via_port_ops
	};
	/* VIA UDMA 66 devices */
	static struct ata_port_info via_udma66_info = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x1f,
		.port_ops = &via_port_ops
	};
	/* VIA UDMA 100 devices */
	static struct ata_port_info via_udma100_info = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x3f,
		.port_ops = &via_port_ops
	};
	/* UDMA133 with bad AST (All current 133) */
	static struct ata_port_info via_udma133_info = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x7f,	/* FIXME: should check north bridge */
		.port_ops = &via_port_ops
	};
	struct ata_port_info *port_info[2], *type;
	struct pci_dev *isa = NULL;
	const struct via_isa_bridge *config;
	static int printed_version;
	u8 t;
	u8 enable;
	u32 timing;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	/* To find out how the IDE will behave and what features we
	   actually have to look at the bridge not the IDE controller */
	for (config = via_isa_bridges; config->id; config++)
		if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(config->flags & VIA_BAD_ID),
			config->id, NULL))) {

			pci_read_config_byte(isa, PCI_REVISION_ID, &t);
			if (t >= config->rev_min &&
			    t <= config->rev_max)
				break;
			pci_dev_put(isa);
		}

	if (!config->id) {
		printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
		return -ENODEV;
	}
	pci_dev_put(isa);

	/* 0x40 low bits indicate enabled channels */
	pci_read_config_byte(pdev, 0x40 , &enable);
	enable &= 3;
	if (enable == 0) {
		return -ENODEV;
	}

	/* Initialise the FIFO for the enabled channels. */
	via_config_fifo(pdev, config->flags);
	
	/* Clock set up */
	switch(config->flags & VIA_UDMA) {
		case VIA_UDMA_NONE:
			if (config->flags & VIA_NO_UNMASK)
				type = &via_mwdma_info_borked;
			else
				type = &via_mwdma_info;
			break;
		case VIA_UDMA_33:
			type = &via_udma33_info;
			break;
		case VIA_UDMA_66:
			type = &via_udma66_info;
			/* The 66 MHz devices require we enable the clock */
			pci_read_config_dword(pdev, 0x50, &timing);
			timing |= 0x80008;
			pci_write_config_dword(pdev, 0x50, timing);
			break;
		case VIA_UDMA_100:
			type = &via_udma100_info;
			break;
		case VIA_UDMA_133:
			type = &via_udma133_info;
			break;
		default:
			WARN_ON(1);
			return -ENODEV;
	}

	if (config->flags & VIA_BAD_CLK66) {
		/* Disable the 66MHz clock on problem devices */
		pci_read_config_dword(pdev, 0x50, &timing);
		timing &= ~0x80008;
		pci_write_config_dword(pdev, 0x50, timing);
	}

	/* We have established the device type, now fire it up */
	type->private_data = (void *)config;

	port_info[0] = port_info[1] = type;
	return ata_pci_init_one(pdev, port_info, 2);
}

/**
 *	via_reinit_one		-	reinit after resume
 *	@pdev; PCI device
 *
 *	Called when the VIA PATA device is resumed. We must then
 *	reconfigure the fifo and other setup we may have altered. In
 *	addition the kernel needs to have the resume methods on PCI
 *	quirk supported.
 */

static int via_reinit_one(struct pci_dev *pdev)
{
	u32 timing;
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	const struct via_isa_bridge *config = host->private_data;
	
	via_config_fifo(pdev, config->flags);

	if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
		/* The 66 MHz devices require we enable the clock */
		pci_read_config_dword(pdev, 0x50, &timing);
		timing |= 0x80008;
		pci_write_config_dword(pdev, 0x50, timing);
	}
	if (config->flags & VIA_BAD_CLK66) {
		/* Disable the 66MHz clock on problem devices */
		pci_read_config_dword(pdev, 0x50, &timing);
		timing &= ~0x80008;
		pci_write_config_dword(pdev, 0x50, timing);
	}
	return ata_pci_device_resume(pdev);	
}

static const struct pci_device_id via[] = {
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },

	{ },
};

static struct pci_driver via_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= via,
	.probe 		= via_init_one,
	.remove		= ata_pci_remove_one,
	.suspend	= ata_pci_device_suspend,
	.resume		= via_reinit_one,
};

static int __init via_init(void)
{
	return pci_register_driver(&via_pci_driver);
}

static void __exit via_exit(void)
{
	pci_unregister_driver(&via_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for VIA PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, via);
MODULE_VERSION(DRV_VERSION);

module_init(via_init);
module_exit(via_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_via.c - VIA PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* Documentation
	7	* Most chipset documentation available under NDA only
	8	*
	9	* VIA version guide
	10	* VIA VT82C561 - early design, uses ata_generic currently
	11	* VIA VT82C576 - MWDMA, 33Mhz
	12	* VIA VT82C586 - MWDMA, 33Mhz
	13	* VIA VT82C586a - Added UDMA to 33Mhz
	14	* VIA VT82C586b - UDMA33
	15	* VIA VT82C596a - Nonfunctional UDMA66
	16	* VIA VT82C596b - Working UDMA66
	17	* VIA VT82C686 - Nonfunctional UDMA66
	18	* VIA VT82C686a - Working UDMA66
	19	* VIA VT82C686b - Updated to UDMA100
	20	* VIA VT8231 - UDMA100
	21	* VIA VT8233 - UDMA100
	22	* VIA VT8233a - UDMA133
	23	* VIA VT8233c - UDMA100
	24	* VIA VT8235 - UDMA133
	25	* VIA VT8237 - UDMA133
75f609d2	26	* VIA VT8251 - UDMA133
669a5db4 JG	27	*
	28	* Most registers remain compatible across chips. Others start reserved
	29	* and acquire sensible semantics if set to 1 (eg cable detect). A few
	30	* exceptions exist, notably around the FIFO settings.
	31	*
	32	* One additional quirk of the VIA design is that like ALi they use few
	33	* PCI IDs for a lot of chips.
	34	*
	35	* Based heavily on:
	36	*
	37	* Version 3.38
	38	*
	39	* VIA IDE driver for Linux. Supported southbridges:
	40	*
	41	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	42	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
	43	* vt8235, vt8237
	44	*
	45	* Copyright (c) 2000-2002 Vojtech Pavlik
	46	*
	47	* Based on the work of:
	48	* Michel Aubry
	49	* Jeff Garzik
	50	* Andre Hedrick
	51
	52	*/
	53
	54	#include <linux/kernel.h>
	55	#include <linux/module.h>
	56	#include <linux/pci.h>
	57	#include <linux/init.h>
	58	#include <linux/blkdev.h>
	59	#include <linux/delay.h>
	60	#include <scsi/scsi_host.h>
	61	#include <linux/libata.h>
	62
	63	#define DRV_NAME "pata_via"
627d2d32	64	#define DRV_VERSION "0.2.0"
669a5db4 JG	65
	66	/*
	67	* The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
	68	* driver.
	69	*/
	70
	71	enum {
	72	VIA_UDMA = 0x007,
	73	VIA_UDMA_NONE = 0x000,
	74	VIA_UDMA_33 = 0x001,
	75	VIA_UDMA_66 = 0x002,
	76	VIA_UDMA_100 = 0x003,
	77	VIA_UDMA_133 = 0x004,
	78	VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
	79	VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
	80	VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
	81	VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
	82	VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
	83	VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
	84	VIA_NO_ENABLES = 0x400, /* Has no enablebits */
	85	};
	86
	87	/*
	88	* VIA SouthBridge chips.
	89	*/
	90
	91	static const struct via_isa_bridge {
	92	const char *name;
	93	u16 id;
	94	u8 rev_min;
	95	u8 rev_max;
	96	u16 flags;
	97	} via_isa_bridges[] = {
e0b874df	98	{ "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
75f609d2	99	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
669a5db4 JG	100	{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	101	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST \| VIA_NO_ENABLES},
	102	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	103	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	104	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	105	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	106	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
	107	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
	108	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
	109	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
	110	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
	111	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 \| VIA_BAD_CLK66 },
	112	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
	113	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 \| VIA_BAD_CLK66 },
	114	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 \| VIA_SET_FIFO },
	115	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 \| VIA_SET_FIFO \| VIA_BAD_PREQ },
	116	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 \| VIA_SET_FIFO },
	117	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 \| VIA_SET_FIFO },
	118	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE \| VIA_SET_FIFO },
	119	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE \| VIA_SET_FIFO \| VIA_NO_UNMASK },
	120	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE \| VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
	121	{ NULL }
	122	};
	123
	124	/**
	125	* via_cable_detect - cable detection
	126	* @ap: ATA port
	127	*
	128	* Perform cable detection. Actually for the VIA case the BIOS
	129	* already did this for us. We read the values provided by the
	130	* BIOS. If you are using an 8235 in a non-PC configuration you
	131	* may need to update this code.
	132	*
	133	* Hotplug also impacts on this.
	134	*/
	135
	136	static int via_cable_detect(struct ata_port *ap) {
	137	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	138	u32 ata66;
	139
	140	pci_read_config_dword(pdev, 0x50, &ata66);
	141	/* Check both the drive cable reporting bits, we might not have
	142	two drives */
	143	if (ata66 & (0x10100000 >> (16 * ap->port_no)))
	144	return ATA_CBL_PATA80;
	145	else
	146	return ATA_CBL_PATA40;
	147	}
	148
	149	static int via_pre_reset(struct ata_port *ap)
	150	{
	151	const struct via_isa_bridge *config = ap->host->private_data;
	152
	153	if (!(config->flags & VIA_NO_ENABLES)) {
	154	static const struct pci_bits via_enable_bits[] = {
	155	{ 0x40, 1, 0x02, 0x02 },
	156	{ 0x40, 1, 0x01, 0x01 }
	157	};
	158
	159	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	160
c961922b AC	161	if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
c961922b AC	162	return -ENOENT;
669a5db4 JG	163	}
669a5db4 JG	164
5c9a7611	165	if ((config->flags & VIA_UDMA) >= VIA_UDMA_100)
669a5db4	166	ap->cbl = via_cable_detect(ap);
5c9a7611 AC	167	/* The UDMA66 series has no cable detect so do drive side detect */
5c9a7611 AC	168	else if ((config->flags & VIA_UDMA) < VIA_UDMA_66)
669a5db4	169	ap->cbl = ATA_CBL_PATA40;
5c9a7611 AC	170	else
	171	ap->cbl = ATA_CBL_PATA_UNK;
	172
	173
669a5db4 JG	174	return ata_std_prereset(ap);
	175	}
	176
	177
	178	/**
	179	* via_error_handler - reset for VIA chips
	180	* @ap: ATA port
	181	*
	182	* Handle the reset callback for the later chips with cable detect
	183	*/
	184
	185	static void via_error_handler(struct ata_port *ap)
	186	{
	187	ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	188	}
	189
	190	/**
	191	* via_do_set_mode - set initial PIO mode data
	192	* @ap: ATA interface
	193	* @adev: ATA device
	194	* @mode: ATA mode being programmed
	195	* @tdiv: Clocks per PCI clock
	196	* @set_ast: Set to program address setup
	197	* @udma_type: UDMA mode/format of registers
	198	*
	199	* Program the VIA registers for DMA and PIO modes. Uses the ata timing
	200	* support in order to compute modes.
	201	*
	202	* FIXME: Hotplug will require we serialize multiple mode changes
	203	* on the two channels.
	204	*/
	205
	206	static void via_do_set_mode(struct ata_port ap, struct ata_device adev, int mode, int tdiv, int set_ast, int udma_type)
	207	{
	208	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	209	struct ata_device *peer = ata_dev_pair(adev);
	210	struct ata_timing t, p;
	211	static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
	212	unsigned long T = 1000000000 / via_clock;
	213	unsigned long UT = T/tdiv;
	214	int ut;
	215	int offset = 3 - (2*ap->port_no) - adev->devno;
	216
	217
	218	/* Calculate the timing values we require */
	219	ata_timing_compute(adev, mode, &t, T, UT);
	220
	221	/* We share 8bit timing so we must merge the constraints */
	222	if (peer) {
	223	if (peer->pio_mode) {
	224	ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
	225	ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
	226	}
	227	}
	228
	229	/* Address setup is programmable but breaks on UDMA133 setups */
	230	if (set_ast) {
	231	u8 setup; /* 2 bits per drive */
	232	int shift = 2 * offset;
	233
	234	pci_read_config_byte(pdev, 0x4C, &setup);
	235	setup &= ~(3 << shift);
	236	setup \|= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
	237	pci_write_config_byte(pdev, 0x4C, setup);
238	}
239
240	/* Load the PIO mode bits */
241	pci_write_config_byte(pdev, 0x4F - ap->port_no,
242	((FIT(t.act8b, 1, 16) - 1) << 4) \| (FIT(t.rec8b, 1, 16) - 1));
243	pci_write_config_byte(pdev, 0x48 + offset,
244	((FIT(t.active, 1, 16) - 1) << 4) \| (FIT(t.recover, 1, 16) - 1));
245
246	/* Load the UDMA bits according to type */
247	switch(udma_type) {
248	default:
249	/* BUG() ? */
250	/* fall through */
251	case 33:
252	ut = t.udma ? (0xe0 \| (FIT(t.udma, 2, 5) - 2)) : 0x03;
253	break;
254	case 66:
255	ut = t.udma ? (0xe8 \| (FIT(t.udma, 2, 9) - 2)) : 0x0f;
256	break;
257	case 100:
258	ut = t.udma ? (0xe0 \| (FIT(t.udma, 2, 9) - 2)) : 0x07;
259	break;
260	case 133:
261	ut = t.udma ? (0xe0 \| (FIT(t.udma, 2, 9) - 2)) : 0x07;
262	break;
263	}
264	/* Set UDMA unless device is not UDMA capable */
265	if (udma_type)
266	pci_write_config_byte(pdev, 0x50 + offset, ut);
267	}
268
269	static void via_set_piomode(struct ata_port ap, struct ata_device adev)
270	{
271	const struct via_isa_bridge *config = ap->host->private_data;
272	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
273	int mode = config->flags & VIA_UDMA;
274	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
275	static u8 udma[5] = { 0, 33, 66, 100, 133 };
276
277	via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
278	}
279
280	static void via_set_dmamode(struct ata_port ap, struct ata_device adev)
281	{
282	const struct via_isa_bridge *config = ap->host->private_data;
283	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
284	int mode = config->flags & VIA_UDMA;
285	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
286	static u8 udma[5] = { 0, 33, 66, 100, 133 };
287
288	via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
289	}
290
291	static struct scsi_host_template via_sht = {
292	.module = THIS_MODULE,
293	.name = DRV_NAME,
294	.ioctl = ata_scsi_ioctl,
295	.queuecommand = ata_scsi_queuecmd,
296	.can_queue = ATA_DEF_QUEUE,
297	.this_id = ATA_SHT_THIS_ID,
298	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	299	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	300	.emulated = ATA_SHT_EMULATED,
	301	.use_clustering = ATA_SHT_USE_CLUSTERING,
	302	.proc_name = DRV_NAME,
	303	.dma_boundary = ATA_DMA_BOUNDARY,
	304	.slave_configure = ata_scsi_slave_config,
afdfe899	305	.slave_destroy = ata_scsi_slave_destroy,
669a5db4	306	.bios_param = ata_std_bios_param,
627d2d32 AC	307	.resume = ata_scsi_device_resume,
627d2d32 AC	308	.suspend = ata_scsi_device_suspend,
669a5db4 JG	309	};
	310
	311	static struct ata_port_operations via_port_ops = {
	312	.port_disable = ata_port_disable,
	313	.set_piomode = via_set_piomode,
	314	.set_dmamode = via_set_dmamode,
	315	.mode_filter = ata_pci_default_filter,
	316
	317	.tf_load = ata_tf_load,
	318	.tf_read = ata_tf_read,
	319	.check_status = ata_check_status,
	320	.exec_command = ata_exec_command,
	321	.dev_select = ata_std_dev_select,
	322
	323	.freeze = ata_bmdma_freeze,
	324	.thaw = ata_bmdma_thaw,
	325	.error_handler = via_error_handler,
	326	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	327
	328	.bmdma_setup = ata_bmdma_setup,
	329	.bmdma_start = ata_bmdma_start,
	330	.bmdma_stop = ata_bmdma_stop,
	331	.bmdma_status = ata_bmdma_status,
	332
	333	.qc_prep = ata_qc_prep,
	334	.qc_issue = ata_qc_issue_prot,
bda30288	335
669a5db4 JG	336	.data_xfer = ata_pio_data_xfer,
	337
	338	.irq_handler = ata_interrupt,
	339	.irq_clear = ata_bmdma_irq_clear,
	340
	341	.port_start = ata_port_start,
	342	.port_stop = ata_port_stop,
	343	.host_stop = ata_host_stop
	344	};
	345
	346	static struct ata_port_operations via_port_ops_noirq = {
	347	.port_disable = ata_port_disable,
	348	.set_piomode = via_set_piomode,
	349	.set_dmamode = via_set_dmamode,
	350	.mode_filter = ata_pci_default_filter,
	351
	352	.tf_load = ata_tf_load,
	353	.tf_read = ata_tf_read,
	354	.check_status = ata_check_status,
	355	.exec_command = ata_exec_command,
	356	.dev_select = ata_std_dev_select,
	357
	358	.freeze = ata_bmdma_freeze,
	359	.thaw = ata_bmdma_thaw,
	360	.error_handler = via_error_handler,
	361	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	362
	363	.bmdma_setup = ata_bmdma_setup,
	364	.bmdma_start = ata_bmdma_start,
	365	.bmdma_stop = ata_bmdma_stop,
	366	.bmdma_status = ata_bmdma_status,
	367
	368	.qc_prep = ata_qc_prep,
	369	.qc_issue = ata_qc_issue_prot,
bda30288	370
669a5db4 JG	371	.data_xfer = ata_pio_data_xfer_noirq,
	372
	373	.irq_handler = ata_interrupt,
	374	.irq_clear = ata_bmdma_irq_clear,
	375
	376	.port_start = ata_port_start,
	377	.port_stop = ata_port_stop,
	378	.host_stop = ata_host_stop
	379	};
	380
627d2d32 AC	381	/**
	382	* via_config_fifo - set up the FIFO
	383	* @pdev: PCI device
	384	* @flags: configuration flags
	385	*
	386	* Set the FIFO properties for this device if neccessary. Used both on
	387	* set up and on and the resume path
	388	*/
	389
	390	static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
	391	{
	392	u8 enable;
	393
	394	/* 0x40 low bits indicate enabled channels */
	395	pci_read_config_byte(pdev, 0x40 , &enable);
	396	enable &= 3;
	397
	398	if (flags & VIA_SET_FIFO) {
73720861	399	static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
627d2d32 AC	400	u8 fifo;
	401
	402	pci_read_config_byte(pdev, 0x43, &fifo);
	403
	404	/* Clear PREQ# until DDACK# for errata */
	405	if (flags & VIA_BAD_PREQ)
	406	fifo &= 0x7F;
	407	else
	408	fifo &= 0x9f;
	409	/* Turn on FIFO for enabled channels */
	410	fifo \|= fifo_setting[enable];
	411	pci_write_config_byte(pdev, 0x43, fifo);
	412	}
	413	}
	414
669a5db4 JG	415	/**
669a5db4 JG	416	* via_init_one - discovery callback
627d2d32	417	* @pdev: PCI device
669a5db4 JG	418	* @id: PCI table info
	419	*
	420	* A VIA IDE interface has been discovered. Figure out what revision
	421	* and perform configuration work before handing it to the ATA layer
	422	*/
	423
	424	static int via_init_one(struct pci_dev pdev, const struct pci_device_id id)
	425	{
	426	/* Early VIA without UDMA support */
	427	static struct ata_port_info via_mwdma_info = {
	428	.sht = &via_sht,
3d3cca37	429	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SETXFER_POLLING,
669a5db4 JG	430	.pio_mask = 0x1f,
	431	.mwdma_mask = 0x07,
	432	.port_ops = &via_port_ops
	433	};
	434	/* Ditto with IRQ masking required */
	435	static struct ata_port_info via_mwdma_info_borked = {
	436	.sht = &via_sht,
3d3cca37	437	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SETXFER_POLLING,
669a5db4 JG	438	.pio_mask = 0x1f,
	439	.mwdma_mask = 0x07,
	440	.port_ops = &via_port_ops_noirq,
	441	};
	442	/* VIA UDMA 33 devices (and borked 66) */
	443	static struct ata_port_info via_udma33_info = {
	444	.sht = &via_sht,
3d3cca37	445	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SETXFER_POLLING,
669a5db4 JG	446	.pio_mask = 0x1f,
	447	.mwdma_mask = 0x07,
	448	.udma_mask = 0x7,
	449	.port_ops = &via_port_ops
	450	};
	451	/* VIA UDMA 66 devices */
	452	static struct ata_port_info via_udma66_info = {
	453	.sht = &via_sht,
3d3cca37	454	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SETXFER_POLLING,
669a5db4 JG	455	.pio_mask = 0x1f,
	456	.mwdma_mask = 0x07,
	457	.udma_mask = 0x1f,
	458	.port_ops = &via_port_ops
	459	};
	460	/* VIA UDMA 100 devices */
	461	static struct ata_port_info via_udma100_info = {
	462	.sht = &via_sht,
3d3cca37	463	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SETXFER_POLLING,
669a5db4 JG	464	.pio_mask = 0x1f,
	465	.mwdma_mask = 0x07,
	466	.udma_mask = 0x3f,
	467	.port_ops = &via_port_ops
	468	};
	469	/* UDMA133 with bad AST (All current 133) */
	470	static struct ata_port_info via_udma133_info = {
	471	.sht = &via_sht,
3d3cca37	472	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SETXFER_POLLING,
669a5db4 JG	473	.pio_mask = 0x1f,
	474	.mwdma_mask = 0x07,
	475	.udma_mask = 0x7f, /* FIXME: should check north bridge */
	476	.port_ops = &via_port_ops
	477	};
	478	struct ata_port_info port_info[2], type;
	479	struct pci_dev *isa = NULL;
	480	const struct via_isa_bridge *config;
	481	static int printed_version;
	482	u8 t;
	483	u8 enable;
	484	u32 timing;
	485
	486	if (!printed_version++)
	487	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	488
	489	/* To find out how the IDE will behave and what features we
	490	actually have to look at the bridge not the IDE controller */
	491	for (config = via_isa_bridges; config->id; config++)
	492	if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
	493	!!(config->flags & VIA_BAD_ID),
	494	config->id, NULL))) {
	495
	496	pci_read_config_byte(isa, PCI_REVISION_ID, &t);
	497	if (t >= config->rev_min &&
	498	t <= config->rev_max)
	499	break;
	500	pci_dev_put(isa);
	501	}
	502
	503	if (!config->id) {
	504	printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
	505	return -ENODEV;
	506	}
	507	pci_dev_put(isa);
	508
	509	/* 0x40 low bits indicate enabled channels */
	510	pci_read_config_byte(pdev, 0x40 , &enable);
	511	enable &= 3;
	512	if (enable == 0) {
	513	return -ENODEV;
	514	}
	515
	516	/* Initialise the FIFO for the enabled channels. */
627d2d32 AC	517	via_config_fifo(pdev, config->flags);
627d2d32 AC	518
669a5db4 JG	519	/* Clock set up */
	520	switch(config->flags & VIA_UDMA) {
	521	case VIA_UDMA_NONE:
	522	if (config->flags & VIA_NO_UNMASK)
	523	type = &via_mwdma_info_borked;
	524	else
	525	type = &via_mwdma_info;
	526	break;
	527	case VIA_UDMA_33:
	528	type = &via_udma33_info;
	529	break;
	530	case VIA_UDMA_66:
	531	type = &via_udma66_info;
	532	/* The 66 MHz devices require we enable the clock */
	533	pci_read_config_dword(pdev, 0x50, &timing);
	534	timing \|= 0x80008;
	535	pci_write_config_dword(pdev, 0x50, timing);
	536	break;
	537	case VIA_UDMA_100:
	538	type = &via_udma100_info;
	539	break;
	540	case VIA_UDMA_133:
	541	type = &via_udma133_info;
	542	break;
	543	default:
	544	WARN_ON(1);
	545	return -ENODEV;
	546	}
	547
	548	if (config->flags & VIA_BAD_CLK66) {
	549	/* Disable the 66MHz clock on problem devices */
	550	pci_read_config_dword(pdev, 0x50, &timing);
	551	timing &= ~0x80008;
	552	pci_write_config_dword(pdev, 0x50, timing);
	553	}
	554
	555	/* We have established the device type, now fire it up */
	556	type->private_data = (void *)config;
	557
	558	port_info[0] = port_info[1] = type;
	559	return ata_pci_init_one(pdev, port_info, 2);
	560	}
	561
627d2d32 AC	562	/**
	563	* via_reinit_one - reinit after resume
	564	* @pdev; PCI device
	565	*
	566	* Called when the VIA PATA device is resumed. We must then
	567	* reconfigure the fifo and other setup we may have altered. In
	568	* addition the kernel needs to have the resume methods on PCI
	569	* quirk supported.
	570	*/
	571
	572	static int via_reinit_one(struct pci_dev *pdev)
	573	{
	574	u32 timing;
	575	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	576	const struct via_isa_bridge *config = host->private_data;
	577
	578	via_config_fifo(pdev, config->flags);
	579
	580	if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
	581	/* The 66 MHz devices require we enable the clock */
	582	pci_read_config_dword(pdev, 0x50, &timing);
	583	timing \|= 0x80008;
	584	pci_write_config_dword(pdev, 0x50, timing);
	585	}
	586	if (config->flags & VIA_BAD_CLK66) {
	587	/* Disable the 66MHz clock on problem devices */
	588	pci_read_config_dword(pdev, 0x50, &timing);
	589	timing &= ~0x80008;
	590	pci_write_config_dword(pdev, 0x50, timing);
	591	}
	592	return ata_pci_device_resume(pdev);
	593	}
	594
669a5db4	595	static const struct pci_device_id via[] = {
2d2744fc JG	596	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), },
	597	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), },
	598	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), },
	599	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },
	600
	601	{ },
669a5db4 JG	602	};
	603
	604	static struct pci_driver via_pci_driver = {
2d2744fc	605	.name = DRV_NAME,
669a5db4 JG	606	.id_table = via,
669a5db4 JG	607	.probe = via_init_one,
627d2d32 AC	608	.remove = ata_pci_remove_one,
	609	.suspend = ata_pci_device_suspend,
	610	.resume = via_reinit_one,
669a5db4 JG	611	};
	612
	613	static int __init via_init(void)
	614	{
	615	return pci_register_driver(&via_pci_driver);
	616	}
	617
669a5db4 JG	618	static void __exit via_exit(void)
	619	{
	620	pci_unregister_driver(&via_pci_driver);
	621	}
	622
669a5db4 JG	623	MODULE_AUTHOR("Alan Cox");
	624	MODULE_DESCRIPTION("low-level driver for VIA PATA");
	625	MODULE_LICENSE("GPL");
	626	MODULE_DEVICE_TABLE(pci, via);
	627	MODULE_VERSION(DRV_VERSION);
	628
	629	module_init(via_init);
	630	module_exit(via_exit);