[mirror_ubuntu-zesty-kernel.git] / drivers / ata / pata_via.c

/*
 * pata_via.c 	- VIA PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 *  Documentation
 *	Most chipset documentation available under NDA only
 *
 *  VIA version guide
 *	VIA VT82C561	-	early design, uses ata_generic currently
 *	VIA VT82C576	-	MWDMA, 33Mhz
 *	VIA VT82C586	-	MWDMA, 33Mhz
 *	VIA VT82C586a	-	Added UDMA to 33Mhz
 *	VIA VT82C586b	-	UDMA33
 *	VIA VT82C596a	-	Nonfunctional UDMA66
 *	VIA VT82C596b	-	Working UDMA66
 *	VIA VT82C686	-	Nonfunctional UDMA66
 *	VIA VT82C686a	-	Working UDMA66
 *	VIA VT82C686b	-	Updated to UDMA100
 *	VIA VT8231	-	UDMA100
 *	VIA VT8233	-	UDMA100
 *	VIA VT8233a	-	UDMA133
 *	VIA VT8233c	-	UDMA100
 *	VIA VT8235	-	UDMA133
 *	VIA VT8237	-	UDMA133
 *	VIA VT8237S	-	UDMA133
 *	VIA VT8251	-	UDMA133
 *
 *	Most registers remain compatible across chips. Others start reserved
 *	and acquire sensible semantics if set to 1 (eg cable detect). A few
 *	exceptions exist, notably around the FIFO settings.
 *
 *	One additional quirk of the VIA design is that like ALi they use few
 *	PCI IDs for a lot of chips.
 *
 *	Based heavily on:
 *
 * Version 3.38
 *
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick

 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/dmi.h>

#define DRV_NAME "pata_via"
#define DRV_VERSION "0.3.3"

/*
 *	The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
 *	driver.
 */

enum {
	VIA_UDMA	= 0x007,
	VIA_UDMA_NONE	= 0x000,
	VIA_UDMA_33	= 0x001,
	VIA_UDMA_66	= 0x002,
	VIA_UDMA_100	= 0x003,
	VIA_UDMA_133	= 0x004,
	VIA_BAD_PREQ	= 0x010, /* Crashes if PREQ# till DDACK# set */
	VIA_BAD_CLK66	= 0x020, /* 66 MHz clock doesn't work correctly */
	VIA_SET_FIFO	= 0x040, /* Needs to have FIFO split set */
	VIA_NO_UNMASK	= 0x080, /* Doesn't work with IRQ unmasking on */
	VIA_BAD_ID	= 0x100, /* Has wrong vendor ID (0x1107) */
	VIA_BAD_AST	= 0x200, /* Don't touch Address Setup Timing */
	VIA_NO_ENABLES	= 0x400, /* Has no enablebits */
	VIA_SATA_PATA	= 0x800, /* SATA/PATA combined configuration */
};

/*
 * VIA SouthBridge chips.
 */

static const struct via_isa_bridge {
	const char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u16 flags;
} via_isa_bridges[] = {
	{ "vx800",	PCI_DEVICE_ID_VIA_VX800,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8237s",	PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA },
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, VIA_UDMA_100 },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, VIA_UDMA_100 },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, VIA_UDMA_100 },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, VIA_UDMA_100 },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, VIA_UDMA_66 },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, VIA_UDMA_66 },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ NULL }
};


/*
 *	Cable special cases
 */

static const struct dmi_system_id cable_dmi_table[] = {
	{
		.ident = "Acer Ferrari 3400",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
		},
	},
	{ }
};

static int via_cable_override(struct pci_dev *pdev)
{
	/* Systems by DMI */
	if (dmi_check_system(cable_dmi_table))
		return 1;
	/* Arima W730-K8/Targa Visionary 811/... */
	if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)
		return 1;
	return 0;
}


/**
 *	via_cable_detect	-	cable detection
 *	@ap: ATA port
 *
 *	Perform cable detection. Actually for the VIA case the BIOS
 *	already did this for us. We read the values provided by the
 *	BIOS. If you are using an 8235 in a non-PC configuration you
 *	may need to update this code.
 *
 *	Hotplug also impacts on this.
 */

static int via_cable_detect(struct ata_port *ap) {
	const struct via_isa_bridge *config = ap->host->private_data;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 ata66;

	if (via_cable_override(pdev))
		return ATA_CBL_PATA40_SHORT;

	if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0)
		return ATA_CBL_SATA;

	/* Early chips are 40 wire */
	if ((config->flags & VIA_UDMA) < VIA_UDMA_66)
		return ATA_CBL_PATA40;
	/* UDMA 66 chips have only drive side logic */
	else if ((config->flags & VIA_UDMA) < VIA_UDMA_100)
		return ATA_CBL_PATA_UNK;
	/* UDMA 100 or later */
	pci_read_config_dword(pdev, 0x50, &ata66);
	/* Check both the drive cable reporting bits, we might not have
	   two drives */
	if (ata66 & (0x10100000 >> (16 * ap->port_no)))
		return ATA_CBL_PATA80;
	/* Check with ACPI so we can spot BIOS reported SATA bridges */
	if (ata_acpi_init_gtm(ap) &&
	    ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

static int via_pre_reset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	const struct via_isa_bridge *config = ap->host->private_data;

	if (!(config->flags & VIA_NO_ENABLES)) {
		static const struct pci_bits via_enable_bits[] = {
			{ 0x40, 1, 0x02, 0x02 },
			{ 0x40, 1, 0x01, 0x01 }
		};
		struct pci_dev *pdev = to_pci_dev(ap->host->dev);
		if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
			return -ENOENT;
	}

	return ata_sff_prereset(link, deadline);
}


/**
 *	via_do_set_mode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: ATA mode being programmed
 *	@tdiv: Clocks per PCI clock
 *	@set_ast: Set to program address setup
 *	@udma_type: UDMA mode/format of registers
 *
 *	Program the VIA registers for DMA and PIO modes. Uses the ata timing
 *	support in order to compute modes.
 *
 *	FIXME: Hotplug will require we serialize multiple mode changes
 *	on the two channels.
 */

static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_device *peer = ata_dev_pair(adev);
	struct ata_timing t, p;
	static int via_clock = 33333;	/* Bus clock in kHZ - ought to be tunable one day */
	unsigned long T =  1000000000 / via_clock;
	unsigned long UT = T/tdiv;
	int ut;
	int offset = 3 - (2*ap->port_no) - adev->devno;

	/* Calculate the timing values we require */
	ata_timing_compute(adev, mode, &t, T, UT);

	/* We share 8bit timing so we must merge the constraints */
	if (peer) {
		if (peer->pio_mode) {
			ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
			ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
		}
	}

	/* Address setup is programmable but breaks on UDMA133 setups */
	if (set_ast) {
		u8 setup;	/* 2 bits per drive */
		int shift = 2 * offset;

		pci_read_config_byte(pdev, 0x4C, &setup);
		setup &= ~(3 << shift);
		setup |= clamp_val(t.setup, 1, 4) << shift;	/* 1,4 or 1,4 - 1  FIXME */
		pci_write_config_byte(pdev, 0x4C, setup);
	}

	/* Load the PIO mode bits */
	pci_write_config_byte(pdev, 0x4F - ap->port_no,
		((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1));
	pci_write_config_byte(pdev, 0x48 + offset,
		((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1));

	/* Load the UDMA bits according to type */
	switch(udma_type) {
		default:
			/* BUG() ? */
			/* fall through */
		case 33:
			ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03;
			break;
		case 66:
			ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;
			break;
		case 100:
			ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
			break;
		case 133:
			ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
			break;
	}

	/* Set UDMA unless device is not UDMA capable */
	if (udma_type && t.udma) {
		u8 cable80_status;

		/* Get 80-wire cable detection bit */
		pci_read_config_byte(pdev, 0x50 + offset, &cable80_status);
		cable80_status &= 0x10;

		pci_write_config_byte(pdev, 0x50 + offset, ut | cable80_status);
	}
}

static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	const struct via_isa_bridge *config = ap->host->private_data;
	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
	int mode = config->flags & VIA_UDMA;
	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
	static u8 udma[5] = { 0, 33, 66, 100, 133 };

	via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
}

static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	const struct via_isa_bridge *config = ap->host->private_data;
	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
	int mode = config->flags & VIA_UDMA;
	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
	static u8 udma[5] = { 0, 33, 66, 100, 133 };

	via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
}

static struct scsi_host_template via_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations via_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= via_cable_detect,
	.set_piomode	= via_set_piomode,
	.set_dmamode	= via_set_dmamode,
	.prereset	= via_pre_reset,
};

static struct ata_port_operations via_port_ops_noirq = {
	.inherits	= &via_port_ops,
	.sff_data_xfer	= ata_sff_data_xfer_noirq,
};

/**
 *	via_config_fifo		-	set up the FIFO
 *	@pdev: PCI device
 *	@flags: configuration flags
 *
 *	Set the FIFO properties for this device if necessary. Used both on
 *	set up and on and the resume path
 */

static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
{
	u8 enable;

	/* 0x40 low bits indicate enabled channels */
	pci_read_config_byte(pdev, 0x40 , &enable);
	enable &= 3;

	if (flags & VIA_SET_FIFO) {
		static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
		u8 fifo;

		pci_read_config_byte(pdev, 0x43, &fifo);

		/* Clear PREQ# until DDACK# for errata */
		if (flags & VIA_BAD_PREQ)
			fifo &= 0x7F;
		else
			fifo &= 0x9f;
		/* Turn on FIFO for enabled channels */
		fifo |= fifo_setting[enable];
		pci_write_config_byte(pdev, 0x43, fifo);
	}
}

/**
 *	via_init_one		-	discovery callback
 *	@pdev: PCI device
 *	@id: PCI table info
 *
 *	A VIA IDE interface has been discovered. Figure out what revision
 *	and perform configuration work before handing it to the ATA layer
 */

static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	/* Early VIA without UDMA support */
	static const struct ata_port_info via_mwdma_info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &via_port_ops
	};
	/* Ditto with IRQ masking required */
	static const struct ata_port_info via_mwdma_info_borked = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &via_port_ops_noirq,
	};
	/* VIA UDMA 33 devices (and borked 66) */
	static const struct ata_port_info via_udma33_info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = ATA_UDMA2,
		.port_ops = &via_port_ops
	};
	/* VIA UDMA 66 devices */
	static const struct ata_port_info via_udma66_info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = ATA_UDMA4,
		.port_ops = &via_port_ops
	};
	/* VIA UDMA 100 devices */
	static const struct ata_port_info via_udma100_info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = ATA_UDMA5,
		.port_ops = &via_port_ops
	};
	/* UDMA133 with bad AST (All current 133) */
	static const struct ata_port_info via_udma133_info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = ATA_UDMA6,	/* FIXME: should check north bridge */
		.port_ops = &via_port_ops
	};
	const struct ata_port_info *ppi[] = { NULL, NULL };
	struct pci_dev *isa = NULL;
	const struct via_isa_bridge *config;
	static int printed_version;
	u8 enable;
	u32 timing;
	int rc;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* To find out how the IDE will behave and what features we
	   actually have to look at the bridge not the IDE controller */
	for (config = via_isa_bridges; config->id; config++)
		if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(config->flags & VIA_BAD_ID),
			config->id, NULL))) {

			if (isa->revision >= config->rev_min &&
			    isa->revision <= config->rev_max)
				break;
			pci_dev_put(isa);
		}

	if (!config->id) {
		printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
		return -ENODEV;
	}
	pci_dev_put(isa);

	if (!(config->flags & VIA_NO_ENABLES)) {
		/* 0x40 low bits indicate enabled channels */
		pci_read_config_byte(pdev, 0x40 , &enable);
		enable &= 3;
		if (enable == 0)
			return -ENODEV;
	}

	/* Initialise the FIFO for the enabled channels. */
	via_config_fifo(pdev, config->flags);

	/* Clock set up */
	switch(config->flags & VIA_UDMA) {
		case VIA_UDMA_NONE:
			if (config->flags & VIA_NO_UNMASK)
				ppi[0] = &via_mwdma_info_borked;
			else
				ppi[0] = &via_mwdma_info;
			break;
		case VIA_UDMA_33:
			ppi[0] = &via_udma33_info;
			break;
		case VIA_UDMA_66:
			ppi[0] = &via_udma66_info;
			/* The 66 MHz devices require we enable the clock */
			pci_read_config_dword(pdev, 0x50, &timing);
			timing |= 0x80008;
			pci_write_config_dword(pdev, 0x50, timing);
			break;
		case VIA_UDMA_100:
			ppi[0] = &via_udma100_info;
			break;
		case VIA_UDMA_133:
			ppi[0] = &via_udma133_info;
			break;
		default:
			WARN_ON(1);
			return -ENODEV;
	}

	if (config->flags & VIA_BAD_CLK66) {
		/* Disable the 66MHz clock on problem devices */
		pci_read_config_dword(pdev, 0x50, &timing);
		timing &= ~0x80008;
		pci_write_config_dword(pdev, 0x50, timing);
	}

	/* We have established the device type, now fire it up */
	return ata_pci_sff_init_one(pdev, ppi, &via_sht, (void *)config);
}

#ifdef CONFIG_PM
/**
 *	via_reinit_one		-	reinit after resume
 *	@pdev; PCI device
 *
 *	Called when the VIA PATA device is resumed. We must then
 *	reconfigure the fifo and other setup we may have altered. In
 *	addition the kernel needs to have the resume methods on PCI
 *	quirk supported.
 */

static int via_reinit_one(struct pci_dev *pdev)
{
	u32 timing;
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	const struct via_isa_bridge *config = host->private_data;
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	via_config_fifo(pdev, config->flags);

	if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
		/* The 66 MHz devices require we enable the clock */
		pci_read_config_dword(pdev, 0x50, &timing);
		timing |= 0x80008;
		pci_write_config_dword(pdev, 0x50, timing);
	}
	if (config->flags & VIA_BAD_CLK66) {
		/* Disable the 66MHz clock on problem devices */
		pci_read_config_dword(pdev, 0x50, &timing);
		timing &= ~0x80008;
		pci_write_config_dword(pdev, 0x50, timing);
	}

	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id via[] = {
	{ PCI_VDEVICE(VIA, 0x0571), },
	{ PCI_VDEVICE(VIA, 0x0581), },
	{ PCI_VDEVICE(VIA, 0x1571), },
	{ PCI_VDEVICE(VIA, 0x3164), },
	{ PCI_VDEVICE(VIA, 0x5324), },

	{ },
};

static struct pci_driver via_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= via,
	.probe 		= via_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= via_reinit_one,
#endif
};

static int __init via_init(void)
{
	return pci_register_driver(&via_pci_driver);
}

static void __exit via_exit(void)
{
	pci_unregister_driver(&via_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for VIA PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, via);
MODULE_VERSION(DRV_VERSION);

module_init(via_init);
module_exit(via_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_via.c - VIA PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* Documentation
	7	* Most chipset documentation available under NDA only
	8	*
	9	* VIA version guide
	10	* VIA VT82C561 - early design, uses ata_generic currently
	11	* VIA VT82C576 - MWDMA, 33Mhz
	12	* VIA VT82C586 - MWDMA, 33Mhz
	13	* VIA VT82C586a - Added UDMA to 33Mhz
	14	* VIA VT82C586b - UDMA33
	15	* VIA VT82C596a - Nonfunctional UDMA66
	16	* VIA VT82C596b - Working UDMA66
	17	* VIA VT82C686 - Nonfunctional UDMA66
	18	* VIA VT82C686a - Working UDMA66
	19	* VIA VT82C686b - Updated to UDMA100
	20	* VIA VT8231 - UDMA100
	21	* VIA VT8233 - UDMA100
	22	* VIA VT8233a - UDMA133
	23	* VIA VT8233c - UDMA100
	24	* VIA VT8235 - UDMA133
	25	* VIA VT8237 - UDMA133
05c39e50	26	* VIA VT8237S - UDMA133
75f609d2	27	* VIA VT8251 - UDMA133
669a5db4 JG	28	*
	29	* Most registers remain compatible across chips. Others start reserved
	30	* and acquire sensible semantics if set to 1 (eg cable detect). A few
	31	* exceptions exist, notably around the FIFO settings.
	32	*
	33	* One additional quirk of the VIA design is that like ALi they use few
	34	* PCI IDs for a lot of chips.
	35	*
	36	* Based heavily on:
	37	*
	38	* Version 3.38
	39	*
	40	* VIA IDE driver for Linux. Supported southbridges:
	41	*
	42	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	43	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
	44	* vt8235, vt8237
	45	*
	46	* Copyright (c) 2000-2002 Vojtech Pavlik
	47	*
	48	* Based on the work of:
	49	* Michel Aubry
	50	* Jeff Garzik
	51	* Andre Hedrick
	52
	53	*/
	54
	55	#include <linux/kernel.h>
	56	#include <linux/module.h>
	57	#include <linux/pci.h>
	58	#include <linux/init.h>
	59	#include <linux/blkdev.h>
	60	#include <linux/delay.h>
	61	#include <scsi/scsi_host.h>
	62	#include <linux/libata.h>
cf5792d2	63	#include <linux/dmi.h>
669a5db4 JG	64
669a5db4 JG	65	#define DRV_NAME "pata_via"
943547ab	66	#define DRV_VERSION "0.3.3"
669a5db4 JG	67
	68	/*
	69	* The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
	70	* driver.
	71	*/
	72
	73	enum {
	74	VIA_UDMA = 0x007,
	75	VIA_UDMA_NONE = 0x000,
	76	VIA_UDMA_33 = 0x001,
	77	VIA_UDMA_66 = 0x002,
	78	VIA_UDMA_100 = 0x003,
	79	VIA_UDMA_133 = 0x004,
	80	VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
	81	VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
	82	VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
	83	VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
	84	VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
	85	VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
	86	VIA_NO_ENABLES = 0x400, /* Has no enablebits */
7585eb1b	87	VIA_SATA_PATA = 0x800, /* SATA/PATA combined configuration */
669a5db4 JG	88	};
	89
	90	/*
	91	* VIA SouthBridge chips.
	92	*/
	93
	94	static const struct via_isa_bridge {
	95	const char *name;
	96	u16 id;
	97	u8 rev_min;
	98	u8 rev_max;
	99	u16 flags;
	100	} via_isa_bridges[] = {
b311ec4a	101	{ "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
e0b874df	102	{ "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
75f609d2	103	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
7585eb1b	104	{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST \| VIA_SATA_PATA },
669a5db4 JG	105	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST \| VIA_NO_ENABLES},
	106	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	107	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	108	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	109	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	110	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
	111	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
	112	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
	113	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
	114	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
	115	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 \| VIA_BAD_CLK66 },
	116	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
	117	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 \| VIA_BAD_CLK66 },
	118	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 \| VIA_SET_FIFO },
	119	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 \| VIA_SET_FIFO \| VIA_BAD_PREQ },
	120	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 \| VIA_SET_FIFO },
	121	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 \| VIA_SET_FIFO },
	122	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE \| VIA_SET_FIFO },
	123	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE \| VIA_SET_FIFO \| VIA_NO_UNMASK },
	124	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE \| VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
	125	{ NULL }
	126	};
	127
cf5792d2 AC	128
	129	/*
	130	* Cable special cases
	131	*/
	132
1855256c	133	static const struct dmi_system_id cable_dmi_table[] = {
cf5792d2 AC	134	{
	135	.ident = "Acer Ferrari 3400",
	136	.matches = {
	137	DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
	138	DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
	139	},
	140	},
	141	{ }
	142	};
	143
	144	static int via_cable_override(struct pci_dev *pdev)
	145	{
	146	/* Systems by DMI */
	147	if (dmi_check_system(cable_dmi_table))
	148	return 1;
9edbdbea AC	149	/* Arima W730-K8/Targa Visionary 811/... */
	150	if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)
	151	return 1;
cf5792d2 AC	152	return 0;
	153	}
	154
	155
669a5db4 JG	156	/**
	157	* via_cable_detect - cable detection
	158	* @ap: ATA port
	159	*
	160	* Perform cable detection. Actually for the VIA case the BIOS
	161	* already did this for us. We read the values provided by the
	162	* BIOS. If you are using an 8235 in a non-PC configuration you
	163	* may need to update this code.
	164	*
	165	* Hotplug also impacts on this.
	166	*/
	167
	168	static int via_cable_detect(struct ata_port *ap) {
97cb81c3	169	const struct via_isa_bridge *config = ap->host->private_data;
669a5db4 JG	170	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	171	u32 ata66;
	172
cf5792d2 AC	173	if (via_cable_override(pdev))
	174	return ATA_CBL_PATA40_SHORT;
	175
7585eb1b TH	176	if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0)
	177	return ATA_CBL_SATA;
	178
97cb81c3 AC	179	/* Early chips are 40 wire */
	180	if ((config->flags & VIA_UDMA) < VIA_UDMA_66)
	181	return ATA_CBL_PATA40;
	182	/* UDMA 66 chips have only drive side logic */
b447916e	183	else if ((config->flags & VIA_UDMA) < VIA_UDMA_100)
97cb81c3 AC	184	return ATA_CBL_PATA_UNK;
97cb81c3 AC	185	/* UDMA 100 or later */
669a5db4 JG	186	pci_read_config_dword(pdev, 0x50, &ata66);
	187	/* Check both the drive cable reporting bits, we might not have
	188	two drives */
	189	if (ata66 & (0x10100000 >> (16 * ap->port_no)))
	190	return ATA_CBL_PATA80;
7d73a363	191	/* Check with ACPI so we can spot BIOS reported SATA bridges */
021ee9a6 TH	192	if (ata_acpi_init_gtm(ap) &&
021ee9a6 TH	193	ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))
7d73a363	194	return ATA_CBL_PATA80;
97cb81c3	195	return ATA_CBL_PATA40;
669a5db4 JG	196	}
669a5db4 JG	197
cc0680a5	198	static int via_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	199	{
cc0680a5	200	struct ata_port *ap = link->ap;
669a5db4 JG	201	const struct via_isa_bridge *config = ap->host->private_data;
	202
	203	if (!(config->flags & VIA_NO_ENABLES)) {
	204	static const struct pci_bits via_enable_bits[] = {
	205	{ 0x40, 1, 0x02, 0x02 },
	206	{ 0x40, 1, 0x01, 0x01 }
	207	};
669a5db4	208	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
c961922b AC	209	if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
c961922b AC	210	return -ENOENT;
669a5db4	211	}
d4b2bab4	212
9363c382	213	return ata_sff_prereset(link, deadline);
669a5db4 JG	214	}
	215
	216
669a5db4 JG	217	/**
	218	* via_do_set_mode - set initial PIO mode data
	219	* @ap: ATA interface
	220	* @adev: ATA device
	221	* @mode: ATA mode being programmed
	222	* @tdiv: Clocks per PCI clock
	223	* @set_ast: Set to program address setup
	224	* @udma_type: UDMA mode/format of registers
	225	*
	226	* Program the VIA registers for DMA and PIO modes. Uses the ata timing
	227	* support in order to compute modes.
	228	*
	229	* FIXME: Hotplug will require we serialize multiple mode changes
	230	* on the two channels.
	231	*/
	232
	233	static void via_do_set_mode(struct ata_port ap, struct ata_device adev, int mode, int tdiv, int set_ast, int udma_type)
	234	{
	235	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	236	struct ata_device *peer = ata_dev_pair(adev);
	237	struct ata_timing t, p;
	238	static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
	239	unsigned long T = 1000000000 / via_clock;
	240	unsigned long UT = T/tdiv;
	241	int ut;
	242	int offset = 3 - (2*ap->port_no) - adev->devno;
	243
669a5db4 JG	244	/* Calculate the timing values we require */
	245	ata_timing_compute(adev, mode, &t, T, UT);
	246
	247	/* We share 8bit timing so we must merge the constraints */
	248	if (peer) {
	249	if (peer->pio_mode) {
	250	ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
	251	ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
	252	}
	253	}
	254
	255	/* Address setup is programmable but breaks on UDMA133 setups */
	256	if (set_ast) {
	257	u8 setup; /* 2 bits per drive */
	258	int shift = 2 * offset;
	259
	260	pci_read_config_byte(pdev, 0x4C, &setup);
	261	setup &= ~(3 << shift);
07633b5d	262	setup \|= clamp_val(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
669a5db4 JG	263	pci_write_config_byte(pdev, 0x4C, setup);
	264	}
	265
	266	/* Load the PIO mode bits */
	267	pci_write_config_byte(pdev, 0x4F - ap->port_no,
07633b5d	268	((clamp_val(t.act8b, 1, 16) - 1) << 4) \| (clamp_val(t.rec8b, 1, 16) - 1));
669a5db4	269	pci_write_config_byte(pdev, 0x48 + offset,
07633b5d	270	((clamp_val(t.active, 1, 16) - 1) << 4) \| (clamp_val(t.recover, 1, 16) - 1));
669a5db4 JG	271
	272	/* Load the UDMA bits according to type */
	273	switch(udma_type) {
	274	default:
	275	/* BUG() ? */
	276	/* fall through */
	277	case 33:
07633b5d	278	ut = t.udma ? (0xe0 \| (clamp_val(t.udma, 2, 5) - 2)) : 0x03;
669a5db4 JG	279	break;
669a5db4 JG	280	case 66:
07633b5d	281	ut = t.udma ? (0xe8 \| (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;
669a5db4 JG	282	break;
669a5db4 JG	283	case 100:
07633b5d	284	ut = t.udma ? (0xe0 \| (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
669a5db4 JG	285	break;
669a5db4 JG	286	case 133:
07633b5d	287	ut = t.udma ? (0xe0 \| (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
669a5db4 JG	288	break;
669a5db4 JG	289	}
08ebd43d	290
669a5db4	291	/* Set UDMA unless device is not UDMA capable */
943547ab	292	if (udma_type && t.udma) {
08ebd43d LR	293	u8 cable80_status;
	294
	295	/* Get 80-wire cable detection bit */
	296	pci_read_config_byte(pdev, 0x50 + offset, &cable80_status);
	297	cable80_status &= 0x10;
	298
	299	pci_write_config_byte(pdev, 0x50 + offset, ut \| cable80_status);
	300	}
669a5db4 JG	301	}
	302
	303	static void via_set_piomode(struct ata_port ap, struct ata_device adev)
	304	{
	305	const struct via_isa_bridge *config = ap->host->private_data;
	306	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
	307	int mode = config->flags & VIA_UDMA;
	308	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
	309	static u8 udma[5] = { 0, 33, 66, 100, 133 };
	310
	311	via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
	312	}
	313
	314	static void via_set_dmamode(struct ata_port ap, struct ata_device adev)
	315	{
	316	const struct via_isa_bridge *config = ap->host->private_data;
	317	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
	318	int mode = config->flags & VIA_UDMA;
	319	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
	320	static u8 udma[5] = { 0, 33, 66, 100, 133 };
	321
	322	via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
	323	}
	324
	325	static struct scsi_host_template via_sht = {
68d1d07b	326	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	327	};
	328
	329	static struct ata_port_operations via_port_ops = {
029cfd6b TH	330	.inherits = &ata_bmdma_port_ops,
029cfd6b TH	331	.cable_detect = via_cable_detect,
669a5db4 JG	332	.set_piomode = via_set_piomode,
669a5db4 JG	333	.set_dmamode = via_set_dmamode,
a1efdaba	334	.prereset = via_pre_reset,
669a5db4 JG	335	};
	336
	337	static struct ata_port_operations via_port_ops_noirq = {
029cfd6b	338	.inherits = &via_port_ops,
5682ed33	339	.sff_data_xfer = ata_sff_data_xfer_noirq,
669a5db4 JG	340	};
669a5db4 JG	341
627d2d32 AC	342	/**
	343	* via_config_fifo - set up the FIFO
	344	* @pdev: PCI device
	345	* @flags: configuration flags
	346	*
3a4fa0a2	347	* Set the FIFO properties for this device if necessary. Used both on
627d2d32 AC	348	* set up and on and the resume path
	349	*/
	350
	351	static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
	352	{
	353	u8 enable;
f20b16ff	354
627d2d32 AC	355	/* 0x40 low bits indicate enabled channels */
	356	pci_read_config_byte(pdev, 0x40 , &enable);
	357	enable &= 3;
f20b16ff	358
627d2d32	359	if (flags & VIA_SET_FIFO) {
73720861	360	static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
627d2d32 AC	361	u8 fifo;
	362
	363	pci_read_config_byte(pdev, 0x43, &fifo);
	364
	365	/* Clear PREQ# until DDACK# for errata */
	366	if (flags & VIA_BAD_PREQ)
	367	fifo &= 0x7F;
	368	else
	369	fifo &= 0x9f;
	370	/* Turn on FIFO for enabled channels */
	371	fifo \|= fifo_setting[enable];
	372	pci_write_config_byte(pdev, 0x43, fifo);
	373	}
	374	}
	375
669a5db4 JG	376	/**
669a5db4 JG	377	* via_init_one - discovery callback
627d2d32	378	* @pdev: PCI device
669a5db4 JG	379	* @id: PCI table info
	380	*
	381	* A VIA IDE interface has been discovered. Figure out what revision
	382	* and perform configuration work before handing it to the ATA layer
	383	*/
	384
	385	static int via_init_one(struct pci_dev pdev, const struct pci_device_id id)
	386	{
	387	/* Early VIA without UDMA support */
1626aeb8	388	static const struct ata_port_info via_mwdma_info = {
464cf177	389	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	390	.pio_mask = 0x1f,
	391	.mwdma_mask = 0x07,
	392	.port_ops = &via_port_ops
	393	};
	394	/* Ditto with IRQ masking required */
1626aeb8	395	static const struct ata_port_info via_mwdma_info_borked = {
464cf177	396	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	397	.pio_mask = 0x1f,
	398	.mwdma_mask = 0x07,
	399	.port_ops = &via_port_ops_noirq,
	400	};
	401	/* VIA UDMA 33 devices (and borked 66) */
1626aeb8	402	static const struct ata_port_info via_udma33_info = {
464cf177	403	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	404	.pio_mask = 0x1f,
669a5db4 JG	405	.mwdma_mask = 0x07,
bf6263a8	406	.udma_mask = ATA_UDMA2,
669a5db4 JG	407	.port_ops = &via_port_ops
	408	};
	409	/* VIA UDMA 66 devices */
1626aeb8	410	static const struct ata_port_info via_udma66_info = {
464cf177	411	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	412	.pio_mask = 0x1f,
669a5db4 JG	413	.mwdma_mask = 0x07,
bf6263a8	414	.udma_mask = ATA_UDMA4,
669a5db4 JG	415	.port_ops = &via_port_ops
	416	};
	417	/* VIA UDMA 100 devices */
1626aeb8	418	static const struct ata_port_info via_udma100_info = {
464cf177	419	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	420	.pio_mask = 0x1f,
669a5db4 JG	421	.mwdma_mask = 0x07,
bf6263a8	422	.udma_mask = ATA_UDMA5,
669a5db4 JG	423	.port_ops = &via_port_ops
	424	};
	425	/* UDMA133 with bad AST (All current 133) */
1626aeb8	426	static const struct ata_port_info via_udma133_info = {
464cf177	427	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	428	.pio_mask = 0x1f,
669a5db4 JG	429	.mwdma_mask = 0x07,
bf6263a8	430	.udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */
669a5db4 JG	431	.port_ops = &via_port_ops
669a5db4 JG	432	};
887125e3	433	const struct ata_port_info *ppi[] = { NULL, NULL };
669a5db4 JG	434	struct pci_dev *isa = NULL;
	435	const struct via_isa_bridge *config;
	436	static int printed_version;
669a5db4 JG	437	u8 enable;
669a5db4 JG	438	u32 timing;
f08048e9	439	int rc;
669a5db4 JG	440
	441	if (!printed_version++)
	442	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	443
f08048e9 TH	444	rc = pcim_enable_device(pdev);
	445	if (rc)
	446	return rc;
	447
669a5db4 JG	448	/* To find out how the IDE will behave and what features we
	449	actually have to look at the bridge not the IDE controller */
	450	for (config = via_isa_bridges; config->id; config++)
	451	if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
	452	!!(config->flags & VIA_BAD_ID),
	453	config->id, NULL))) {
	454
44c10138 AK	455	if (isa->revision >= config->rev_min &&
44c10138 AK	456	isa->revision <= config->rev_max)
669a5db4 JG	457	break;
	458	pci_dev_put(isa);
	459	}
	460
	461	if (!config->id) {
	462	printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
	463	return -ENODEV;
	464	}
	465	pci_dev_put(isa);
	466
11f6400e AC	467	if (!(config->flags & VIA_NO_ENABLES)) {
	468	/* 0x40 low bits indicate enabled channels */
	469	pci_read_config_byte(pdev, 0x40 , &enable);
	470	enable &= 3;
	471	if (enable == 0)
	472	return -ENODEV;
669a5db4 JG	473	}
	474
	475	/* Initialise the FIFO for the enabled channels. */
627d2d32	476	via_config_fifo(pdev, config->flags);
f20b16ff	477
669a5db4 JG	478	/* Clock set up */
	479	switch(config->flags & VIA_UDMA) {
	480	case VIA_UDMA_NONE:
	481	if (config->flags & VIA_NO_UNMASK)
887125e3	482	ppi[0] = &via_mwdma_info_borked;
669a5db4	483	else
887125e3	484	ppi[0] = &via_mwdma_info;
669a5db4 JG	485	break;
669a5db4 JG	486	case VIA_UDMA_33:
887125e3	487	ppi[0] = &via_udma33_info;
669a5db4 JG	488	break;
669a5db4 JG	489	case VIA_UDMA_66:
887125e3	490	ppi[0] = &via_udma66_info;
669a5db4 JG	491	/* The 66 MHz devices require we enable the clock */
	492	pci_read_config_dword(pdev, 0x50, &timing);
	493	timing \|= 0x80008;
	494	pci_write_config_dword(pdev, 0x50, timing);
	495	break;
	496	case VIA_UDMA_100:
887125e3	497	ppi[0] = &via_udma100_info;
669a5db4 JG	498	break;
669a5db4 JG	499	case VIA_UDMA_133:
887125e3	500	ppi[0] = &via_udma133_info;
669a5db4 JG	501	break;
	502	default:
	503	WARN_ON(1);
	504	return -ENODEV;
	505	}
	506
	507	if (config->flags & VIA_BAD_CLK66) {
	508	/* Disable the 66MHz clock on problem devices */
	509	pci_read_config_dword(pdev, 0x50, &timing);
	510	timing &= ~0x80008;
	511	pci_write_config_dword(pdev, 0x50, timing);
	512	}
	513
	514	/* We have established the device type, now fire it up */
9363c382	515	return ata_pci_sff_init_one(pdev, ppi, &via_sht, (void *)config);
669a5db4 JG	516	}
669a5db4 JG	517
438ac6d5	518	#ifdef CONFIG_PM
627d2d32 AC	519	/**
	520	* via_reinit_one - reinit after resume
	521	* @pdev; PCI device
	522	*
	523	* Called when the VIA PATA device is resumed. We must then
	524	* reconfigure the fifo and other setup we may have altered. In
	525	* addition the kernel needs to have the resume methods on PCI
	526	* quirk supported.
	527	*/
	528
	529	static int via_reinit_one(struct pci_dev *pdev)
	530	{
	531	u32 timing;
	532	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	533	const struct via_isa_bridge *config = host->private_data;
f08048e9 TH	534	int rc;
	535
	536	rc = ata_pci_device_do_resume(pdev);
	537	if (rc)
	538	return rc;
f20b16ff	539
627d2d32 AC	540	via_config_fifo(pdev, config->flags);
	541
	542	if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
	543	/* The 66 MHz devices require we enable the clock */
	544	pci_read_config_dword(pdev, 0x50, &timing);
	545	timing \|= 0x80008;
	546	pci_write_config_dword(pdev, 0x50, timing);
	547	}
	548	if (config->flags & VIA_BAD_CLK66) {
	549	/* Disable the 66MHz clock on problem devices */
	550	pci_read_config_dword(pdev, 0x50, &timing);
	551	timing &= ~0x80008;
	552	pci_write_config_dword(pdev, 0x50, timing);
	553	}
f08048e9 TH	554
	555	ata_host_resume(host);
	556	return 0;
627d2d32	557	}
438ac6d5	558	#endif
627d2d32	559
669a5db4	560	static const struct pci_device_id via[] = {
52df0ee0 JG	561	{ PCI_VDEVICE(VIA, 0x0571), },
	562	{ PCI_VDEVICE(VIA, 0x0581), },
	563	{ PCI_VDEVICE(VIA, 0x1571), },
	564	{ PCI_VDEVICE(VIA, 0x3164), },
	565	{ PCI_VDEVICE(VIA, 0x5324), },
2d2744fc JG	566
2d2744fc JG	567	{ },
669a5db4 JG	568	};
	569
	570	static struct pci_driver via_pci_driver = {
2d2744fc	571	.name = DRV_NAME,
669a5db4 JG	572	.id_table = via,
669a5db4 JG	573	.probe = via_init_one,
627d2d32	574	.remove = ata_pci_remove_one,
438ac6d5	575	#ifdef CONFIG_PM
627d2d32 AC	576	.suspend = ata_pci_device_suspend,
627d2d32 AC	577	.resume = via_reinit_one,
438ac6d5	578	#endif
669a5db4 JG	579	};
	580
	581	static int __init via_init(void)
	582	{
	583	return pci_register_driver(&via_pci_driver);
	584	}
	585
669a5db4 JG	586	static void __exit via_exit(void)
	587	{
	588	pci_unregister_driver(&via_pci_driver);
	589	}
	590
669a5db4 JG	591	MODULE_AUTHOR("Alan Cox");
	592	MODULE_DESCRIPTION("low-level driver for VIA PATA");
	593	MODULE_LICENSE("GPL");
	594	MODULE_DEVICE_TABLE(pci, via);
	595	MODULE_VERSION(DRV_VERSION);
	596
	597	module_init(via_init);
	598	module_exit(via_exit);