[mirror_ubuntu-hirsute-kernel.git] / drivers / ata / pdc_adma.c

/*
 *  pdc_adma.c - Pacific Digital Corporation ADMA
 *
 *  Maintained by:  Mark Lord <mlord@pobox.com>
 *
 *  Copyright 2005 Mark Lord
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *
 *  Supports ATA disks in single-packet ADMA mode.
 *  Uses PIO for everything else.
 *
 *  TODO:  Use ADMA transfers for ATAPI devices, when possible.
 *  This requires careful attention to a number of quirks of the chip.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pdc_adma"
#define DRV_VERSION	"0.06"

/* macro to calculate base address for ATA regs */
#define ADMA_ATA_REGS(base,port_no)	((base) + ((port_no) * 0x40))

/* macro to calculate base address for ADMA regs */
#define ADMA_REGS(base,port_no)		((base) + 0x80 + ((port_no) * 0x20))

/* macro to obtain addresses from ata_port */
#define ADMA_PORT_REGS(ap) \
	ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)

enum {
	ADMA_MMIO_BAR		= 4,

	ADMA_PORTS		= 2,
	ADMA_CPB_BYTES		= 40,
	ADMA_PRD_BYTES		= LIBATA_MAX_PRD * 16,
	ADMA_PKT_BYTES		= ADMA_CPB_BYTES + ADMA_PRD_BYTES,

	ADMA_DMA_BOUNDARY	= 0xffffffff,

	/* global register offsets */
	ADMA_MODE_LOCK		= 0x00c7,

	/* per-channel register offsets */
	ADMA_CONTROL		= 0x0000, /* ADMA control */
	ADMA_STATUS		= 0x0002, /* ADMA status */
	ADMA_CPB_COUNT		= 0x0004, /* CPB count */
	ADMA_CPB_CURRENT	= 0x000c, /* current CPB address */
	ADMA_CPB_NEXT		= 0x000c, /* next CPB address */
	ADMA_CPB_LOOKUP		= 0x0010, /* CPB lookup table */
	ADMA_FIFO_IN		= 0x0014, /* input FIFO threshold */
	ADMA_FIFO_OUT		= 0x0016, /* output FIFO threshold */

	/* ADMA_CONTROL register bits */
	aNIEN			= (1 << 8), /* irq mask: 1==masked */
	aGO			= (1 << 7), /* packet trigger ("Go!") */
	aRSTADM			= (1 << 5), /* ADMA logic reset */
	aPIOMD4			= 0x0003,   /* PIO mode 4 */

	/* ADMA_STATUS register bits */
	aPSD			= (1 << 6),
	aUIRQ			= (1 << 4),
	aPERR			= (1 << 0),

	/* CPB bits */
	cDONE			= (1 << 0),
	cVLD			= (1 << 0),
	cDAT			= (1 << 2),
	cIEN			= (1 << 3),

	/* PRD bits */
	pORD			= (1 << 4),
	pDIRO			= (1 << 5),
	pEND			= (1 << 7),

	/* ATA register flags */
	rIGN			= (1 << 5),
	rEND			= (1 << 7),

	/* ATA register addresses */
	ADMA_REGS_CONTROL	= 0x0e,
	ADMA_REGS_SECTOR_COUNT	= 0x12,
	ADMA_REGS_LBA_LOW	= 0x13,
	ADMA_REGS_LBA_MID	= 0x14,
	ADMA_REGS_LBA_HIGH	= 0x15,
	ADMA_REGS_DEVICE	= 0x16,
	ADMA_REGS_COMMAND	= 0x17,

	/* PCI device IDs */
	board_1841_idx		= 0,	/* ADMA 2-port controller */
};

typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;

struct adma_port_priv {
	u8			*pkt;
	dma_addr_t		pkt_dma;
	adma_state_t		state;
};

static int adma_ata_init_one (struct pci_dev *pdev,
				const struct pci_device_id *ent);
static int adma_port_start(struct ata_port *ap);
static void adma_host_stop(struct ata_host *host);
static void adma_port_stop(struct ata_port *ap);
static void adma_phy_reset(struct ata_port *ap);
static void adma_qc_prep(struct ata_queued_cmd *qc);
static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
static void adma_bmdma_stop(struct ata_queued_cmd *qc);
static u8 adma_bmdma_status(struct ata_port *ap);
static void adma_irq_clear(struct ata_port *ap);
static void adma_eng_timeout(struct ata_port *ap);

static struct scsi_host_template adma_ata_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ENABLE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ADMA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations adma_ata_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.check_atapi_dma	= adma_check_atapi_dma,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= adma_phy_reset,
	.qc_prep		= adma_qc_prep,
	.qc_issue		= adma_qc_issue,
	.eng_timeout		= adma_eng_timeout,
	.data_xfer		= ata_data_xfer,
	.irq_clear		= adma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,
	.port_start		= adma_port_start,
	.port_stop		= adma_port_stop,
	.host_stop		= adma_host_stop,
	.bmdma_stop		= adma_bmdma_stop,
	.bmdma_status		= adma_bmdma_status,
};

static struct ata_port_info adma_port_info[] = {
	/* board_1841_idx */
	{
		.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
				  ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
				  ATA_FLAG_PIO_POLLING,
		.pio_mask	= 0x10, /* pio4 */
		.udma_mask	= 0x1f, /* udma0-4 */
		.port_ops	= &adma_ata_ops,
	},
};

static const struct pci_device_id adma_ata_pci_tbl[] = {
	{ PCI_VDEVICE(PDC, 0x1841), board_1841_idx },

	{ }	/* terminate list */
};

static struct pci_driver adma_ata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= adma_ata_pci_tbl,
	.probe			= adma_ata_init_one,
	.remove			= ata_pci_remove_one,
};

static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
{
	return 1;	/* ATAPI DMA not yet supported */
}

static void adma_bmdma_stop(struct ata_queued_cmd *qc)
{
	/* nothing */
}

static u8 adma_bmdma_status(struct ata_port *ap)
{
	return 0;
}

static void adma_irq_clear(struct ata_port *ap)
{
	/* nothing */
}

static void adma_reset_engine(struct ata_port *ap)
{
	void __iomem *chan = ADMA_PORT_REGS(ap);

	/* reset ADMA to idle state */
	writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
	udelay(2);
	writew(aPIOMD4, chan + ADMA_CONTROL);
	udelay(2);
}

static void adma_reinit_engine(struct ata_port *ap)
{
	struct adma_port_priv *pp = ap->private_data;
	void __iomem *chan = ADMA_PORT_REGS(ap);

	/* mask/clear ATA interrupts */
	writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
	ata_check_status(ap);

	/* reset the ADMA engine */
	adma_reset_engine(ap);

	/* set in-FIFO threshold to 0x100 */
	writew(0x100, chan + ADMA_FIFO_IN);

	/* set CPB pointer */
	writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);

	/* set out-FIFO threshold to 0x100 */
	writew(0x100, chan + ADMA_FIFO_OUT);

	/* set CPB count */
	writew(1, chan + ADMA_CPB_COUNT);

	/* read/discard ADMA status */
	readb(chan + ADMA_STATUS);
}

static inline void adma_enter_reg_mode(struct ata_port *ap)
{
	void __iomem *chan = ADMA_PORT_REGS(ap);

	writew(aPIOMD4, chan + ADMA_CONTROL);
	readb(chan + ADMA_STATUS);	/* flush */
}

static void adma_phy_reset(struct ata_port *ap)
{
	struct adma_port_priv *pp = ap->private_data;

	pp->state = adma_state_idle;
	adma_reinit_engine(ap);
	ata_port_probe(ap);
	ata_bus_reset(ap);
}

static void adma_eng_timeout(struct ata_port *ap)
{
	struct adma_port_priv *pp = ap->private_data;

	if (pp->state != adma_state_idle) /* healthy paranoia */
		pp->state = adma_state_mmio;
	adma_reinit_engine(ap);
	ata_eng_timeout(ap);
}

static int adma_fill_sg(struct ata_queued_cmd *qc)
{
	struct scatterlist *sg;
	struct ata_port *ap = qc->ap;
	struct adma_port_priv *pp = ap->private_data;
	u8  *buf = pp->pkt;
	int i = (2 + buf[3]) * 8;
	u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);

	ata_for_each_sg(sg, qc) {
		u32 addr;
		u32 len;

		addr = (u32)sg_dma_address(sg);
		*(__le32 *)(buf + i) = cpu_to_le32(addr);
		i += 4;

		len = sg_dma_len(sg) >> 3;
		*(__le32 *)(buf + i) = cpu_to_le32(len);
		i += 4;

		if (ata_sg_is_last(sg, qc))
			pFLAGS |= pEND;
		buf[i++] = pFLAGS;
		buf[i++] = qc->dev->dma_mode & 0xf;
		buf[i++] = 0;	/* pPKLW */
		buf[i++] = 0;	/* reserved */

		*(__le32 *)(buf + i)
			= (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
		i += 4;

		VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
					(unsigned long)addr, len);
	}
	return i;
}

static void adma_qc_prep(struct ata_queued_cmd *qc)
{
	struct adma_port_priv *pp = qc->ap->private_data;
	u8  *buf = pp->pkt;
	u32 pkt_dma = (u32)pp->pkt_dma;
	int i = 0;

	VPRINTK("ENTER\n");

	adma_enter_reg_mode(qc->ap);
	if (qc->tf.protocol != ATA_PROT_DMA) {
		ata_qc_prep(qc);
		return;
	}

	buf[i++] = 0;	/* Response flags */
	buf[i++] = 0;	/* reserved */
	buf[i++] = cVLD | cDAT | cIEN;
	i++;		/* cLEN, gets filled in below */

	*(__le32 *)(buf+i) = cpu_to_le32(pkt_dma);	/* cNCPB */
	i += 4;		/* cNCPB */
	i += 4;		/* cPRD, gets filled in below */

	buf[i++] = 0;	/* reserved */
	buf[i++] = 0;	/* reserved */
	buf[i++] = 0;	/* reserved */
	buf[i++] = 0;	/* reserved */

	/* ATA registers; must be a multiple of 4 */
	buf[i++] = qc->tf.device;
	buf[i++] = ADMA_REGS_DEVICE;
	if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
		buf[i++] = qc->tf.hob_nsect;
		buf[i++] = ADMA_REGS_SECTOR_COUNT;
		buf[i++] = qc->tf.hob_lbal;
		buf[i++] = ADMA_REGS_LBA_LOW;
		buf[i++] = qc->tf.hob_lbam;
		buf[i++] = ADMA_REGS_LBA_MID;
		buf[i++] = qc->tf.hob_lbah;
		buf[i++] = ADMA_REGS_LBA_HIGH;
	}
	buf[i++] = qc->tf.nsect;
	buf[i++] = ADMA_REGS_SECTOR_COUNT;
	buf[i++] = qc->tf.lbal;
	buf[i++] = ADMA_REGS_LBA_LOW;
	buf[i++] = qc->tf.lbam;
	buf[i++] = ADMA_REGS_LBA_MID;
	buf[i++] = qc->tf.lbah;
	buf[i++] = ADMA_REGS_LBA_HIGH;
	buf[i++] = 0;
	buf[i++] = ADMA_REGS_CONTROL;
	buf[i++] = rIGN;
	buf[i++] = 0;
	buf[i++] = qc->tf.command;
	buf[i++] = ADMA_REGS_COMMAND | rEND;

	buf[3] = (i >> 3) - 2;				/* cLEN */
	*(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i);	/* cPRD */

	i = adma_fill_sg(qc);
	wmb();	/* flush PRDs and pkt to memory */
#if 0
	/* dump out CPB + PRDs for debug */
	{
		int j, len = 0;
		static char obuf[2048];
		for (j = 0; j < i; ++j) {
			len += sprintf(obuf+len, "%02x ", buf[j]);
			if ((j & 7) == 7) {
				printk("%s\n", obuf);
				len = 0;
			}
		}
		if (len)
			printk("%s\n", obuf);
	}
#endif
}

static inline void adma_packet_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void __iomem *chan = ADMA_PORT_REGS(ap);

	VPRINTK("ENTER, ap %p\n", ap);

	/* fire up the ADMA engine */
	writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
}

static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
{
	struct adma_port_priv *pp = qc->ap->private_data;

	switch (qc->tf.protocol) {
	case ATA_PROT_DMA:
		pp->state = adma_state_pkt;
		adma_packet_start(qc);
		return 0;

	case ATA_PROT_ATAPI_DMA:
		BUG();
		break;

	default:
		break;
	}

	pp->state = adma_state_mmio;
	return ata_qc_issue_prot(qc);
}

static inline unsigned int adma_intr_pkt(struct ata_host *host)
{
	unsigned int handled = 0, port_no;

	for (port_no = 0; port_no < host->n_ports; ++port_no) {
		struct ata_port *ap = host->ports[port_no];
		struct adma_port_priv *pp;
		struct ata_queued_cmd *qc;
		void __iomem *chan = ADMA_PORT_REGS(ap);
		u8 status = readb(chan + ADMA_STATUS);

		if (status == 0)
			continue;
		handled = 1;
		adma_enter_reg_mode(ap);
		if (ap->flags & ATA_FLAG_DISABLED)
			continue;
		pp = ap->private_data;
		if (!pp || pp->state != adma_state_pkt)
			continue;
		qc = ata_qc_from_tag(ap, ap->active_tag);
		if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
			if ((status & (aPERR | aPSD | aUIRQ)))
				qc->err_mask |= AC_ERR_OTHER;
			else if (pp->pkt[0] != cDONE)
				qc->err_mask |= AC_ERR_OTHER;

			ata_qc_complete(qc);
		}
	}
	return handled;
}

static inline unsigned int adma_intr_mmio(struct ata_host *host)
{
	unsigned int handled = 0, port_no;

	for (port_no = 0; port_no < host->n_ports; ++port_no) {
		struct ata_port *ap;
		ap = host->ports[port_no];
		if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
			struct ata_queued_cmd *qc;
			struct adma_port_priv *pp = ap->private_data;
			if (!pp || pp->state != adma_state_mmio)
				continue;
			qc = ata_qc_from_tag(ap, ap->active_tag);
			if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {

				/* check main status, clearing INTRQ */
				u8 status = ata_check_status(ap);
				if ((status & ATA_BUSY))
					continue;
				DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
					ap->print_id, qc->tf.protocol, status);

				/* complete taskfile transaction */
				pp->state = adma_state_idle;
				qc->err_mask |= ac_err_mask(status);
				ata_qc_complete(qc);
				handled = 1;
			}
		}
	}
	return handled;
}

static irqreturn_t adma_intr(int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	unsigned int handled = 0;

	VPRINTK("ENTER\n");

	spin_lock(&host->lock);
	handled  = adma_intr_pkt(host) | adma_intr_mmio(host);
	spin_unlock(&host->lock);

	VPRINTK("EXIT\n");

	return IRQ_RETVAL(handled);
}

static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		=
	port->data_addr		= base + 0x000;
	port->error_addr	=
	port->feature_addr	= base + 0x004;
	port->nsect_addr	= base + 0x008;
	port->lbal_addr		= base + 0x00c;
	port->lbam_addr		= base + 0x010;
	port->lbah_addr		= base + 0x014;
	port->device_addr	= base + 0x018;
	port->status_addr	=
	port->command_addr	= base + 0x01c;
	port->altstatus_addr	=
	port->ctl_addr		= base + 0x038;
}

static int adma_port_start(struct ata_port *ap)
{
	struct device *dev = ap->host->dev;
	struct adma_port_priv *pp;
	int rc;

	rc = ata_port_start(ap);
	if (rc)
		return rc;
	adma_enter_reg_mode(ap);
	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
	if (!pp)
		return -ENOMEM;
	pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
				      GFP_KERNEL);
	if (!pp->pkt)
		return -ENOMEM;
	/* paranoia? */
	if ((pp->pkt_dma & 7) != 0) {
		printk("bad alignment for pp->pkt_dma: %08x\n",
						(u32)pp->pkt_dma);
		return -ENOMEM;
	}
	memset(pp->pkt, 0, ADMA_PKT_BYTES);
	ap->private_data = pp;
	adma_reinit_engine(ap);
	return 0;
}

static void adma_port_stop(struct ata_port *ap)
{
	adma_reset_engine(ap);
}

static void adma_host_stop(struct ata_host *host)
{
	unsigned int port_no;

	for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
		adma_reset_engine(host->ports[port_no]);
}

static void adma_host_init(struct ata_host *host, unsigned int chip_id)
{
	unsigned int port_no;

	/* enable/lock aGO operation */
	writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);

	/* reset the ADMA logic */
	for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
		adma_reset_engine(host->ports[port_no]);
}

static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
{
	int rc;

	rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
	if (rc) {
		dev_printk(KERN_ERR, &pdev->dev,
			"32-bit DMA enable failed\n");
		return rc;
	}
	rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
	if (rc) {
		dev_printk(KERN_ERR, &pdev->dev,
			"32-bit consistent DMA enable failed\n");
		return rc;
	}
	return 0;
}

static int adma_ata_init_one(struct pci_dev *pdev,
			     const struct pci_device_id *ent)
{
	static int printed_version;
	unsigned int board_idx = (unsigned int) ent->driver_data;
	const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int rc, port_no;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	/* alloc host */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
	if (!host)
		return -ENOMEM;

	/* acquire resources and fill host */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
		return -ENODEV;

	rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	mmio_base = host->iomap[ADMA_MMIO_BAR];

	rc = adma_set_dma_masks(pdev, mmio_base);
	if (rc)
		return rc;

	for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
		adma_ata_setup_port(&host->ports[port_no]->ioaddr,
				    ADMA_ATA_REGS(mmio_base, port_no));

	/* initialize adapter */
	adma_host_init(host, board_idx);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
				 &adma_ata_sht);
}

static int __init adma_ata_init(void)
{
	return pci_register_driver(&adma_ata_pci_driver);
}

static void __exit adma_ata_exit(void)
{
	pci_unregister_driver(&adma_ata_pci_driver);
}

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
MODULE_VERSION(DRV_VERSION);

module_init(adma_ata_init);
module_exit(adma_ata_exit);
Commit	Line	Data
edea3ab5 ML	1	/*
	2	* pdc_adma.c - Pacific Digital Corporation ADMA
	3	*
	4	* Maintained by: Mark Lord <mlord@pobox.com>
	5	*
	6	* Copyright 2005 Mark Lord
	7	*
68399bb5 JG	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2, or (at your option)
	11	* any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; see the file COPYING. If not, write to
	20	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*
	22	*
	23	* libata documentation is available via 'make {ps\|pdf}docs',
	24	* as Documentation/DocBook/libata.*
edea3ab5	25	*
edea3ab5 ML	26	*
	27	* Supports ATA disks in single-packet ADMA mode.
	28	* Uses PIO for everything else.
	29	*
	30	* TODO: Use ADMA transfers for ATAPI devices, when possible.
	31	* This requires careful attention to a number of quirks of the chip.
	32	*
	33	*/
	34
	35	#include <linux/kernel.h>
	36	#include <linux/module.h>
	37	#include <linux/pci.h>
	38	#include <linux/init.h>
	39	#include <linux/blkdev.h>
	40	#include <linux/delay.h>
	41	#include <linux/interrupt.h>
a9524a76	42	#include <linux/device.h>
edea3ab5	43	#include <scsi/scsi_host.h>
edea3ab5 ML	44	#include <linux/libata.h>
	45
	46	#define DRV_NAME "pdc_adma"
8bc3fc47	47	#define DRV_VERSION "0.06"
edea3ab5 ML	48
	49	/* macro to calculate base address for ATA regs */
	50	#define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40))
	51
	52	/* macro to calculate base address for ADMA regs */
0d5ff566 TH	53	#define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20))
0d5ff566 TH	54
5d728824 TH	55	/* macro to obtain addresses from ata_port */
	56	#define ADMA_PORT_REGS(ap) \
	57	ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
edea3ab5 ML	58
edea3ab5 ML	59	enum {
0d5ff566 TH	60	ADMA_MMIO_BAR = 4,
0d5ff566 TH	61
edea3ab5 ML	62	ADMA_PORTS = 2,
	63	ADMA_CPB_BYTES = 40,
	64	ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
	65	ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
	66
	67	ADMA_DMA_BOUNDARY = 0xffffffff,
	68
	69	/* global register offsets */
	70	ADMA_MODE_LOCK = 0x00c7,
	71
	72	/* per-channel register offsets */
	73	ADMA_CONTROL = 0x0000, /* ADMA control */
	74	ADMA_STATUS = 0x0002, /* ADMA status */
	75	ADMA_CPB_COUNT = 0x0004, /* CPB count */
	76	ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
	77	ADMA_CPB_NEXT = 0x000c, /* next CPB address */
	78	ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
	79	ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
	80	ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
	81
	82	/* ADMA_CONTROL register bits */
	83	aNIEN = (1 << 8), /* irq mask: 1==masked */
	84	aGO = (1 << 7), /* packet trigger ("Go!") */
	85	aRSTADM = (1 << 5), /* ADMA logic reset */
edea3ab5 ML	86	aPIOMD4 = 0x0003, /* PIO mode 4 */
	87
	88	/* ADMA_STATUS register bits */
	89	aPSD = (1 << 6),
	90	aUIRQ = (1 << 4),
	91	aPERR = (1 << 0),
	92
	93	/* CPB bits */
	94	cDONE = (1 << 0),
	95	cVLD = (1 << 0),
	96	cDAT = (1 << 2),
	97	cIEN = (1 << 3),
	98
	99	/* PRD bits */
	100	pORD = (1 << 4),
	101	pDIRO = (1 << 5),
	102	pEND = (1 << 7),
	103
	104	/* ATA register flags */
	105	rIGN = (1 << 5),
	106	rEND = (1 << 7),
	107
	108	/* ATA register addresses */
	109	ADMA_REGS_CONTROL = 0x0e,
	110	ADMA_REGS_SECTOR_COUNT = 0x12,
	111	ADMA_REGS_LBA_LOW = 0x13,
	112	ADMA_REGS_LBA_MID = 0x14,
	113	ADMA_REGS_LBA_HIGH = 0x15,
	114	ADMA_REGS_DEVICE = 0x16,
	115	ADMA_REGS_COMMAND = 0x17,
	116
	117	/* PCI device IDs */
	118	board_1841_idx = 0, /* ADMA 2-port controller */
	119	};
	120
	121	typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
	122
	123	struct adma_port_priv {
	124	u8 *pkt;
	125	dma_addr_t pkt_dma;
	126	adma_state_t state;
	127	};
	128
	129	static int adma_ata_init_one (struct pci_dev *pdev,
	130	const struct pci_device_id *ent);
edea3ab5	131	static int adma_port_start(struct ata_port *ap);
cca3974e	132	static void adma_host_stop(struct ata_host *host);
edea3ab5 ML	133	static void adma_port_stop(struct ata_port *ap);
	134	static void adma_phy_reset(struct ata_port *ap);
	135	static void adma_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0	136	static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
edea3ab5 ML	137	static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
	138	static void adma_bmdma_stop(struct ata_queued_cmd *qc);
	139	static u8 adma_bmdma_status(struct ata_port *ap);
	140	static void adma_irq_clear(struct ata_port *ap);
	141	static void adma_eng_timeout(struct ata_port *ap);
	142
193515d5	143	static struct scsi_host_template adma_ata_sht = {
edea3ab5 ML	144	.module = THIS_MODULE,
	145	.name = DRV_NAME,
	146	.ioctl = ata_scsi_ioctl,
	147	.queuecommand = ata_scsi_queuecmd,
edea3ab5 ML	148	.can_queue = ATA_DEF_QUEUE,
	149	.this_id = ATA_SHT_THIS_ID,
	150	.sg_tablesize = LIBATA_MAX_PRD,
edea3ab5 ML	151	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	152	.emulated = ATA_SHT_EMULATED,
	153	.use_clustering = ENABLE_CLUSTERING,
	154	.proc_name = DRV_NAME,
	155	.dma_boundary = ADMA_DMA_BOUNDARY,
	156	.slave_configure = ata_scsi_slave_config,
ccf68c34	157	.slave_destroy = ata_scsi_slave_destroy,
edea3ab5 ML	158	.bios_param = ata_std_bios_param,
	159	};
	160
057ace5e	161	static const struct ata_port_operations adma_ata_ops = {
edea3ab5 ML	162	.port_disable = ata_port_disable,
	163	.tf_load = ata_tf_load,
	164	.tf_read = ata_tf_read,
	165	.check_status = ata_check_status,
	166	.check_atapi_dma = adma_check_atapi_dma,
	167	.exec_command = ata_exec_command,
	168	.dev_select = ata_std_dev_select,
	169	.phy_reset = adma_phy_reset,
	170	.qc_prep = adma_qc_prep,
	171	.qc_issue = adma_qc_issue,
	172	.eng_timeout = adma_eng_timeout,
0d5ff566	173	.data_xfer = ata_data_xfer,
edea3ab5	174	.irq_clear = adma_irq_clear,
246ce3b6 AI	175	.irq_on = ata_irq_on,
246ce3b6 AI	176	.irq_ack = ata_irq_ack,
edea3ab5 ML	177	.port_start = adma_port_start,
	178	.port_stop = adma_port_stop,
	179	.host_stop = adma_host_stop,
	180	.bmdma_stop = adma_bmdma_stop,
	181	.bmdma_status = adma_bmdma_status,
	182	};
	183
	184	static struct ata_port_info adma_port_info[] = {
	185	/* board_1841_idx */
	186	{
cca3974e	187	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST \|
51704c60 AL	188	ATA_FLAG_NO_LEGACY \| ATA_FLAG_MMIO \|
51704c60 AL	189	ATA_FLAG_PIO_POLLING,
edea3ab5 ML	190	.pio_mask = 0x10, /* pio4 */
	191	.udma_mask = 0x1f, /* udma0-4 */
	192	.port_ops = &adma_ata_ops,
	193	},
	194	};
	195
3b7d697d	196	static const struct pci_device_id adma_ata_pci_tbl[] = {
54bb3a94	197	{ PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
edea3ab5 ML	198
	199	{ } /* terminate list */
	200	};
	201
	202	static struct pci_driver adma_ata_pci_driver = {
	203	.name = DRV_NAME,
	204	.id_table = adma_ata_pci_tbl,
	205	.probe = adma_ata_init_one,
	206	.remove = ata_pci_remove_one,
	207	};
	208
	209	static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
	210	{
	211	return 1; /* ATAPI DMA not yet supported */
	212	}
	213
	214	static void adma_bmdma_stop(struct ata_queued_cmd *qc)
	215	{
	216	/* nothing */
	217	}
	218
	219	static u8 adma_bmdma_status(struct ata_port *ap)
	220	{
	221	return 0;
	222	}
	223
	224	static void adma_irq_clear(struct ata_port *ap)
	225	{
	226	/* nothing */
	227	}
	228
5d728824	229	static void adma_reset_engine(struct ata_port *ap)
edea3ab5	230	{
5d728824 TH	231	void __iomem *chan = ADMA_PORT_REGS(ap);
5d728824 TH	232
edea3ab5 ML	233	/* reset ADMA to idle state */
	234	writew(aPIOMD4 \| aNIEN \| aRSTADM, chan + ADMA_CONTROL);
	235	udelay(2);
	236	writew(aPIOMD4, chan + ADMA_CONTROL);
	237	udelay(2);
	238	}
	239
	240	static void adma_reinit_engine(struct ata_port *ap)
	241	{
	242	struct adma_port_priv *pp = ap->private_data;
5d728824	243	void __iomem *chan = ADMA_PORT_REGS(ap);
edea3ab5 ML	244
edea3ab5 ML	245	/* mask/clear ATA interrupts */
0d5ff566	246	writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
edea3ab5 ML	247	ata_check_status(ap);
	248
	249	/* reset the ADMA engine */
5d728824	250	adma_reset_engine(ap);
edea3ab5 ML	251
	252	/* set in-FIFO threshold to 0x100 */
	253	writew(0x100, chan + ADMA_FIFO_IN);
	254
	255	/* set CPB pointer */
	256	writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
	257
	258	/* set out-FIFO threshold to 0x100 */
	259	writew(0x100, chan + ADMA_FIFO_OUT);
	260
	261	/* set CPB count */
	262	writew(1, chan + ADMA_CPB_COUNT);
	263
	264	/* read/discard ADMA status */
	265	readb(chan + ADMA_STATUS);
	266	}
	267
	268	static inline void adma_enter_reg_mode(struct ata_port *ap)
	269	{
5d728824	270	void __iomem *chan = ADMA_PORT_REGS(ap);
edea3ab5 ML	271
	272	writew(aPIOMD4, chan + ADMA_CONTROL);
	273	readb(chan + ADMA_STATUS); /* flush */
	274	}
	275
	276	static void adma_phy_reset(struct ata_port *ap)
	277	{
	278	struct adma_port_priv *pp = ap->private_data;
	279
	280	pp->state = adma_state_idle;
	281	adma_reinit_engine(ap);
	282	ata_port_probe(ap);
	283	ata_bus_reset(ap);
	284	}
	285
	286	static void adma_eng_timeout(struct ata_port *ap)
	287	{
	288	struct adma_port_priv *pp = ap->private_data;
	289
	290	if (pp->state != adma_state_idle) /* healthy paranoia */
	291	pp->state = adma_state_mmio;
	292	adma_reinit_engine(ap);
	293	ata_eng_timeout(ap);
	294	}
	295
	296	static int adma_fill_sg(struct ata_queued_cmd *qc)
	297	{
972c26bd	298	struct scatterlist *sg;
edea3ab5 ML	299	struct ata_port *ap = qc->ap;
	300	struct adma_port_priv *pp = ap->private_data;
	301	u8 *buf = pp->pkt;
972c26bd	302	int i = (2 + buf[3]) * 8;
edea3ab5 ML	303	u8 pFLAGS = pORD \| ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
edea3ab5 ML	304
972c26bd	305	ata_for_each_sg(sg, qc) {
edea3ab5 ML	306	u32 addr;
	307	u32 len;
	308
	309	addr = (u32)sg_dma_address(sg);
	310	(__le32 )(buf + i) = cpu_to_le32(addr);
	311	i += 4;
	312
	313	len = sg_dma_len(sg) >> 3;
	314	(__le32 )(buf + i) = cpu_to_le32(len);
	315	i += 4;
	316
972c26bd	317	if (ata_sg_is_last(sg, qc))
edea3ab5 ML	318	pFLAGS \|= pEND;
	319	buf[i++] = pFLAGS;
	320	buf[i++] = qc->dev->dma_mode & 0xf;
	321	buf[i++] = 0; /* pPKLW */
	322	buf[i++] = 0; /* reserved */
	323
	324	(__le32 )(buf + i)
	325	= (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
	326	i += 4;
	327
db7f44d9	328	VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
edea3ab5 ML	329	(unsigned long)addr, len);
	330	}
	331	return i;
	332	}
	333
	334	static void adma_qc_prep(struct ata_queued_cmd *qc)
	335	{
	336	struct adma_port_priv *pp = qc->ap->private_data;
	337	u8 *buf = pp->pkt;
	338	u32 pkt_dma = (u32)pp->pkt_dma;
	339	int i = 0;
	340
	341	VPRINTK("ENTER\n");
	342
	343	adma_enter_reg_mode(qc->ap);
	344	if (qc->tf.protocol != ATA_PROT_DMA) {
	345	ata_qc_prep(qc);
	346	return;
	347	}
	348
	349	buf[i++] = 0; /* Response flags */
	350	buf[i++] = 0; /* reserved */
	351	buf[i++] = cVLD \| cDAT \| cIEN;
	352	i++; /* cLEN, gets filled in below */
	353
	354	(__le32 )(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
	355	i += 4; /* cNCPB */
	356	i += 4; /* cPRD, gets filled in below */
	357
	358	buf[i++] = 0; /* reserved */
	359	buf[i++] = 0; /* reserved */
	360	buf[i++] = 0; /* reserved */
	361	buf[i++] = 0; /* reserved */
	362
	363	/* ATA registers; must be a multiple of 4 */
	364	buf[i++] = qc->tf.device;
	365	buf[i++] = ADMA_REGS_DEVICE;
	366	if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
	367	buf[i++] = qc->tf.hob_nsect;
	368	buf[i++] = ADMA_REGS_SECTOR_COUNT;
	369	buf[i++] = qc->tf.hob_lbal;
	370	buf[i++] = ADMA_REGS_LBA_LOW;
	371	buf[i++] = qc->tf.hob_lbam;
	372	buf[i++] = ADMA_REGS_LBA_MID;
	373	buf[i++] = qc->tf.hob_lbah;
	374	buf[i++] = ADMA_REGS_LBA_HIGH;
	375	}
	376	buf[i++] = qc->tf.nsect;
	377	buf[i++] = ADMA_REGS_SECTOR_COUNT;
	378	buf[i++] = qc->tf.lbal;
	379	buf[i++] = ADMA_REGS_LBA_LOW;
	380	buf[i++] = qc->tf.lbam;
	381	buf[i++] = ADMA_REGS_LBA_MID;
	382	buf[i++] = qc->tf.lbah;
	383	buf[i++] = ADMA_REGS_LBA_HIGH;
	384	buf[i++] = 0;
	385	buf[i++] = ADMA_REGS_CONTROL;
	386	buf[i++] = rIGN;
	387	buf[i++] = 0;
	388	buf[i++] = qc->tf.command;
	389	buf[i++] = ADMA_REGS_COMMAND \| rEND;
	390
	391	buf[3] = (i >> 3) - 2; /* cLEN */
	392	(__le32 )(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
393
394	i = adma_fill_sg(qc);
395	wmb(); /* flush PRDs and pkt to memory */
396	#if 0
397	/* dump out CPB + PRDs for debug */
398	{
399	int j, len = 0;
400	static char obuf[2048];
401	for (j = 0; j < i; ++j) {
402	len += sprintf(obuf+len, "%02x ", buf[j]);
403	if ((j & 7) == 7) {
404	printk("%s\n", obuf);
405	len = 0;
406	}
407	}
408	if (len)
409	printk("%s\n", obuf);
410	}
411	#endif
412	}
413
414	static inline void adma_packet_start(struct ata_queued_cmd *qc)
415	{
416	struct ata_port *ap = qc->ap;
5d728824	417	void __iomem *chan = ADMA_PORT_REGS(ap);
edea3ab5 ML	418
	419	VPRINTK("ENTER, ap %p\n", ap);
	420
	421	/* fire up the ADMA engine */
68399bb5	422	writew(aPIOMD4 \| aGO, chan + ADMA_CONTROL);
edea3ab5 ML	423	}
edea3ab5 ML	424
9a3d9eb0	425	static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
edea3ab5 ML	426	{
	427	struct adma_port_priv *pp = qc->ap->private_data;
	428
	429	switch (qc->tf.protocol) {
	430	case ATA_PROT_DMA:
	431	pp->state = adma_state_pkt;
	432	adma_packet_start(qc);
	433	return 0;
	434
	435	case ATA_PROT_ATAPI_DMA:
	436	BUG();
	437	break;
	438
	439	default:
	440	break;
	441	}
	442
	443	pp->state = adma_state_mmio;
	444	return ata_qc_issue_prot(qc);
	445	}
	446
cca3974e	447	static inline unsigned int adma_intr_pkt(struct ata_host *host)
edea3ab5 ML	448	{
edea3ab5 ML	449	unsigned int handled = 0, port_no;
edea3ab5	450
cca3974e JG	451	for (port_no = 0; port_no < host->n_ports; ++port_no) {
cca3974e JG	452	struct ata_port *ap = host->ports[port_no];
edea3ab5 ML	453	struct adma_port_priv *pp;
edea3ab5 ML	454	struct ata_queued_cmd *qc;
5d728824	455	void __iomem *chan = ADMA_PORT_REGS(ap);
a7dac447	456	u8 status = readb(chan + ADMA_STATUS);
edea3ab5 ML	457
	458	if (status == 0)
	459	continue;
	460	handled = 1;
	461	adma_enter_reg_mode(ap);
029f5468	462	if (ap->flags & ATA_FLAG_DISABLED)
edea3ab5 ML	463	continue;
	464	pp = ap->private_data;
	465	if (!pp \|\| pp->state != adma_state_pkt)
	466	continue;
	467	qc = ata_qc_from_tag(ap, ap->active_tag);
94ec1ef1	468	if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
a21a84a3	469	if ((status & (aPERR \| aPSD \| aUIRQ)))
a22e2eb0	470	qc->err_mask \|= AC_ERR_OTHER;
a21a84a3	471	else if (pp->pkt[0] != cDONE)
a22e2eb0	472	qc->err_mask \|= AC_ERR_OTHER;
a7dac447	473
a22e2eb0	474	ata_qc_complete(qc);
a21a84a3	475	}
edea3ab5 ML	476	}
	477	return handled;
	478	}
	479
cca3974e	480	static inline unsigned int adma_intr_mmio(struct ata_host *host)
edea3ab5 ML	481	{
	482	unsigned int handled = 0, port_no;
	483
cca3974e	484	for (port_no = 0; port_no < host->n_ports; ++port_no) {
edea3ab5	485	struct ata_port *ap;
cca3974e	486	ap = host->ports[port_no];
029f5468	487	if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
edea3ab5 ML	488	struct ata_queued_cmd *qc;
	489	struct adma_port_priv *pp = ap->private_data;
	490	if (!pp \|\| pp->state != adma_state_mmio)
	491	continue;
	492	qc = ata_qc_from_tag(ap, ap->active_tag);
be697c3f	493	if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
edea3ab5 ML	494
edea3ab5 ML	495	/* check main status, clearing INTRQ */
ac19bff2	496	u8 status = ata_check_status(ap);
edea3ab5 ML	497	if ((status & ATA_BUSY))
	498	continue;
	499	DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
44877b4e	500	ap->print_id, qc->tf.protocol, status);
9bec2e38	501
edea3ab5 ML	502	/* complete taskfile transaction */
edea3ab5 ML	503	pp->state = adma_state_idle;
a22e2eb0 AL	504	qc->err_mask \|= ac_err_mask(status);
a22e2eb0 AL	505	ata_qc_complete(qc);
edea3ab5 ML	506	handled = 1;
	507	}
	508	}
	509	}
	510	return handled;
	511	}
	512
7d12e780	513	static irqreturn_t adma_intr(int irq, void *dev_instance)
edea3ab5	514	{
cca3974e	515	struct ata_host *host = dev_instance;
edea3ab5 ML	516	unsigned int handled = 0;
	517
	518	VPRINTK("ENTER\n");
	519
cca3974e JG	520	spin_lock(&host->lock);
	521	handled = adma_intr_pkt(host) \| adma_intr_mmio(host);
	522	spin_unlock(&host->lock);
edea3ab5 ML	523
	524	VPRINTK("EXIT\n");
	525
	526	return IRQ_RETVAL(handled);
	527	}
	528
0d5ff566	529	static void adma_ata_setup_port(struct ata_ioports port, void __iomem base)
edea3ab5 ML	530	{
	531	port->cmd_addr =
	532	port->data_addr = base + 0x000;
	533	port->error_addr =
	534	port->feature_addr = base + 0x004;
	535	port->nsect_addr = base + 0x008;
	536	port->lbal_addr = base + 0x00c;
	537	port->lbam_addr = base + 0x010;
	538	port->lbah_addr = base + 0x014;
	539	port->device_addr = base + 0x018;
	540	port->status_addr =
	541	port->command_addr = base + 0x01c;
	542	port->altstatus_addr =
	543	port->ctl_addr = base + 0x038;
	544	}
	545
	546	static int adma_port_start(struct ata_port *ap)
	547	{
cca3974e	548	struct device *dev = ap->host->dev;
edea3ab5 ML	549	struct adma_port_priv *pp;
	550	int rc;
	551
	552	rc = ata_port_start(ap);
	553	if (rc)
	554	return rc;
	555	adma_enter_reg_mode(ap);
24dc5f33	556	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
edea3ab5	557	if (!pp)
24dc5f33 TH	558	return -ENOMEM;
	559	pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
	560	GFP_KERNEL);
edea3ab5	561	if (!pp->pkt)
24dc5f33	562	return -ENOMEM;
edea3ab5 ML	563	/* paranoia? */
	564	if ((pp->pkt_dma & 7) != 0) {
	565	printk("bad alignment for pp->pkt_dma: %08x\n",
	566	(u32)pp->pkt_dma);
24dc5f33	567	return -ENOMEM;
edea3ab5 ML	568	}
	569	memset(pp->pkt, 0, ADMA_PKT_BYTES);
	570	ap->private_data = pp;
	571	adma_reinit_engine(ap);
	572	return 0;
edea3ab5 ML	573	}
	574
	575	static void adma_port_stop(struct ata_port *ap)
	576	{
5d728824	577	adma_reset_engine(ap);
edea3ab5 ML	578	}
edea3ab5 ML	579
cca3974e	580	static void adma_host_stop(struct ata_host *host)
edea3ab5 ML	581	{
	582	unsigned int port_no;
	583
	584	for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
5d728824	585	adma_reset_engine(host->ports[port_no]);
edea3ab5 ML	586	}
edea3ab5 ML	587
5d728824	588	static void adma_host_init(struct ata_host *host, unsigned int chip_id)
edea3ab5 ML	589	{
edea3ab5 ML	590	unsigned int port_no;
edea3ab5 ML	591
edea3ab5 ML	592	/* enable/lock aGO operation */
5d728824	593	writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
edea3ab5 ML	594
	595	/* reset the ADMA logic */
	596	for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
5d728824	597	adma_reset_engine(host->ports[port_no]);
edea3ab5 ML	598	}
	599
	600	static int adma_set_dma_masks(struct pci_dev pdev, void __iomem mmio_base)
	601	{
	602	int rc;
	603
	604	rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
	605	if (rc) {
a9524a76 JG	606	dev_printk(KERN_ERR, &pdev->dev,
a9524a76 JG	607	"32-bit DMA enable failed\n");
edea3ab5 ML	608	return rc;
	609	}
	610	rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
	611	if (rc) {
a9524a76 JG	612	dev_printk(KERN_ERR, &pdev->dev,
a9524a76 JG	613	"32-bit consistent DMA enable failed\n");
edea3ab5 ML	614	return rc;
	615	}
	616	return 0;
	617	}
	618
	619	static int adma_ata_init_one(struct pci_dev *pdev,
0d5ff566	620	const struct pci_device_id *ent)
edea3ab5 ML	621	{
edea3ab5 ML	622	static int printed_version;
edea3ab5	623	unsigned int board_idx = (unsigned int) ent->driver_data;
5d728824 TH	624	const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
	625	struct ata_host *host;
	626	void __iomem *mmio_base;
edea3ab5 ML	627	int rc, port_no;
	628
	629	if (!printed_version++)
a9524a76	630	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
edea3ab5	631
5d728824 TH	632	/* alloc host */
	633	host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
	634	if (!host)
	635	return -ENOMEM;
	636
	637	/* acquire resources and fill host */
24dc5f33	638	rc = pcim_enable_device(pdev);
edea3ab5 ML	639	if (rc)
	640	return rc;
	641
24dc5f33 TH	642	if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
24dc5f33 TH	643	return -ENODEV;
edea3ab5	644
0d5ff566 TH	645	rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
	646	if (rc)
	647	return rc;
5d728824 TH	648	host->iomap = pcim_iomap_table(pdev);
5d728824 TH	649	mmio_base = host->iomap[ADMA_MMIO_BAR];
edea3ab5 ML	650
	651	rc = adma_set_dma_masks(pdev, mmio_base);
	652	if (rc)
24dc5f33	653	return rc;
edea3ab5	654
5d728824 TH	655	for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
5d728824 TH	656	adma_ata_setup_port(&host->ports[port_no]->ioaddr,
0d5ff566	657	ADMA_ATA_REGS(mmio_base, port_no));
edea3ab5 ML	658
edea3ab5 ML	659	/* initialize adapter */
5d728824	660	adma_host_init(host, board_idx);
edea3ab5	661
5d728824 TH	662	pci_set_master(pdev);
	663	return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
	664	&adma_ata_sht);
edea3ab5 ML	665	}
	666
	667	static int __init adma_ata_init(void)
	668	{
b7887196	669	return pci_register_driver(&adma_ata_pci_driver);
edea3ab5 ML	670	}
	671
	672	static void __exit adma_ata_exit(void)
	673	{
	674	pci_unregister_driver(&adma_ata_pci_driver);
	675	}
	676
	677	MODULE_AUTHOR("Mark Lord");
	678	MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
	679	MODULE_LICENSE("GPL");
	680	MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
	681	MODULE_VERSION(DRV_VERSION);
	682
	683	module_init(adma_ata_init);
	684	module_exit(adma_ata_exit);