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edea3ab5 ML |
1 | /* |
2 | * pdc_adma.c - Pacific Digital Corporation ADMA | |
3 | * | |
4 | * Maintained by: Mark Lord <mlord@pobox.com> | |
5 | * | |
6 | * Copyright 2005 Mark Lord | |
7 | * | |
68399bb5 JG |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; see the file COPYING. If not, write to | |
20 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | * | |
23 | * libata documentation is available via 'make {ps|pdf}docs', | |
24 | * as Documentation/DocBook/libata.* | |
edea3ab5 | 25 | * |
edea3ab5 ML |
26 | * |
27 | * Supports ATA disks in single-packet ADMA mode. | |
28 | * Uses PIO for everything else. | |
29 | * | |
30 | * TODO: Use ADMA transfers for ATAPI devices, when possible. | |
31 | * This requires careful attention to a number of quirks of the chip. | |
32 | * | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
a9524a76 | 42 | #include <linux/device.h> |
edea3ab5 | 43 | #include <scsi/scsi_host.h> |
edea3ab5 ML |
44 | #include <linux/libata.h> |
45 | ||
46 | #define DRV_NAME "pdc_adma" | |
2a3103ce | 47 | #define DRV_VERSION "1.0" |
edea3ab5 ML |
48 | |
49 | /* macro to calculate base address for ATA regs */ | |
50 | #define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40)) | |
51 | ||
52 | /* macro to calculate base address for ADMA regs */ | |
0d5ff566 TH |
53 | #define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20)) |
54 | ||
5d728824 TH |
55 | /* macro to obtain addresses from ata_port */ |
56 | #define ADMA_PORT_REGS(ap) \ | |
57 | ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no) | |
edea3ab5 ML |
58 | |
59 | enum { | |
0d5ff566 TH |
60 | ADMA_MMIO_BAR = 4, |
61 | ||
edea3ab5 ML |
62 | ADMA_PORTS = 2, |
63 | ADMA_CPB_BYTES = 40, | |
64 | ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, | |
65 | ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES, | |
66 | ||
67 | ADMA_DMA_BOUNDARY = 0xffffffff, | |
68 | ||
69 | /* global register offsets */ | |
70 | ADMA_MODE_LOCK = 0x00c7, | |
71 | ||
72 | /* per-channel register offsets */ | |
73 | ADMA_CONTROL = 0x0000, /* ADMA control */ | |
74 | ADMA_STATUS = 0x0002, /* ADMA status */ | |
75 | ADMA_CPB_COUNT = 0x0004, /* CPB count */ | |
76 | ADMA_CPB_CURRENT = 0x000c, /* current CPB address */ | |
77 | ADMA_CPB_NEXT = 0x000c, /* next CPB address */ | |
78 | ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */ | |
79 | ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */ | |
80 | ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */ | |
81 | ||
82 | /* ADMA_CONTROL register bits */ | |
83 | aNIEN = (1 << 8), /* irq mask: 1==masked */ | |
84 | aGO = (1 << 7), /* packet trigger ("Go!") */ | |
85 | aRSTADM = (1 << 5), /* ADMA logic reset */ | |
edea3ab5 ML |
86 | aPIOMD4 = 0x0003, /* PIO mode 4 */ |
87 | ||
88 | /* ADMA_STATUS register bits */ | |
89 | aPSD = (1 << 6), | |
90 | aUIRQ = (1 << 4), | |
91 | aPERR = (1 << 0), | |
92 | ||
93 | /* CPB bits */ | |
94 | cDONE = (1 << 0), | |
640fdb50 JG |
95 | cATERR = (1 << 3), |
96 | ||
edea3ab5 ML |
97 | cVLD = (1 << 0), |
98 | cDAT = (1 << 2), | |
99 | cIEN = (1 << 3), | |
100 | ||
101 | /* PRD bits */ | |
102 | pORD = (1 << 4), | |
103 | pDIRO = (1 << 5), | |
104 | pEND = (1 << 7), | |
105 | ||
106 | /* ATA register flags */ | |
107 | rIGN = (1 << 5), | |
108 | rEND = (1 << 7), | |
109 | ||
110 | /* ATA register addresses */ | |
111 | ADMA_REGS_CONTROL = 0x0e, | |
112 | ADMA_REGS_SECTOR_COUNT = 0x12, | |
113 | ADMA_REGS_LBA_LOW = 0x13, | |
114 | ADMA_REGS_LBA_MID = 0x14, | |
115 | ADMA_REGS_LBA_HIGH = 0x15, | |
116 | ADMA_REGS_DEVICE = 0x16, | |
117 | ADMA_REGS_COMMAND = 0x17, | |
118 | ||
119 | /* PCI device IDs */ | |
120 | board_1841_idx = 0, /* ADMA 2-port controller */ | |
121 | }; | |
122 | ||
123 | typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t; | |
124 | ||
125 | struct adma_port_priv { | |
126 | u8 *pkt; | |
127 | dma_addr_t pkt_dma; | |
128 | adma_state_t state; | |
129 | }; | |
130 | ||
131 | static int adma_ata_init_one (struct pci_dev *pdev, | |
132 | const struct pci_device_id *ent); | |
edea3ab5 | 133 | static int adma_port_start(struct ata_port *ap); |
cca3974e | 134 | static void adma_host_stop(struct ata_host *host); |
edea3ab5 | 135 | static void adma_port_stop(struct ata_port *ap); |
edea3ab5 | 136 | static void adma_qc_prep(struct ata_queued_cmd *qc); |
9a3d9eb0 | 137 | static unsigned int adma_qc_issue(struct ata_queued_cmd *qc); |
edea3ab5 ML |
138 | static int adma_check_atapi_dma(struct ata_queued_cmd *qc); |
139 | static void adma_bmdma_stop(struct ata_queued_cmd *qc); | |
140 | static u8 adma_bmdma_status(struct ata_port *ap); | |
141 | static void adma_irq_clear(struct ata_port *ap); | |
640fdb50 JG |
142 | static void adma_freeze(struct ata_port *ap); |
143 | static void adma_thaw(struct ata_port *ap); | |
144 | static void adma_error_handler(struct ata_port *ap); | |
edea3ab5 | 145 | |
193515d5 | 146 | static struct scsi_host_template adma_ata_sht = { |
edea3ab5 ML |
147 | .module = THIS_MODULE, |
148 | .name = DRV_NAME, | |
149 | .ioctl = ata_scsi_ioctl, | |
150 | .queuecommand = ata_scsi_queuecmd, | |
49de0ac8 JG |
151 | .slave_configure = ata_scsi_slave_config, |
152 | .slave_destroy = ata_scsi_slave_destroy, | |
153 | .bios_param = ata_std_bios_param, | |
154 | .proc_name = DRV_NAME, | |
edea3ab5 ML |
155 | .can_queue = ATA_DEF_QUEUE, |
156 | .this_id = ATA_SHT_THIS_ID, | |
157 | .sg_tablesize = LIBATA_MAX_PRD, | |
49de0ac8 | 158 | .dma_boundary = ADMA_DMA_BOUNDARY, |
edea3ab5 | 159 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
edea3ab5 | 160 | .use_clustering = ENABLE_CLUSTERING, |
49de0ac8 | 161 | .emulated = ATA_SHT_EMULATED, |
edea3ab5 ML |
162 | }; |
163 | ||
057ace5e | 164 | static const struct ata_port_operations adma_ata_ops = { |
edea3ab5 ML |
165 | .port_disable = ata_port_disable, |
166 | .tf_load = ata_tf_load, | |
167 | .tf_read = ata_tf_read, | |
edea3ab5 | 168 | .exec_command = ata_exec_command, |
49de0ac8 | 169 | .check_status = ata_check_status, |
edea3ab5 | 170 | .dev_select = ata_std_dev_select, |
49de0ac8 JG |
171 | .check_atapi_dma = adma_check_atapi_dma, |
172 | .data_xfer = ata_data_xfer, | |
edea3ab5 ML |
173 | .qc_prep = adma_qc_prep, |
174 | .qc_issue = adma_qc_issue, | |
640fdb50 JG |
175 | .freeze = adma_freeze, |
176 | .thaw = adma_thaw, | |
177 | .error_handler = adma_error_handler, | |
edea3ab5 | 178 | .irq_clear = adma_irq_clear, |
246ce3b6 AI |
179 | .irq_on = ata_irq_on, |
180 | .irq_ack = ata_irq_ack, | |
edea3ab5 ML |
181 | .port_start = adma_port_start, |
182 | .port_stop = adma_port_stop, | |
183 | .host_stop = adma_host_stop, | |
184 | .bmdma_stop = adma_bmdma_stop, | |
185 | .bmdma_status = adma_bmdma_status, | |
186 | }; | |
187 | ||
188 | static struct ata_port_info adma_port_info[] = { | |
189 | /* board_1841_idx */ | |
190 | { | |
640fdb50 | 191 | .flags = ATA_FLAG_SLAVE_POSS | |
51704c60 AL |
192 | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | |
193 | ATA_FLAG_PIO_POLLING, | |
edea3ab5 | 194 | .pio_mask = 0x10, /* pio4 */ |
bf6263a8 | 195 | .udma_mask = ATA_UDMA4, |
edea3ab5 ML |
196 | .port_ops = &adma_ata_ops, |
197 | }, | |
198 | }; | |
199 | ||
3b7d697d | 200 | static const struct pci_device_id adma_ata_pci_tbl[] = { |
54bb3a94 | 201 | { PCI_VDEVICE(PDC, 0x1841), board_1841_idx }, |
edea3ab5 ML |
202 | |
203 | { } /* terminate list */ | |
204 | }; | |
205 | ||
206 | static struct pci_driver adma_ata_pci_driver = { | |
207 | .name = DRV_NAME, | |
208 | .id_table = adma_ata_pci_tbl, | |
209 | .probe = adma_ata_init_one, | |
210 | .remove = ata_pci_remove_one, | |
211 | }; | |
212 | ||
213 | static int adma_check_atapi_dma(struct ata_queued_cmd *qc) | |
214 | { | |
215 | return 1; /* ATAPI DMA not yet supported */ | |
216 | } | |
217 | ||
218 | static void adma_bmdma_stop(struct ata_queued_cmd *qc) | |
219 | { | |
220 | /* nothing */ | |
221 | } | |
222 | ||
223 | static u8 adma_bmdma_status(struct ata_port *ap) | |
224 | { | |
225 | return 0; | |
226 | } | |
227 | ||
228 | static void adma_irq_clear(struct ata_port *ap) | |
229 | { | |
230 | /* nothing */ | |
231 | } | |
232 | ||
5d728824 | 233 | static void adma_reset_engine(struct ata_port *ap) |
edea3ab5 | 234 | { |
5d728824 TH |
235 | void __iomem *chan = ADMA_PORT_REGS(ap); |
236 | ||
edea3ab5 ML |
237 | /* reset ADMA to idle state */ |
238 | writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); | |
239 | udelay(2); | |
240 | writew(aPIOMD4, chan + ADMA_CONTROL); | |
241 | udelay(2); | |
242 | } | |
243 | ||
244 | static void adma_reinit_engine(struct ata_port *ap) | |
245 | { | |
246 | struct adma_port_priv *pp = ap->private_data; | |
5d728824 | 247 | void __iomem *chan = ADMA_PORT_REGS(ap); |
edea3ab5 ML |
248 | |
249 | /* mask/clear ATA interrupts */ | |
0d5ff566 | 250 | writeb(ATA_NIEN, ap->ioaddr.ctl_addr); |
edea3ab5 ML |
251 | ata_check_status(ap); |
252 | ||
253 | /* reset the ADMA engine */ | |
5d728824 | 254 | adma_reset_engine(ap); |
edea3ab5 ML |
255 | |
256 | /* set in-FIFO threshold to 0x100 */ | |
257 | writew(0x100, chan + ADMA_FIFO_IN); | |
258 | ||
259 | /* set CPB pointer */ | |
260 | writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT); | |
261 | ||
262 | /* set out-FIFO threshold to 0x100 */ | |
263 | writew(0x100, chan + ADMA_FIFO_OUT); | |
264 | ||
265 | /* set CPB count */ | |
266 | writew(1, chan + ADMA_CPB_COUNT); | |
267 | ||
268 | /* read/discard ADMA status */ | |
269 | readb(chan + ADMA_STATUS); | |
270 | } | |
271 | ||
272 | static inline void adma_enter_reg_mode(struct ata_port *ap) | |
273 | { | |
5d728824 | 274 | void __iomem *chan = ADMA_PORT_REGS(ap); |
edea3ab5 ML |
275 | |
276 | writew(aPIOMD4, chan + ADMA_CONTROL); | |
277 | readb(chan + ADMA_STATUS); /* flush */ | |
278 | } | |
279 | ||
640fdb50 | 280 | static void adma_freeze(struct ata_port *ap) |
edea3ab5 | 281 | { |
640fdb50 JG |
282 | void __iomem *chan = ADMA_PORT_REGS(ap); |
283 | ||
284 | /* mask/clear ATA interrupts */ | |
285 | writeb(ATA_NIEN, ap->ioaddr.ctl_addr); | |
286 | ata_check_status(ap); | |
287 | ||
288 | /* reset ADMA to idle state */ | |
289 | writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); | |
290 | udelay(2); | |
291 | writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL); | |
292 | udelay(2); | |
293 | } | |
edea3ab5 | 294 | |
640fdb50 JG |
295 | static void adma_thaw(struct ata_port *ap) |
296 | { | |
edea3ab5 | 297 | adma_reinit_engine(ap); |
edea3ab5 ML |
298 | } |
299 | ||
640fdb50 | 300 | static int adma_prereset(struct ata_port *ap, unsigned long deadline) |
edea3ab5 ML |
301 | { |
302 | struct adma_port_priv *pp = ap->private_data; | |
303 | ||
304 | if (pp->state != adma_state_idle) /* healthy paranoia */ | |
305 | pp->state = adma_state_mmio; | |
306 | adma_reinit_engine(ap); | |
640fdb50 JG |
307 | |
308 | return ata_std_prereset(ap, deadline); | |
309 | } | |
310 | ||
311 | static void adma_error_handler(struct ata_port *ap) | |
312 | { | |
313 | ata_do_eh(ap, adma_prereset, ata_std_softreset, NULL, | |
314 | ata_std_postreset); | |
edea3ab5 ML |
315 | } |
316 | ||
317 | static int adma_fill_sg(struct ata_queued_cmd *qc) | |
318 | { | |
972c26bd | 319 | struct scatterlist *sg; |
edea3ab5 ML |
320 | struct ata_port *ap = qc->ap; |
321 | struct adma_port_priv *pp = ap->private_data; | |
322 | u8 *buf = pp->pkt; | |
972c26bd | 323 | int i = (2 + buf[3]) * 8; |
edea3ab5 ML |
324 | u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0); |
325 | ||
972c26bd | 326 | ata_for_each_sg(sg, qc) { |
edea3ab5 ML |
327 | u32 addr; |
328 | u32 len; | |
329 | ||
330 | addr = (u32)sg_dma_address(sg); | |
331 | *(__le32 *)(buf + i) = cpu_to_le32(addr); | |
332 | i += 4; | |
333 | ||
334 | len = sg_dma_len(sg) >> 3; | |
335 | *(__le32 *)(buf + i) = cpu_to_le32(len); | |
336 | i += 4; | |
337 | ||
972c26bd | 338 | if (ata_sg_is_last(sg, qc)) |
edea3ab5 ML |
339 | pFLAGS |= pEND; |
340 | buf[i++] = pFLAGS; | |
341 | buf[i++] = qc->dev->dma_mode & 0xf; | |
342 | buf[i++] = 0; /* pPKLW */ | |
343 | buf[i++] = 0; /* reserved */ | |
344 | ||
345 | *(__le32 *)(buf + i) | |
346 | = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4); | |
347 | i += 4; | |
348 | ||
db7f44d9 | 349 | VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4, |
edea3ab5 ML |
350 | (unsigned long)addr, len); |
351 | } | |
352 | return i; | |
353 | } | |
354 | ||
355 | static void adma_qc_prep(struct ata_queued_cmd *qc) | |
356 | { | |
357 | struct adma_port_priv *pp = qc->ap->private_data; | |
358 | u8 *buf = pp->pkt; | |
359 | u32 pkt_dma = (u32)pp->pkt_dma; | |
360 | int i = 0; | |
361 | ||
362 | VPRINTK("ENTER\n"); | |
363 | ||
364 | adma_enter_reg_mode(qc->ap); | |
365 | if (qc->tf.protocol != ATA_PROT_DMA) { | |
366 | ata_qc_prep(qc); | |
367 | return; | |
368 | } | |
369 | ||
370 | buf[i++] = 0; /* Response flags */ | |
371 | buf[i++] = 0; /* reserved */ | |
372 | buf[i++] = cVLD | cDAT | cIEN; | |
373 | i++; /* cLEN, gets filled in below */ | |
374 | ||
375 | *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */ | |
376 | i += 4; /* cNCPB */ | |
377 | i += 4; /* cPRD, gets filled in below */ | |
378 | ||
379 | buf[i++] = 0; /* reserved */ | |
380 | buf[i++] = 0; /* reserved */ | |
381 | buf[i++] = 0; /* reserved */ | |
382 | buf[i++] = 0; /* reserved */ | |
383 | ||
384 | /* ATA registers; must be a multiple of 4 */ | |
385 | buf[i++] = qc->tf.device; | |
386 | buf[i++] = ADMA_REGS_DEVICE; | |
387 | if ((qc->tf.flags & ATA_TFLAG_LBA48)) { | |
388 | buf[i++] = qc->tf.hob_nsect; | |
389 | buf[i++] = ADMA_REGS_SECTOR_COUNT; | |
390 | buf[i++] = qc->tf.hob_lbal; | |
391 | buf[i++] = ADMA_REGS_LBA_LOW; | |
392 | buf[i++] = qc->tf.hob_lbam; | |
393 | buf[i++] = ADMA_REGS_LBA_MID; | |
394 | buf[i++] = qc->tf.hob_lbah; | |
395 | buf[i++] = ADMA_REGS_LBA_HIGH; | |
396 | } | |
397 | buf[i++] = qc->tf.nsect; | |
398 | buf[i++] = ADMA_REGS_SECTOR_COUNT; | |
399 | buf[i++] = qc->tf.lbal; | |
400 | buf[i++] = ADMA_REGS_LBA_LOW; | |
401 | buf[i++] = qc->tf.lbam; | |
402 | buf[i++] = ADMA_REGS_LBA_MID; | |
403 | buf[i++] = qc->tf.lbah; | |
404 | buf[i++] = ADMA_REGS_LBA_HIGH; | |
405 | buf[i++] = 0; | |
406 | buf[i++] = ADMA_REGS_CONTROL; | |
407 | buf[i++] = rIGN; | |
408 | buf[i++] = 0; | |
409 | buf[i++] = qc->tf.command; | |
410 | buf[i++] = ADMA_REGS_COMMAND | rEND; | |
411 | ||
412 | buf[3] = (i >> 3) - 2; /* cLEN */ | |
413 | *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */ | |
414 | ||
415 | i = adma_fill_sg(qc); | |
416 | wmb(); /* flush PRDs and pkt to memory */ | |
417 | #if 0 | |
418 | /* dump out CPB + PRDs for debug */ | |
419 | { | |
420 | int j, len = 0; | |
421 | static char obuf[2048]; | |
422 | for (j = 0; j < i; ++j) { | |
423 | len += sprintf(obuf+len, "%02x ", buf[j]); | |
424 | if ((j & 7) == 7) { | |
425 | printk("%s\n", obuf); | |
426 | len = 0; | |
427 | } | |
428 | } | |
429 | if (len) | |
430 | printk("%s\n", obuf); | |
431 | } | |
432 | #endif | |
433 | } | |
434 | ||
435 | static inline void adma_packet_start(struct ata_queued_cmd *qc) | |
436 | { | |
437 | struct ata_port *ap = qc->ap; | |
5d728824 | 438 | void __iomem *chan = ADMA_PORT_REGS(ap); |
edea3ab5 ML |
439 | |
440 | VPRINTK("ENTER, ap %p\n", ap); | |
441 | ||
442 | /* fire up the ADMA engine */ | |
68399bb5 | 443 | writew(aPIOMD4 | aGO, chan + ADMA_CONTROL); |
edea3ab5 ML |
444 | } |
445 | ||
9a3d9eb0 | 446 | static unsigned int adma_qc_issue(struct ata_queued_cmd *qc) |
edea3ab5 ML |
447 | { |
448 | struct adma_port_priv *pp = qc->ap->private_data; | |
449 | ||
450 | switch (qc->tf.protocol) { | |
451 | case ATA_PROT_DMA: | |
452 | pp->state = adma_state_pkt; | |
453 | adma_packet_start(qc); | |
454 | return 0; | |
455 | ||
456 | case ATA_PROT_ATAPI_DMA: | |
457 | BUG(); | |
458 | break; | |
459 | ||
460 | default: | |
461 | break; | |
462 | } | |
463 | ||
464 | pp->state = adma_state_mmio; | |
465 | return ata_qc_issue_prot(qc); | |
466 | } | |
467 | ||
cca3974e | 468 | static inline unsigned int adma_intr_pkt(struct ata_host *host) |
edea3ab5 ML |
469 | { |
470 | unsigned int handled = 0, port_no; | |
edea3ab5 | 471 | |
cca3974e JG |
472 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
473 | struct ata_port *ap = host->ports[port_no]; | |
edea3ab5 ML |
474 | struct adma_port_priv *pp; |
475 | struct ata_queued_cmd *qc; | |
5d728824 | 476 | void __iomem *chan = ADMA_PORT_REGS(ap); |
a7dac447 | 477 | u8 status = readb(chan + ADMA_STATUS); |
edea3ab5 ML |
478 | |
479 | if (status == 0) | |
480 | continue; | |
481 | handled = 1; | |
482 | adma_enter_reg_mode(ap); | |
029f5468 | 483 | if (ap->flags & ATA_FLAG_DISABLED) |
edea3ab5 ML |
484 | continue; |
485 | pp = ap->private_data; | |
486 | if (!pp || pp->state != adma_state_pkt) | |
487 | continue; | |
488 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
94ec1ef1 | 489 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
640fdb50 JG |
490 | if (status & aPERR) |
491 | qc->err_mask |= AC_ERR_HOST_BUS; | |
492 | else if ((status & (aPSD | aUIRQ))) | |
a22e2eb0 | 493 | qc->err_mask |= AC_ERR_OTHER; |
640fdb50 JG |
494 | |
495 | if (pp->pkt[0] & cATERR) | |
496 | qc->err_mask |= AC_ERR_DEV; | |
a21a84a3 | 497 | else if (pp->pkt[0] != cDONE) |
a22e2eb0 | 498 | qc->err_mask |= AC_ERR_OTHER; |
a7dac447 | 499 | |
640fdb50 JG |
500 | if (!qc->err_mask) |
501 | ata_qc_complete(qc); | |
502 | else { | |
503 | struct ata_eh_info *ehi = &ap->eh_info; | |
504 | ata_ehi_clear_desc(ehi); | |
505 | ata_ehi_push_desc(ehi, | |
506 | "ADMA-status 0x%02X", status); | |
507 | ata_ehi_push_desc(ehi, | |
508 | "pkt[0] 0x%02X", pp->pkt[0]); | |
509 | ||
510 | if (qc->err_mask == AC_ERR_DEV) | |
511 | ata_port_abort(ap); | |
512 | else | |
513 | ata_port_freeze(ap); | |
514 | } | |
a21a84a3 | 515 | } |
edea3ab5 ML |
516 | } |
517 | return handled; | |
518 | } | |
519 | ||
cca3974e | 520 | static inline unsigned int adma_intr_mmio(struct ata_host *host) |
edea3ab5 ML |
521 | { |
522 | unsigned int handled = 0, port_no; | |
523 | ||
cca3974e | 524 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
edea3ab5 | 525 | struct ata_port *ap; |
cca3974e | 526 | ap = host->ports[port_no]; |
029f5468 | 527 | if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) { |
edea3ab5 ML |
528 | struct ata_queued_cmd *qc; |
529 | struct adma_port_priv *pp = ap->private_data; | |
530 | if (!pp || pp->state != adma_state_mmio) | |
531 | continue; | |
532 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
be697c3f | 533 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
edea3ab5 ML |
534 | |
535 | /* check main status, clearing INTRQ */ | |
ac19bff2 | 536 | u8 status = ata_check_status(ap); |
edea3ab5 ML |
537 | if ((status & ATA_BUSY)) |
538 | continue; | |
539 | DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n", | |
44877b4e | 540 | ap->print_id, qc->tf.protocol, status); |
9bec2e38 | 541 | |
edea3ab5 ML |
542 | /* complete taskfile transaction */ |
543 | pp->state = adma_state_idle; | |
a22e2eb0 | 544 | qc->err_mask |= ac_err_mask(status); |
640fdb50 JG |
545 | if (!qc->err_mask) |
546 | ata_qc_complete(qc); | |
547 | else { | |
548 | struct ata_eh_info *ehi = &ap->eh_info; | |
549 | ata_ehi_clear_desc(ehi); | |
550 | ata_ehi_push_desc(ehi, | |
551 | "status 0x%02X", status); | |
552 | ||
553 | if (qc->err_mask == AC_ERR_DEV) | |
554 | ata_port_abort(ap); | |
555 | else | |
556 | ata_port_freeze(ap); | |
557 | } | |
edea3ab5 ML |
558 | handled = 1; |
559 | } | |
560 | } | |
561 | } | |
562 | return handled; | |
563 | } | |
564 | ||
7d12e780 | 565 | static irqreturn_t adma_intr(int irq, void *dev_instance) |
edea3ab5 | 566 | { |
cca3974e | 567 | struct ata_host *host = dev_instance; |
edea3ab5 ML |
568 | unsigned int handled = 0; |
569 | ||
570 | VPRINTK("ENTER\n"); | |
571 | ||
cca3974e JG |
572 | spin_lock(&host->lock); |
573 | handled = adma_intr_pkt(host) | adma_intr_mmio(host); | |
574 | spin_unlock(&host->lock); | |
edea3ab5 ML |
575 | |
576 | VPRINTK("EXIT\n"); | |
577 | ||
578 | return IRQ_RETVAL(handled); | |
579 | } | |
580 | ||
0d5ff566 | 581 | static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base) |
edea3ab5 ML |
582 | { |
583 | port->cmd_addr = | |
584 | port->data_addr = base + 0x000; | |
585 | port->error_addr = | |
586 | port->feature_addr = base + 0x004; | |
587 | port->nsect_addr = base + 0x008; | |
588 | port->lbal_addr = base + 0x00c; | |
589 | port->lbam_addr = base + 0x010; | |
590 | port->lbah_addr = base + 0x014; | |
591 | port->device_addr = base + 0x018; | |
592 | port->status_addr = | |
593 | port->command_addr = base + 0x01c; | |
594 | port->altstatus_addr = | |
595 | port->ctl_addr = base + 0x038; | |
596 | } | |
597 | ||
598 | static int adma_port_start(struct ata_port *ap) | |
599 | { | |
cca3974e | 600 | struct device *dev = ap->host->dev; |
edea3ab5 ML |
601 | struct adma_port_priv *pp; |
602 | int rc; | |
603 | ||
604 | rc = ata_port_start(ap); | |
605 | if (rc) | |
606 | return rc; | |
607 | adma_enter_reg_mode(ap); | |
24dc5f33 | 608 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
edea3ab5 | 609 | if (!pp) |
24dc5f33 TH |
610 | return -ENOMEM; |
611 | pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma, | |
612 | GFP_KERNEL); | |
edea3ab5 | 613 | if (!pp->pkt) |
24dc5f33 | 614 | return -ENOMEM; |
edea3ab5 ML |
615 | /* paranoia? */ |
616 | if ((pp->pkt_dma & 7) != 0) { | |
617 | printk("bad alignment for pp->pkt_dma: %08x\n", | |
618 | (u32)pp->pkt_dma); | |
24dc5f33 | 619 | return -ENOMEM; |
edea3ab5 ML |
620 | } |
621 | memset(pp->pkt, 0, ADMA_PKT_BYTES); | |
622 | ap->private_data = pp; | |
623 | adma_reinit_engine(ap); | |
624 | return 0; | |
edea3ab5 ML |
625 | } |
626 | ||
627 | static void adma_port_stop(struct ata_port *ap) | |
628 | { | |
5d728824 | 629 | adma_reset_engine(ap); |
edea3ab5 ML |
630 | } |
631 | ||
cca3974e | 632 | static void adma_host_stop(struct ata_host *host) |
edea3ab5 ML |
633 | { |
634 | unsigned int port_no; | |
635 | ||
636 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) | |
5d728824 | 637 | adma_reset_engine(host->ports[port_no]); |
edea3ab5 ML |
638 | } |
639 | ||
5d728824 | 640 | static void adma_host_init(struct ata_host *host, unsigned int chip_id) |
edea3ab5 ML |
641 | { |
642 | unsigned int port_no; | |
edea3ab5 ML |
643 | |
644 | /* enable/lock aGO operation */ | |
5d728824 | 645 | writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK); |
edea3ab5 ML |
646 | |
647 | /* reset the ADMA logic */ | |
648 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) | |
5d728824 | 649 | adma_reset_engine(host->ports[port_no]); |
edea3ab5 ML |
650 | } |
651 | ||
652 | static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) | |
653 | { | |
654 | int rc; | |
655 | ||
656 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
657 | if (rc) { | |
a9524a76 JG |
658 | dev_printk(KERN_ERR, &pdev->dev, |
659 | "32-bit DMA enable failed\n"); | |
edea3ab5 ML |
660 | return rc; |
661 | } | |
662 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
663 | if (rc) { | |
a9524a76 JG |
664 | dev_printk(KERN_ERR, &pdev->dev, |
665 | "32-bit consistent DMA enable failed\n"); | |
edea3ab5 ML |
666 | return rc; |
667 | } | |
668 | return 0; | |
669 | } | |
670 | ||
671 | static int adma_ata_init_one(struct pci_dev *pdev, | |
0d5ff566 | 672 | const struct pci_device_id *ent) |
edea3ab5 ML |
673 | { |
674 | static int printed_version; | |
edea3ab5 | 675 | unsigned int board_idx = (unsigned int) ent->driver_data; |
5d728824 TH |
676 | const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL }; |
677 | struct ata_host *host; | |
678 | void __iomem *mmio_base; | |
edea3ab5 ML |
679 | int rc, port_no; |
680 | ||
681 | if (!printed_version++) | |
a9524a76 | 682 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
edea3ab5 | 683 | |
5d728824 TH |
684 | /* alloc host */ |
685 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS); | |
686 | if (!host) | |
687 | return -ENOMEM; | |
688 | ||
689 | /* acquire resources and fill host */ | |
24dc5f33 | 690 | rc = pcim_enable_device(pdev); |
edea3ab5 ML |
691 | if (rc) |
692 | return rc; | |
693 | ||
24dc5f33 TH |
694 | if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) |
695 | return -ENODEV; | |
edea3ab5 | 696 | |
0d5ff566 TH |
697 | rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME); |
698 | if (rc) | |
699 | return rc; | |
5d728824 TH |
700 | host->iomap = pcim_iomap_table(pdev); |
701 | mmio_base = host->iomap[ADMA_MMIO_BAR]; | |
edea3ab5 ML |
702 | |
703 | rc = adma_set_dma_masks(pdev, mmio_base); | |
704 | if (rc) | |
24dc5f33 | 705 | return rc; |
edea3ab5 | 706 | |
5d728824 TH |
707 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) |
708 | adma_ata_setup_port(&host->ports[port_no]->ioaddr, | |
0d5ff566 | 709 | ADMA_ATA_REGS(mmio_base, port_no)); |
edea3ab5 ML |
710 | |
711 | /* initialize adapter */ | |
5d728824 | 712 | adma_host_init(host, board_idx); |
edea3ab5 | 713 | |
5d728824 TH |
714 | pci_set_master(pdev); |
715 | return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED, | |
716 | &adma_ata_sht); | |
edea3ab5 ML |
717 | } |
718 | ||
719 | static int __init adma_ata_init(void) | |
720 | { | |
b7887196 | 721 | return pci_register_driver(&adma_ata_pci_driver); |
edea3ab5 ML |
722 | } |
723 | ||
724 | static void __exit adma_ata_exit(void) | |
725 | { | |
726 | pci_unregister_driver(&adma_ata_pci_driver); | |
727 | } | |
728 | ||
729 | MODULE_AUTHOR("Mark Lord"); | |
730 | MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver"); | |
731 | MODULE_LICENSE("GPL"); | |
732 | MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl); | |
733 | MODULE_VERSION(DRV_VERSION); | |
734 | ||
735 | module_init(adma_ata_init); | |
736 | module_exit(adma_ata_exit); |