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62936009 RS |
1 | /* |
2 | * drivers/ata/sata_dwc_460ex.c | |
3 | * | |
4 | * Synopsys DesignWare Cores (DWC) SATA host driver | |
5 | * | |
6 | * Author: Mark Miesfeld <mmiesfeld@amcc.com> | |
7 | * | |
8 | * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de> | |
9 | * Copyright 2008 DENX Software Engineering | |
10 | * | |
11 | * Based on versions provided by AMCC and Synopsys which are: | |
12 | * Copyright 2006 Applied Micro Circuits Corporation | |
13 | * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | */ | |
20 | ||
21 | #ifdef CONFIG_SATA_DWC_DEBUG | |
22 | #define DEBUG | |
23 | #endif | |
24 | ||
25 | #ifdef CONFIG_SATA_DWC_VDEBUG | |
26 | #define VERBOSE_DEBUG | |
27 | #define DEBUG_NCQ | |
28 | #endif | |
29 | ||
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
62936009 | 32 | #include <linux/device.h> |
50b43375 | 33 | #include <linux/dmaengine.h> |
c11eede6 RH |
34 | #include <linux/of_address.h> |
35 | #include <linux/of_irq.h> | |
62936009 RS |
36 | #include <linux/of_platform.h> |
37 | #include <linux/platform_device.h> | |
0f48debd | 38 | #include <linux/phy/phy.h> |
62936009 RS |
39 | #include <linux/libata.h> |
40 | #include <linux/slab.h> | |
8b344485 | 41 | |
62936009 RS |
42 | #include "libata.h" |
43 | ||
44 | #include <scsi/scsi_host.h> | |
45 | #include <scsi/scsi_cmnd.h> | |
46 | ||
c211962d SS |
47 | /* These two are defined in "libata.h" */ |
48 | #undef DRV_NAME | |
49 | #undef DRV_VERSION | |
72d5f2da | 50 | |
62936009 | 51 | #define DRV_NAME "sata-dwc" |
84b47e3b | 52 | #define DRV_VERSION "1.3" |
62936009 | 53 | |
84683a7e AS |
54 | #ifndef out_le32 |
55 | #define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (void __iomem *)(a)) | |
56 | #endif | |
57 | ||
58 | #ifndef in_le32 | |
59 | #define in_le32(a) __le32_to_cpu(__raw_readl((void __iomem *)(a))) | |
60 | #endif | |
61 | ||
62 | #ifndef NO_IRQ | |
63 | #define NO_IRQ 0 | |
64 | #endif | |
65 | ||
4ea8c205 | 66 | #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */ |
62936009 | 67 | |
62936009 | 68 | enum { |
62936009 RS |
69 | SATA_DWC_MAX_PORTS = 1, |
70 | ||
71 | SATA_DWC_SCR_OFFSET = 0x24, | |
72 | SATA_DWC_REG_OFFSET = 0x64, | |
73 | }; | |
74 | ||
75 | /* DWC SATA Registers */ | |
76 | struct sata_dwc_regs { | |
77 | u32 fptagr; /* 1st party DMA tag */ | |
78 | u32 fpbor; /* 1st party DMA buffer offset */ | |
79 | u32 fptcr; /* 1st party DMA Xfr count */ | |
80 | u32 dmacr; /* DMA Control */ | |
81 | u32 dbtsr; /* DMA Burst Transac size */ | |
82 | u32 intpr; /* Interrupt Pending */ | |
83 | u32 intmr; /* Interrupt Mask */ | |
84 | u32 errmr; /* Error Mask */ | |
85 | u32 llcr; /* Link Layer Control */ | |
86 | u32 phycr; /* PHY Control */ | |
87 | u32 physr; /* PHY Status */ | |
88 | u32 rxbistpd; /* Recvd BIST pattern def register */ | |
89 | u32 rxbistpd1; /* Recvd BIST data dword1 */ | |
90 | u32 rxbistpd2; /* Recvd BIST pattern data dword2 */ | |
91 | u32 txbistpd; /* Trans BIST pattern def register */ | |
92 | u32 txbistpd1; /* Trans BIST data dword1 */ | |
93 | u32 txbistpd2; /* Trans BIST data dword2 */ | |
94 | u32 bistcr; /* BIST Control Register */ | |
95 | u32 bistfctr; /* BIST FIS Count Register */ | |
96 | u32 bistsr; /* BIST Status Register */ | |
97 | u32 bistdecr; /* BIST Dword Error count register */ | |
98 | u32 res[15]; /* Reserved locations */ | |
99 | u32 testr; /* Test Register */ | |
100 | u32 versionr; /* Version Register */ | |
101 | u32 idr; /* ID Register */ | |
102 | u32 unimpl[192]; /* Unimplemented */ | |
103 | u32 dmadr[256]; /* FIFO Locations in DMA Mode */ | |
104 | }; | |
105 | ||
106 | enum { | |
107 | SCR_SCONTROL_DET_ENABLE = 0x00000001, | |
108 | SCR_SSTATUS_DET_PRESENT = 0x00000001, | |
109 | SCR_SERROR_DIAG_X = 0x04000000, | |
110 | /* DWC SATA Register Operations */ | |
111 | SATA_DWC_TXFIFO_DEPTH = 0x01FF, | |
112 | SATA_DWC_RXFIFO_DEPTH = 0x01FF, | |
113 | SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004, | |
114 | SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN), | |
115 | SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN), | |
116 | SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN, | |
117 | SATA_DWC_INTPR_DMAT = 0x00000001, | |
118 | SATA_DWC_INTPR_NEWFP = 0x00000002, | |
119 | SATA_DWC_INTPR_PMABRT = 0x00000004, | |
120 | SATA_DWC_INTPR_ERR = 0x00000008, | |
121 | SATA_DWC_INTPR_NEWBIST = 0x00000010, | |
122 | SATA_DWC_INTPR_IPF = 0x10000000, | |
123 | SATA_DWC_INTMR_DMATM = 0x00000001, | |
124 | SATA_DWC_INTMR_NEWFPM = 0x00000002, | |
125 | SATA_DWC_INTMR_PMABRTM = 0x00000004, | |
126 | SATA_DWC_INTMR_ERRM = 0x00000008, | |
127 | SATA_DWC_INTMR_NEWBISTM = 0x00000010, | |
128 | SATA_DWC_LLCR_SCRAMEN = 0x00000001, | |
129 | SATA_DWC_LLCR_DESCRAMEN = 0x00000002, | |
130 | SATA_DWC_LLCR_RPDEN = 0x00000004, | |
131 | /* This is all error bits, zero's are reserved fields. */ | |
132 | SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03 | |
133 | }; | |
134 | ||
135 | #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F) | |
136 | #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\ | |
137 | SATA_DWC_DMACR_TMOD_TXCHEN) | |
138 | #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\ | |
139 | SATA_DWC_DMACR_TMOD_TXCHEN) | |
140 | #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH) | |
141 | #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\ | |
142 | << 16) | |
143 | struct sata_dwc_device { | |
144 | struct device *dev; /* generic device struct */ | |
145 | struct ata_probe_ent *pe; /* ptr to probe-ent */ | |
146 | struct ata_host *host; | |
d7c256e8 | 147 | u8 __iomem *reg_base; |
62936009 | 148 | struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */ |
2d20da00 MR |
149 | u32 sactive_issued; |
150 | u32 sactive_queued; | |
0f48debd | 151 | struct phy *phy; |
50b43375 | 152 | #ifdef CONFIG_SATA_DWC_OLD_DMA |
8b344485 | 153 | struct dw_dma_chip *dma; |
50b43375 | 154 | #endif |
62936009 RS |
155 | }; |
156 | ||
157 | #define SATA_DWC_QCMD_MAX 32 | |
158 | ||
159 | struct sata_dwc_device_port { | |
160 | struct sata_dwc_device *hsdev; | |
161 | int cmd_issued[SATA_DWC_QCMD_MAX]; | |
62936009 | 162 | int dma_pending[SATA_DWC_QCMD_MAX]; |
8b344485 AS |
163 | |
164 | /* DMA info */ | |
8b344485 AS |
165 | struct dma_chan *chan; |
166 | struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX]; | |
167 | u32 dma_interrupt_count; | |
62936009 RS |
168 | }; |
169 | ||
170 | /* | |
4bb41be5 | 171 | * Commonly used DWC SATA driver macros |
62936009 | 172 | */ |
4bb41be5 AS |
173 | #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data) |
174 | #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data) | |
175 | #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data) | |
176 | #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data) | |
177 | #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev) | |
62936009 RS |
178 | |
179 | enum { | |
180 | SATA_DWC_CMD_ISSUED_NOT = 0, | |
181 | SATA_DWC_CMD_ISSUED_PEND = 1, | |
182 | SATA_DWC_CMD_ISSUED_EXEC = 2, | |
183 | SATA_DWC_CMD_ISSUED_NODATA = 3, | |
184 | ||
185 | SATA_DWC_DMA_PENDING_NONE = 0, | |
186 | SATA_DWC_DMA_PENDING_TX = 1, | |
187 | SATA_DWC_DMA_PENDING_RX = 2, | |
188 | }; | |
189 | ||
62936009 RS |
190 | /* |
191 | * Prototypes | |
192 | */ | |
193 | static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag); | |
194 | static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc, | |
195 | u32 check_status); | |
196 | static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status); | |
197 | static void sata_dwc_port_stop(struct ata_port *ap); | |
198 | static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag); | |
62936009 | 199 | |
50b43375 MR |
200 | #ifdef CONFIG_SATA_DWC_OLD_DMA |
201 | ||
202 | #include <linux/platform_data/dma-dw.h> | |
203 | #include <linux/dma/dw.h> | |
204 | ||
205 | static struct dw_dma_slave sata_dwc_dma_dws = { | |
206 | .src_id = 0, | |
207 | .dst_id = 0, | |
208 | .m_master = 1, | |
209 | .p_master = 0, | |
210 | }; | |
211 | ||
212 | static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param) | |
213 | { | |
214 | struct dw_dma_slave *dws = &sata_dwc_dma_dws; | |
215 | ||
216 | if (dws->dma_dev != chan->device->dev) | |
217 | return false; | |
218 | ||
219 | chan->private = dws; | |
220 | return true; | |
221 | } | |
222 | ||
223 | static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp) | |
224 | { | |
225 | struct sata_dwc_device *hsdev = hsdevp->hsdev; | |
226 | struct dw_dma_slave *dws = &sata_dwc_dma_dws; | |
227 | dma_cap_mask_t mask; | |
228 | ||
229 | dws->dma_dev = hsdev->dev; | |
230 | ||
231 | dma_cap_zero(mask); | |
232 | dma_cap_set(DMA_SLAVE, mask); | |
233 | ||
234 | /* Acquire DMA channel */ | |
235 | hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp); | |
236 | if (!hsdevp->chan) { | |
237 | dev_err(hsdev->dev, "%s: dma channel unavailable\n", | |
238 | __func__); | |
239 | return -EAGAIN; | |
240 | } | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static int sata_dwc_dma_init_old(struct platform_device *pdev, | |
246 | struct sata_dwc_device *hsdev) | |
247 | { | |
248 | struct device_node *np = pdev->dev.of_node; | |
249 | int err; | |
250 | ||
251 | hsdev->dma = devm_kzalloc(&pdev->dev, sizeof(*hsdev->dma), GFP_KERNEL); | |
252 | if (!hsdev->dma) | |
253 | return -ENOMEM; | |
254 | ||
255 | hsdev->dma->dev = &pdev->dev; | |
256 | ||
257 | /* Get SATA DMA interrupt number */ | |
258 | hsdev->dma->irq = irq_of_parse_and_map(np, 1); | |
259 | if (hsdev->dma->irq == NO_IRQ) { | |
260 | dev_err(&pdev->dev, "no SATA DMA irq\n"); | |
261 | return -ENODEV; | |
262 | } | |
263 | ||
264 | /* Get physical SATA DMA register base address */ | |
265 | hsdev->dma->regs = of_iomap(np, 1); | |
266 | if (!hsdev->dma->regs) { | |
267 | dev_err(&pdev->dev, | |
268 | "ioremap failed for AHBDMA register address\n"); | |
269 | return -ENODEV; | |
270 | } | |
271 | ||
272 | /* Initialize AHB DMAC */ | |
273 | err = dw_dma_probe(hsdev->dma); | |
274 | if (err) { | |
275 | iounmap(hsdev->dma->regs); | |
276 | return err; | |
277 | } | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev) | |
283 | { | |
284 | if (!hsdev->dma) | |
285 | return; | |
286 | ||
287 | dw_dma_remove(hsdev->dma); | |
288 | iounmap(hsdev->dma->regs); | |
289 | } | |
290 | ||
291 | #endif | |
292 | ||
84b47e3b SS |
293 | static const char *get_prot_descript(u8 protocol) |
294 | { | |
295 | switch ((enum ata_tf_protocols)protocol) { | |
296 | case ATA_PROT_NODATA: | |
297 | return "ATA no data"; | |
298 | case ATA_PROT_PIO: | |
299 | return "ATA PIO"; | |
300 | case ATA_PROT_DMA: | |
301 | return "ATA DMA"; | |
302 | case ATA_PROT_NCQ: | |
303 | return "ATA NCQ"; | |
304 | case ATAPI_PROT_NODATA: | |
305 | return "ATAPI no data"; | |
306 | case ATAPI_PROT_PIO: | |
307 | return "ATAPI PIO"; | |
308 | case ATAPI_PROT_DMA: | |
309 | return "ATAPI DMA"; | |
310 | default: | |
311 | return "unknown"; | |
312 | } | |
313 | } | |
314 | ||
315 | static const char *get_dma_dir_descript(int dma_dir) | |
316 | { | |
317 | switch ((enum dma_data_direction)dma_dir) { | |
318 | case DMA_BIDIRECTIONAL: | |
319 | return "bidirectional"; | |
320 | case DMA_TO_DEVICE: | |
321 | return "to device"; | |
322 | case DMA_FROM_DEVICE: | |
323 | return "from device"; | |
324 | default: | |
325 | return "none"; | |
326 | } | |
327 | } | |
328 | ||
db7a657f | 329 | static void sata_dwc_tf_dump(struct ata_port *ap, struct ata_taskfile *tf) |
62936009 | 330 | { |
db7a657f | 331 | dev_vdbg(ap->dev, |
d578514b AS |
332 | "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n", |
333 | tf->command, get_prot_descript(tf->protocol), tf->flags, | |
334 | tf->device); | |
db7a657f | 335 | dev_vdbg(ap->dev, |
d578514b AS |
336 | "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n", |
337 | tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah); | |
db7a657f | 338 | dev_vdbg(ap->dev, |
d578514b | 339 | "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n", |
62936009 RS |
340 | tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam, |
341 | tf->hob_lbah); | |
342 | } | |
343 | ||
8b344485 | 344 | static void dma_dwc_xfer_done(void *hsdev_instance) |
62936009 | 345 | { |
62936009 | 346 | unsigned long flags; |
d5185d65 | 347 | struct sata_dwc_device *hsdev = hsdev_instance; |
62936009 RS |
348 | struct ata_host *host = (struct ata_host *)hsdev->host; |
349 | struct ata_port *ap; | |
350 | struct sata_dwc_device_port *hsdevp; | |
351 | u8 tag = 0; | |
352 | unsigned int port = 0; | |
353 | ||
354 | spin_lock_irqsave(&host->lock, flags); | |
355 | ap = host->ports[port]; | |
356 | hsdevp = HSDEVP_FROM_AP(ap); | |
357 | tag = ap->link.active_tag; | |
358 | ||
62936009 | 359 | /* |
8b344485 AS |
360 | * Each DMA command produces 2 interrupts. Only |
361 | * complete the command after both interrupts have been | |
362 | * seen. (See sata_dwc_isr()) | |
62936009 | 363 | */ |
8b344485 AS |
364 | hsdevp->dma_interrupt_count++; |
365 | sata_dwc_clear_dmacr(hsdevp, tag); | |
62936009 | 366 | |
8b344485 AS |
367 | if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) { |
368 | dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n", | |
369 | tag, hsdevp->dma_pending[tag]); | |
62936009 RS |
370 | } |
371 | ||
8b344485 | 372 | if ((hsdevp->dma_interrupt_count % 2) == 0) |
8d5fe8d5 | 373 | sata_dwc_dma_xfer_complete(ap, 1); |
62936009 | 374 | |
8b344485 | 375 | spin_unlock_irqrestore(&host->lock, flags); |
62936009 RS |
376 | } |
377 | ||
8b344485 | 378 | static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc) |
62936009 | 379 | { |
8b344485 AS |
380 | struct ata_port *ap = qc->ap; |
381 | struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); | |
382 | struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap); | |
383 | dma_addr_t addr = (dma_addr_t)&hsdev->sata_dwc_regs->dmadr; | |
384 | struct dma_slave_config sconf; | |
385 | struct dma_async_tx_descriptor *desc; | |
386 | ||
387 | if (qc->dma_dir == DMA_DEV_TO_MEM) { | |
388 | sconf.src_addr = addr; | |
59a75cef | 389 | sconf.device_fc = false; |
8b344485 AS |
390 | } else { /* DMA_MEM_TO_DEV */ |
391 | sconf.dst_addr = addr; | |
392 | sconf.device_fc = false; | |
62936009 RS |
393 | } |
394 | ||
8b344485 | 395 | sconf.direction = qc->dma_dir; |
4ea8c205 AS |
396 | sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */ |
397 | sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */ | |
8b344485 AS |
398 | sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
399 | sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
62936009 | 400 | |
8b344485 | 401 | dmaengine_slave_config(hsdevp->chan, &sconf); |
62936009 | 402 | |
8b344485 AS |
403 | /* Convert SG list to linked list of items (LLIs) for AHB DMA */ |
404 | desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem, | |
405 | qc->dma_dir, | |
406 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
62936009 | 407 | |
8b344485 AS |
408 | if (!desc) |
409 | return NULL; | |
62936009 | 410 | |
8b344485 AS |
411 | desc->callback = dma_dwc_xfer_done; |
412 | desc->callback_param = hsdev; | |
62936009 | 413 | |
db7a657f | 414 | dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pad\n", |
8b344485 | 415 | __func__, qc->sg, qc->n_elem, &addr); |
62936009 | 416 | |
8b344485 | 417 | return desc; |
62936009 RS |
418 | } |
419 | ||
420 | static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val) | |
421 | { | |
422 | if (scr > SCR_NOTIFICATION) { | |
423 | dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n", | |
424 | __func__, scr); | |
425 | return -EINVAL; | |
426 | } | |
427 | ||
d7c256e8 | 428 | *val = in_le32(link->ap->ioaddr.scr_addr + (scr * 4)); |
62936009 RS |
429 | dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n", |
430 | __func__, link->ap->print_id, scr, *val); | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
435 | static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val) | |
436 | { | |
437 | dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n", | |
438 | __func__, link->ap->print_id, scr, val); | |
439 | if (scr > SCR_NOTIFICATION) { | |
440 | dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n", | |
441 | __func__, scr); | |
442 | return -EINVAL; | |
443 | } | |
d7c256e8 | 444 | out_le32(link->ap->ioaddr.scr_addr + (scr * 4), val); |
62936009 RS |
445 | |
446 | return 0; | |
447 | } | |
448 | ||
2d20da00 | 449 | static void clear_serror(struct ata_port *ap) |
62936009 RS |
450 | { |
451 | u32 val; | |
2d20da00 MR |
452 | sata_dwc_scr_read(&ap->link, SCR_ERROR, &val); |
453 | sata_dwc_scr_write(&ap->link, SCR_ERROR, val); | |
62936009 RS |
454 | } |
455 | ||
456 | static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit) | |
457 | { | |
458 | out_le32(&hsdev->sata_dwc_regs->intpr, | |
459 | in_le32(&hsdev->sata_dwc_regs->intpr)); | |
460 | } | |
461 | ||
462 | static u32 qcmd_tag_to_mask(u8 tag) | |
463 | { | |
464 | return 0x00000001 << (tag & 0x1f); | |
465 | } | |
466 | ||
467 | /* See ahci.c */ | |
468 | static void sata_dwc_error_intr(struct ata_port *ap, | |
469 | struct sata_dwc_device *hsdev, uint intpr) | |
470 | { | |
471 | struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); | |
472 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
473 | unsigned int err_mask = 0, action = 0; | |
474 | struct ata_queued_cmd *qc; | |
475 | u32 serror; | |
476 | u8 status, tag; | |
62936009 RS |
477 | |
478 | ata_ehi_clear_desc(ehi); | |
479 | ||
2d20da00 | 480 | sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror); |
62936009 RS |
481 | status = ap->ops->sff_check_status(ap); |
482 | ||
62936009 RS |
483 | tag = ap->link.active_tag; |
484 | ||
8b344485 AS |
485 | dev_err(ap->dev, |
486 | "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d", | |
487 | __func__, serror, intpr, status, hsdevp->dma_interrupt_count, | |
488 | hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]); | |
62936009 RS |
489 | |
490 | /* Clear error register and interrupt bit */ | |
2d20da00 | 491 | clear_serror(ap); |
62936009 RS |
492 | clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR); |
493 | ||
494 | /* This is the only error happening now. TODO check for exact error */ | |
495 | ||
496 | err_mask |= AC_ERR_HOST_BUS; | |
497 | action |= ATA_EH_RESET; | |
498 | ||
499 | /* Pass this on to EH */ | |
500 | ehi->serror |= serror; | |
501 | ehi->action |= action; | |
502 | ||
503 | qc = ata_qc_from_tag(ap, tag); | |
504 | if (qc) | |
505 | qc->err_mask |= err_mask; | |
506 | else | |
507 | ehi->err_mask |= err_mask; | |
508 | ||
509 | ata_port_abort(ap); | |
510 | } | |
511 | ||
512 | /* | |
513 | * Function : sata_dwc_isr | |
514 | * arguments : irq, void *dev_instance, struct pt_regs *regs | |
515 | * Return value : irqreturn_t - status of IRQ | |
516 | * This Interrupt handler called via port ops registered function. | |
517 | * .irq_handler = sata_dwc_isr | |
518 | */ | |
519 | static irqreturn_t sata_dwc_isr(int irq, void *dev_instance) | |
520 | { | |
521 | struct ata_host *host = (struct ata_host *)dev_instance; | |
522 | struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host); | |
523 | struct ata_port *ap; | |
524 | struct ata_queued_cmd *qc; | |
525 | unsigned long flags; | |
526 | u8 status, tag; | |
527 | int handled, num_processed, port = 0; | |
528 | uint intpr, sactive, sactive2, tag_mask; | |
529 | struct sata_dwc_device_port *hsdevp; | |
2d20da00 | 530 | hsdev->sactive_issued = 0; |
62936009 RS |
531 | |
532 | spin_lock_irqsave(&host->lock, flags); | |
533 | ||
534 | /* Read the interrupt register */ | |
535 | intpr = in_le32(&hsdev->sata_dwc_regs->intpr); | |
536 | ||
537 | ap = host->ports[port]; | |
538 | hsdevp = HSDEVP_FROM_AP(ap); | |
539 | ||
540 | dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr, | |
541 | ap->link.active_tag); | |
542 | ||
543 | /* Check for error interrupt */ | |
544 | if (intpr & SATA_DWC_INTPR_ERR) { | |
545 | sata_dwc_error_intr(ap, hsdev, intpr); | |
546 | handled = 1; | |
547 | goto DONE; | |
548 | } | |
549 | ||
550 | /* Check for DMA SETUP FIS (FP DMA) interrupt */ | |
551 | if (intpr & SATA_DWC_INTPR_NEWFP) { | |
552 | clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP); | |
553 | ||
554 | tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr)); | |
555 | dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag); | |
556 | if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND) | |
557 | dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag); | |
558 | ||
2d20da00 | 559 | hsdev->sactive_issued |= qcmd_tag_to_mask(tag); |
62936009 RS |
560 | |
561 | qc = ata_qc_from_tag(ap, tag); | |
562 | /* | |
563 | * Start FP DMA for NCQ command. At this point the tag is the | |
564 | * active tag. It is the tag that matches the command about to | |
565 | * be completed. | |
566 | */ | |
567 | qc->ap->link.active_tag = tag; | |
568 | sata_dwc_bmdma_start_by_tag(qc, tag); | |
569 | ||
570 | handled = 1; | |
571 | goto DONE; | |
572 | } | |
2d20da00 MR |
573 | sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive); |
574 | tag_mask = (hsdev->sactive_issued | sactive) ^ sactive; | |
62936009 RS |
575 | |
576 | /* If no sactive issued and tag_mask is zero then this is not NCQ */ | |
2d20da00 | 577 | if (hsdev->sactive_issued == 0 && tag_mask == 0) { |
62936009 RS |
578 | if (ap->link.active_tag == ATA_TAG_POISON) |
579 | tag = 0; | |
580 | else | |
581 | tag = ap->link.active_tag; | |
582 | qc = ata_qc_from_tag(ap, tag); | |
583 | ||
584 | /* DEV interrupt w/ no active qc? */ | |
585 | if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { | |
d578514b AS |
586 | dev_err(ap->dev, |
587 | "%s interrupt with no active qc qc=%p\n", | |
588 | __func__, qc); | |
62936009 RS |
589 | ap->ops->sff_check_status(ap); |
590 | handled = 1; | |
591 | goto DONE; | |
592 | } | |
593 | status = ap->ops->sff_check_status(ap); | |
594 | ||
595 | qc->ap->link.active_tag = tag; | |
596 | hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT; | |
597 | ||
598 | if (status & ATA_ERR) { | |
599 | dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status); | |
600 | sata_dwc_qc_complete(ap, qc, 1); | |
601 | handled = 1; | |
602 | goto DONE; | |
603 | } | |
604 | ||
605 | dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n", | |
84b47e3b | 606 | __func__, get_prot_descript(qc->tf.protocol)); |
62936009 RS |
607 | DRVSTILLBUSY: |
608 | if (ata_is_dma(qc->tf.protocol)) { | |
609 | /* | |
610 | * Each DMA transaction produces 2 interrupts. The DMAC | |
611 | * transfer complete interrupt and the SATA controller | |
612 | * operation done interrupt. The command should be | |
613 | * completed only after both interrupts are seen. | |
614 | */ | |
8b344485 | 615 | hsdevp->dma_interrupt_count++; |
62936009 RS |
616 | if (hsdevp->dma_pending[tag] == \ |
617 | SATA_DWC_DMA_PENDING_NONE) { | |
d578514b AS |
618 | dev_err(ap->dev, |
619 | "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n", | |
620 | __func__, intpr, status, | |
62936009 RS |
621 | hsdevp->dma_pending[tag]); |
622 | } | |
623 | ||
8b344485 | 624 | if ((hsdevp->dma_interrupt_count % 2) == 0) |
62936009 RS |
625 | sata_dwc_dma_xfer_complete(ap, 1); |
626 | } else if (ata_is_pio(qc->tf.protocol)) { | |
627 | ata_sff_hsm_move(ap, qc, status, 0); | |
628 | handled = 1; | |
629 | goto DONE; | |
630 | } else { | |
631 | if (unlikely(sata_dwc_qc_complete(ap, qc, 1))) | |
632 | goto DRVSTILLBUSY; | |
633 | } | |
634 | ||
635 | handled = 1; | |
636 | goto DONE; | |
637 | } | |
638 | ||
639 | /* | |
640 | * This is a NCQ command. At this point we need to figure out for which | |
641 | * tags we have gotten a completion interrupt. One interrupt may serve | |
642 | * as completion for more than one operation when commands are queued | |
643 | * (NCQ). We need to process each completed command. | |
644 | */ | |
645 | ||
646 | /* process completed commands */ | |
2d20da00 MR |
647 | sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive); |
648 | tag_mask = (hsdev->sactive_issued | sactive) ^ sactive; | |
62936009 | 649 | |
2d20da00 | 650 | if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) { |
d578514b AS |
651 | dev_dbg(ap->dev, |
652 | "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n", | |
2d20da00 | 653 | __func__, sactive, hsdev->sactive_issued, tag_mask); |
62936009 RS |
654 | } |
655 | ||
2d20da00 | 656 | if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) { |
d578514b | 657 | dev_warn(ap->dev, |
2d20da00 MR |
658 | "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n", |
659 | sactive, hsdev->sactive_issued, tag_mask); | |
62936009 RS |
660 | } |
661 | ||
662 | /* read just to clear ... not bad if currently still busy */ | |
663 | status = ap->ops->sff_check_status(ap); | |
664 | dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status); | |
665 | ||
666 | tag = 0; | |
667 | num_processed = 0; | |
668 | while (tag_mask) { | |
669 | num_processed++; | |
670 | while (!(tag_mask & 0x00000001)) { | |
671 | tag++; | |
672 | tag_mask <<= 1; | |
673 | } | |
674 | ||
675 | tag_mask &= (~0x00000001); | |
676 | qc = ata_qc_from_tag(ap, tag); | |
677 | ||
678 | /* To be picked up by completion functions */ | |
679 | qc->ap->link.active_tag = tag; | |
680 | hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT; | |
681 | ||
682 | /* Let libata/scsi layers handle error */ | |
683 | if (status & ATA_ERR) { | |
684 | dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__, | |
685 | status); | |
686 | sata_dwc_qc_complete(ap, qc, 1); | |
687 | handled = 1; | |
688 | goto DONE; | |
689 | } | |
690 | ||
691 | /* Process completed command */ | |
692 | dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__, | |
84b47e3b | 693 | get_prot_descript(qc->tf.protocol)); |
62936009 | 694 | if (ata_is_dma(qc->tf.protocol)) { |
8b344485 | 695 | hsdevp->dma_interrupt_count++; |
62936009 RS |
696 | if (hsdevp->dma_pending[tag] == \ |
697 | SATA_DWC_DMA_PENDING_NONE) | |
698 | dev_warn(ap->dev, "%s: DMA not pending?\n", | |
699 | __func__); | |
8b344485 | 700 | if ((hsdevp->dma_interrupt_count % 2) == 0) |
62936009 RS |
701 | sata_dwc_dma_xfer_complete(ap, 1); |
702 | } else { | |
703 | if (unlikely(sata_dwc_qc_complete(ap, qc, 1))) | |
704 | goto STILLBUSY; | |
705 | } | |
706 | continue; | |
707 | ||
708 | STILLBUSY: | |
709 | ap->stats.idle_irq++; | |
710 | dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n", | |
711 | ap->print_id); | |
712 | } /* while tag_mask */ | |
713 | ||
714 | /* | |
715 | * Check to see if any commands completed while we were processing our | |
716 | * initial set of completed commands (read status clears interrupts, | |
717 | * so we might miss a completed command interrupt if one came in while | |
718 | * we were processing --we read status as part of processing a completed | |
719 | * command). | |
720 | */ | |
2d20da00 | 721 | sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2); |
62936009 | 722 | if (sactive2 != sactive) { |
d578514b AS |
723 | dev_dbg(ap->dev, |
724 | "More completed - sactive=0x%x sactive2=0x%x\n", | |
725 | sactive, sactive2); | |
62936009 RS |
726 | } |
727 | handled = 1; | |
728 | ||
729 | DONE: | |
730 | spin_unlock_irqrestore(&host->lock, flags); | |
731 | return IRQ_RETVAL(handled); | |
732 | } | |
733 | ||
734 | static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag) | |
735 | { | |
736 | struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp); | |
737 | ||
738 | if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) { | |
739 | out_le32(&(hsdev->sata_dwc_regs->dmacr), | |
740 | SATA_DWC_DMACR_RX_CLEAR( | |
741 | in_le32(&(hsdev->sata_dwc_regs->dmacr)))); | |
742 | } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) { | |
743 | out_le32(&(hsdev->sata_dwc_regs->dmacr), | |
744 | SATA_DWC_DMACR_TX_CLEAR( | |
745 | in_le32(&(hsdev->sata_dwc_regs->dmacr)))); | |
746 | } else { | |
747 | /* | |
748 | * This should not happen, it indicates the driver is out of | |
749 | * sync. If it does happen, clear dmacr anyway. | |
750 | */ | |
db7a657f | 751 | dev_err(hsdev->dev, |
d578514b AS |
752 | "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n", |
753 | __func__, tag, hsdevp->dma_pending[tag], | |
754 | in_le32(&hsdev->sata_dwc_regs->dmacr)); | |
62936009 RS |
755 | out_le32(&(hsdev->sata_dwc_regs->dmacr), |
756 | SATA_DWC_DMACR_TXRXCH_CLEAR); | |
757 | } | |
758 | } | |
759 | ||
760 | static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status) | |
761 | { | |
762 | struct ata_queued_cmd *qc; | |
763 | struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); | |
764 | struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap); | |
765 | u8 tag = 0; | |
766 | ||
767 | tag = ap->link.active_tag; | |
768 | qc = ata_qc_from_tag(ap, tag); | |
769 | if (!qc) { | |
770 | dev_err(ap->dev, "failed to get qc"); | |
771 | return; | |
772 | } | |
773 | ||
774 | #ifdef DEBUG_NCQ | |
775 | if (tag > 0) { | |
d578514b AS |
776 | dev_info(ap->dev, |
777 | "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n", | |
778 | __func__, qc->tag, qc->tf.command, | |
84b47e3b SS |
779 | get_dma_dir_descript(qc->dma_dir), |
780 | get_prot_descript(qc->tf.protocol), | |
62936009 RS |
781 | in_le32(&(hsdev->sata_dwc_regs->dmacr))); |
782 | } | |
783 | #endif | |
784 | ||
785 | if (ata_is_dma(qc->tf.protocol)) { | |
786 | if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) { | |
d578514b AS |
787 | dev_err(ap->dev, |
788 | "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n", | |
789 | __func__, | |
62936009 RS |
790 | in_le32(&(hsdev->sata_dwc_regs->dmacr))); |
791 | } | |
792 | ||
793 | hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE; | |
794 | sata_dwc_qc_complete(ap, qc, check_status); | |
795 | ap->link.active_tag = ATA_TAG_POISON; | |
796 | } else { | |
797 | sata_dwc_qc_complete(ap, qc, check_status); | |
798 | } | |
799 | } | |
800 | ||
801 | static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc, | |
802 | u32 check_status) | |
803 | { | |
804 | u8 status = 0; | |
805 | u32 mask = 0x0; | |
806 | u8 tag = qc->tag; | |
2d20da00 | 807 | struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap); |
62936009 | 808 | struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); |
2d20da00 | 809 | hsdev->sactive_queued = 0; |
62936009 RS |
810 | dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status); |
811 | ||
812 | if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) | |
813 | dev_err(ap->dev, "TX DMA PENDING\n"); | |
814 | else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) | |
815 | dev_err(ap->dev, "RX DMA PENDING\n"); | |
d578514b AS |
816 | dev_dbg(ap->dev, |
817 | "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n", | |
818 | qc->tf.command, status, ap->print_id, qc->tf.protocol); | |
62936009 RS |
819 | |
820 | /* clear active bit */ | |
821 | mask = (~(qcmd_tag_to_mask(tag))); | |
2d20da00 MR |
822 | hsdev->sactive_queued = hsdev->sactive_queued & mask; |
823 | hsdev->sactive_issued = hsdev->sactive_issued & mask; | |
62936009 RS |
824 | ata_qc_complete(qc); |
825 | return 0; | |
826 | } | |
827 | ||
828 | static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev) | |
829 | { | |
830 | /* Enable selective interrupts by setting the interrupt maskregister*/ | |
831 | out_le32(&hsdev->sata_dwc_regs->intmr, | |
832 | SATA_DWC_INTMR_ERRM | | |
833 | SATA_DWC_INTMR_NEWFPM | | |
834 | SATA_DWC_INTMR_PMABRTM | | |
835 | SATA_DWC_INTMR_DMATM); | |
836 | /* | |
837 | * Unmask the error bits that should trigger an error interrupt by | |
838 | * setting the error mask register. | |
839 | */ | |
840 | out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS); | |
841 | ||
db7a657f | 842 | dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n", |
62936009 RS |
843 | __func__, in_le32(&hsdev->sata_dwc_regs->intmr), |
844 | in_le32(&hsdev->sata_dwc_regs->errmr)); | |
845 | } | |
846 | ||
ae95d951 | 847 | static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base) |
62936009 | 848 | { |
ae95d951 MR |
849 | port->cmd_addr = base + 0x00; |
850 | port->data_addr = base + 0x00; | |
62936009 | 851 | |
ae95d951 MR |
852 | port->error_addr = base + 0x04; |
853 | port->feature_addr = base + 0x04; | |
62936009 | 854 | |
ae95d951 | 855 | port->nsect_addr = base + 0x08; |
62936009 | 856 | |
ae95d951 MR |
857 | port->lbal_addr = base + 0x0c; |
858 | port->lbam_addr = base + 0x10; | |
859 | port->lbah_addr = base + 0x14; | |
62936009 | 860 | |
ae95d951 MR |
861 | port->device_addr = base + 0x18; |
862 | port->command_addr = base + 0x1c; | |
863 | port->status_addr = base + 0x1c; | |
62936009 | 864 | |
ae95d951 MR |
865 | port->altstatus_addr = base + 0x20; |
866 | port->ctl_addr = base + 0x20; | |
62936009 RS |
867 | } |
868 | ||
50b43375 MR |
869 | static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp) |
870 | { | |
871 | struct sata_dwc_device *hsdev = hsdevp->hsdev; | |
872 | struct device *dev = hsdev->dev; | |
873 | ||
874 | #ifdef CONFIG_SATA_DWC_OLD_DMA | |
875 | if (!of_find_property(dev->of_node, "dmas", NULL)) | |
876 | return sata_dwc_dma_get_channel_old(hsdevp); | |
877 | #endif | |
878 | ||
879 | hsdevp->chan = dma_request_chan(dev, "sata-dma"); | |
880 | if (IS_ERR(hsdevp->chan)) { | |
881 | dev_err(dev, "failed to allocate dma channel: %ld\n", | |
882 | PTR_ERR(hsdevp->chan)); | |
883 | return PTR_ERR(hsdevp->chan); | |
884 | } | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
62936009 RS |
889 | /* |
890 | * Function : sata_dwc_port_start | |
891 | * arguments : struct ata_ioports *port | |
892 | * Return value : returns 0 if success, error code otherwise | |
893 | * This function allocates the scatter gather LLI table for AHB DMA | |
894 | */ | |
895 | static int sata_dwc_port_start(struct ata_port *ap) | |
896 | { | |
897 | int err = 0; | |
898 | struct sata_dwc_device *hsdev; | |
899 | struct sata_dwc_device_port *hsdevp = NULL; | |
900 | struct device *pdev; | |
901 | int i; | |
902 | ||
903 | hsdev = HSDEV_FROM_AP(ap); | |
904 | ||
905 | dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no); | |
906 | ||
907 | hsdev->host = ap->host; | |
908 | pdev = ap->host->dev; | |
909 | if (!pdev) { | |
910 | dev_err(ap->dev, "%s: no ap->host->dev\n", __func__); | |
911 | err = -ENODEV; | |
912 | goto CLEANUP; | |
913 | } | |
914 | ||
915 | /* Allocate Port Struct */ | |
916 | hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL); | |
917 | if (!hsdevp) { | |
918 | dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__); | |
919 | err = -ENOMEM; | |
920 | goto CLEANUP; | |
921 | } | |
922 | hsdevp->hsdev = hsdev; | |
923 | ||
50b43375 MR |
924 | err = sata_dwc_dma_get_channel(hsdevp); |
925 | if (err) | |
8b344485 | 926 | goto CLEANUP_ALLOC; |
8b344485 | 927 | |
0f48debd MR |
928 | err = phy_power_on(hsdev->phy); |
929 | if (err) | |
930 | goto CLEANUP_ALLOC; | |
931 | ||
62936009 RS |
932 | for (i = 0; i < SATA_DWC_QCMD_MAX; i++) |
933 | hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT; | |
934 | ||
d7c256e8 | 935 | ap->bmdma_prd = NULL; /* set these so libata doesn't use them */ |
62936009 RS |
936 | ap->bmdma_prd_dma = 0; |
937 | ||
62936009 RS |
938 | if (ap->port_no == 0) { |
939 | dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n", | |
940 | __func__); | |
941 | out_le32(&hsdev->sata_dwc_regs->dmacr, | |
942 | SATA_DWC_DMACR_TXRXCH_CLEAR); | |
943 | ||
944 | dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n", | |
945 | __func__); | |
946 | out_le32(&hsdev->sata_dwc_regs->dbtsr, | |
947 | (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) | | |
948 | SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT))); | |
949 | } | |
950 | ||
951 | /* Clear any error bits before libata starts issuing commands */ | |
2d20da00 | 952 | clear_serror(ap); |
62936009 | 953 | ap->private_data = hsdevp; |
a081da63 JL |
954 | dev_dbg(ap->dev, "%s: done\n", __func__); |
955 | return 0; | |
62936009 | 956 | |
a081da63 JL |
957 | CLEANUP_ALLOC: |
958 | kfree(hsdevp); | |
62936009 | 959 | CLEANUP: |
a081da63 | 960 | dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id); |
62936009 RS |
961 | return err; |
962 | } | |
963 | ||
964 | static void sata_dwc_port_stop(struct ata_port *ap) | |
965 | { | |
62936009 | 966 | struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); |
0f48debd | 967 | struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap); |
62936009 RS |
968 | |
969 | dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id); | |
970 | ||
8b344485 AS |
971 | dmaengine_terminate_all(hsdevp->chan); |
972 | dma_release_channel(hsdevp->chan); | |
0f48debd | 973 | phy_power_off(hsdev->phy); |
62936009 | 974 | |
8b344485 | 975 | kfree(hsdevp); |
62936009 RS |
976 | ap->private_data = NULL; |
977 | } | |
978 | ||
979 | /* | |
980 | * Function : sata_dwc_exec_command_by_tag | |
981 | * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued | |
982 | * Return value : None | |
983 | * This function keeps track of individual command tag ids and calls | |
984 | * ata_exec_command in libata | |
985 | */ | |
986 | static void sata_dwc_exec_command_by_tag(struct ata_port *ap, | |
987 | struct ata_taskfile *tf, | |
988 | u8 tag, u32 cmd_issued) | |
989 | { | |
62936009 RS |
990 | struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); |
991 | ||
992 | dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command, | |
c211962d | 993 | ata_get_cmd_descript(tf->command), tag); |
62936009 | 994 | |
62936009 | 995 | hsdevp->cmd_issued[tag] = cmd_issued; |
55e610cd | 996 | |
62936009 RS |
997 | /* |
998 | * Clear SError before executing a new command. | |
999 | * sata_dwc_scr_write and read can not be used here. Clearing the PM | |
1000 | * managed SError register for the disk needs to be done before the | |
1001 | * task file is loaded. | |
1002 | */ | |
2d20da00 | 1003 | clear_serror(ap); |
62936009 RS |
1004 | ata_sff_exec_command(ap, tf); |
1005 | } | |
1006 | ||
1007 | static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag) | |
1008 | { | |
1009 | sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag, | |
1010 | SATA_DWC_CMD_ISSUED_PEND); | |
1011 | } | |
1012 | ||
1013 | static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc) | |
1014 | { | |
1015 | u8 tag = qc->tag; | |
1016 | ||
1017 | if (ata_is_ncq(qc->tf.protocol)) { | |
1018 | dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n", | |
1019 | __func__, qc->ap->link.sactive, tag); | |
1020 | } else { | |
1021 | tag = 0; | |
1022 | } | |
1023 | sata_dwc_bmdma_setup_by_tag(qc, tag); | |
1024 | } | |
1025 | ||
1026 | static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag) | |
1027 | { | |
1028 | int start_dma; | |
8b344485 | 1029 | u32 reg; |
62936009 RS |
1030 | struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc); |
1031 | struct ata_port *ap = qc->ap; | |
1032 | struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); | |
8b344485 | 1033 | struct dma_async_tx_descriptor *desc = hsdevp->desc[tag]; |
62936009 | 1034 | int dir = qc->dma_dir; |
62936009 RS |
1035 | |
1036 | if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) { | |
1037 | start_dma = 1; | |
1038 | if (dir == DMA_TO_DEVICE) | |
1039 | hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX; | |
1040 | else | |
1041 | hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX; | |
1042 | } else { | |
d578514b AS |
1043 | dev_err(ap->dev, |
1044 | "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n", | |
1045 | __func__, hsdevp->cmd_issued[tag], tag); | |
62936009 RS |
1046 | start_dma = 0; |
1047 | } | |
1048 | ||
d578514b AS |
1049 | dev_dbg(ap->dev, |
1050 | "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n", | |
1051 | __func__, qc, tag, qc->tf.command, | |
84b47e3b | 1052 | get_dma_dir_descript(qc->dma_dir), start_dma); |
db7a657f | 1053 | sata_dwc_tf_dump(ap, &qc->tf); |
62936009 RS |
1054 | |
1055 | if (start_dma) { | |
2d20da00 | 1056 | sata_dwc_scr_read(&ap->link, SCR_ERROR, ®); |
62936009 RS |
1057 | if (reg & SATA_DWC_SERROR_ERR_BITS) { |
1058 | dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n", | |
1059 | __func__, reg); | |
1060 | } | |
1061 | ||
1062 | if (dir == DMA_TO_DEVICE) | |
1063 | out_le32(&hsdev->sata_dwc_regs->dmacr, | |
1064 | SATA_DWC_DMACR_TXCHEN); | |
1065 | else | |
1066 | out_le32(&hsdev->sata_dwc_regs->dmacr, | |
1067 | SATA_DWC_DMACR_RXCHEN); | |
1068 | ||
1069 | /* Enable AHB DMA transfer on the specified channel */ | |
8b344485 AS |
1070 | dmaengine_submit(desc); |
1071 | dma_async_issue_pending(hsdevp->chan); | |
62936009 RS |
1072 | } |
1073 | } | |
1074 | ||
1075 | static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc) | |
1076 | { | |
1077 | u8 tag = qc->tag; | |
1078 | ||
1079 | if (ata_is_ncq(qc->tf.protocol)) { | |
1080 | dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n", | |
1081 | __func__, qc->ap->link.sactive, tag); | |
1082 | } else { | |
1083 | tag = 0; | |
1084 | } | |
1085 | dev_dbg(qc->ap->dev, "%s\n", __func__); | |
1086 | sata_dwc_bmdma_start_by_tag(qc, tag); | |
1087 | } | |
1088 | ||
62936009 RS |
1089 | static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc) |
1090 | { | |
1091 | u32 sactive; | |
1092 | u8 tag = qc->tag; | |
1093 | struct ata_port *ap = qc->ap; | |
ae4c3485 | 1094 | struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap); |
62936009 RS |
1095 | |
1096 | #ifdef DEBUG_NCQ | |
1097 | if (qc->tag > 0 || ap->link.sactive > 1) | |
d578514b AS |
1098 | dev_info(ap->dev, |
1099 | "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n", | |
62936009 | 1100 | __func__, ap->print_id, qc->tf.command, |
c211962d | 1101 | ata_get_cmd_descript(qc->tf.command), |
84b47e3b | 1102 | qc->tag, get_prot_descript(qc->tf.protocol), |
62936009 RS |
1103 | ap->link.active_tag, ap->link.sactive); |
1104 | #endif | |
1105 | ||
1106 | if (!ata_is_ncq(qc->tf.protocol)) | |
1107 | tag = 0; | |
ae4c3485 MR |
1108 | |
1109 | if (ata_is_dma(qc->tf.protocol)) { | |
1110 | hsdevp->desc[tag] = dma_dwc_xfer_setup(qc); | |
1111 | if (!hsdevp->desc[tag]) | |
1112 | return AC_ERR_SYSTEM; | |
1113 | } else { | |
1114 | hsdevp->desc[tag] = NULL; | |
1115 | } | |
62936009 RS |
1116 | |
1117 | if (ata_is_ncq(qc->tf.protocol)) { | |
2d20da00 | 1118 | sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive); |
62936009 | 1119 | sactive |= (0x00000001 << tag); |
2d20da00 | 1120 | sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive); |
62936009 | 1121 | |
d578514b AS |
1122 | dev_dbg(qc->ap->dev, |
1123 | "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n", | |
1124 | __func__, tag, qc->ap->link.sactive, sactive); | |
62936009 RS |
1125 | |
1126 | ap->ops->sff_tf_load(ap, &qc->tf); | |
077028ec | 1127 | sata_dwc_exec_command_by_tag(ap, &qc->tf, tag, |
62936009 RS |
1128 | SATA_DWC_CMD_ISSUED_PEND); |
1129 | } else { | |
077028ec | 1130 | return ata_bmdma_qc_issue(qc); |
62936009 RS |
1131 | } |
1132 | return 0; | |
1133 | } | |
1134 | ||
62936009 RS |
1135 | static void sata_dwc_error_handler(struct ata_port *ap) |
1136 | { | |
62936009 RS |
1137 | ata_sff_error_handler(ap); |
1138 | } | |
1139 | ||
d7c256e8 AS |
1140 | static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class, |
1141 | unsigned long deadline) | |
3a8b788f TN |
1142 | { |
1143 | struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap); | |
1144 | int ret; | |
1145 | ||
1146 | ret = sata_sff_hardreset(link, class, deadline); | |
1147 | ||
1148 | sata_dwc_enable_interrupts(hsdev); | |
1149 | ||
1150 | /* Reconfigure the DMA control register */ | |
1151 | out_le32(&hsdev->sata_dwc_regs->dmacr, | |
1152 | SATA_DWC_DMACR_TXRXCH_CLEAR); | |
1153 | ||
1154 | /* Reconfigure the DMA Burst Transaction Size register */ | |
1155 | out_le32(&hsdev->sata_dwc_regs->dbtsr, | |
1156 | SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) | | |
1157 | SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)); | |
1158 | ||
1159 | return ret; | |
1160 | } | |
1161 | ||
a7e6de54 CL |
1162 | static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device) |
1163 | { | |
1164 | /* SATA DWC is master only */ | |
1165 | } | |
1166 | ||
62936009 RS |
1167 | /* |
1168 | * scsi mid-layer and libata interface structures | |
1169 | */ | |
1170 | static struct scsi_host_template sata_dwc_sht = { | |
1171 | ATA_NCQ_SHT(DRV_NAME), | |
1172 | /* | |
1173 | * test-only: Currently this driver doesn't handle NCQ | |
1174 | * correctly. We enable NCQ but set the queue depth to a | |
1175 | * max of 1. This will get fixed in in a future release. | |
1176 | */ | |
1177 | .sg_tablesize = LIBATA_MAX_PRD, | |
d7c256e8 | 1178 | /* .can_queue = ATA_MAX_QUEUE, */ |
6689dfac AS |
1179 | /* |
1180 | * Make sure a LLI block is not created that will span 8K max FIS | |
1181 | * boundary. If the block spans such a FIS boundary, there is a chance | |
1182 | * that a DMA burst will cross that boundary -- this results in an | |
1183 | * error in the host controller. | |
1184 | */ | |
1185 | .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */, | |
62936009 RS |
1186 | }; |
1187 | ||
1188 | static struct ata_port_operations sata_dwc_ops = { | |
1189 | .inherits = &ata_sff_port_ops, | |
1190 | ||
1191 | .error_handler = sata_dwc_error_handler, | |
3a8b788f | 1192 | .hardreset = sata_dwc_hardreset, |
62936009 | 1193 | |
62936009 RS |
1194 | .qc_issue = sata_dwc_qc_issue, |
1195 | ||
1196 | .scr_read = sata_dwc_scr_read, | |
1197 | .scr_write = sata_dwc_scr_write, | |
1198 | ||
1199 | .port_start = sata_dwc_port_start, | |
1200 | .port_stop = sata_dwc_port_stop, | |
1201 | ||
a7e6de54 CL |
1202 | .sff_dev_select = sata_dwc_dev_select, |
1203 | ||
62936009 RS |
1204 | .bmdma_setup = sata_dwc_bmdma_setup, |
1205 | .bmdma_start = sata_dwc_bmdma_start, | |
1206 | }; | |
1207 | ||
1208 | static const struct ata_port_info sata_dwc_port_info[] = { | |
1209 | { | |
9cbe056f | 1210 | .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ, |
b83a4c39 | 1211 | .pio_mask = ATA_PIO4, |
62936009 RS |
1212 | .udma_mask = ATA_UDMA6, |
1213 | .port_ops = &sata_dwc_ops, | |
1214 | }, | |
1215 | }; | |
1216 | ||
1c48a5c9 | 1217 | static int sata_dwc_probe(struct platform_device *ofdev) |
62936009 RS |
1218 | { |
1219 | struct sata_dwc_device *hsdev; | |
1220 | u32 idr, versionr; | |
1221 | char *ver = (char *)&versionr; | |
175553ed | 1222 | void __iomem *base; |
62936009 | 1223 | int err = 0; |
4aaa7187 | 1224 | int irq; |
62936009 RS |
1225 | struct ata_host *host; |
1226 | struct ata_port_info pi = sata_dwc_port_info[0]; | |
1227 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
dc7f71f4 | 1228 | struct device_node *np = ofdev->dev.of_node; |
62936009 RS |
1229 | |
1230 | /* Allocate DWC SATA device */ | |
d537fc0c AS |
1231 | host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS); |
1232 | hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL); | |
1233 | if (!host || !hsdev) | |
c592b74f | 1234 | return -ENOMEM; |
62936009 | 1235 | |
d537fc0c AS |
1236 | host->private_data = hsdev; |
1237 | ||
62936009 | 1238 | /* Ioremap SATA registers */ |
9037908f | 1239 | base = of_iomap(np, 0); |
62936009 | 1240 | if (!base) { |
d578514b AS |
1241 | dev_err(&ofdev->dev, |
1242 | "ioremap failed for SATA register address\n"); | |
d537fc0c | 1243 | return -ENODEV; |
62936009 RS |
1244 | } |
1245 | hsdev->reg_base = base; | |
1246 | dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n"); | |
1247 | ||
1248 | /* Synopsys DWC SATA specific Registers */ | |
175553ed | 1249 | hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET; |
62936009 | 1250 | |
62936009 RS |
1251 | /* Setup port */ |
1252 | host->ports[0]->ioaddr.cmd_addr = base; | |
1253 | host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET; | |
ae95d951 | 1254 | sata_dwc_setup_port(&host->ports[0]->ioaddr, base); |
62936009 RS |
1255 | |
1256 | /* Read the ID and Version Registers */ | |
1257 | idr = in_le32(&hsdev->sata_dwc_regs->idr); | |
1258 | versionr = in_le32(&hsdev->sata_dwc_regs->versionr); | |
1259 | dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n", | |
1260 | idr, ver[0], ver[1], ver[2]); | |
1261 | ||
62936009 | 1262 | /* Save dev for later use in dev_xxx() routines */ |
db7a657f | 1263 | hsdev->dev = &ofdev->dev; |
62936009 | 1264 | |
62936009 RS |
1265 | /* Enable SATA Interrupts */ |
1266 | sata_dwc_enable_interrupts(hsdev); | |
1267 | ||
1268 | /* Get SATA interrupt number */ | |
9037908f | 1269 | irq = irq_of_parse_and_map(np, 0); |
62936009 RS |
1270 | if (irq == NO_IRQ) { |
1271 | dev_err(&ofdev->dev, "no SATA DMA irq\n"); | |
1272 | err = -ENODEV; | |
1273 | goto error_out; | |
1274 | } | |
1275 | ||
50b43375 MR |
1276 | #ifdef CONFIG_SATA_DWC_OLD_DMA |
1277 | if (!of_find_property(np, "dmas", NULL)) { | |
1278 | err = sata_dwc_dma_init_old(ofdev, hsdev); | |
1279 | if (err) | |
1280 | goto error_out; | |
1281 | } | |
1282 | #endif | |
1283 | ||
0f48debd MR |
1284 | hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy"); |
1285 | if (IS_ERR(hsdev->phy)) { | |
1286 | err = PTR_ERR(hsdev->phy); | |
1287 | hsdev->phy = NULL; | |
1288 | goto error_out; | |
1289 | } | |
1290 | ||
1291 | err = phy_init(hsdev->phy); | |
1292 | if (err) | |
1293 | goto error_out; | |
1294 | ||
62936009 RS |
1295 | /* |
1296 | * Now, register with libATA core, this will also initiate the | |
1297 | * device discovery process, invoking our port_start() handler & | |
1298 | * error_handler() to execute a dummy Softreset EH session | |
1299 | */ | |
4aaa7187 AS |
1300 | err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht); |
1301 | if (err) | |
62936009 RS |
1302 | dev_err(&ofdev->dev, "failed to activate host"); |
1303 | ||
1304 | dev_set_drvdata(&ofdev->dev, host); | |
1305 | return 0; | |
1306 | ||
1307 | error_out: | |
0f48debd | 1308 | phy_exit(hsdev->phy); |
04e506b5 | 1309 | iounmap(base); |
62936009 RS |
1310 | return err; |
1311 | } | |
1312 | ||
60652d07 | 1313 | static int sata_dwc_remove(struct platform_device *ofdev) |
62936009 RS |
1314 | { |
1315 | struct device *dev = &ofdev->dev; | |
1316 | struct ata_host *host = dev_get_drvdata(dev); | |
1317 | struct sata_dwc_device *hsdev = host->private_data; | |
1318 | ||
1319 | ata_host_detach(host); | |
62936009 | 1320 | |
0f48debd MR |
1321 | phy_exit(hsdev->phy); |
1322 | ||
50b43375 | 1323 | #ifdef CONFIG_SATA_DWC_OLD_DMA |
62936009 | 1324 | /* Free SATA DMA resources */ |
50b43375 MR |
1325 | sata_dwc_dma_exit_old(hsdev); |
1326 | #endif | |
62936009 RS |
1327 | |
1328 | iounmap(hsdev->reg_base); | |
62936009 RS |
1329 | dev_dbg(&ofdev->dev, "done\n"); |
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | static const struct of_device_id sata_dwc_match[] = { | |
1334 | { .compatible = "amcc,sata-460ex", }, | |
1335 | {} | |
1336 | }; | |
1337 | MODULE_DEVICE_TABLE(of, sata_dwc_match); | |
1338 | ||
1c48a5c9 | 1339 | static struct platform_driver sata_dwc_driver = { |
62936009 RS |
1340 | .driver = { |
1341 | .name = DRV_NAME, | |
62936009 RS |
1342 | .of_match_table = sata_dwc_match, |
1343 | }, | |
1344 | .probe = sata_dwc_probe, | |
1345 | .remove = sata_dwc_remove, | |
1346 | }; | |
1347 | ||
99c8ea3e | 1348 | module_platform_driver(sata_dwc_driver); |
62936009 RS |
1349 | |
1350 | MODULE_LICENSE("GPL"); | |
1351 | MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>"); | |
d578514b | 1352 | MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver"); |
62936009 | 1353 | MODULE_VERSION(DRV_VERSION); |