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ata: sata_dwc_460ex: get rid of global data
[mirror_ubuntu-artful-kernel.git] / drivers / ata / sata_dwc_460ex.c
CommitLineData
62936009
RS		 1/*
2 * drivers/ata/sata_dwc_460ex.c
3 *
4 * Synopsys DesignWare Cores (DWC) SATA host driver
5 *
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
7 *
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
10 *
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifdef CONFIG_SATA_DWC_DEBUG
22#define DEBUG
23#endif
24
25#ifdef CONFIG_SATA_DWC_VDEBUG
26#define VERBOSE_DEBUG
27#define DEBUG_NCQ
28#endif
29
30#include <linux/kernel.h>
31#include <linux/module.h>
62936009 32#include <linux/device.h>
50b43375 33#include <linux/dmaengine.h>
c11eede6
RH		 34#include <linux/of_address.h>
35#include <linux/of_irq.h>
62936009
RS		 36#include <linux/of_platform.h>
37#include <linux/platform_device.h>
0f48debd 38#include <linux/phy/phy.h>
62936009
RS		 39#include <linux/libata.h>
40#include <linux/slab.h>
8b344485 41
62936009
RS		 42#include "libata.h"
43
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46
c211962d
SS		 47/* These two are defined in "libata.h" */
48#undef DRV_NAME
49#undef DRV_VERSION
72d5f2da 50
62936009 51#define DRV_NAME "sata-dwc"
84b47e3b 52#define DRV_VERSION "1.3"
62936009 53
84683a7e
AS		 54#ifndef out_le32
55#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (void __iomem *)(a))
56#endif
57
58#ifndef in_le32
59#define in_le32(a) __le32_to_cpu(__raw_readl((void __iomem *)(a)))
60#endif
61
62#ifndef NO_IRQ
63#define NO_IRQ 0
64#endif
65
4ea8c205 66#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
62936009 67
62936009 68enum {
62936009
RS		 69 SATA_DWC_MAX_PORTS = 1,
70
71 SATA_DWC_SCR_OFFSET = 0x24,
72 SATA_DWC_REG_OFFSET = 0x64,
73};
74
75/* DWC SATA Registers */
76struct sata_dwc_regs {
77 u32 fptagr; /* 1st party DMA tag */
78 u32 fpbor; /* 1st party DMA buffer offset */
79 u32 fptcr; /* 1st party DMA Xfr count */
80 u32 dmacr; /* DMA Control */
81 u32 dbtsr; /* DMA Burst Transac size */
82 u32 intpr; /* Interrupt Pending */
83 u32 intmr; /* Interrupt Mask */
84 u32 errmr; /* Error Mask */
85 u32 llcr; /* Link Layer Control */
86 u32 phycr; /* PHY Control */
87 u32 physr; /* PHY Status */
88 u32 rxbistpd; /* Recvd BIST pattern def register */
89 u32 rxbistpd1; /* Recvd BIST data dword1 */
90 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
91 u32 txbistpd; /* Trans BIST pattern def register */
92 u32 txbistpd1; /* Trans BIST data dword1 */
93 u32 txbistpd2; /* Trans BIST data dword2 */
94 u32 bistcr; /* BIST Control Register */
95 u32 bistfctr; /* BIST FIS Count Register */
96 u32 bistsr; /* BIST Status Register */
97 u32 bistdecr; /* BIST Dword Error count register */
98 u32 res[15]; /* Reserved locations */
99 u32 testr; /* Test Register */
100 u32 versionr; /* Version Register */
101 u32 idr; /* ID Register */
102 u32 unimpl[192]; /* Unimplemented */
103 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
104};
105
106enum {
107 SCR_SCONTROL_DET_ENABLE = 0x00000001,
108 SCR_SSTATUS_DET_PRESENT = 0x00000001,
109 SCR_SERROR_DIAG_X = 0x04000000,
110/* DWC SATA Register Operations */
111 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
112 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
113 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
114 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
115 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
116 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
117 SATA_DWC_INTPR_DMAT = 0x00000001,
118 SATA_DWC_INTPR_NEWFP = 0x00000002,
119 SATA_DWC_INTPR_PMABRT = 0x00000004,
120 SATA_DWC_INTPR_ERR = 0x00000008,
121 SATA_DWC_INTPR_NEWBIST = 0x00000010,
122 SATA_DWC_INTPR_IPF = 0x10000000,
123 SATA_DWC_INTMR_DMATM = 0x00000001,
124 SATA_DWC_INTMR_NEWFPM = 0x00000002,
125 SATA_DWC_INTMR_PMABRTM = 0x00000004,
126 SATA_DWC_INTMR_ERRM = 0x00000008,
127 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
128 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
129 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
130 SATA_DWC_LLCR_RPDEN = 0x00000004,
131/* This is all error bits, zero's are reserved fields. */
132 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
133};
134
135#define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
136#define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
137 SATA_DWC_DMACR_TMOD_TXCHEN)
138#define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
139 SATA_DWC_DMACR_TMOD_TXCHEN)
140#define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
141#define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
142 << 16)
143struct sata_dwc_device {
144 struct device *dev; /* generic device struct */
145 struct ata_probe_ent *pe; /* ptr to probe-ent */
146 struct ata_host *host;
d7c256e8 147 u8 __iomem *reg_base;
62936009 148 struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */
2d20da00
MR		 149 u32 sactive_issued;
150 u32 sactive_queued;
0f48debd 151 struct phy *phy;
50b43375 152#ifdef CONFIG_SATA_DWC_OLD_DMA
8b344485 153 struct dw_dma_chip *dma;
50b43375 154#endif
62936009
RS		 155};
156
157#define SATA_DWC_QCMD_MAX 32
158
159struct sata_dwc_device_port {
160 struct sata_dwc_device *hsdev;
161 int cmd_issued[SATA_DWC_QCMD_MAX];
62936009 162 int dma_pending[SATA_DWC_QCMD_MAX];
8b344485
AS		 163
164 /* DMA info */
8b344485
AS		 165 struct dma_chan *chan;
166 struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX];
167 u32 dma_interrupt_count;
62936009
RS		 168};
169
170/*
171 * Commonly used DWC SATA driver Macros
172 */
173#define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\
174 (host)->private_data)
175#define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\
176 (ap)->host->private_data)
177#define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\
178 (ap)->private_data)
179#define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\
180 (qc)->ap->host->private_data)
181#define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\
182 (hsdevp)->hsdev)
183
184enum {
185 SATA_DWC_CMD_ISSUED_NOT = 0,
186 SATA_DWC_CMD_ISSUED_PEND = 1,
187 SATA_DWC_CMD_ISSUED_EXEC = 2,
188 SATA_DWC_CMD_ISSUED_NODATA = 3,
189
190 SATA_DWC_DMA_PENDING_NONE = 0,
191 SATA_DWC_DMA_PENDING_TX = 1,
192 SATA_DWC_DMA_PENDING_RX = 2,
193};
194
62936009
RS		 195/*
196 * Prototypes
197 */
198static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
199static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
200 u32 check_status);
201static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
202static void sata_dwc_port_stop(struct ata_port *ap);
203static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
62936009 204
50b43375
MR		 205#ifdef CONFIG_SATA_DWC_OLD_DMA
206
207#include <linux/platform_data/dma-dw.h>
208#include <linux/dma/dw.h>
209
210static struct dw_dma_slave sata_dwc_dma_dws = {
211 .src_id = 0,
212 .dst_id = 0,
213 .m_master = 1,
214 .p_master = 0,
215};
216
217static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
218{
219 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
220
221 if (dws->dma_dev != chan->device->dev)
222 return false;
223
224 chan->private = dws;
225 return true;
226}
227
228static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
229{
230 struct sata_dwc_device *hsdev = hsdevp->hsdev;
231 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
232 dma_cap_mask_t mask;
233
234 dws->dma_dev = hsdev->dev;
235
236 dma_cap_zero(mask);
237 dma_cap_set(DMA_SLAVE, mask);
238
239 /* Acquire DMA channel */
240 hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
241 if (!hsdevp->chan) {
242 dev_err(hsdev->dev, "%s: dma channel unavailable\n",
243 __func__);
244 return -EAGAIN;
245 }
246
247 return 0;
248}
249
250static int sata_dwc_dma_init_old(struct platform_device *pdev,
251 struct sata_dwc_device *hsdev)
252{
253 struct device_node *np = pdev->dev.of_node;
254 int err;
255
256 hsdev->dma = devm_kzalloc(&pdev->dev, sizeof(*hsdev->dma), GFP_KERNEL);
257 if (!hsdev->dma)
258 return -ENOMEM;
259
260 hsdev->dma->dev = &pdev->dev;
261
262 /* Get SATA DMA interrupt number */
263 hsdev->dma->irq = irq_of_parse_and_map(np, 1);
264 if (hsdev->dma->irq == NO_IRQ) {
265 dev_err(&pdev->dev, "no SATA DMA irq\n");
266 return -ENODEV;
267 }
268
269 /* Get physical SATA DMA register base address */
270 hsdev->dma->regs = of_iomap(np, 1);
271 if (!hsdev->dma->regs) {
272 dev_err(&pdev->dev,
273 "ioremap failed for AHBDMA register address\n");
274 return -ENODEV;
275 }
276
277 /* Initialize AHB DMAC */
278 err = dw_dma_probe(hsdev->dma);
279 if (err) {
280 iounmap(hsdev->dma->regs);
281 return err;
282 }
283
284 return 0;
285}
286
287static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
288{
289 if (!hsdev->dma)
290 return;
291
292 dw_dma_remove(hsdev->dma);
293 iounmap(hsdev->dma->regs);
294}
295
296#endif
297
84b47e3b
SS		 298static const char *get_prot_descript(u8 protocol)
299{
300 switch ((enum ata_tf_protocols)protocol) {
301 case ATA_PROT_NODATA:
302 return "ATA no data";
303 case ATA_PROT_PIO:
304 return "ATA PIO";
305 case ATA_PROT_DMA:
306 return "ATA DMA";
307 case ATA_PROT_NCQ:
308 return "ATA NCQ";
309 case ATAPI_PROT_NODATA:
310 return "ATAPI no data";
311 case ATAPI_PROT_PIO:
312 return "ATAPI PIO";
313 case ATAPI_PROT_DMA:
314 return "ATAPI DMA";
315 default:
316 return "unknown";
317 }
318}
319
320static const char *get_dma_dir_descript(int dma_dir)
321{
322 switch ((enum dma_data_direction)dma_dir) {
323 case DMA_BIDIRECTIONAL:
324 return "bidirectional";
325 case DMA_TO_DEVICE:
326 return "to device";
327 case DMA_FROM_DEVICE:
328 return "from device";
329 default:
330 return "none";
331 }
332}
333
db7a657f 334static void sata_dwc_tf_dump(struct ata_port *ap, struct ata_taskfile *tf)
62936009 335{
db7a657f 336 dev_vdbg(ap->dev,
d578514b
AS		 337 "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
338 tf->command, get_prot_descript(tf->protocol), tf->flags,
339 tf->device);
db7a657f 340 dev_vdbg(ap->dev,
d578514b
AS		 341 "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
342 tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
db7a657f 343 dev_vdbg(ap->dev,
d578514b 344 "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
62936009
RS		 345 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
346 tf->hob_lbah);
347}
348
8b344485 349static void dma_dwc_xfer_done(void *hsdev_instance)
62936009 350{
62936009 351 unsigned long flags;
d5185d65 352 struct sata_dwc_device *hsdev = hsdev_instance;
62936009
RS		 353 struct ata_host *host = (struct ata_host *)hsdev->host;
354 struct ata_port *ap;
355 struct sata_dwc_device_port *hsdevp;
356 u8 tag = 0;
357 unsigned int port = 0;
358
359 spin_lock_irqsave(&host->lock, flags);
360 ap = host->ports[port];
361 hsdevp = HSDEVP_FROM_AP(ap);
362 tag = ap->link.active_tag;
363
62936009 364 /*
8b344485
AS		 365 * Each DMA command produces 2 interrupts. Only
366 * complete the command after both interrupts have been
367 * seen. (See sata_dwc_isr())
62936009 368 */
8b344485
AS		 369 hsdevp->dma_interrupt_count++;
370 sata_dwc_clear_dmacr(hsdevp, tag);
62936009 371
8b344485
AS		 372 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
373 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
374 tag, hsdevp->dma_pending[tag]);
62936009
RS		 375 }
376
8b344485 377 if ((hsdevp->dma_interrupt_count % 2) == 0)
8d5fe8d5 378 sata_dwc_dma_xfer_complete(ap, 1);
62936009 379
8b344485 380 spin_unlock_irqrestore(&host->lock, flags);
62936009
RS		 381}
382
8b344485 383static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
62936009 384{
8b344485
AS		 385 struct ata_port *ap = qc->ap;
386 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
387 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
388 dma_addr_t addr = (dma_addr_t)&hsdev->sata_dwc_regs->dmadr;
389 struct dma_slave_config sconf;
390 struct dma_async_tx_descriptor *desc;
391
392 if (qc->dma_dir == DMA_DEV_TO_MEM) {
393 sconf.src_addr = addr;
59a75cef 394 sconf.device_fc = false;
8b344485
AS		 395 } else { /* DMA_MEM_TO_DEV */
396 sconf.dst_addr = addr;
397 sconf.device_fc = false;
62936009
RS		 398 }
399
8b344485 400 sconf.direction = qc->dma_dir;
4ea8c205
AS		 401 sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
402 sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
8b344485
AS		 403 sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
404 sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
62936009 405
8b344485 406 dmaengine_slave_config(hsdevp->chan, &sconf);
62936009 407
8b344485
AS		 408 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
409 desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
410 qc->dma_dir,
411 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
62936009 412
8b344485
AS		 413 if (!desc)
414 return NULL;
62936009 415
8b344485
AS		 416 desc->callback = dma_dwc_xfer_done;
417 desc->callback_param = hsdev;
62936009 418
db7a657f 419 dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pad\n",
8b344485 420 __func__, qc->sg, qc->n_elem, &addr);
62936009 421
8b344485 422 return desc;
62936009
RS		 423}
424
425static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
426{
427 if (scr > SCR_NOTIFICATION) {
428 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
429 __func__, scr);
430 return -EINVAL;
431 }
432
d7c256e8 433 *val = in_le32(link->ap->ioaddr.scr_addr + (scr * 4));
62936009
RS		 434 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
435 __func__, link->ap->print_id, scr, *val);
436
437 return 0;
438}
439
440static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
441{
442 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
443 __func__, link->ap->print_id, scr, val);
444 if (scr > SCR_NOTIFICATION) {
445 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
446 __func__, scr);
447 return -EINVAL;
448 }
d7c256e8 449 out_le32(link->ap->ioaddr.scr_addr + (scr * 4), val);
62936009
RS		 450
451 return 0;
452}
453
2d20da00 454static void clear_serror(struct ata_port *ap)
62936009
RS		 455{
456 u32 val;
2d20da00
MR		 457 sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
458 sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
62936009
RS		 459}
460
461static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
462{
463 out_le32(&hsdev->sata_dwc_regs->intpr,
464 in_le32(&hsdev->sata_dwc_regs->intpr));
465}
466
467static u32 qcmd_tag_to_mask(u8 tag)
468{
469 return 0x00000001 << (tag & 0x1f);
470}
471
472/* See ahci.c */
473static void sata_dwc_error_intr(struct ata_port *ap,
474 struct sata_dwc_device *hsdev, uint intpr)
475{
476 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
477 struct ata_eh_info *ehi = &ap->link.eh_info;
478 unsigned int err_mask = 0, action = 0;
479 struct ata_queued_cmd *qc;
480 u32 serror;
481 u8 status, tag;
62936009
RS		 482
483 ata_ehi_clear_desc(ehi);
484
2d20da00 485 sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
62936009
RS		 486 status = ap->ops->sff_check_status(ap);
487
62936009
RS		 488 tag = ap->link.active_tag;
489
8b344485
AS		 490 dev_err(ap->dev,
491 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
492 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
493 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
62936009
RS		 494
495 /* Clear error register and interrupt bit */
2d20da00 496 clear_serror(ap);
62936009
RS		 497 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
498
499 /* This is the only error happening now. TODO check for exact error */
500
501 err_mask |= AC_ERR_HOST_BUS;
502 action |= ATA_EH_RESET;
503
504 /* Pass this on to EH */
505 ehi->serror |= serror;
506 ehi->action |= action;
507
508 qc = ata_qc_from_tag(ap, tag);
509 if (qc)
510 qc->err_mask |= err_mask;
511 else
512 ehi->err_mask |= err_mask;
513
514 ata_port_abort(ap);
515}
516
517/*
518 * Function : sata_dwc_isr
519 * arguments : irq, void *dev_instance, struct pt_regs *regs
520 * Return value : irqreturn_t - status of IRQ
521 * This Interrupt handler called via port ops registered function.
522 * .irq_handler = sata_dwc_isr
523 */
524static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
525{
526 struct ata_host *host = (struct ata_host *)dev_instance;
527 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
528 struct ata_port *ap;
529 struct ata_queued_cmd *qc;
530 unsigned long flags;
531 u8 status, tag;
532 int handled, num_processed, port = 0;
533 uint intpr, sactive, sactive2, tag_mask;
534 struct sata_dwc_device_port *hsdevp;
2d20da00 535 hsdev->sactive_issued = 0;
62936009
RS		 536
537 spin_lock_irqsave(&host->lock, flags);
538
539 /* Read the interrupt register */
540 intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
541
542 ap = host->ports[port];
543 hsdevp = HSDEVP_FROM_AP(ap);
544
545 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
546 ap->link.active_tag);
547
548 /* Check for error interrupt */
549 if (intpr & SATA_DWC_INTPR_ERR) {
550 sata_dwc_error_intr(ap, hsdev, intpr);
551 handled = 1;
552 goto DONE;
553 }
554
555 /* Check for DMA SETUP FIS (FP DMA) interrupt */
556 if (intpr & SATA_DWC_INTPR_NEWFP) {
557 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
558
559 tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
560 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
561 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
562 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
563
2d20da00 564 hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
62936009
RS		 565
566 qc = ata_qc_from_tag(ap, tag);
567 /*
568 * Start FP DMA for NCQ command. At this point the tag is the
569 * active tag. It is the tag that matches the command about to
570 * be completed.
571 */
572 qc->ap->link.active_tag = tag;
573 sata_dwc_bmdma_start_by_tag(qc, tag);
574
575 handled = 1;
576 goto DONE;
577 }
2d20da00
MR		 578 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
579 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
62936009
RS		 580
581 /* If no sactive issued and tag_mask is zero then this is not NCQ */
2d20da00 582 if (hsdev->sactive_issued == 0 && tag_mask == 0) {
62936009
RS		 583 if (ap->link.active_tag == ATA_TAG_POISON)
584 tag = 0;
585 else
586 tag = ap->link.active_tag;
587 qc = ata_qc_from_tag(ap, tag);
588
589 /* DEV interrupt w/ no active qc? */
590 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
d578514b
AS		 591 dev_err(ap->dev,
592 "%s interrupt with no active qc qc=%p\n",
593 __func__, qc);
62936009
RS		 594 ap->ops->sff_check_status(ap);
595 handled = 1;
596 goto DONE;
597 }
598 status = ap->ops->sff_check_status(ap);
599
600 qc->ap->link.active_tag = tag;
601 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
602
603 if (status & ATA_ERR) {
604 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
605 sata_dwc_qc_complete(ap, qc, 1);
606 handled = 1;
607 goto DONE;
608 }
609
610 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
84b47e3b 611 __func__, get_prot_descript(qc->tf.protocol));
62936009
RS		 612DRVSTILLBUSY:
613 if (ata_is_dma(qc->tf.protocol)) {
614 /*
615 * Each DMA transaction produces 2 interrupts. The DMAC
616 * transfer complete interrupt and the SATA controller
617 * operation done interrupt. The command should be
618 * completed only after both interrupts are seen.
619 */
8b344485 620 hsdevp->dma_interrupt_count++;
62936009
RS		 621 if (hsdevp->dma_pending[tag] == \
622 SATA_DWC_DMA_PENDING_NONE) {
d578514b
AS		 623 dev_err(ap->dev,
624 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
625 __func__, intpr, status,
62936009
RS		 626 hsdevp->dma_pending[tag]);
627 }
628
8b344485 629 if ((hsdevp->dma_interrupt_count % 2) == 0)
62936009
RS		 630 sata_dwc_dma_xfer_complete(ap, 1);
631 } else if (ata_is_pio(qc->tf.protocol)) {
632 ata_sff_hsm_move(ap, qc, status, 0);
633 handled = 1;
634 goto DONE;
635 } else {
636 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
637 goto DRVSTILLBUSY;
638 }
639
640 handled = 1;
641 goto DONE;
642 }
643
644 /*
645 * This is a NCQ command. At this point we need to figure out for which
646 * tags we have gotten a completion interrupt. One interrupt may serve
647 * as completion for more than one operation when commands are queued
648 * (NCQ). We need to process each completed command.
649 */
650
651 /* process completed commands */
2d20da00
MR		 652 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
653 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
62936009 654
2d20da00 655 if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
d578514b
AS		 656 dev_dbg(ap->dev,
657 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
2d20da00 658 __func__, sactive, hsdev->sactive_issued, tag_mask);
62936009
RS		 659 }
660
2d20da00 661 if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
d578514b 662 dev_warn(ap->dev,
2d20da00
MR		 663 "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
664 sactive, hsdev->sactive_issued, tag_mask);
62936009
RS		 665 }
666
667 /* read just to clear ... not bad if currently still busy */
668 status = ap->ops->sff_check_status(ap);
669 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
670
671 tag = 0;
672 num_processed = 0;
673 while (tag_mask) {
674 num_processed++;
675 while (!(tag_mask & 0x00000001)) {
676 tag++;
677 tag_mask <<= 1;
678 }
679
680 tag_mask &= (~0x00000001);
681 qc = ata_qc_from_tag(ap, tag);
682
683 /* To be picked up by completion functions */
684 qc->ap->link.active_tag = tag;
685 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
686
687 /* Let libata/scsi layers handle error */
688 if (status & ATA_ERR) {
689 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
690 status);
691 sata_dwc_qc_complete(ap, qc, 1);
692 handled = 1;
693 goto DONE;
694 }
695
696 /* Process completed command */
697 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
84b47e3b 698 get_prot_descript(qc->tf.protocol));
62936009 699 if (ata_is_dma(qc->tf.protocol)) {
8b344485 700 hsdevp->dma_interrupt_count++;
62936009
RS		 701 if (hsdevp->dma_pending[tag] == \
702 SATA_DWC_DMA_PENDING_NONE)
703 dev_warn(ap->dev, "%s: DMA not pending?\n",
704 __func__);
8b344485 705 if ((hsdevp->dma_interrupt_count % 2) == 0)
62936009
RS		 706 sata_dwc_dma_xfer_complete(ap, 1);
707 } else {
708 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
709 goto STILLBUSY;
710 }
711 continue;
712
713STILLBUSY:
714 ap->stats.idle_irq++;
715 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
716 ap->print_id);
717 } /* while tag_mask */
718
719 /*
720 * Check to see if any commands completed while we were processing our
721 * initial set of completed commands (read status clears interrupts,
722 * so we might miss a completed command interrupt if one came in while
723 * we were processing --we read status as part of processing a completed
724 * command).
725 */
2d20da00 726 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
62936009 727 if (sactive2 != sactive) {
d578514b
AS		 728 dev_dbg(ap->dev,
729 "More completed - sactive=0x%x sactive2=0x%x\n",
730 sactive, sactive2);
62936009
RS		 731 }
732 handled = 1;
733
734DONE:
735 spin_unlock_irqrestore(&host->lock, flags);
736 return IRQ_RETVAL(handled);
737}
738
739static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
740{
741 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
742
743 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
744 out_le32(&(hsdev->sata_dwc_regs->dmacr),
745 SATA_DWC_DMACR_RX_CLEAR(
746 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
747 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
748 out_le32(&(hsdev->sata_dwc_regs->dmacr),
749 SATA_DWC_DMACR_TX_CLEAR(
750 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
751 } else {
752 /*
753 * This should not happen, it indicates the driver is out of
754 * sync. If it does happen, clear dmacr anyway.
755 */
db7a657f 756 dev_err(hsdev->dev,
d578514b
AS		 757 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
758 __func__, tag, hsdevp->dma_pending[tag],
759 in_le32(&hsdev->sata_dwc_regs->dmacr));
62936009
RS		 760 out_le32(&(hsdev->sata_dwc_regs->dmacr),
761 SATA_DWC_DMACR_TXRXCH_CLEAR);
762 }
763}
764
765static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
766{
767 struct ata_queued_cmd *qc;
768 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
769 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
770 u8 tag = 0;
771
772 tag = ap->link.active_tag;
773 qc = ata_qc_from_tag(ap, tag);
774 if (!qc) {
775 dev_err(ap->dev, "failed to get qc");
776 return;
777 }
778
779#ifdef DEBUG_NCQ
780 if (tag > 0) {
d578514b
AS		 781 dev_info(ap->dev,
782 "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
783 __func__, qc->tag, qc->tf.command,
84b47e3b
SS		 784 get_dma_dir_descript(qc->dma_dir),
785 get_prot_descript(qc->tf.protocol),
62936009
RS		 786 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
787 }
788#endif
789
790 if (ata_is_dma(qc->tf.protocol)) {
791 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
d578514b
AS		 792 dev_err(ap->dev,
793 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
794 __func__,
62936009
RS		 795 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
796 }
797
798 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
799 sata_dwc_qc_complete(ap, qc, check_status);
800 ap->link.active_tag = ATA_TAG_POISON;
801 } else {
802 sata_dwc_qc_complete(ap, qc, check_status);
803 }
804}
805
806static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
807 u32 check_status)
808{
809 u8 status = 0;
810 u32 mask = 0x0;
811 u8 tag = qc->tag;
2d20da00 812 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
62936009 813 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
2d20da00 814 hsdev->sactive_queued = 0;
62936009
RS		 815 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
816
817 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
818 dev_err(ap->dev, "TX DMA PENDING\n");
819 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
820 dev_err(ap->dev, "RX DMA PENDING\n");
d578514b
AS		 821 dev_dbg(ap->dev,
822 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
823 qc->tf.command, status, ap->print_id, qc->tf.protocol);
62936009
RS		 824
825 /* clear active bit */
826 mask = (~(qcmd_tag_to_mask(tag)));
2d20da00
MR		 827 hsdev->sactive_queued = hsdev->sactive_queued & mask;
828 hsdev->sactive_issued = hsdev->sactive_issued & mask;
62936009
RS		 829 ata_qc_complete(qc);
830 return 0;
831}
832
833static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
834{
835 /* Enable selective interrupts by setting the interrupt maskregister*/
836 out_le32(&hsdev->sata_dwc_regs->intmr,
837 SATA_DWC_INTMR_ERRM |
838 SATA_DWC_INTMR_NEWFPM |
839 SATA_DWC_INTMR_PMABRTM |
840 SATA_DWC_INTMR_DMATM);
841 /*
842 * Unmask the error bits that should trigger an error interrupt by
843 * setting the error mask register.
844 */
845 out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
846
db7a657f 847 dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
62936009
RS		 848 __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
849 in_le32(&hsdev->sata_dwc_regs->errmr));
850}
851
852static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
853{
d7c256e8
AS		 854 port->cmd_addr = (void __iomem *)base + 0x00;
855 port->data_addr = (void __iomem *)base + 0x00;
62936009 856
d7c256e8
AS		 857 port->error_addr = (void __iomem *)base + 0x04;
858 port->feature_addr = (void __iomem *)base + 0x04;
62936009 859
d7c256e8 860 port->nsect_addr = (void __iomem *)base + 0x08;
62936009 861
d7c256e8
AS		 862 port->lbal_addr = (void __iomem *)base + 0x0c;
863 port->lbam_addr = (void __iomem *)base + 0x10;
864 port->lbah_addr = (void __iomem *)base + 0x14;
62936009 865
d7c256e8
AS		 866 port->device_addr = (void __iomem *)base + 0x18;
867 port->command_addr = (void __iomem *)base + 0x1c;
868 port->status_addr = (void __iomem *)base + 0x1c;
62936009 869
d7c256e8
AS		 870 port->altstatus_addr = (void __iomem *)base + 0x20;
871 port->ctl_addr = (void __iomem *)base + 0x20;
62936009
RS		 872}
873
50b43375
MR		 874static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
875{
876 struct sata_dwc_device *hsdev = hsdevp->hsdev;
877 struct device *dev = hsdev->dev;
878
879#ifdef CONFIG_SATA_DWC_OLD_DMA
880 if (!of_find_property(dev->of_node, "dmas", NULL))
881 return sata_dwc_dma_get_channel_old(hsdevp);
882#endif
883
884 hsdevp->chan = dma_request_chan(dev, "sata-dma");
885 if (IS_ERR(hsdevp->chan)) {
886 dev_err(dev, "failed to allocate dma channel: %ld\n",
887 PTR_ERR(hsdevp->chan));
888 return PTR_ERR(hsdevp->chan);
889 }
890
891 return 0;
892}
893
62936009
RS		 894/*
895 * Function : sata_dwc_port_start
896 * arguments : struct ata_ioports *port
897 * Return value : returns 0 if success, error code otherwise
898 * This function allocates the scatter gather LLI table for AHB DMA
899 */
900static int sata_dwc_port_start(struct ata_port *ap)
901{
902 int err = 0;
903 struct sata_dwc_device *hsdev;
904 struct sata_dwc_device_port *hsdevp = NULL;
905 struct device *pdev;
906 int i;
907
908 hsdev = HSDEV_FROM_AP(ap);
909
910 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
911
912 hsdev->host = ap->host;
913 pdev = ap->host->dev;
914 if (!pdev) {
915 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
916 err = -ENODEV;
917 goto CLEANUP;
918 }
919
920 /* Allocate Port Struct */
921 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
922 if (!hsdevp) {
923 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
924 err = -ENOMEM;
925 goto CLEANUP;
926 }
927 hsdevp->hsdev = hsdev;
928
50b43375
MR		 929 err = sata_dwc_dma_get_channel(hsdevp);
930 if (err)
8b344485 931 goto CLEANUP_ALLOC;
8b344485 932
0f48debd
MR		 933 err = phy_power_on(hsdev->phy);
934 if (err)
935 goto CLEANUP_ALLOC;
936
62936009
RS		 937 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
938 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
939
d7c256e8 940 ap->bmdma_prd = NULL; /* set these so libata doesn't use them */
62936009
RS		 941 ap->bmdma_prd_dma = 0;
942
62936009
RS		 943 if (ap->port_no == 0) {
944 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
945 __func__);
946 out_le32(&hsdev->sata_dwc_regs->dmacr,
947 SATA_DWC_DMACR_TXRXCH_CLEAR);
948
949 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
950 __func__);
951 out_le32(&hsdev->sata_dwc_regs->dbtsr,
952 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
953 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
954 }
955
956 /* Clear any error bits before libata starts issuing commands */
2d20da00 957 clear_serror(ap);
62936009 958 ap->private_data = hsdevp;
a081da63
JL		 959 dev_dbg(ap->dev, "%s: done\n", __func__);
960 return 0;
62936009 961
a081da63
JL		 962CLEANUP_ALLOC:
963 kfree(hsdevp);
62936009 964CLEANUP:
a081da63 965 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
62936009
RS		 966 return err;
967}
968
969static void sata_dwc_port_stop(struct ata_port *ap)
970{
62936009 971 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
0f48debd 972 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
62936009
RS		 973
974 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
975
8b344485
AS		 976 dmaengine_terminate_all(hsdevp->chan);
977 dma_release_channel(hsdevp->chan);
0f48debd 978 phy_power_off(hsdev->phy);
62936009 979
8b344485 980 kfree(hsdevp);
62936009
RS		 981 ap->private_data = NULL;
982}
983
984/*
985 * Function : sata_dwc_exec_command_by_tag
986 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
987 * Return value : None
988 * This function keeps track of individual command tag ids and calls
989 * ata_exec_command in libata
990 */
991static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
992 struct ata_taskfile *tf,
993 u8 tag, u32 cmd_issued)
994{
62936009
RS		 995 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
996
997 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
c211962d 998 ata_get_cmd_descript(tf->command), tag);
62936009 999
62936009 1000 hsdevp->cmd_issued[tag] = cmd_issued;
55e610cd 1001
62936009
RS		 1002 /*
1003 * Clear SError before executing a new command.
1004 * sata_dwc_scr_write and read can not be used here. Clearing the PM
1005 * managed SError register for the disk needs to be done before the
1006 * task file is loaded.
1007 */
2d20da00 1008 clear_serror(ap);
62936009
RS		 1009 ata_sff_exec_command(ap, tf);
1010}
1011
1012static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1013{
1014 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1015 SATA_DWC_CMD_ISSUED_PEND);
1016}
1017
1018static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1019{
1020 u8 tag = qc->tag;
1021
1022 if (ata_is_ncq(qc->tf.protocol)) {
1023 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1024 __func__, qc->ap->link.sactive, tag);
1025 } else {
1026 tag = 0;
1027 }
1028 sata_dwc_bmdma_setup_by_tag(qc, tag);
1029}
1030
1031static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1032{
1033 int start_dma;
8b344485 1034 u32 reg;
62936009
RS		 1035 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1036 struct ata_port *ap = qc->ap;
1037 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
8b344485 1038 struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
62936009 1039 int dir = qc->dma_dir;
62936009
RS		 1040
1041 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1042 start_dma = 1;
1043 if (dir == DMA_TO_DEVICE)
1044 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1045 else
1046 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1047 } else {
d578514b
AS		 1048 dev_err(ap->dev,
1049 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
1050 __func__, hsdevp->cmd_issued[tag], tag);
62936009
RS		 1051 start_dma = 0;
1052 }
1053
d578514b
AS		 1054 dev_dbg(ap->dev,
1055 "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
1056 __func__, qc, tag, qc->tf.command,
84b47e3b 1057 get_dma_dir_descript(qc->dma_dir), start_dma);
db7a657f 1058 sata_dwc_tf_dump(ap, &qc->tf);
62936009
RS		 1059
1060 if (start_dma) {
2d20da00 1061 sata_dwc_scr_read(&ap->link, SCR_ERROR, &reg);
62936009
RS		 1062 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1063 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1064 __func__, reg);
1065 }
1066
1067 if (dir == DMA_TO_DEVICE)
1068 out_le32(&hsdev->sata_dwc_regs->dmacr,
1069 SATA_DWC_DMACR_TXCHEN);
1070 else
1071 out_le32(&hsdev->sata_dwc_regs->dmacr,
1072 SATA_DWC_DMACR_RXCHEN);
1073
1074 /* Enable AHB DMA transfer on the specified channel */
8b344485
AS		 1075 dmaengine_submit(desc);
1076 dma_async_issue_pending(hsdevp->chan);
62936009
RS		 1077 }
1078}
1079
1080static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1081{
1082 u8 tag = qc->tag;
1083
1084 if (ata_is_ncq(qc->tf.protocol)) {
1085 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1086 __func__, qc->ap->link.sactive, tag);
1087 } else {
1088 tag = 0;
1089 }
1090 dev_dbg(qc->ap->dev, "%s\n", __func__);
1091 sata_dwc_bmdma_start_by_tag(qc, tag);
1092}
1093
62936009
RS		 1094static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1095{
1096 u32 sactive;
1097 u8 tag = qc->tag;
1098 struct ata_port *ap = qc->ap;
ae4c3485 1099 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
62936009
RS		 1100
1101#ifdef DEBUG_NCQ
1102 if (qc->tag > 0 || ap->link.sactive > 1)
d578514b
AS		 1103 dev_info(ap->dev,
1104 "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
62936009 1105 __func__, ap->print_id, qc->tf.command,
c211962d 1106 ata_get_cmd_descript(qc->tf.command),
84b47e3b 1107 qc->tag, get_prot_descript(qc->tf.protocol),
62936009
RS		 1108 ap->link.active_tag, ap->link.sactive);
1109#endif
1110
1111 if (!ata_is_ncq(qc->tf.protocol))
1112 tag = 0;
ae4c3485
MR		 1113
1114 if (ata_is_dma(qc->tf.protocol)) {
1115 hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
1116 if (!hsdevp->desc[tag])
1117 return AC_ERR_SYSTEM;
1118 } else {
1119 hsdevp->desc[tag] = NULL;
1120 }
62936009
RS		 1121
1122 if (ata_is_ncq(qc->tf.protocol)) {
2d20da00 1123 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
62936009 1124 sactive |= (0x00000001 << tag);
2d20da00 1125 sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
62936009 1126
d578514b
AS		 1127 dev_dbg(qc->ap->dev,
1128 "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
1129 __func__, tag, qc->ap->link.sactive, sactive);
62936009
RS		 1130
1131 ap->ops->sff_tf_load(ap, &qc->tf);
077028ec 1132 sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
62936009
RS		 1133 SATA_DWC_CMD_ISSUED_PEND);
1134 } else {
077028ec 1135 return ata_bmdma_qc_issue(qc);
62936009
RS		 1136 }
1137 return 0;
1138}
1139
1140/*
1141 * Function : sata_dwc_qc_prep
1142 * arguments : ata_queued_cmd *qc
1143 * Return value : None
1144 * qc_prep for a particular queued command
1145 */
1146
1147static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
1148{
1149 if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
1150 return;
1151
1152#ifdef DEBUG_NCQ
1153 if (qc->tag > 0)
1154 dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
c211962d 1155 __func__, qc->tag, qc->ap->link.active_tag);
62936009
RS		 1156
1157 return ;
1158#endif
1159}
1160
1161static void sata_dwc_error_handler(struct ata_port *ap)
1162{
62936009
RS		 1163 ata_sff_error_handler(ap);
1164}
1165
d7c256e8
AS		 1166static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1167 unsigned long deadline)
3a8b788f
TN		 1168{
1169 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1170 int ret;
1171
1172 ret = sata_sff_hardreset(link, class, deadline);
1173
1174 sata_dwc_enable_interrupts(hsdev);
1175
1176 /* Reconfigure the DMA control register */
1177 out_le32(&hsdev->sata_dwc_regs->dmacr,
1178 SATA_DWC_DMACR_TXRXCH_CLEAR);
1179
1180 /* Reconfigure the DMA Burst Transaction Size register */
1181 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1182 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1183 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1184
1185 return ret;
1186}
1187
a7e6de54
CL		 1188static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
1189{
1190 /* SATA DWC is master only */
1191}
1192
62936009
RS		 1193/*
1194 * scsi mid-layer and libata interface structures
1195 */
1196static struct scsi_host_template sata_dwc_sht = {
1197 ATA_NCQ_SHT(DRV_NAME),
1198 /*
1199 * test-only: Currently this driver doesn't handle NCQ
1200 * correctly. We enable NCQ but set the queue depth to a
1201 * max of 1. This will get fixed in in a future release.
1202 */
1203 .sg_tablesize = LIBATA_MAX_PRD,
d7c256e8 1204 /* .can_queue = ATA_MAX_QUEUE, */
6689dfac
AS		 1205 /*
1206 * Make sure a LLI block is not created that will span 8K max FIS
1207 * boundary. If the block spans such a FIS boundary, there is a chance
1208 * that a DMA burst will cross that boundary -- this results in an
1209 * error in the host controller.
1210 */
1211 .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */,
62936009
RS		 1212};
1213
1214static struct ata_port_operations sata_dwc_ops = {
1215 .inherits = &ata_sff_port_ops,
1216
1217 .error_handler = sata_dwc_error_handler,
3a8b788f 1218 .hardreset = sata_dwc_hardreset,
62936009
RS		 1219
1220 .qc_prep = sata_dwc_qc_prep,
1221 .qc_issue = sata_dwc_qc_issue,
1222
1223 .scr_read = sata_dwc_scr_read,
1224 .scr_write = sata_dwc_scr_write,
1225
1226 .port_start = sata_dwc_port_start,
1227 .port_stop = sata_dwc_port_stop,
1228
a7e6de54
CL		 1229 .sff_dev_select = sata_dwc_dev_select,
1230
62936009
RS		 1231 .bmdma_setup = sata_dwc_bmdma_setup,
1232 .bmdma_start = sata_dwc_bmdma_start,
1233};
1234
1235static const struct ata_port_info sata_dwc_port_info[] = {
1236 {
9cbe056f 1237 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
b83a4c39 1238 .pio_mask = ATA_PIO4,
62936009
RS		 1239 .udma_mask = ATA_UDMA6,
1240 .port_ops = &sata_dwc_ops,
1241 },
1242};
1243
1c48a5c9 1244static int sata_dwc_probe(struct platform_device *ofdev)
62936009
RS		 1245{
1246 struct sata_dwc_device *hsdev;
1247 u32 idr, versionr;
1248 char *ver = (char *)&versionr;
d7c256e8 1249 u8 __iomem *base;
62936009 1250 int err = 0;
4aaa7187 1251 int irq;
62936009
RS		 1252 struct ata_host *host;
1253 struct ata_port_info pi = sata_dwc_port_info[0];
1254 const struct ata_port_info *ppi[] = { &pi, NULL };
dc7f71f4 1255 struct device_node *np = ofdev->dev.of_node;
62936009
RS		 1256
1257 /* Allocate DWC SATA device */
d537fc0c
AS		 1258 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1259 hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL);
1260 if (!host || !hsdev)
c592b74f 1261 return -ENOMEM;
62936009 1262
d537fc0c
AS		 1263 host->private_data = hsdev;
1264
62936009 1265 /* Ioremap SATA registers */
9037908f 1266 base = of_iomap(np, 0);
62936009 1267 if (!base) {
d578514b
AS		 1268 dev_err(&ofdev->dev,
1269 "ioremap failed for SATA register address\n");
d537fc0c 1270 return -ENODEV;
62936009
RS		 1271 }
1272 hsdev->reg_base = base;
1273 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1274
1275 /* Synopsys DWC SATA specific Registers */
1276 hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
1277
62936009
RS		 1278 /* Setup port */
1279 host->ports[0]->ioaddr.cmd_addr = base;
1280 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
62936009
RS		 1281 sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
1282
1283 /* Read the ID and Version Registers */
1284 idr = in_le32(&hsdev->sata_dwc_regs->idr);
1285 versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
1286 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1287 idr, ver[0], ver[1], ver[2]);
1288
62936009 1289 /* Save dev for later use in dev_xxx() routines */
db7a657f 1290 hsdev->dev = &ofdev->dev;
62936009 1291
62936009
RS		 1292 /* Enable SATA Interrupts */
1293 sata_dwc_enable_interrupts(hsdev);
1294
1295 /* Get SATA interrupt number */
9037908f 1296 irq = irq_of_parse_and_map(np, 0);
62936009
RS		 1297 if (irq == NO_IRQ) {
1298 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1299 err = -ENODEV;
1300 goto error_out;
1301 }
1302
50b43375
MR		 1303#ifdef CONFIG_SATA_DWC_OLD_DMA
1304 if (!of_find_property(np, "dmas", NULL)) {
1305 err = sata_dwc_dma_init_old(ofdev, hsdev);
1306 if (err)
1307 goto error_out;
1308 }
1309#endif
1310
0f48debd
MR		 1311 hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
1312 if (IS_ERR(hsdev->phy)) {
1313 err = PTR_ERR(hsdev->phy);
1314 hsdev->phy = NULL;
1315 goto error_out;
1316 }
1317
1318 err = phy_init(hsdev->phy);
1319 if (err)
1320 goto error_out;
1321
62936009
RS		 1322 /*
1323 * Now, register with libATA core, this will also initiate the
1324 * device discovery process, invoking our port_start() handler &
1325 * error_handler() to execute a dummy Softreset EH session
1326 */
4aaa7187
AS		 1327 err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1328 if (err)
62936009
RS		 1329 dev_err(&ofdev->dev, "failed to activate host");
1330
1331 dev_set_drvdata(&ofdev->dev, host);
1332 return 0;
1333
1334error_out:
0f48debd 1335 phy_exit(hsdev->phy);
04e506b5 1336 iounmap(base);
62936009
RS		 1337 return err;
1338}
1339
60652d07 1340static int sata_dwc_remove(struct platform_device *ofdev)
62936009
RS		 1341{
1342 struct device *dev = &ofdev->dev;
1343 struct ata_host *host = dev_get_drvdata(dev);
1344 struct sata_dwc_device *hsdev = host->private_data;
1345
1346 ata_host_detach(host);
62936009 1347
0f48debd
MR		 1348 phy_exit(hsdev->phy);
1349
50b43375 1350#ifdef CONFIG_SATA_DWC_OLD_DMA
62936009 1351 /* Free SATA DMA resources */
50b43375
MR		 1352 sata_dwc_dma_exit_old(hsdev);
1353#endif
62936009
RS		 1354
1355 iounmap(hsdev->reg_base);
62936009
RS		 1356 dev_dbg(&ofdev->dev, "done\n");
1357 return 0;
1358}
1359
1360static const struct of_device_id sata_dwc_match[] = {
1361 { .compatible = "amcc,sata-460ex", },
1362 {}
1363};
1364MODULE_DEVICE_TABLE(of, sata_dwc_match);
1365
1c48a5c9 1366static struct platform_driver sata_dwc_driver = {
62936009
RS		 1367 .driver = {
1368 .name = DRV_NAME,
62936009
RS		 1369 .of_match_table = sata_dwc_match,
1370 },
1371 .probe = sata_dwc_probe,
1372 .remove = sata_dwc_remove,
1373};
1374
99c8ea3e 1375module_platform_driver(sata_dwc_driver);
62936009
RS		 1376
1377MODULE_LICENSE("GPL");
1378MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
d578514b 1379MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
62936009 1380MODULE_VERSION(DRV_VERSION);
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