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faf0b2e5 LY |
1 | /* |
2 | * drivers/ata/sata_fsl.c | |
3 | * | |
4 | * Freescale 3.0Gbps SATA device driver | |
5 | * | |
6 | * Author: Ashish Kalra <ashish.kalra@freescale.com> | |
7 | * Li Yang <leoli@freescale.com> | |
8 | * | |
9 | * Copyright (c) 2006-2007 Freescale Semiconductor, Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | ||
22 | #include <scsi/scsi_host.h> | |
23 | #include <scsi/scsi_cmnd.h> | |
24 | #include <linux/libata.h> | |
25 | #include <asm/io.h> | |
26 | #include <linux/of_platform.h> | |
27 | ||
28 | /* Controller information */ | |
29 | enum { | |
30 | SATA_FSL_QUEUE_DEPTH = 16, | |
31 | SATA_FSL_MAX_PRD = 63, | |
32 | SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, | |
33 | SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ | |
34 | ||
35 | SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
36 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
1bf617b7 LY |
37 | ATA_FLAG_NCQ), |
38 | SATA_FSL_HOST_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY, | |
faf0b2e5 LY |
39 | |
40 | SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, | |
41 | SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ | |
42 | SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), | |
43 | ||
44 | /* | |
45 | * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and | |
46 | * chained indirect PRDEs upto a max count of 63. | |
47 | * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will | |
48 | * be setup as an indirect descriptor, pointing to it's next | |
49 | * (contigious) PRDE. Though chained indirect PRDE arrays are | |
50 | * supported,it will be more efficient to use a direct PRDT and | |
51 | * a single chain/link to indirect PRDE array/PRDT. | |
52 | */ | |
53 | ||
54 | SATA_FSL_CMD_DESC_CFIS_SZ = 32, | |
55 | SATA_FSL_CMD_DESC_SFIS_SZ = 32, | |
56 | SATA_FSL_CMD_DESC_ACMD_SZ = 16, | |
57 | SATA_FSL_CMD_DESC_RSRVD = 16, | |
58 | ||
59 | SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + | |
60 | SATA_FSL_CMD_DESC_SFIS_SZ + | |
61 | SATA_FSL_CMD_DESC_ACMD_SZ + | |
62 | SATA_FSL_CMD_DESC_RSRVD + | |
63 | SATA_FSL_MAX_PRD * 16), | |
64 | ||
65 | SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = | |
66 | (SATA_FSL_CMD_DESC_CFIS_SZ + | |
67 | SATA_FSL_CMD_DESC_SFIS_SZ + | |
68 | SATA_FSL_CMD_DESC_ACMD_SZ + | |
69 | SATA_FSL_CMD_DESC_RSRVD), | |
70 | ||
71 | SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), | |
72 | SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + | |
73 | SATA_FSL_CMD_DESC_AR_SZ), | |
74 | ||
75 | /* | |
76 | * MPC8315 has two SATA controllers, SATA1 & SATA2 | |
77 | * (one port per controller) | |
78 | * MPC837x has 2/4 controllers, one port per controller | |
79 | */ | |
80 | ||
81 | SATA_FSL_MAX_PORTS = 1, | |
82 | ||
83 | SATA_FSL_IRQ_FLAG = IRQF_SHARED, | |
84 | }; | |
85 | ||
86 | /* | |
87 | * Host Controller command register set - per port | |
88 | */ | |
89 | enum { | |
90 | CQ = 0, | |
91 | CA = 8, | |
92 | CC = 0x10, | |
93 | CE = 0x18, | |
94 | DE = 0x20, | |
95 | CHBA = 0x24, | |
96 | HSTATUS = 0x28, | |
97 | HCONTROL = 0x2C, | |
98 | CQPMP = 0x30, | |
99 | SIGNATURE = 0x34, | |
100 | ICC = 0x38, | |
101 | ||
102 | /* | |
103 | * Host Status Register (HStatus) bitdefs | |
104 | */ | |
105 | ONLINE = (1 << 31), | |
106 | GOING_OFFLINE = (1 << 30), | |
107 | BIST_ERR = (1 << 29), | |
108 | ||
109 | FATAL_ERR_HC_MASTER_ERR = (1 << 18), | |
110 | FATAL_ERR_PARITY_ERR_TX = (1 << 17), | |
111 | FATAL_ERR_PARITY_ERR_RX = (1 << 16), | |
112 | FATAL_ERR_DATA_UNDERRUN = (1 << 13), | |
113 | FATAL_ERR_DATA_OVERRUN = (1 << 12), | |
114 | FATAL_ERR_CRC_ERR_TX = (1 << 11), | |
115 | FATAL_ERR_CRC_ERR_RX = (1 << 10), | |
116 | FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), | |
117 | FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), | |
118 | ||
119 | FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | | |
120 | FATAL_ERR_PARITY_ERR_TX | | |
121 | FATAL_ERR_PARITY_ERR_RX | | |
122 | FATAL_ERR_DATA_UNDERRUN | | |
123 | FATAL_ERR_DATA_OVERRUN | | |
124 | FATAL_ERR_CRC_ERR_TX | | |
125 | FATAL_ERR_CRC_ERR_RX | | |
126 | FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, | |
127 | ||
128 | INT_ON_FATAL_ERR = (1 << 5), | |
129 | INT_ON_PHYRDY_CHG = (1 << 4), | |
130 | ||
131 | INT_ON_SIGNATURE_UPDATE = (1 << 3), | |
132 | INT_ON_SNOTIFY_UPDATE = (1 << 2), | |
133 | INT_ON_SINGL_DEVICE_ERR = (1 << 1), | |
134 | INT_ON_CMD_COMPLETE = 1, | |
135 | ||
136 | INT_ON_ERROR = INT_ON_FATAL_ERR | | |
137 | INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, | |
138 | ||
139 | /* | |
140 | * Host Control Register (HControl) bitdefs | |
141 | */ | |
142 | HCONTROL_ONLINE_PHY_RST = (1 << 31), | |
143 | HCONTROL_FORCE_OFFLINE = (1 << 30), | |
144 | HCONTROL_PARITY_PROT_MOD = (1 << 14), | |
145 | HCONTROL_DPATH_PARITY = (1 << 12), | |
146 | HCONTROL_SNOOP_ENABLE = (1 << 10), | |
147 | HCONTROL_PMP_ATTACHED = (1 << 9), | |
148 | HCONTROL_COPYOUT_STATFIS = (1 << 8), | |
149 | IE_ON_FATAL_ERR = (1 << 5), | |
150 | IE_ON_PHYRDY_CHG = (1 << 4), | |
151 | IE_ON_SIGNATURE_UPDATE = (1 << 3), | |
152 | IE_ON_SNOTIFY_UPDATE = (1 << 2), | |
153 | IE_ON_SINGL_DEVICE_ERR = (1 << 1), | |
154 | IE_ON_CMD_COMPLETE = 1, | |
155 | ||
156 | DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | | |
157 | IE_ON_SIGNATURE_UPDATE | | |
158 | IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, | |
159 | ||
160 | EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), | |
161 | DATA_SNOOP_ENABLE = (1 << 22), | |
162 | }; | |
163 | ||
164 | /* | |
165 | * SATA Superset Registers | |
166 | */ | |
167 | enum { | |
168 | SSTATUS = 0, | |
169 | SERROR = 4, | |
170 | SCONTROL = 8, | |
171 | SNOTIFY = 0xC, | |
172 | }; | |
173 | ||
174 | /* | |
175 | * Control Status Register Set | |
176 | */ | |
177 | enum { | |
178 | TRANSCFG = 0, | |
179 | TRANSSTATUS = 4, | |
180 | LINKCFG = 8, | |
181 | LINKCFG1 = 0xC, | |
182 | LINKCFG2 = 0x10, | |
183 | LINKSTATUS = 0x14, | |
184 | LINKSTATUS1 = 0x18, | |
185 | PHYCTRLCFG = 0x1C, | |
186 | COMMANDSTAT = 0x20, | |
187 | }; | |
188 | ||
189 | /* PHY (link-layer) configuration control */ | |
190 | enum { | |
191 | PHY_BIST_ENABLE = 0x01, | |
192 | }; | |
193 | ||
194 | /* | |
195 | * Command Header Table entry, i.e, command slot | |
196 | * 4 Dwords per command slot, command header size == 64 Dwords. | |
197 | */ | |
198 | struct cmdhdr_tbl_entry { | |
199 | u32 cda; | |
200 | u32 prde_fis_len; | |
201 | u32 ttl; | |
202 | u32 desc_info; | |
203 | }; | |
204 | ||
205 | /* | |
206 | * Description information bitdefs | |
207 | */ | |
208 | enum { | |
209 | VENDOR_SPECIFIC_BIST = (1 << 10), | |
210 | CMD_DESC_SNOOP_ENABLE = (1 << 9), | |
211 | FPDMA_QUEUED_CMD = (1 << 8), | |
212 | SRST_CMD = (1 << 7), | |
213 | BIST = (1 << 6), | |
214 | ATAPI_CMD = (1 << 5), | |
215 | }; | |
216 | ||
217 | /* | |
218 | * Command Descriptor | |
219 | */ | |
220 | struct command_desc { | |
221 | u8 cfis[8 * 4]; | |
222 | u8 sfis[8 * 4]; | |
223 | u8 acmd[4 * 4]; | |
224 | u8 fill[4 * 4]; | |
225 | u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; | |
226 | u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; | |
227 | }; | |
228 | ||
229 | /* | |
230 | * Physical region table descriptor(PRD) | |
231 | */ | |
232 | ||
233 | struct prde { | |
234 | u32 dba; | |
235 | u8 fill[2 * 4]; | |
236 | u32 ddc_and_ext; | |
237 | }; | |
238 | ||
239 | /* | |
240 | * ata_port private data | |
241 | * This is our per-port instance data. | |
242 | */ | |
243 | struct sata_fsl_port_priv { | |
244 | struct cmdhdr_tbl_entry *cmdslot; | |
245 | dma_addr_t cmdslot_paddr; | |
246 | struct command_desc *cmdentry; | |
247 | dma_addr_t cmdentry_paddr; | |
248 | ||
249 | /* | |
250 | * SATA FSL controller has a Status FIS which should contain the | |
251 | * received D2H FIS & taskfile registers. This SFIS is present in | |
252 | * the command descriptor, and to have a ready reference to it, | |
253 | * we are caching it here, quite similar to what is done in H/W on | |
254 | * AHCI compliant devices by copying taskfile fields to a 32-bit | |
255 | * register. | |
256 | */ | |
257 | ||
258 | struct ata_taskfile tf; | |
259 | }; | |
260 | ||
261 | /* | |
262 | * ata_port->host_set private data | |
263 | */ | |
264 | struct sata_fsl_host_priv { | |
265 | void __iomem *hcr_base; | |
266 | void __iomem *ssr_base; | |
267 | void __iomem *csr_base; | |
268 | }; | |
269 | ||
270 | static inline unsigned int sata_fsl_tag(unsigned int tag, | |
271 | void __iomem * hcr_base) | |
272 | { | |
273 | /* We let libATA core do actual (queue) tag allocation */ | |
274 | ||
275 | /* all non NCQ/queued commands should have tag#0 */ | |
276 | if (ata_tag_internal(tag)) { | |
277 | DPRINTK("mapping internal cmds to tag#0\n"); | |
278 | return 0; | |
279 | } | |
280 | ||
281 | if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { | |
282 | DPRINTK("tag %d invalid : out of range\n", tag); | |
283 | return 0; | |
284 | } | |
285 | ||
286 | if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { | |
287 | DPRINTK("tag %d invalid : in use!!\n", tag); | |
288 | return 0; | |
289 | } | |
290 | ||
291 | return tag; | |
292 | } | |
293 | ||
294 | static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, | |
295 | unsigned int tag, u32 desc_info, | |
296 | u32 data_xfer_len, u8 num_prde, | |
297 | u8 fis_len) | |
298 | { | |
299 | dma_addr_t cmd_descriptor_address; | |
300 | ||
301 | cmd_descriptor_address = pp->cmdentry_paddr + | |
302 | tag * SATA_FSL_CMD_DESC_SIZE; | |
303 | ||
304 | /* NOTE: both data_xfer_len & fis_len are Dword counts */ | |
305 | ||
306 | pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); | |
307 | pp->cmdslot[tag].prde_fis_len = | |
308 | cpu_to_le32((num_prde << 16) | (fis_len << 2)); | |
309 | pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); | |
310 | pp->cmdslot[tag].desc_info = cpu_to_le32((desc_info | (tag & 0x1F))); | |
311 | ||
312 | VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", | |
313 | pp->cmdslot[tag].cda, | |
314 | pp->cmdslot[tag].prde_fis_len, | |
315 | pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); | |
316 | ||
317 | } | |
318 | ||
319 | static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, | |
320 | u32 * ttl, dma_addr_t cmd_desc_paddr) | |
321 | { | |
322 | struct scatterlist *sg; | |
323 | unsigned int num_prde = 0; | |
324 | u32 ttl_dwords = 0; | |
325 | ||
326 | /* | |
327 | * NOTE : direct & indirect prdt's are contigiously allocated | |
328 | */ | |
329 | struct prde *prd = (struct prde *)&((struct command_desc *) | |
330 | cmd_desc)->prdt; | |
331 | ||
332 | struct prde *prd_ptr_to_indirect_ext = NULL; | |
333 | unsigned indirect_ext_segment_sz = 0; | |
334 | dma_addr_t indirect_ext_segment_paddr; | |
335 | ||
336 | VPRINTK("SATA FSL : cd = 0x%x, prd = 0x%x\n", cmd_desc, prd); | |
337 | ||
338 | indirect_ext_segment_paddr = cmd_desc_paddr + | |
339 | SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; | |
340 | ||
341 | ata_for_each_sg(sg, qc) { | |
342 | dma_addr_t sg_addr = sg_dma_address(sg); | |
343 | u32 sg_len = sg_dma_len(sg); | |
344 | ||
345 | VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n", | |
346 | sg_addr, sg_len); | |
347 | ||
348 | /* warn if each s/g element is not dword aligned */ | |
349 | if (sg_addr & 0x03) | |
350 | ata_port_printk(qc->ap, KERN_ERR, | |
351 | "s/g addr unaligned : 0x%x\n", sg_addr); | |
352 | if (sg_len & 0x03) | |
353 | ata_port_printk(qc->ap, KERN_ERR, | |
354 | "s/g len unaligned : 0x%x\n", sg_len); | |
355 | ||
356 | if ((num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1)) && | |
357 | !ata_sg_is_last(sg, qc)) { | |
358 | VPRINTK("setting indirect prde\n"); | |
359 | prd_ptr_to_indirect_ext = prd; | |
360 | prd->dba = cpu_to_le32(indirect_ext_segment_paddr); | |
361 | indirect_ext_segment_sz = 0; | |
362 | ++prd; | |
363 | ++num_prde; | |
364 | } | |
365 | ||
366 | ttl_dwords += sg_len; | |
367 | prd->dba = cpu_to_le32(sg_addr); | |
368 | prd->ddc_and_ext = | |
369 | cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03)); | |
370 | ||
371 | VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", | |
372 | ttl_dwords, prd->dba, prd->ddc_and_ext); | |
373 | ||
374 | ++num_prde; | |
375 | ++prd; | |
376 | if (prd_ptr_to_indirect_ext) | |
377 | indirect_ext_segment_sz += sg_len; | |
378 | } | |
379 | ||
380 | if (prd_ptr_to_indirect_ext) { | |
381 | /* set indirect extension flag along with indirect ext. size */ | |
382 | prd_ptr_to_indirect_ext->ddc_and_ext = | |
383 | cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | | |
384 | DATA_SNOOP_ENABLE | | |
385 | (indirect_ext_segment_sz & ~0x03))); | |
386 | } | |
387 | ||
388 | *ttl = ttl_dwords; | |
389 | return num_prde; | |
390 | } | |
391 | ||
392 | static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) | |
393 | { | |
394 | struct ata_port *ap = qc->ap; | |
395 | struct sata_fsl_port_priv *pp = ap->private_data; | |
396 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
397 | void __iomem *hcr_base = host_priv->hcr_base; | |
398 | unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); | |
399 | struct command_desc *cd; | |
400 | u32 desc_info = CMD_DESC_SNOOP_ENABLE; | |
401 | u32 num_prde = 0; | |
402 | u32 ttl_dwords = 0; | |
403 | dma_addr_t cd_paddr; | |
404 | ||
405 | cd = (struct command_desc *)pp->cmdentry + tag; | |
406 | cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; | |
407 | ||
408 | ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) & cd->cfis); | |
409 | ||
410 | VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", | |
411 | cd->cfis[0], cd->cfis[1], cd->cfis[2]); | |
412 | ||
413 | if (qc->tf.protocol == ATA_PROT_NCQ) { | |
414 | VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", | |
415 | cd->cfis[3], cd->cfis[11]); | |
416 | } | |
417 | ||
418 | /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ | |
419 | if (is_atapi_taskfile(&qc->tf)) { | |
420 | desc_info |= ATAPI_CMD; | |
421 | memset((void *)&cd->acmd, 0, 32); | |
422 | memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); | |
423 | } | |
424 | ||
425 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
426 | num_prde = sata_fsl_fill_sg(qc, (void *)cd, | |
427 | &ttl_dwords, cd_paddr); | |
428 | ||
429 | if (qc->tf.protocol == ATA_PROT_NCQ) | |
430 | desc_info |= FPDMA_QUEUED_CMD; | |
431 | ||
432 | sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, | |
433 | num_prde, 5); | |
434 | ||
435 | VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", | |
436 | desc_info, ttl_dwords, num_prde); | |
437 | } | |
438 | ||
439 | static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) | |
440 | { | |
441 | struct ata_port *ap = qc->ap; | |
442 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
443 | void __iomem *hcr_base = host_priv->hcr_base; | |
444 | unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); | |
445 | ||
446 | VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", | |
447 | ioread32(CQ + hcr_base), | |
448 | ioread32(CA + hcr_base), | |
449 | ioread32(CE + hcr_base), ioread32(CC + hcr_base)); | |
450 | ||
451 | /* Simply queue command to the controller/device */ | |
452 | iowrite32(1 << tag, CQ + hcr_base); | |
453 | ||
454 | VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", | |
455 | tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); | |
456 | ||
457 | VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", | |
458 | ioread32(CE + hcr_base), | |
459 | ioread32(DE + hcr_base), | |
460 | ioread32(CC + hcr_base), ioread32(COMMANDSTAT + csr_base)); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
465 | static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in, | |
466 | u32 val) | |
467 | { | |
468 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
469 | void __iomem *ssr_base = host_priv->ssr_base; | |
470 | unsigned int sc_reg; | |
471 | ||
472 | switch (sc_reg_in) { | |
473 | case SCR_STATUS: | |
474 | sc_reg = 0; | |
475 | break; | |
476 | case SCR_ERROR: | |
477 | sc_reg = 1; | |
478 | break; | |
479 | case SCR_CONTROL: | |
480 | sc_reg = 2; | |
481 | break; | |
482 | case SCR_ACTIVE: | |
483 | sc_reg = 3; | |
484 | break; | |
485 | default: | |
486 | return -EINVAL; | |
487 | } | |
488 | ||
489 | VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); | |
490 | ||
491 | iowrite32(val, (void __iomem *)ssr_base + (sc_reg * 4)); | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in, | |
496 | u32 *val) | |
497 | { | |
498 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
499 | void __iomem *ssr_base = host_priv->ssr_base; | |
500 | unsigned int sc_reg; | |
501 | ||
502 | switch (sc_reg_in) { | |
503 | case SCR_STATUS: | |
504 | sc_reg = 0; | |
505 | break; | |
506 | case SCR_ERROR: | |
507 | sc_reg = 1; | |
508 | break; | |
509 | case SCR_CONTROL: | |
510 | sc_reg = 2; | |
511 | break; | |
512 | case SCR_ACTIVE: | |
513 | sc_reg = 3; | |
514 | break; | |
515 | default: | |
516 | return -EINVAL; | |
517 | } | |
518 | ||
519 | VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); | |
520 | ||
521 | *val = ioread32((void __iomem *)ssr_base + (sc_reg * 4)); | |
522 | return 0; | |
523 | } | |
524 | ||
525 | static void sata_fsl_freeze(struct ata_port *ap) | |
526 | { | |
527 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
528 | void __iomem *hcr_base = host_priv->hcr_base; | |
529 | u32 temp; | |
530 | ||
531 | VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", | |
532 | ioread32(CQ + hcr_base), | |
533 | ioread32(CA + hcr_base), | |
534 | ioread32(CE + hcr_base), ioread32(DE + hcr_base)); | |
535 | VPRINTK("CmdStat = 0x%x\n", ioread32(csr_base + COMMANDSTAT)); | |
536 | ||
537 | /* disable interrupts on the controller/port */ | |
538 | temp = ioread32(hcr_base + HCONTROL); | |
539 | iowrite32((temp & ~0x3F), hcr_base + HCONTROL); | |
540 | ||
541 | VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", | |
542 | ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); | |
543 | } | |
544 | ||
545 | static void sata_fsl_thaw(struct ata_port *ap) | |
546 | { | |
547 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
548 | void __iomem *hcr_base = host_priv->hcr_base; | |
549 | u32 temp; | |
550 | ||
551 | /* ack. any pending IRQs for this controller/port */ | |
552 | temp = ioread32(hcr_base + HSTATUS); | |
553 | ||
554 | VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); | |
555 | ||
556 | if (temp & 0x3F) | |
557 | iowrite32((temp & 0x3F), hcr_base + HSTATUS); | |
558 | ||
559 | /* enable interrupts on the controller/port */ | |
560 | temp = ioread32(hcr_base + HCONTROL); | |
561 | iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); | |
562 | ||
563 | VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", | |
564 | ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); | |
565 | } | |
566 | ||
567 | /* | |
568 | * NOTE : 1st D2H FIS from device does not update sfis in command descriptor. | |
569 | */ | |
570 | static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd | |
571 | *qc, | |
572 | struct ata_port *ap) | |
573 | { | |
574 | struct sata_fsl_port_priv *pp = ap->private_data; | |
575 | u8 fis[6 * 4]; | |
576 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
577 | void __iomem *hcr_base = host_priv->hcr_base; | |
578 | unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); | |
579 | struct command_desc *cd; | |
580 | ||
581 | cd = pp->cmdentry + tag; | |
582 | ||
583 | memcpy(fis, &cd->sfis, 6 * 4); /* should we use memcpy_from_io() */ | |
584 | ata_tf_from_fis(fis, &pp->tf); | |
585 | } | |
586 | ||
587 | static u8 sata_fsl_check_status(struct ata_port *ap) | |
588 | { | |
589 | struct sata_fsl_port_priv *pp = ap->private_data; | |
590 | ||
591 | return pp->tf.command; | |
592 | } | |
593 | ||
594 | static void sata_fsl_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
595 | { | |
596 | struct sata_fsl_port_priv *pp = ap->private_data; | |
597 | ||
598 | *tf = pp->tf; | |
599 | } | |
600 | ||
601 | static int sata_fsl_port_start(struct ata_port *ap) | |
602 | { | |
603 | struct device *dev = ap->host->dev; | |
604 | struct sata_fsl_port_priv *pp; | |
605 | int retval; | |
606 | void *mem; | |
607 | dma_addr_t mem_dma; | |
608 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
609 | void __iomem *hcr_base = host_priv->hcr_base; | |
610 | u32 temp; | |
611 | ||
612 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); | |
613 | if (!pp) | |
614 | return -ENOMEM; | |
615 | ||
616 | /* | |
617 | * allocate per command dma alignment pad buffer, which is used | |
618 | * internally by libATA to ensure that all transfers ending on | |
619 | * unaligned boundaries are padded, to align on Dword boundaries | |
620 | */ | |
621 | retval = ata_pad_alloc(ap, dev); | |
622 | if (retval) { | |
623 | kfree(pp); | |
624 | return retval; | |
625 | } | |
626 | ||
627 | mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, | |
628 | GFP_KERNEL); | |
629 | if (!mem) { | |
630 | ata_pad_free(ap, dev); | |
631 | kfree(pp); | |
632 | return -ENOMEM; | |
633 | } | |
634 | memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); | |
635 | ||
636 | pp->cmdslot = mem; | |
637 | pp->cmdslot_paddr = mem_dma; | |
638 | ||
639 | mem += SATA_FSL_CMD_SLOT_SIZE; | |
640 | mem_dma += SATA_FSL_CMD_SLOT_SIZE; | |
641 | ||
642 | pp->cmdentry = mem; | |
643 | pp->cmdentry_paddr = mem_dma; | |
644 | ||
645 | ap->private_data = pp; | |
646 | ||
647 | VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", | |
648 | pp->cmdslot_paddr, pp->cmdentry_paddr); | |
649 | ||
650 | /* Now, update the CHBA register in host controller cmd register set */ | |
651 | iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); | |
652 | ||
653 | /* | |
654 | * Now, we can bring the controller on-line & also initiate | |
655 | * the COMINIT sequence, we simply return here and the boot-probing | |
656 | * & device discovery process is re-initiated by libATA using a | |
657 | * Softreset EH (dummy) session. Hence, boot probing and device | |
658 | * discovey will be part of sata_fsl_softreset() callback. | |
659 | */ | |
660 | ||
661 | temp = ioread32(hcr_base + HCONTROL); | |
662 | iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); | |
663 | ||
664 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
665 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
666 | VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); | |
667 | ||
668 | /* | |
669 | * Workaround for 8315DS board 3gbps link-up issue, | |
670 | * currently limit SATA port to GEN1 speed | |
671 | */ | |
672 | sata_fsl_scr_read(ap, SCR_CONTROL, &temp); | |
673 | temp &= ~(0xF << 4); | |
674 | temp |= (0x1 << 4); | |
675 | sata_fsl_scr_write(ap, SCR_CONTROL, temp); | |
676 | ||
677 | sata_fsl_scr_read(ap, SCR_CONTROL, &temp); | |
678 | dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n", | |
679 | temp); | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | static void sata_fsl_port_stop(struct ata_port *ap) | |
685 | { | |
686 | struct device *dev = ap->host->dev; | |
687 | struct sata_fsl_port_priv *pp = ap->private_data; | |
688 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
689 | void __iomem *hcr_base = host_priv->hcr_base; | |
690 | u32 temp; | |
691 | ||
692 | /* | |
693 | * Force host controller to go off-line, aborting current operations | |
694 | */ | |
695 | temp = ioread32(hcr_base + HCONTROL); | |
696 | temp &= ~HCONTROL_ONLINE_PHY_RST; | |
697 | temp |= HCONTROL_FORCE_OFFLINE; | |
698 | iowrite32(temp, hcr_base + HCONTROL); | |
699 | ||
700 | /* Poll for controller to go offline - should happen immediately */ | |
701 | ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); | |
702 | ||
703 | ap->private_data = NULL; | |
704 | dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, | |
705 | pp->cmdslot, pp->cmdslot_paddr); | |
706 | ||
707 | ata_pad_free(ap, dev); | |
708 | kfree(pp); | |
709 | } | |
710 | ||
711 | static unsigned int sata_fsl_dev_classify(struct ata_port *ap) | |
712 | { | |
713 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
714 | void __iomem *hcr_base = host_priv->hcr_base; | |
715 | struct ata_taskfile tf; | |
716 | u32 temp; | |
717 | ||
718 | temp = ioread32(hcr_base + SIGNATURE); | |
719 | ||
720 | VPRINTK("raw sig = 0x%x\n", temp); | |
721 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
722 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
723 | ||
724 | tf.lbah = (temp >> 24) & 0xff; | |
725 | tf.lbam = (temp >> 16) & 0xff; | |
726 | tf.lbal = (temp >> 8) & 0xff; | |
727 | tf.nsect = temp & 0xff; | |
728 | ||
729 | return ata_dev_classify(&tf); | |
730 | } | |
731 | ||
1bf617b7 | 732 | static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, |
faf0b2e5 LY |
733 | unsigned long deadline) |
734 | { | |
1bf617b7 | 735 | struct ata_port *ap = link->ap; |
faf0b2e5 LY |
736 | struct sata_fsl_port_priv *pp = ap->private_data; |
737 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
738 | void __iomem *hcr_base = host_priv->hcr_base; | |
739 | u32 temp; | |
740 | struct ata_taskfile tf; | |
741 | u8 *cfis; | |
742 | u32 Serror; | |
743 | int i = 0; | |
744 | struct ata_queued_cmd qc; | |
745 | u8 *buf; | |
746 | dma_addr_t dma_address; | |
747 | struct scatterlist *sg; | |
748 | unsigned long start_jiffies; | |
749 | ||
750 | DPRINTK("in xx_softreset\n"); | |
751 | ||
752 | try_offline_again: | |
753 | /* | |
754 | * Force host controller to go off-line, aborting current operations | |
755 | */ | |
756 | temp = ioread32(hcr_base + HCONTROL); | |
757 | temp &= ~HCONTROL_ONLINE_PHY_RST; | |
758 | iowrite32(temp, hcr_base + HCONTROL); | |
759 | ||
760 | /* Poll for controller to go offline */ | |
761 | temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); | |
762 | ||
763 | if (temp & ONLINE) { | |
764 | ata_port_printk(ap, KERN_ERR, | |
765 | "Softreset failed, not off-lined %d\n", i); | |
766 | ||
767 | /* | |
768 | * Try to offline controller atleast twice | |
769 | */ | |
770 | i++; | |
771 | if (i == 2) | |
772 | goto err; | |
773 | else | |
774 | goto try_offline_again; | |
775 | } | |
776 | ||
777 | DPRINTK("softreset, controller off-lined\n"); | |
778 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
779 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
780 | ||
781 | /* | |
782 | * PHY reset should remain asserted for atleast 1ms | |
783 | */ | |
784 | msleep(1); | |
785 | ||
786 | /* | |
787 | * Now, bring the host controller online again, this can take time | |
788 | * as PHY reset and communication establishment, 1st D2H FIS and | |
789 | * device signature update is done, on safe side assume 500ms | |
790 | * NOTE : Host online status may be indicated immediately!! | |
791 | */ | |
792 | ||
793 | temp = ioread32(hcr_base + HCONTROL); | |
794 | temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); | |
795 | iowrite32(temp, hcr_base + HCONTROL); | |
796 | ||
797 | temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); | |
798 | ||
799 | if (!(temp & ONLINE)) { | |
800 | ata_port_printk(ap, KERN_ERR, | |
801 | "Softreset failed, not on-lined\n"); | |
802 | goto err; | |
803 | } | |
804 | ||
805 | DPRINTK("softreset, controller off-lined & on-lined\n"); | |
806 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
807 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
808 | ||
809 | /* | |
810 | * First, wait for the PHYRDY change to occur before waiting for | |
811 | * the signature, and also verify if SStatus indicates device | |
812 | * presence | |
813 | */ | |
814 | ||
815 | temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500); | |
1bf617b7 | 816 | if ((!(temp & 0x10)) || ata_link_offline(link)) { |
faf0b2e5 LY |
817 | ata_port_printk(ap, KERN_WARNING, |
818 | "No Device OR PHYRDY change,Hstatus = 0x%x\n", | |
819 | ioread32(hcr_base + HSTATUS)); | |
820 | goto err; | |
821 | } | |
822 | ||
823 | /* | |
824 | * Wait for the first D2H from device,i.e,signature update notification | |
825 | */ | |
826 | start_jiffies = jiffies; | |
827 | temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10, | |
828 | 500, jiffies_to_msecs(deadline - start_jiffies)); | |
829 | ||
830 | if ((temp & 0xFF) != 0x18) { | |
831 | ata_port_printk(ap, KERN_WARNING, "No Signature Update\n"); | |
832 | goto err; | |
833 | } else { | |
834 | ata_port_printk(ap, KERN_INFO, | |
835 | "Signature Update detected @ %d msecs\n", | |
836 | jiffies_to_msecs(jiffies - start_jiffies)); | |
837 | } | |
838 | ||
839 | /* | |
840 | * Send a device reset (SRST) explicitly on command slot #0 | |
841 | * Check : will the command queue (reg) be cleared during offlining ?? | |
842 | * Also we will be online only if Phy commn. has been established | |
843 | * and device presence has been detected, therefore if we have | |
844 | * reached here, we can send a command to the target device | |
845 | */ | |
846 | ||
1bf617b7 | 847 | if (link->sactive) |
faf0b2e5 LY |
848 | goto skip_srst_do_ncq_error_handling; |
849 | ||
850 | DPRINTK("Sending SRST/device reset\n"); | |
851 | ||
1bf617b7 | 852 | ata_tf_init(link->device, &tf); |
faf0b2e5 LY |
853 | cfis = (u8 *) & pp->cmdentry->cfis; |
854 | ||
855 | /* device reset/SRST is a control register update FIS, uses tag0 */ | |
856 | sata_fsl_setup_cmd_hdr_entry(pp, 0, | |
857 | SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); | |
858 | ||
859 | tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ | |
860 | ata_tf_to_fis(&tf, 0, 0, cfis); | |
861 | ||
862 | DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", | |
863 | cfis[0], cfis[1], cfis[2], cfis[3]); | |
864 | ||
865 | /* | |
866 | * Queue SRST command to the controller/device, ensure that no | |
867 | * other commands are active on the controller/device | |
868 | */ | |
869 | ||
870 | DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", | |
871 | ioread32(CQ + hcr_base), | |
872 | ioread32(CA + hcr_base), ioread32(CC + hcr_base)); | |
873 | ||
874 | iowrite32(0xFFFF, CC + hcr_base); | |
875 | iowrite32(1, CQ + hcr_base); | |
876 | ||
877 | temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); | |
878 | if (temp & 0x1) { | |
879 | ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n"); | |
880 | ||
881 | DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", | |
882 | ioread32(CQ + hcr_base), | |
883 | ioread32(CA + hcr_base), ioread32(CC + hcr_base)); | |
884 | ||
885 | sata_fsl_scr_read(ap, SCR_ERROR, &Serror); | |
886 | ||
887 | DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
888 | DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
889 | DPRINTK("Serror = 0x%x\n", Serror); | |
890 | goto err; | |
891 | } | |
892 | ||
893 | msleep(1); | |
894 | ||
895 | /* | |
896 | * SATA device enters reset state after receving a Control register | |
897 | * FIS with SRST bit asserted and it awaits another H2D Control reg. | |
898 | * FIS with SRST bit cleared, then the device does internal diags & | |
899 | * initialization, followed by indicating it's initialization status | |
900 | * using ATA signature D2H register FIS to the host controller. | |
901 | */ | |
902 | ||
903 | sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5); | |
904 | ||
905 | tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ | |
906 | ata_tf_to_fis(&tf, 0, 0, cfis); | |
907 | ||
908 | iowrite32(1, CQ + hcr_base); | |
909 | msleep(150); /* ?? */ | |
910 | ||
911 | /* | |
912 | * The above command would have signalled an interrupt on command | |
913 | * complete, which needs special handling, by clearing the Nth | |
914 | * command bit of the CCreg | |
915 | */ | |
916 | iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ | |
917 | goto check_device_signature; | |
918 | ||
919 | skip_srst_do_ncq_error_handling: | |
920 | ||
921 | VPRINTK("Sending read log ext(10h) command\n"); | |
922 | ||
923 | memset(&qc, 0, sizeof(struct ata_queued_cmd)); | |
1bf617b7 | 924 | ata_tf_init(link->device, &tf); |
faf0b2e5 LY |
925 | |
926 | tf.command = ATA_CMD_READ_LOG_EXT; | |
927 | tf.lbal = ATA_LOG_SATA_NCQ; | |
928 | tf.nsect = 1; | |
929 | tf.hob_nsect = 0; | |
930 | tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_LBA48 | ATA_TFLAG_DEVICE; | |
931 | tf.protocol = ATA_PROT_PIO; | |
932 | ||
933 | qc.tag = ATA_TAG_INTERNAL; | |
934 | qc.scsicmd = NULL; | |
935 | qc.ap = ap; | |
1bf617b7 | 936 | qc.dev = link->device; |
faf0b2e5 LY |
937 | |
938 | qc.tf = tf; | |
939 | qc.flags |= ATA_QCFLAG_RESULT_TF; | |
940 | qc.dma_dir = DMA_FROM_DEVICE; | |
941 | ||
942 | buf = ap->sector_buf; | |
943 | ata_sg_init_one(&qc, buf, 1 * ATA_SECT_SIZE); | |
944 | ||
945 | /* | |
946 | * Need to DMA-map the memory buffer associated with the command | |
947 | */ | |
948 | ||
949 | sg = qc.__sg; | |
950 | dma_address = dma_map_single(ap->dev, qc.buf_virt, | |
951 | sg->length, DMA_FROM_DEVICE); | |
952 | ||
953 | sg_dma_address(sg) = dma_address; | |
954 | sg_dma_len(sg) = sg->length; | |
955 | ||
956 | VPRINTK("EH, addr = 0x%x, len = 0x%x\n", dma_address, sg->length); | |
957 | ||
958 | sata_fsl_qc_prep(&qc); | |
959 | sata_fsl_qc_issue(&qc); | |
960 | ||
961 | temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); | |
962 | if (temp & 0x1) { | |
963 | VPRINTK("READ_LOG_EXT_10H issue failed\n"); | |
964 | ||
965 | VPRINTK("READ_LOG@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", | |
966 | ioread32(CQ + hcr_base), | |
967 | ioread32(CA + hcr_base), ioread32(CC + hcr_base)); | |
968 | ||
969 | sata_fsl_scr_read(ap, SCR_ERROR, &Serror); | |
970 | ||
971 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
972 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
973 | VPRINTK("Serror = 0x%x\n", Serror); | |
974 | goto err; | |
975 | } | |
976 | ||
977 | iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ | |
978 | ||
979 | check_device_signature: | |
980 | ||
981 | DPRINTK("SATA FSL : Now checking device signature\n"); | |
982 | ||
983 | *class = ATA_DEV_NONE; | |
984 | ||
985 | /* Verify if SStatus indicates device presence */ | |
1bf617b7 | 986 | if (ata_link_online(link)) { |
faf0b2e5 LY |
987 | /* |
988 | * if we are here, device presence has been detected, | |
989 | * 1st D2H FIS would have been received, but sfis in | |
990 | * command desc. is not updated, but signature register | |
991 | * would have been updated | |
992 | */ | |
993 | ||
994 | *class = sata_fsl_dev_classify(ap); | |
995 | ||
996 | DPRINTK("class = %d\n", *class); | |
997 | VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); | |
998 | VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); | |
999 | } | |
1000 | ||
1001 | return 0; | |
1002 | ||
1003 | err: | |
1004 | return -EIO; | |
1005 | } | |
1006 | ||
1007 | static int sata_fsl_hardreset(struct ata_port *ap, unsigned int *class, | |
1008 | unsigned long deadline) | |
1009 | { | |
1010 | int retval; | |
1011 | ||
1012 | retval = sata_std_hardreset(ap, class, deadline); | |
1013 | ||
1014 | DPRINTK("SATA FSL : in xx_hardreset, retval = 0x%d\n", retval); | |
1015 | ||
1016 | return retval; | |
1017 | } | |
1018 | ||
1019 | static void sata_fsl_error_handler(struct ata_port *ap) | |
1020 | { | |
1021 | ||
1022 | DPRINTK("in xx_error_handler\n"); | |
1023 | ||
1024 | /* perform recovery */ | |
1025 | ata_do_eh(ap, ata_std_prereset, sata_fsl_softreset, sata_fsl_hardreset, | |
1026 | ata_std_postreset); | |
1027 | } | |
1028 | ||
1029 | static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) | |
1030 | { | |
1031 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1032 | qc->err_mask |= AC_ERR_OTHER; | |
1033 | ||
1034 | if (qc->err_mask) { | |
1035 | /* make DMA engine forget about the failed command */ | |
1036 | ||
1037 | } | |
1038 | } | |
1039 | ||
1040 | static void sata_fsl_irq_clear(struct ata_port *ap) | |
1041 | { | |
1042 | /* unused */ | |
1043 | } | |
1044 | ||
1045 | static void sata_fsl_error_intr(struct ata_port *ap) | |
1046 | { | |
1bf617b7 LY |
1047 | struct ata_link *link = &ap->link; |
1048 | struct ata_eh_info *ehi = &link->eh_info; | |
faf0b2e5 LY |
1049 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
1050 | void __iomem *hcr_base = host_priv->hcr_base; | |
1051 | u32 hstatus, dereg, cereg = 0, SError = 0; | |
1052 | unsigned int err_mask = 0, action = 0; | |
1053 | struct ata_queued_cmd *qc; | |
1054 | int freeze = 0; | |
1055 | ||
1056 | hstatus = ioread32(hcr_base + HSTATUS); | |
1057 | cereg = ioread32(hcr_base + CE); | |
1058 | ||
1059 | ata_ehi_clear_desc(ehi); | |
1060 | ||
1061 | /* | |
1062 | * Handle & Clear SError | |
1063 | */ | |
1064 | ||
1065 | sata_fsl_scr_read(ap, SCR_ERROR, &SError); | |
1066 | if (unlikely(SError & 0xFFFF0000)) { | |
1067 | sata_fsl_scr_write(ap, SCR_ERROR, SError); | |
1068 | err_mask |= AC_ERR_ATA_BUS; | |
1069 | } | |
1070 | ||
1071 | DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", | |
1072 | hstatus, cereg, ioread32(hcr_base + DE), SError); | |
1073 | ||
1074 | /* handle single device errors */ | |
1075 | if (cereg) { | |
1076 | /* | |
1077 | * clear the command error, also clears queue to the device | |
1078 | * in error, and we can (re)issue commands to this device. | |
1079 | * When a device is in error all commands queued into the | |
1080 | * host controller and at the device are considered aborted | |
1081 | * and the queue for that device is stopped. Now, after | |
1082 | * clearing the device error, we can issue commands to the | |
1083 | * device to interrogate it to find the source of the error. | |
1084 | */ | |
1085 | dereg = ioread32(hcr_base + DE); | |
1086 | iowrite32(dereg, hcr_base + DE); | |
1087 | iowrite32(cereg, hcr_base + CE); | |
1088 | ||
1089 | DPRINTK("single device error, CE=0x%x, DE=0x%x\n", | |
1090 | ioread32(hcr_base + CE), ioread32(hcr_base + DE)); | |
1091 | /* | |
1092 | * We should consider this as non fatal error, and TF must | |
1093 | * be updated as done below. | |
1094 | */ | |
1095 | ||
1096 | err_mask |= AC_ERR_DEV; | |
1097 | } | |
1098 | ||
1099 | /* handle fatal errors */ | |
1100 | if (hstatus & FATAL_ERROR_DECODE) { | |
1101 | err_mask |= AC_ERR_ATA_BUS; | |
1102 | action |= ATA_EH_SOFTRESET; | |
1103 | /* how will fatal error interrupts be completed ?? */ | |
1104 | freeze = 1; | |
1105 | } | |
1106 | ||
1107 | /* Handle PHYRDY change notification */ | |
1108 | if (hstatus & INT_ON_PHYRDY_CHG) { | |
1109 | DPRINTK("SATA FSL: PHYRDY change indication\n"); | |
1110 | ||
1111 | /* Setup a soft-reset EH action */ | |
1112 | ata_ehi_hotplugged(ehi); | |
1113 | freeze = 1; | |
1114 | } | |
1115 | ||
1116 | /* record error info */ | |
1bf617b7 | 1117 | qc = ata_qc_from_tag(ap, link->active_tag); |
faf0b2e5 LY |
1118 | |
1119 | if (qc) { | |
1120 | sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap); | |
1121 | qc->err_mask |= err_mask; | |
1122 | } else | |
1123 | ehi->err_mask |= err_mask; | |
1124 | ||
1125 | ehi->action |= action; | |
1126 | ehi->serror |= SError; | |
1127 | ||
1128 | /* freeze or abort */ | |
1129 | if (freeze) | |
1130 | ata_port_freeze(ap); | |
1131 | else | |
1132 | ata_port_abort(ap); | |
1133 | } | |
1134 | ||
1135 | static void sata_fsl_qc_complete(struct ata_queued_cmd *qc) | |
1136 | { | |
1137 | if (qc->flags & ATA_QCFLAG_RESULT_TF) { | |
1138 | DPRINTK("xx_qc_complete called\n"); | |
1139 | sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap); | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | static void sata_fsl_host_intr(struct ata_port *ap) | |
1144 | { | |
1bf617b7 | 1145 | struct ata_link *link = &ap->link; |
faf0b2e5 LY |
1146 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
1147 | void __iomem *hcr_base = host_priv->hcr_base; | |
1148 | u32 hstatus, qc_active = 0; | |
1149 | struct ata_queued_cmd *qc; | |
1150 | u32 SError; | |
1151 | ||
1152 | hstatus = ioread32(hcr_base + HSTATUS); | |
1153 | ||
1154 | sata_fsl_scr_read(ap, SCR_ERROR, &SError); | |
1155 | ||
1156 | if (unlikely(SError & 0xFFFF0000)) { | |
1157 | DPRINTK("serror @host_intr : 0x%x\n", SError); | |
1158 | sata_fsl_error_intr(ap); | |
1159 | ||
1160 | } | |
1161 | ||
1162 | if (unlikely(hstatus & INT_ON_ERROR)) { | |
1163 | DPRINTK("error interrupt!!\n"); | |
1164 | sata_fsl_error_intr(ap); | |
1165 | return; | |
1166 | } | |
1167 | ||
1bf617b7 | 1168 | if (link->sactive) { /* only true for NCQ commands */ |
faf0b2e5 LY |
1169 | int i; |
1170 | /* Read command completed register */ | |
1171 | qc_active = ioread32(hcr_base + CC); | |
1172 | /* clear CC bit, this will also complete the interrupt */ | |
1173 | iowrite32(qc_active, hcr_base + CC); | |
1174 | ||
1175 | DPRINTK("Status of all queues :\n"); | |
1176 | DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n", | |
1177 | qc_active, ioread32(hcr_base + CA), | |
1178 | ioread32(hcr_base + CE)); | |
1179 | ||
1180 | for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { | |
1181 | if (qc_active & (1 << i)) { | |
1182 | qc = ata_qc_from_tag(ap, i); | |
1183 | if (qc) { | |
1184 | sata_fsl_qc_complete(qc); | |
1185 | ata_qc_complete(qc); | |
1186 | } | |
1187 | DPRINTK | |
1188 | ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", | |
1189 | i, ioread32(hcr_base + CC), | |
1190 | ioread32(hcr_base + CA)); | |
1191 | } | |
1192 | } | |
1193 | return; | |
1194 | ||
1195 | } else if (ap->qc_active) { | |
1196 | iowrite32(1, hcr_base + CC); | |
1bf617b7 | 1197 | qc = ata_qc_from_tag(ap, link->active_tag); |
faf0b2e5 LY |
1198 | |
1199 | DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n", | |
1bf617b7 | 1200 | link->active_tag, ioread32(hcr_base + CC)); |
faf0b2e5 LY |
1201 | |
1202 | if (qc) { | |
1203 | sata_fsl_qc_complete(qc); | |
1204 | ata_qc_complete(qc); | |
1205 | } | |
1206 | } else { | |
1207 | /* Spurious Interrupt!! */ | |
1208 | DPRINTK("spurious interrupt!!, CC = 0x%x\n", | |
1209 | ioread32(hcr_base + CC)); | |
1210 | return; | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) | |
1215 | { | |
1216 | struct ata_host *host = dev_instance; | |
1217 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
1218 | void __iomem *hcr_base = host_priv->hcr_base; | |
1219 | u32 interrupt_enables; | |
1220 | unsigned handled = 0; | |
1221 | struct ata_port *ap; | |
1222 | ||
1223 | /* ack. any pending IRQs for this controller/port */ | |
1224 | interrupt_enables = ioread32(hcr_base + HSTATUS); | |
1225 | interrupt_enables &= 0x3F; | |
1226 | ||
1227 | DPRINTK("interrupt status 0x%x\n", interrupt_enables); | |
1228 | ||
1229 | if (!interrupt_enables) | |
1230 | return IRQ_NONE; | |
1231 | ||
1232 | spin_lock(&host->lock); | |
1233 | ||
1234 | /* Assuming one port per host controller */ | |
1235 | ||
1236 | ap = host->ports[0]; | |
1237 | if (ap) { | |
1238 | sata_fsl_host_intr(ap); | |
1239 | } else { | |
1240 | dev_printk(KERN_WARNING, host->dev, | |
1241 | "interrupt on disabled port 0\n"); | |
1242 | } | |
1243 | ||
1244 | iowrite32(interrupt_enables, hcr_base + HSTATUS); | |
1245 | handled = 1; | |
1246 | ||
1247 | spin_unlock(&host->lock); | |
1248 | ||
1249 | return IRQ_RETVAL(handled); | |
1250 | } | |
1251 | ||
1252 | /* | |
1253 | * Multiple ports are represented by multiple SATA controllers with | |
1254 | * one port per controller | |
1255 | */ | |
1256 | static int sata_fsl_init_controller(struct ata_host *host) | |
1257 | { | |
1258 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
1259 | void __iomem *hcr_base = host_priv->hcr_base; | |
1260 | u32 temp; | |
1261 | ||
1262 | /* | |
1263 | * NOTE : We cannot bring the controller online before setting | |
1264 | * the CHBA, hence main controller initialization is done as | |
1265 | * part of the port_start() callback | |
1266 | */ | |
1267 | ||
1268 | /* ack. any pending IRQs for this controller/port */ | |
1269 | temp = ioread32(hcr_base + HSTATUS); | |
1270 | if (temp & 0x3F) | |
1271 | iowrite32((temp & 0x3F), hcr_base + HSTATUS); | |
1272 | ||
1273 | /* Keep interrupts disabled on the controller */ | |
1274 | temp = ioread32(hcr_base + HCONTROL); | |
1275 | iowrite32((temp & ~0x3F), hcr_base + HCONTROL); | |
1276 | ||
1277 | /* Disable interrupt coalescing control(icc), for the moment */ | |
1278 | DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); | |
1279 | iowrite32(0x01000000, hcr_base + ICC); | |
1280 | ||
1281 | /* clear error registers, SError is cleared by libATA */ | |
1282 | iowrite32(0x00000FFFF, hcr_base + CE); | |
1283 | iowrite32(0x00000FFFF, hcr_base + DE); | |
1284 | ||
1285 | /* initially assuming no Port multiplier, set CQPMP to 0 */ | |
1286 | iowrite32(0x0, hcr_base + CQPMP); | |
1287 | ||
1288 | /* | |
1289 | * host controller will be brought on-line, during xx_port_start() | |
1290 | * callback, that should also initiate the OOB, COMINIT sequence | |
1291 | */ | |
1292 | ||
1293 | DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
1294 | DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
1295 | ||
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | /* | |
1300 | * scsi mid-layer and libata interface structures | |
1301 | */ | |
1302 | static struct scsi_host_template sata_fsl_sht = { | |
1303 | .module = THIS_MODULE, | |
1304 | .name = "sata_fsl", | |
1305 | .ioctl = ata_scsi_ioctl, | |
1306 | .queuecommand = ata_scsi_queuecmd, | |
1307 | .change_queue_depth = ata_scsi_change_queue_depth, | |
1308 | .can_queue = SATA_FSL_QUEUE_DEPTH, | |
1309 | .this_id = ATA_SHT_THIS_ID, | |
1310 | .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, | |
1311 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
1312 | .emulated = ATA_SHT_EMULATED, | |
1313 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
1314 | .proc_name = "sata_fsl", | |
1315 | .dma_boundary = ATA_DMA_BOUNDARY, | |
1316 | .slave_configure = ata_scsi_slave_config, | |
1317 | .slave_destroy = ata_scsi_slave_destroy, | |
1318 | .bios_param = ata_std_bios_param, | |
1319 | #ifdef CONFIG_PM | |
1320 | .suspend = ata_scsi_device_suspend, | |
1321 | .resume = ata_scsi_device_resume, | |
1322 | #endif | |
1323 | }; | |
1324 | ||
1325 | static const struct ata_port_operations sata_fsl_ops = { | |
faf0b2e5 LY |
1326 | .check_status = sata_fsl_check_status, |
1327 | .check_altstatus = sata_fsl_check_status, | |
1328 | .dev_select = ata_noop_dev_select, | |
1329 | ||
1330 | .tf_read = sata_fsl_tf_read, | |
1331 | ||
1332 | .qc_prep = sata_fsl_qc_prep, | |
1333 | .qc_issue = sata_fsl_qc_issue, | |
1334 | .irq_clear = sata_fsl_irq_clear, | |
faf0b2e5 LY |
1335 | |
1336 | .scr_read = sata_fsl_scr_read, | |
1337 | .scr_write = sata_fsl_scr_write, | |
1338 | ||
1339 | .freeze = sata_fsl_freeze, | |
1340 | .thaw = sata_fsl_thaw, | |
1341 | .error_handler = sata_fsl_error_handler, | |
1342 | .post_internal_cmd = sata_fsl_post_internal_cmd, | |
1343 | ||
1344 | .port_start = sata_fsl_port_start, | |
1345 | .port_stop = sata_fsl_port_stop, | |
1346 | }; | |
1347 | ||
1348 | static const struct ata_port_info sata_fsl_port_info[] = { | |
1349 | { | |
1350 | .flags = SATA_FSL_HOST_FLAGS, | |
1bf617b7 | 1351 | .link_flags = SATA_FSL_HOST_LFLAGS, |
faf0b2e5 LY |
1352 | .pio_mask = 0x1f, /* pio 0-4 */ |
1353 | .udma_mask = 0x7f, /* udma 0-6 */ | |
1354 | .port_ops = &sata_fsl_ops, | |
1355 | }, | |
1356 | }; | |
1357 | ||
1358 | static int sata_fsl_probe(struct of_device *ofdev, | |
1359 | const struct of_device_id *match) | |
1360 | { | |
1361 | int retval = 0; | |
1362 | void __iomem *hcr_base = NULL; | |
1363 | void __iomem *ssr_base = NULL; | |
1364 | void __iomem *csr_base = NULL; | |
1365 | struct sata_fsl_host_priv *host_priv = NULL; | |
1366 | struct resource *r; | |
1367 | int irq; | |
1368 | struct ata_host *host; | |
1369 | ||
1370 | struct ata_port_info pi = sata_fsl_port_info[0]; | |
1371 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
1372 | ||
1373 | dev_printk(KERN_INFO, &ofdev->dev, | |
1374 | "Sata FSL Platform/CSB Driver init\n"); | |
1375 | ||
1376 | r = kmalloc(sizeof(struct resource), GFP_KERNEL); | |
1377 | ||
1378 | hcr_base = of_iomap(ofdev->node, 0); | |
1379 | if (!hcr_base) | |
1380 | goto error_exit_with_cleanup; | |
1381 | ||
1382 | ssr_base = hcr_base + 0x100; | |
1383 | csr_base = hcr_base + 0x140; | |
1384 | ||
1385 | DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); | |
1386 | DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); | |
1387 | DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); | |
1388 | ||
1389 | host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); | |
1390 | if (!host_priv) | |
1391 | goto error_exit_with_cleanup; | |
1392 | ||
1393 | host_priv->hcr_base = hcr_base; | |
1394 | host_priv->ssr_base = ssr_base; | |
1395 | host_priv->csr_base = csr_base; | |
1396 | ||
1397 | irq = irq_of_parse_and_map(ofdev->node, 0); | |
1398 | if (irq < 0) { | |
1399 | dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n"); | |
1400 | goto error_exit_with_cleanup; | |
1401 | } | |
1402 | ||
1403 | /* allocate host structure */ | |
1404 | host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); | |
1405 | ||
1406 | /* host->iomap is not used currently */ | |
1407 | host->private_data = host_priv; | |
1408 | ||
1409 | /* setup port(s) */ | |
1410 | ||
1411 | host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base; | |
1412 | host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base; | |
1413 | ||
1414 | /* initialize host controller */ | |
1415 | sata_fsl_init_controller(host); | |
1416 | ||
1417 | /* | |
1418 | * Now, register with libATA core, this will also initiate the | |
1419 | * device discovery process, invoking our port_start() handler & | |
1420 | * error_handler() to execute a dummy Softreset EH session | |
1421 | */ | |
1422 | ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, | |
1423 | &sata_fsl_sht); | |
1424 | ||
1425 | dev_set_drvdata(&ofdev->dev, host); | |
1426 | ||
1427 | return 0; | |
1428 | ||
1429 | error_exit_with_cleanup: | |
1430 | ||
1431 | if (hcr_base) | |
1432 | iounmap(hcr_base); | |
1433 | if (host_priv) | |
1434 | kfree(host_priv); | |
1435 | ||
1436 | return retval; | |
1437 | } | |
1438 | ||
1439 | static int sata_fsl_remove(struct of_device *ofdev) | |
1440 | { | |
1441 | struct ata_host *host = dev_get_drvdata(&ofdev->dev); | |
1442 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
1443 | ||
1444 | ata_host_detach(host); | |
1445 | ||
1446 | dev_set_drvdata(&ofdev->dev, NULL); | |
1447 | ||
1448 | irq_dispose_mapping(host->irq); | |
1449 | iounmap(host_priv->hcr_base); | |
1450 | kfree(host_priv); | |
1451 | ||
1452 | return 0; | |
1453 | } | |
1454 | ||
1455 | static struct of_device_id fsl_sata_match[] = { | |
1456 | { | |
1457 | .compatible = "fsl,mpc8315-sata", | |
1458 | }, | |
1459 | { | |
1460 | .compatible = "fsl,mpc8379-sata", | |
1461 | }, | |
1462 | {}, | |
1463 | }; | |
1464 | ||
1465 | MODULE_DEVICE_TABLE(of, fsl_sata_match); | |
1466 | ||
1467 | static struct of_platform_driver fsl_sata_driver = { | |
1468 | .name = "fsl-sata", | |
1469 | .match_table = fsl_sata_match, | |
1470 | .probe = sata_fsl_probe, | |
1471 | .remove = sata_fsl_remove, | |
1472 | }; | |
1473 | ||
1474 | static int __init sata_fsl_init(void) | |
1475 | { | |
1476 | of_register_platform_driver(&fsl_sata_driver); | |
1477 | return 0; | |
1478 | } | |
1479 | ||
1480 | static void __exit sata_fsl_exit(void) | |
1481 | { | |
1482 | of_unregister_platform_driver(&fsl_sata_driver); | |
1483 | } | |
1484 | ||
1485 | MODULE_LICENSE("GPL"); | |
1486 | MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); | |
1487 | MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); | |
1488 | MODULE_VERSION("1.10"); | |
1489 | ||
1490 | module_init(sata_fsl_init); | |
1491 | module_exit(sata_fsl_exit); |