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faf0b2e5 LY |
1 | /* |
2 | * drivers/ata/sata_fsl.c | |
3 | * | |
4 | * Freescale 3.0Gbps SATA device driver | |
5 | * | |
6 | * Author: Ashish Kalra <ashish.kalra@freescale.com> | |
7 | * Li Yang <leoli@freescale.com> | |
8 | * | |
9 | * Copyright (c) 2006-2007 Freescale Semiconductor, Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | ||
22 | #include <scsi/scsi_host.h> | |
23 | #include <scsi/scsi_cmnd.h> | |
24 | #include <linux/libata.h> | |
25 | #include <asm/io.h> | |
26 | #include <linux/of_platform.h> | |
27 | ||
28 | /* Controller information */ | |
29 | enum { | |
30 | SATA_FSL_QUEUE_DEPTH = 16, | |
31 | SATA_FSL_MAX_PRD = 63, | |
32 | SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, | |
33 | SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ | |
34 | ||
35 | SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
36 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
034d8e8f | 37 | ATA_FLAG_PMP | ATA_FLAG_NCQ), |
faf0b2e5 LY |
38 | |
39 | SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, | |
40 | SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ | |
41 | SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), | |
42 | ||
43 | /* | |
44 | * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and | |
45 | * chained indirect PRDEs upto a max count of 63. | |
46 | * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will | |
47 | * be setup as an indirect descriptor, pointing to it's next | |
48 | * (contigious) PRDE. Though chained indirect PRDE arrays are | |
49 | * supported,it will be more efficient to use a direct PRDT and | |
50 | * a single chain/link to indirect PRDE array/PRDT. | |
51 | */ | |
52 | ||
53 | SATA_FSL_CMD_DESC_CFIS_SZ = 32, | |
54 | SATA_FSL_CMD_DESC_SFIS_SZ = 32, | |
55 | SATA_FSL_CMD_DESC_ACMD_SZ = 16, | |
56 | SATA_FSL_CMD_DESC_RSRVD = 16, | |
57 | ||
58 | SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + | |
59 | SATA_FSL_CMD_DESC_SFIS_SZ + | |
60 | SATA_FSL_CMD_DESC_ACMD_SZ + | |
61 | SATA_FSL_CMD_DESC_RSRVD + | |
62 | SATA_FSL_MAX_PRD * 16), | |
63 | ||
64 | SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = | |
65 | (SATA_FSL_CMD_DESC_CFIS_SZ + | |
66 | SATA_FSL_CMD_DESC_SFIS_SZ + | |
67 | SATA_FSL_CMD_DESC_ACMD_SZ + | |
68 | SATA_FSL_CMD_DESC_RSRVD), | |
69 | ||
70 | SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), | |
71 | SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + | |
72 | SATA_FSL_CMD_DESC_AR_SZ), | |
73 | ||
74 | /* | |
75 | * MPC8315 has two SATA controllers, SATA1 & SATA2 | |
76 | * (one port per controller) | |
77 | * MPC837x has 2/4 controllers, one port per controller | |
78 | */ | |
79 | ||
80 | SATA_FSL_MAX_PORTS = 1, | |
81 | ||
82 | SATA_FSL_IRQ_FLAG = IRQF_SHARED, | |
83 | }; | |
84 | ||
85 | /* | |
86 | * Host Controller command register set - per port | |
87 | */ | |
88 | enum { | |
89 | CQ = 0, | |
90 | CA = 8, | |
91 | CC = 0x10, | |
92 | CE = 0x18, | |
93 | DE = 0x20, | |
94 | CHBA = 0x24, | |
95 | HSTATUS = 0x28, | |
96 | HCONTROL = 0x2C, | |
97 | CQPMP = 0x30, | |
98 | SIGNATURE = 0x34, | |
99 | ICC = 0x38, | |
100 | ||
101 | /* | |
102 | * Host Status Register (HStatus) bitdefs | |
103 | */ | |
104 | ONLINE = (1 << 31), | |
105 | GOING_OFFLINE = (1 << 30), | |
106 | BIST_ERR = (1 << 29), | |
107 | ||
108 | FATAL_ERR_HC_MASTER_ERR = (1 << 18), | |
109 | FATAL_ERR_PARITY_ERR_TX = (1 << 17), | |
110 | FATAL_ERR_PARITY_ERR_RX = (1 << 16), | |
111 | FATAL_ERR_DATA_UNDERRUN = (1 << 13), | |
112 | FATAL_ERR_DATA_OVERRUN = (1 << 12), | |
113 | FATAL_ERR_CRC_ERR_TX = (1 << 11), | |
114 | FATAL_ERR_CRC_ERR_RX = (1 << 10), | |
115 | FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), | |
116 | FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), | |
117 | ||
118 | FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | | |
119 | FATAL_ERR_PARITY_ERR_TX | | |
120 | FATAL_ERR_PARITY_ERR_RX | | |
121 | FATAL_ERR_DATA_UNDERRUN | | |
122 | FATAL_ERR_DATA_OVERRUN | | |
123 | FATAL_ERR_CRC_ERR_TX | | |
124 | FATAL_ERR_CRC_ERR_RX | | |
125 | FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, | |
126 | ||
127 | INT_ON_FATAL_ERR = (1 << 5), | |
128 | INT_ON_PHYRDY_CHG = (1 << 4), | |
129 | ||
130 | INT_ON_SIGNATURE_UPDATE = (1 << 3), | |
131 | INT_ON_SNOTIFY_UPDATE = (1 << 2), | |
132 | INT_ON_SINGL_DEVICE_ERR = (1 << 1), | |
133 | INT_ON_CMD_COMPLETE = 1, | |
134 | ||
135 | INT_ON_ERROR = INT_ON_FATAL_ERR | | |
136 | INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, | |
137 | ||
138 | /* | |
139 | * Host Control Register (HControl) bitdefs | |
140 | */ | |
141 | HCONTROL_ONLINE_PHY_RST = (1 << 31), | |
142 | HCONTROL_FORCE_OFFLINE = (1 << 30), | |
143 | HCONTROL_PARITY_PROT_MOD = (1 << 14), | |
144 | HCONTROL_DPATH_PARITY = (1 << 12), | |
145 | HCONTROL_SNOOP_ENABLE = (1 << 10), | |
146 | HCONTROL_PMP_ATTACHED = (1 << 9), | |
147 | HCONTROL_COPYOUT_STATFIS = (1 << 8), | |
148 | IE_ON_FATAL_ERR = (1 << 5), | |
149 | IE_ON_PHYRDY_CHG = (1 << 4), | |
150 | IE_ON_SIGNATURE_UPDATE = (1 << 3), | |
151 | IE_ON_SNOTIFY_UPDATE = (1 << 2), | |
152 | IE_ON_SINGL_DEVICE_ERR = (1 << 1), | |
153 | IE_ON_CMD_COMPLETE = 1, | |
154 | ||
155 | DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | | |
156 | IE_ON_SIGNATURE_UPDATE | | |
157 | IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, | |
158 | ||
159 | EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), | |
160 | DATA_SNOOP_ENABLE = (1 << 22), | |
161 | }; | |
162 | ||
163 | /* | |
164 | * SATA Superset Registers | |
165 | */ | |
166 | enum { | |
167 | SSTATUS = 0, | |
168 | SERROR = 4, | |
169 | SCONTROL = 8, | |
170 | SNOTIFY = 0xC, | |
171 | }; | |
172 | ||
173 | /* | |
174 | * Control Status Register Set | |
175 | */ | |
176 | enum { | |
177 | TRANSCFG = 0, | |
178 | TRANSSTATUS = 4, | |
179 | LINKCFG = 8, | |
180 | LINKCFG1 = 0xC, | |
181 | LINKCFG2 = 0x10, | |
182 | LINKSTATUS = 0x14, | |
183 | LINKSTATUS1 = 0x18, | |
184 | PHYCTRLCFG = 0x1C, | |
185 | COMMANDSTAT = 0x20, | |
186 | }; | |
187 | ||
188 | /* PHY (link-layer) configuration control */ | |
189 | enum { | |
190 | PHY_BIST_ENABLE = 0x01, | |
191 | }; | |
192 | ||
193 | /* | |
194 | * Command Header Table entry, i.e, command slot | |
195 | * 4 Dwords per command slot, command header size == 64 Dwords. | |
196 | */ | |
197 | struct cmdhdr_tbl_entry { | |
198 | u32 cda; | |
199 | u32 prde_fis_len; | |
200 | u32 ttl; | |
201 | u32 desc_info; | |
202 | }; | |
203 | ||
204 | /* | |
205 | * Description information bitdefs | |
206 | */ | |
207 | enum { | |
208 | VENDOR_SPECIFIC_BIST = (1 << 10), | |
209 | CMD_DESC_SNOOP_ENABLE = (1 << 9), | |
210 | FPDMA_QUEUED_CMD = (1 << 8), | |
211 | SRST_CMD = (1 << 7), | |
212 | BIST = (1 << 6), | |
213 | ATAPI_CMD = (1 << 5), | |
214 | }; | |
215 | ||
216 | /* | |
217 | * Command Descriptor | |
218 | */ | |
219 | struct command_desc { | |
220 | u8 cfis[8 * 4]; | |
221 | u8 sfis[8 * 4]; | |
222 | u8 acmd[4 * 4]; | |
223 | u8 fill[4 * 4]; | |
224 | u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; | |
225 | u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; | |
226 | }; | |
227 | ||
228 | /* | |
229 | * Physical region table descriptor(PRD) | |
230 | */ | |
231 | ||
232 | struct prde { | |
233 | u32 dba; | |
234 | u8 fill[2 * 4]; | |
235 | u32 ddc_and_ext; | |
236 | }; | |
237 | ||
238 | /* | |
239 | * ata_port private data | |
240 | * This is our per-port instance data. | |
241 | */ | |
242 | struct sata_fsl_port_priv { | |
243 | struct cmdhdr_tbl_entry *cmdslot; | |
244 | dma_addr_t cmdslot_paddr; | |
245 | struct command_desc *cmdentry; | |
246 | dma_addr_t cmdentry_paddr; | |
faf0b2e5 LY |
247 | }; |
248 | ||
249 | /* | |
250 | * ata_port->host_set private data | |
251 | */ | |
252 | struct sata_fsl_host_priv { | |
253 | void __iomem *hcr_base; | |
254 | void __iomem *ssr_base; | |
255 | void __iomem *csr_base; | |
79b3edc9 | 256 | int irq; |
faf0b2e5 LY |
257 | }; |
258 | ||
259 | static inline unsigned int sata_fsl_tag(unsigned int tag, | |
520d3a1a | 260 | void __iomem *hcr_base) |
faf0b2e5 LY |
261 | { |
262 | /* We let libATA core do actual (queue) tag allocation */ | |
263 | ||
264 | /* all non NCQ/queued commands should have tag#0 */ | |
265 | if (ata_tag_internal(tag)) { | |
266 | DPRINTK("mapping internal cmds to tag#0\n"); | |
267 | return 0; | |
268 | } | |
269 | ||
270 | if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { | |
271 | DPRINTK("tag %d invalid : out of range\n", tag); | |
272 | return 0; | |
273 | } | |
274 | ||
275 | if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { | |
276 | DPRINTK("tag %d invalid : in use!!\n", tag); | |
277 | return 0; | |
278 | } | |
279 | ||
280 | return tag; | |
281 | } | |
282 | ||
283 | static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, | |
284 | unsigned int tag, u32 desc_info, | |
285 | u32 data_xfer_len, u8 num_prde, | |
286 | u8 fis_len) | |
287 | { | |
288 | dma_addr_t cmd_descriptor_address; | |
289 | ||
290 | cmd_descriptor_address = pp->cmdentry_paddr + | |
291 | tag * SATA_FSL_CMD_DESC_SIZE; | |
292 | ||
293 | /* NOTE: both data_xfer_len & fis_len are Dword counts */ | |
294 | ||
295 | pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); | |
296 | pp->cmdslot[tag].prde_fis_len = | |
297 | cpu_to_le32((num_prde << 16) | (fis_len << 2)); | |
298 | pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); | |
520d3a1a | 299 | pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); |
faf0b2e5 LY |
300 | |
301 | VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", | |
302 | pp->cmdslot[tag].cda, | |
303 | pp->cmdslot[tag].prde_fis_len, | |
304 | pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); | |
305 | ||
306 | } | |
307 | ||
308 | static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, | |
520d3a1a | 309 | u32 *ttl, dma_addr_t cmd_desc_paddr) |
faf0b2e5 LY |
310 | { |
311 | struct scatterlist *sg; | |
312 | unsigned int num_prde = 0; | |
313 | u32 ttl_dwords = 0; | |
314 | ||
315 | /* | |
316 | * NOTE : direct & indirect prdt's are contigiously allocated | |
317 | */ | |
318 | struct prde *prd = (struct prde *)&((struct command_desc *) | |
319 | cmd_desc)->prdt; | |
320 | ||
321 | struct prde *prd_ptr_to_indirect_ext = NULL; | |
322 | unsigned indirect_ext_segment_sz = 0; | |
323 | dma_addr_t indirect_ext_segment_paddr; | |
ff2aeb1e | 324 | unsigned int si; |
faf0b2e5 | 325 | |
b1f5dc48 | 326 | VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); |
faf0b2e5 LY |
327 | |
328 | indirect_ext_segment_paddr = cmd_desc_paddr + | |
329 | SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; | |
330 | ||
ff2aeb1e | 331 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
faf0b2e5 LY |
332 | dma_addr_t sg_addr = sg_dma_address(sg); |
333 | u32 sg_len = sg_dma_len(sg); | |
334 | ||
f48c019f KG |
335 | VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n", |
336 | (unsigned long long)sg_addr, sg_len); | |
faf0b2e5 LY |
337 | |
338 | /* warn if each s/g element is not dword aligned */ | |
339 | if (sg_addr & 0x03) | |
340 | ata_port_printk(qc->ap, KERN_ERR, | |
f48c019f KG |
341 | "s/g addr unaligned : 0x%llx\n", |
342 | (unsigned long long)sg_addr); | |
faf0b2e5 LY |
343 | if (sg_len & 0x03) |
344 | ata_port_printk(qc->ap, KERN_ERR, | |
345 | "s/g len unaligned : 0x%x\n", sg_len); | |
346 | ||
37198e30 JB |
347 | if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && |
348 | sg_next(sg) != NULL) { | |
faf0b2e5 LY |
349 | VPRINTK("setting indirect prde\n"); |
350 | prd_ptr_to_indirect_ext = prd; | |
351 | prd->dba = cpu_to_le32(indirect_ext_segment_paddr); | |
352 | indirect_ext_segment_sz = 0; | |
353 | ++prd; | |
354 | ++num_prde; | |
355 | } | |
356 | ||
357 | ttl_dwords += sg_len; | |
358 | prd->dba = cpu_to_le32(sg_addr); | |
359 | prd->ddc_and_ext = | |
360 | cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03)); | |
361 | ||
362 | VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", | |
363 | ttl_dwords, prd->dba, prd->ddc_and_ext); | |
364 | ||
365 | ++num_prde; | |
366 | ++prd; | |
367 | if (prd_ptr_to_indirect_ext) | |
368 | indirect_ext_segment_sz += sg_len; | |
369 | } | |
370 | ||
371 | if (prd_ptr_to_indirect_ext) { | |
372 | /* set indirect extension flag along with indirect ext. size */ | |
373 | prd_ptr_to_indirect_ext->ddc_and_ext = | |
374 | cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | | |
375 | DATA_SNOOP_ENABLE | | |
376 | (indirect_ext_segment_sz & ~0x03))); | |
377 | } | |
378 | ||
379 | *ttl = ttl_dwords; | |
380 | return num_prde; | |
381 | } | |
382 | ||
383 | static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) | |
384 | { | |
385 | struct ata_port *ap = qc->ap; | |
386 | struct sata_fsl_port_priv *pp = ap->private_data; | |
387 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
388 | void __iomem *hcr_base = host_priv->hcr_base; | |
389 | unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); | |
390 | struct command_desc *cd; | |
391 | u32 desc_info = CMD_DESC_SNOOP_ENABLE; | |
392 | u32 num_prde = 0; | |
393 | u32 ttl_dwords = 0; | |
394 | dma_addr_t cd_paddr; | |
395 | ||
396 | cd = (struct command_desc *)pp->cmdentry + tag; | |
397 | cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; | |
398 | ||
034d8e8f | 399 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); |
faf0b2e5 LY |
400 | |
401 | VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", | |
402 | cd->cfis[0], cd->cfis[1], cd->cfis[2]); | |
403 | ||
404 | if (qc->tf.protocol == ATA_PROT_NCQ) { | |
405 | VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", | |
406 | cd->cfis[3], cd->cfis[11]); | |
407 | } | |
408 | ||
409 | /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ | |
405e66b3 | 410 | if (ata_is_atapi(qc->tf.protocol)) { |
faf0b2e5 LY |
411 | desc_info |= ATAPI_CMD; |
412 | memset((void *)&cd->acmd, 0, 32); | |
413 | memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); | |
414 | } | |
415 | ||
416 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
417 | num_prde = sata_fsl_fill_sg(qc, (void *)cd, | |
418 | &ttl_dwords, cd_paddr); | |
419 | ||
420 | if (qc->tf.protocol == ATA_PROT_NCQ) | |
421 | desc_info |= FPDMA_QUEUED_CMD; | |
422 | ||
423 | sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, | |
424 | num_prde, 5); | |
425 | ||
426 | VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", | |
427 | desc_info, ttl_dwords, num_prde); | |
428 | } | |
429 | ||
430 | static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) | |
431 | { | |
432 | struct ata_port *ap = qc->ap; | |
433 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
434 | void __iomem *hcr_base = host_priv->hcr_base; | |
435 | unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); | |
436 | ||
437 | VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", | |
438 | ioread32(CQ + hcr_base), | |
439 | ioread32(CA + hcr_base), | |
440 | ioread32(CE + hcr_base), ioread32(CC + hcr_base)); | |
441 | ||
034d8e8f AK |
442 | iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); |
443 | ||
faf0b2e5 LY |
444 | /* Simply queue command to the controller/device */ |
445 | iowrite32(1 << tag, CQ + hcr_base); | |
446 | ||
447 | VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", | |
448 | tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); | |
449 | ||
450 | VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", | |
451 | ioread32(CE + hcr_base), | |
452 | ioread32(DE + hcr_base), | |
b1f5dc48 AV |
453 | ioread32(CC + hcr_base), |
454 | ioread32(COMMANDSTAT + host_priv->csr_base)); | |
faf0b2e5 LY |
455 | |
456 | return 0; | |
457 | } | |
458 | ||
4c9bf4e7 TH |
459 | static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) |
460 | { | |
461 | struct sata_fsl_port_priv *pp = qc->ap->private_data; | |
462 | struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; | |
463 | void __iomem *hcr_base = host_priv->hcr_base; | |
464 | unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); | |
465 | struct command_desc *cd; | |
466 | ||
467 | cd = pp->cmdentry + tag; | |
468 | ||
469 | ata_tf_from_fis(cd->sfis, &qc->result_tf); | |
470 | return true; | |
471 | } | |
472 | ||
82ef04fb TH |
473 | static int sata_fsl_scr_write(struct ata_link *link, |
474 | unsigned int sc_reg_in, u32 val) | |
faf0b2e5 | 475 | { |
82ef04fb | 476 | struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; |
faf0b2e5 LY |
477 | void __iomem *ssr_base = host_priv->ssr_base; |
478 | unsigned int sc_reg; | |
479 | ||
480 | switch (sc_reg_in) { | |
481 | case SCR_STATUS: | |
faf0b2e5 | 482 | case SCR_ERROR: |
faf0b2e5 | 483 | case SCR_CONTROL: |
faf0b2e5 | 484 | case SCR_ACTIVE: |
9465d532 | 485 | sc_reg = sc_reg_in; |
faf0b2e5 LY |
486 | break; |
487 | default: | |
488 | return -EINVAL; | |
489 | } | |
490 | ||
491 | VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); | |
492 | ||
2a52e8d4 | 493 | iowrite32(val, ssr_base + (sc_reg * 4)); |
faf0b2e5 LY |
494 | return 0; |
495 | } | |
496 | ||
82ef04fb TH |
497 | static int sata_fsl_scr_read(struct ata_link *link, |
498 | unsigned int sc_reg_in, u32 *val) | |
faf0b2e5 | 499 | { |
82ef04fb | 500 | struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; |
faf0b2e5 LY |
501 | void __iomem *ssr_base = host_priv->ssr_base; |
502 | unsigned int sc_reg; | |
503 | ||
504 | switch (sc_reg_in) { | |
505 | case SCR_STATUS: | |
faf0b2e5 | 506 | case SCR_ERROR: |
faf0b2e5 | 507 | case SCR_CONTROL: |
faf0b2e5 | 508 | case SCR_ACTIVE: |
9465d532 | 509 | sc_reg = sc_reg_in; |
faf0b2e5 LY |
510 | break; |
511 | default: | |
512 | return -EINVAL; | |
513 | } | |
514 | ||
515 | VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); | |
516 | ||
2a52e8d4 | 517 | *val = ioread32(ssr_base + (sc_reg * 4)); |
faf0b2e5 LY |
518 | return 0; |
519 | } | |
520 | ||
521 | static void sata_fsl_freeze(struct ata_port *ap) | |
522 | { | |
523 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
524 | void __iomem *hcr_base = host_priv->hcr_base; | |
525 | u32 temp; | |
526 | ||
527 | VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", | |
528 | ioread32(CQ + hcr_base), | |
529 | ioread32(CA + hcr_base), | |
530 | ioread32(CE + hcr_base), ioread32(DE + hcr_base)); | |
b1f5dc48 AV |
531 | VPRINTK("CmdStat = 0x%x\n", |
532 | ioread32(host_priv->csr_base + COMMANDSTAT)); | |
faf0b2e5 LY |
533 | |
534 | /* disable interrupts on the controller/port */ | |
535 | temp = ioread32(hcr_base + HCONTROL); | |
536 | iowrite32((temp & ~0x3F), hcr_base + HCONTROL); | |
537 | ||
538 | VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", | |
539 | ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); | |
540 | } | |
541 | ||
542 | static void sata_fsl_thaw(struct ata_port *ap) | |
543 | { | |
544 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
545 | void __iomem *hcr_base = host_priv->hcr_base; | |
546 | u32 temp; | |
547 | ||
548 | /* ack. any pending IRQs for this controller/port */ | |
549 | temp = ioread32(hcr_base + HSTATUS); | |
550 | ||
551 | VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); | |
552 | ||
553 | if (temp & 0x3F) | |
554 | iowrite32((temp & 0x3F), hcr_base + HSTATUS); | |
555 | ||
556 | /* enable interrupts on the controller/port */ | |
557 | temp = ioread32(hcr_base + HCONTROL); | |
558 | iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); | |
559 | ||
560 | VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", | |
561 | ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); | |
562 | } | |
563 | ||
034d8e8f AK |
564 | static void sata_fsl_pmp_attach(struct ata_port *ap) |
565 | { | |
566 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
567 | void __iomem *hcr_base = host_priv->hcr_base; | |
568 | u32 temp; | |
569 | ||
570 | temp = ioread32(hcr_base + HCONTROL); | |
571 | iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); | |
572 | } | |
573 | ||
574 | static void sata_fsl_pmp_detach(struct ata_port *ap) | |
575 | { | |
576 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
577 | void __iomem *hcr_base = host_priv->hcr_base; | |
578 | u32 temp; | |
579 | ||
580 | temp = ioread32(hcr_base + HCONTROL); | |
581 | temp &= ~HCONTROL_PMP_ATTACHED; | |
582 | iowrite32(temp, hcr_base + HCONTROL); | |
583 | ||
584 | /* enable interrupts on the controller/port */ | |
585 | temp = ioread32(hcr_base + HCONTROL); | |
586 | iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); | |
587 | ||
588 | } | |
589 | ||
faf0b2e5 LY |
590 | static int sata_fsl_port_start(struct ata_port *ap) |
591 | { | |
592 | struct device *dev = ap->host->dev; | |
593 | struct sata_fsl_port_priv *pp; | |
faf0b2e5 LY |
594 | void *mem; |
595 | dma_addr_t mem_dma; | |
596 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
597 | void __iomem *hcr_base = host_priv->hcr_base; | |
598 | u32 temp; | |
599 | ||
600 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); | |
601 | if (!pp) | |
602 | return -ENOMEM; | |
603 | ||
faf0b2e5 LY |
604 | mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, |
605 | GFP_KERNEL); | |
606 | if (!mem) { | |
faf0b2e5 LY |
607 | kfree(pp); |
608 | return -ENOMEM; | |
609 | } | |
610 | memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); | |
611 | ||
612 | pp->cmdslot = mem; | |
613 | pp->cmdslot_paddr = mem_dma; | |
614 | ||
615 | mem += SATA_FSL_CMD_SLOT_SIZE; | |
616 | mem_dma += SATA_FSL_CMD_SLOT_SIZE; | |
617 | ||
618 | pp->cmdentry = mem; | |
619 | pp->cmdentry_paddr = mem_dma; | |
620 | ||
621 | ap->private_data = pp; | |
622 | ||
623 | VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", | |
624 | pp->cmdslot_paddr, pp->cmdentry_paddr); | |
625 | ||
626 | /* Now, update the CHBA register in host controller cmd register set */ | |
627 | iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); | |
628 | ||
629 | /* | |
630 | * Now, we can bring the controller on-line & also initiate | |
631 | * the COMINIT sequence, we simply return here and the boot-probing | |
632 | * & device discovery process is re-initiated by libATA using a | |
633 | * Softreset EH (dummy) session. Hence, boot probing and device | |
634 | * discovey will be part of sata_fsl_softreset() callback. | |
635 | */ | |
636 | ||
637 | temp = ioread32(hcr_base + HCONTROL); | |
638 | iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); | |
639 | ||
640 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
641 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
642 | VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); | |
643 | ||
e7eac96e | 644 | #ifdef CONFIG_MPC8315_DS |
faf0b2e5 LY |
645 | /* |
646 | * Workaround for 8315DS board 3gbps link-up issue, | |
647 | * currently limit SATA port to GEN1 speed | |
648 | */ | |
82ef04fb | 649 | sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); |
faf0b2e5 LY |
650 | temp &= ~(0xF << 4); |
651 | temp |= (0x1 << 4); | |
82ef04fb | 652 | sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp); |
faf0b2e5 | 653 | |
82ef04fb | 654 | sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); |
faf0b2e5 LY |
655 | dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n", |
656 | temp); | |
e7eac96e | 657 | #endif |
faf0b2e5 LY |
658 | |
659 | return 0; | |
660 | } | |
661 | ||
662 | static void sata_fsl_port_stop(struct ata_port *ap) | |
663 | { | |
664 | struct device *dev = ap->host->dev; | |
665 | struct sata_fsl_port_priv *pp = ap->private_data; | |
666 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
667 | void __iomem *hcr_base = host_priv->hcr_base; | |
668 | u32 temp; | |
669 | ||
670 | /* | |
671 | * Force host controller to go off-line, aborting current operations | |
672 | */ | |
673 | temp = ioread32(hcr_base + HCONTROL); | |
674 | temp &= ~HCONTROL_ONLINE_PHY_RST; | |
675 | temp |= HCONTROL_FORCE_OFFLINE; | |
676 | iowrite32(temp, hcr_base + HCONTROL); | |
677 | ||
678 | /* Poll for controller to go offline - should happen immediately */ | |
679 | ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); | |
680 | ||
681 | ap->private_data = NULL; | |
682 | dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, | |
683 | pp->cmdslot, pp->cmdslot_paddr); | |
684 | ||
faf0b2e5 LY |
685 | kfree(pp); |
686 | } | |
687 | ||
688 | static unsigned int sata_fsl_dev_classify(struct ata_port *ap) | |
689 | { | |
690 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
691 | void __iomem *hcr_base = host_priv->hcr_base; | |
692 | struct ata_taskfile tf; | |
693 | u32 temp; | |
694 | ||
695 | temp = ioread32(hcr_base + SIGNATURE); | |
696 | ||
697 | VPRINTK("raw sig = 0x%x\n", temp); | |
698 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
699 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
700 | ||
701 | tf.lbah = (temp >> 24) & 0xff; | |
702 | tf.lbam = (temp >> 16) & 0xff; | |
703 | tf.lbal = (temp >> 8) & 0xff; | |
704 | tf.nsect = temp & 0xff; | |
705 | ||
706 | return ata_dev_classify(&tf); | |
707 | } | |
708 | ||
ac2f217b | 709 | static int sata_fsl_prereset(struct ata_link *link, unsigned long deadline) |
45db2f6c TH |
710 | { |
711 | /* FIXME: Never skip softreset, sata_fsl_softreset() is | |
712 | * combination of soft and hard resets. sata_fsl_softreset() | |
713 | * needs to be splitted into soft and hard resets. | |
714 | */ | |
715 | return 0; | |
716 | } | |
717 | ||
1bf617b7 | 718 | static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, |
034d8e8f | 719 | unsigned long deadline) |
faf0b2e5 | 720 | { |
1bf617b7 | 721 | struct ata_port *ap = link->ap; |
faf0b2e5 LY |
722 | struct sata_fsl_port_priv *pp = ap->private_data; |
723 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
724 | void __iomem *hcr_base = host_priv->hcr_base; | |
034d8e8f | 725 | int pmp = sata_srst_pmp(link); |
faf0b2e5 LY |
726 | u32 temp; |
727 | struct ata_taskfile tf; | |
728 | u8 *cfis; | |
729 | u32 Serror; | |
730 | int i = 0; | |
faf0b2e5 LY |
731 | unsigned long start_jiffies; |
732 | ||
733 | DPRINTK("in xx_softreset\n"); | |
734 | ||
034d8e8f AK |
735 | if (pmp != SATA_PMP_CTRL_PORT) |
736 | goto issue_srst; | |
737 | ||
faf0b2e5 LY |
738 | try_offline_again: |
739 | /* | |
740 | * Force host controller to go off-line, aborting current operations | |
741 | */ | |
742 | temp = ioread32(hcr_base + HCONTROL); | |
743 | temp &= ~HCONTROL_ONLINE_PHY_RST; | |
744 | iowrite32(temp, hcr_base + HCONTROL); | |
745 | ||
746 | /* Poll for controller to go offline */ | |
747 | temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); | |
748 | ||
749 | if (temp & ONLINE) { | |
750 | ata_port_printk(ap, KERN_ERR, | |
751 | "Softreset failed, not off-lined %d\n", i); | |
752 | ||
753 | /* | |
754 | * Try to offline controller atleast twice | |
755 | */ | |
756 | i++; | |
757 | if (i == 2) | |
758 | goto err; | |
759 | else | |
760 | goto try_offline_again; | |
761 | } | |
762 | ||
763 | DPRINTK("softreset, controller off-lined\n"); | |
764 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
765 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
766 | ||
767 | /* | |
768 | * PHY reset should remain asserted for atleast 1ms | |
769 | */ | |
770 | msleep(1); | |
771 | ||
772 | /* | |
773 | * Now, bring the host controller online again, this can take time | |
774 | * as PHY reset and communication establishment, 1st D2H FIS and | |
775 | * device signature update is done, on safe side assume 500ms | |
776 | * NOTE : Host online status may be indicated immediately!! | |
777 | */ | |
778 | ||
779 | temp = ioread32(hcr_base + HCONTROL); | |
780 | temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); | |
034d8e8f | 781 | temp |= HCONTROL_PMP_ATTACHED; |
faf0b2e5 LY |
782 | iowrite32(temp, hcr_base + HCONTROL); |
783 | ||
784 | temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); | |
785 | ||
786 | if (!(temp & ONLINE)) { | |
787 | ata_port_printk(ap, KERN_ERR, | |
788 | "Softreset failed, not on-lined\n"); | |
789 | goto err; | |
790 | } | |
791 | ||
792 | DPRINTK("softreset, controller off-lined & on-lined\n"); | |
793 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
794 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
795 | ||
796 | /* | |
797 | * First, wait for the PHYRDY change to occur before waiting for | |
798 | * the signature, and also verify if SStatus indicates device | |
799 | * presence | |
800 | */ | |
801 | ||
802 | temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500); | |
1bf617b7 | 803 | if ((!(temp & 0x10)) || ata_link_offline(link)) { |
faf0b2e5 LY |
804 | ata_port_printk(ap, KERN_WARNING, |
805 | "No Device OR PHYRDY change,Hstatus = 0x%x\n", | |
806 | ioread32(hcr_base + HSTATUS)); | |
034d8e8f AK |
807 | *class = ATA_DEV_NONE; |
808 | goto out; | |
faf0b2e5 LY |
809 | } |
810 | ||
811 | /* | |
812 | * Wait for the first D2H from device,i.e,signature update notification | |
813 | */ | |
814 | start_jiffies = jiffies; | |
815 | temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10, | |
816 | 500, jiffies_to_msecs(deadline - start_jiffies)); | |
817 | ||
818 | if ((temp & 0xFF) != 0x18) { | |
819 | ata_port_printk(ap, KERN_WARNING, "No Signature Update\n"); | |
034d8e8f AK |
820 | *class = ATA_DEV_NONE; |
821 | goto out; | |
faf0b2e5 LY |
822 | } else { |
823 | ata_port_printk(ap, KERN_INFO, | |
824 | "Signature Update detected @ %d msecs\n", | |
825 | jiffies_to_msecs(jiffies - start_jiffies)); | |
826 | } | |
827 | ||
828 | /* | |
829 | * Send a device reset (SRST) explicitly on command slot #0 | |
830 | * Check : will the command queue (reg) be cleared during offlining ?? | |
831 | * Also we will be online only if Phy commn. has been established | |
832 | * and device presence has been detected, therefore if we have | |
833 | * reached here, we can send a command to the target device | |
834 | */ | |
835 | ||
034d8e8f | 836 | issue_srst: |
faf0b2e5 LY |
837 | DPRINTK("Sending SRST/device reset\n"); |
838 | ||
1bf617b7 | 839 | ata_tf_init(link->device, &tf); |
520d3a1a | 840 | cfis = (u8 *) &pp->cmdentry->cfis; |
faf0b2e5 LY |
841 | |
842 | /* device reset/SRST is a control register update FIS, uses tag0 */ | |
843 | sata_fsl_setup_cmd_hdr_entry(pp, 0, | |
844 | SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); | |
845 | ||
846 | tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ | |
034d8e8f | 847 | ata_tf_to_fis(&tf, pmp, 0, cfis); |
faf0b2e5 LY |
848 | |
849 | DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", | |
850 | cfis[0], cfis[1], cfis[2], cfis[3]); | |
851 | ||
852 | /* | |
853 | * Queue SRST command to the controller/device, ensure that no | |
854 | * other commands are active on the controller/device | |
855 | */ | |
856 | ||
857 | DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", | |
858 | ioread32(CQ + hcr_base), | |
859 | ioread32(CA + hcr_base), ioread32(CC + hcr_base)); | |
860 | ||
861 | iowrite32(0xFFFF, CC + hcr_base); | |
862 | iowrite32(1, CQ + hcr_base); | |
863 | ||
864 | temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); | |
865 | if (temp & 0x1) { | |
866 | ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n"); | |
867 | ||
868 | DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", | |
869 | ioread32(CQ + hcr_base), | |
870 | ioread32(CA + hcr_base), ioread32(CC + hcr_base)); | |
871 | ||
82ef04fb | 872 | sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); |
faf0b2e5 LY |
873 | |
874 | DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
875 | DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
876 | DPRINTK("Serror = 0x%x\n", Serror); | |
877 | goto err; | |
878 | } | |
879 | ||
880 | msleep(1); | |
881 | ||
882 | /* | |
883 | * SATA device enters reset state after receving a Control register | |
884 | * FIS with SRST bit asserted and it awaits another H2D Control reg. | |
885 | * FIS with SRST bit cleared, then the device does internal diags & | |
886 | * initialization, followed by indicating it's initialization status | |
887 | * using ATA signature D2H register FIS to the host controller. | |
888 | */ | |
889 | ||
890 | sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5); | |
891 | ||
892 | tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ | |
034d8e8f | 893 | ata_tf_to_fis(&tf, pmp, 0, cfis); |
faf0b2e5 | 894 | |
034d8e8f AK |
895 | if (pmp != SATA_PMP_CTRL_PORT) |
896 | iowrite32(pmp, CQPMP + hcr_base); | |
faf0b2e5 LY |
897 | iowrite32(1, CQ + hcr_base); |
898 | msleep(150); /* ?? */ | |
899 | ||
900 | /* | |
901 | * The above command would have signalled an interrupt on command | |
902 | * complete, which needs special handling, by clearing the Nth | |
903 | * command bit of the CCreg | |
904 | */ | |
905 | iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ | |
faf0b2e5 LY |
906 | |
907 | DPRINTK("SATA FSL : Now checking device signature\n"); | |
908 | ||
909 | *class = ATA_DEV_NONE; | |
910 | ||
911 | /* Verify if SStatus indicates device presence */ | |
1bf617b7 | 912 | if (ata_link_online(link)) { |
faf0b2e5 LY |
913 | /* |
914 | * if we are here, device presence has been detected, | |
915 | * 1st D2H FIS would have been received, but sfis in | |
916 | * command desc. is not updated, but signature register | |
917 | * would have been updated | |
918 | */ | |
919 | ||
920 | *class = sata_fsl_dev_classify(ap); | |
921 | ||
922 | DPRINTK("class = %d\n", *class); | |
923 | VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); | |
924 | VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); | |
925 | } | |
926 | ||
034d8e8f | 927 | out: |
faf0b2e5 LY |
928 | return 0; |
929 | ||
930 | err: | |
931 | return -EIO; | |
932 | } | |
933 | ||
034d8e8f AK |
934 | static void sata_fsl_error_handler(struct ata_port *ap) |
935 | { | |
936 | ||
937 | DPRINTK("in xx_error_handler\n"); | |
938 | sata_pmp_error_handler(ap); | |
939 | ||
940 | } | |
941 | ||
faf0b2e5 LY |
942 | static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) |
943 | { | |
944 | if (qc->flags & ATA_QCFLAG_FAILED) | |
945 | qc->err_mask |= AC_ERR_OTHER; | |
946 | ||
947 | if (qc->err_mask) { | |
948 | /* make DMA engine forget about the failed command */ | |
949 | ||
950 | } | |
951 | } | |
952 | ||
faf0b2e5 LY |
953 | static void sata_fsl_error_intr(struct ata_port *ap) |
954 | { | |
faf0b2e5 LY |
955 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
956 | void __iomem *hcr_base = host_priv->hcr_base; | |
034d8e8f | 957 | u32 hstatus, dereg=0, cereg = 0, SError = 0; |
faf0b2e5 | 958 | unsigned int err_mask = 0, action = 0; |
034d8e8f AK |
959 | int freeze = 0, abort=0; |
960 | struct ata_link *link = NULL; | |
961 | struct ata_queued_cmd *qc = NULL; | |
962 | struct ata_eh_info *ehi; | |
faf0b2e5 LY |
963 | |
964 | hstatus = ioread32(hcr_base + HSTATUS); | |
965 | cereg = ioread32(hcr_base + CE); | |
966 | ||
034d8e8f AK |
967 | /* first, analyze and record host port events */ |
968 | link = &ap->link; | |
969 | ehi = &link->eh_info; | |
faf0b2e5 LY |
970 | ata_ehi_clear_desc(ehi); |
971 | ||
972 | /* | |
973 | * Handle & Clear SError | |
974 | */ | |
975 | ||
82ef04fb | 976 | sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); |
faf0b2e5 | 977 | if (unlikely(SError & 0xFFFF0000)) { |
82ef04fb | 978 | sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); |
faf0b2e5 LY |
979 | } |
980 | ||
981 | DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", | |
982 | hstatus, cereg, ioread32(hcr_base + DE), SError); | |
983 | ||
034d8e8f AK |
984 | /* handle fatal errors */ |
985 | if (hstatus & FATAL_ERROR_DECODE) { | |
986 | ehi->err_mask |= AC_ERR_ATA_BUS; | |
987 | ehi->action |= ATA_EH_SOFTRESET; | |
faf0b2e5 | 988 | |
faf0b2e5 | 989 | /* |
034d8e8f AK |
990 | * Ignore serror in case of fatal errors as we always want |
991 | * to do a soft-reset of the FSL SATA controller. Analyzing | |
992 | * serror may cause libata to schedule a hard-reset action, | |
993 | * and hard-reset currently does not do controller | |
994 | * offline/online, causing command timeouts and leads to an | |
995 | * un-recoverable state, hence make libATA ignore | |
996 | * autopsy in case of fatal errors. | |
faf0b2e5 LY |
997 | */ |
998 | ||
034d8e8f | 999 | ehi->flags |= ATA_EHI_NO_AUTOPSY; |
faf0b2e5 | 1000 | |
faf0b2e5 LY |
1001 | freeze = 1; |
1002 | } | |
1003 | ||
1004 | /* Handle PHYRDY change notification */ | |
1005 | if (hstatus & INT_ON_PHYRDY_CHG) { | |
1006 | DPRINTK("SATA FSL: PHYRDY change indication\n"); | |
1007 | ||
1008 | /* Setup a soft-reset EH action */ | |
1009 | ata_ehi_hotplugged(ehi); | |
034d8e8f | 1010 | ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); |
faf0b2e5 LY |
1011 | freeze = 1; |
1012 | } | |
1013 | ||
034d8e8f AK |
1014 | /* handle single device errors */ |
1015 | if (cereg) { | |
1016 | /* | |
1017 | * clear the command error, also clears queue to the device | |
1018 | * in error, and we can (re)issue commands to this device. | |
1019 | * When a device is in error all commands queued into the | |
1020 | * host controller and at the device are considered aborted | |
1021 | * and the queue for that device is stopped. Now, after | |
1022 | * clearing the device error, we can issue commands to the | |
1023 | * device to interrogate it to find the source of the error. | |
1024 | */ | |
1025 | abort = 1; | |
1026 | ||
1027 | DPRINTK("single device error, CE=0x%x, DE=0x%x\n", | |
1028 | ioread32(hcr_base + CE), ioread32(hcr_base + DE)); | |
faf0b2e5 | 1029 | |
034d8e8f AK |
1030 | /* find out the offending link and qc */ |
1031 | if (ap->nr_pmp_links) { | |
1032 | dereg = ioread32(hcr_base + DE); | |
1033 | iowrite32(dereg, hcr_base + DE); | |
1034 | iowrite32(cereg, hcr_base + CE); | |
1035 | ||
1036 | if (dereg < ap->nr_pmp_links) { | |
1037 | link = &ap->pmp_link[dereg]; | |
1038 | ehi = &link->eh_info; | |
1039 | qc = ata_qc_from_tag(ap, link->active_tag); | |
1040 | /* | |
1041 | * We should consider this as non fatal error, | |
1042 | * and TF must be updated as done below. | |
1043 | */ | |
1044 | ||
1045 | err_mask |= AC_ERR_DEV; | |
1046 | ||
1047 | } else { | |
1048 | err_mask |= AC_ERR_HSM; | |
1049 | action |= ATA_EH_HARDRESET; | |
1050 | freeze = 1; | |
1051 | } | |
1052 | } else { | |
1053 | dereg = ioread32(hcr_base + DE); | |
1054 | iowrite32(dereg, hcr_base + DE); | |
1055 | iowrite32(cereg, hcr_base + CE); | |
1056 | ||
1057 | qc = ata_qc_from_tag(ap, link->active_tag); | |
1058 | /* | |
1059 | * We should consider this as non fatal error, | |
1060 | * and TF must be updated as done below. | |
1061 | */ | |
1062 | err_mask |= AC_ERR_DEV; | |
1063 | } | |
1064 | } | |
1065 | ||
1066 | /* record error info */ | |
1067 | if (qc) { | |
faf0b2e5 | 1068 | qc->err_mask |= err_mask; |
034d8e8f | 1069 | } else |
faf0b2e5 LY |
1070 | ehi->err_mask |= err_mask; |
1071 | ||
1072 | ehi->action |= action; | |
faf0b2e5 LY |
1073 | |
1074 | /* freeze or abort */ | |
1075 | if (freeze) | |
1076 | ata_port_freeze(ap); | |
034d8e8f AK |
1077 | else if (abort) { |
1078 | if (qc) | |
1079 | ata_link_abort(qc->dev->link); | |
1080 | else | |
1081 | ata_port_abort(ap); | |
1082 | } | |
faf0b2e5 LY |
1083 | } |
1084 | ||
faf0b2e5 LY |
1085 | static void sata_fsl_host_intr(struct ata_port *ap) |
1086 | { | |
1087 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
1088 | void __iomem *hcr_base = host_priv->hcr_base; | |
1089 | u32 hstatus, qc_active = 0; | |
1090 | struct ata_queued_cmd *qc; | |
1091 | u32 SError; | |
1092 | ||
1093 | hstatus = ioread32(hcr_base + HSTATUS); | |
1094 | ||
82ef04fb | 1095 | sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); |
faf0b2e5 LY |
1096 | |
1097 | if (unlikely(SError & 0xFFFF0000)) { | |
1098 | DPRINTK("serror @host_intr : 0x%x\n", SError); | |
1099 | sata_fsl_error_intr(ap); | |
1100 | ||
1101 | } | |
1102 | ||
1103 | if (unlikely(hstatus & INT_ON_ERROR)) { | |
1104 | DPRINTK("error interrupt!!\n"); | |
1105 | sata_fsl_error_intr(ap); | |
1106 | return; | |
1107 | } | |
1108 | ||
034d8e8f AK |
1109 | /* Read command completed register */ |
1110 | qc_active = ioread32(hcr_base + CC); | |
1111 | ||
1112 | VPRINTK("Status of all queues :\n"); | |
1113 | VPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n", | |
1114 | qc_active, | |
1115 | ioread32(hcr_base + CA), | |
1116 | ioread32(hcr_base + CE), | |
1117 | ioread32(hcr_base + CQ), | |
1118 | ap->qc_active); | |
1119 | ||
1120 | if (qc_active & ap->qc_active) { | |
faf0b2e5 | 1121 | int i; |
faf0b2e5 LY |
1122 | /* clear CC bit, this will also complete the interrupt */ |
1123 | iowrite32(qc_active, hcr_base + CC); | |
1124 | ||
1125 | DPRINTK("Status of all queues :\n"); | |
1126 | DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n", | |
1127 | qc_active, ioread32(hcr_base + CA), | |
1128 | ioread32(hcr_base + CE)); | |
1129 | ||
1130 | for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { | |
1131 | if (qc_active & (1 << i)) { | |
1132 | qc = ata_qc_from_tag(ap, i); | |
034d8e8f | 1133 | if (qc) { |
faf0b2e5 | 1134 | ata_qc_complete(qc); |
034d8e8f | 1135 | } |
faf0b2e5 LY |
1136 | DPRINTK |
1137 | ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", | |
1138 | i, ioread32(hcr_base + CC), | |
1139 | ioread32(hcr_base + CA)); | |
1140 | } | |
1141 | } | |
1142 | return; | |
1143 | ||
034d8e8f | 1144 | } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) { |
faf0b2e5 | 1145 | iowrite32(1, hcr_base + CC); |
034d8e8f | 1146 | qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); |
faf0b2e5 | 1147 | |
034d8e8f AK |
1148 | DPRINTK("completing non-ncq cmd, CC=0x%x\n", |
1149 | ioread32(hcr_base + CC)); | |
faf0b2e5 | 1150 | |
034d8e8f | 1151 | if (qc) { |
faf0b2e5 | 1152 | ata_qc_complete(qc); |
034d8e8f | 1153 | } |
faf0b2e5 LY |
1154 | } else { |
1155 | /* Spurious Interrupt!! */ | |
1156 | DPRINTK("spurious interrupt!!, CC = 0x%x\n", | |
1157 | ioread32(hcr_base + CC)); | |
034d8e8f | 1158 | iowrite32(qc_active, hcr_base + CC); |
faf0b2e5 LY |
1159 | return; |
1160 | } | |
1161 | } | |
1162 | ||
1163 | static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) | |
1164 | { | |
1165 | struct ata_host *host = dev_instance; | |
1166 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
1167 | void __iomem *hcr_base = host_priv->hcr_base; | |
1168 | u32 interrupt_enables; | |
1169 | unsigned handled = 0; | |
1170 | struct ata_port *ap; | |
1171 | ||
1172 | /* ack. any pending IRQs for this controller/port */ | |
1173 | interrupt_enables = ioread32(hcr_base + HSTATUS); | |
1174 | interrupt_enables &= 0x3F; | |
1175 | ||
1176 | DPRINTK("interrupt status 0x%x\n", interrupt_enables); | |
1177 | ||
1178 | if (!interrupt_enables) | |
1179 | return IRQ_NONE; | |
1180 | ||
1181 | spin_lock(&host->lock); | |
1182 | ||
1183 | /* Assuming one port per host controller */ | |
1184 | ||
1185 | ap = host->ports[0]; | |
1186 | if (ap) { | |
1187 | sata_fsl_host_intr(ap); | |
1188 | } else { | |
1189 | dev_printk(KERN_WARNING, host->dev, | |
1190 | "interrupt on disabled port 0\n"); | |
1191 | } | |
1192 | ||
1193 | iowrite32(interrupt_enables, hcr_base + HSTATUS); | |
1194 | handled = 1; | |
1195 | ||
1196 | spin_unlock(&host->lock); | |
1197 | ||
1198 | return IRQ_RETVAL(handled); | |
1199 | } | |
1200 | ||
1201 | /* | |
1202 | * Multiple ports are represented by multiple SATA controllers with | |
1203 | * one port per controller | |
1204 | */ | |
1205 | static int sata_fsl_init_controller(struct ata_host *host) | |
1206 | { | |
1207 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
1208 | void __iomem *hcr_base = host_priv->hcr_base; | |
1209 | u32 temp; | |
1210 | ||
1211 | /* | |
1212 | * NOTE : We cannot bring the controller online before setting | |
1213 | * the CHBA, hence main controller initialization is done as | |
1214 | * part of the port_start() callback | |
1215 | */ | |
1216 | ||
1217 | /* ack. any pending IRQs for this controller/port */ | |
1218 | temp = ioread32(hcr_base + HSTATUS); | |
1219 | if (temp & 0x3F) | |
1220 | iowrite32((temp & 0x3F), hcr_base + HSTATUS); | |
1221 | ||
1222 | /* Keep interrupts disabled on the controller */ | |
1223 | temp = ioread32(hcr_base + HCONTROL); | |
1224 | iowrite32((temp & ~0x3F), hcr_base + HCONTROL); | |
1225 | ||
1226 | /* Disable interrupt coalescing control(icc), for the moment */ | |
1227 | DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); | |
1228 | iowrite32(0x01000000, hcr_base + ICC); | |
1229 | ||
1230 | /* clear error registers, SError is cleared by libATA */ | |
1231 | iowrite32(0x00000FFFF, hcr_base + CE); | |
1232 | iowrite32(0x00000FFFF, hcr_base + DE); | |
1233 | ||
faf0b2e5 LY |
1234 | /* |
1235 | * host controller will be brought on-line, during xx_port_start() | |
1236 | * callback, that should also initiate the OOB, COMINIT sequence | |
1237 | */ | |
1238 | ||
1239 | DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
1240 | DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
1241 | ||
1242 | return 0; | |
1243 | } | |
1244 | ||
1245 | /* | |
1246 | * scsi mid-layer and libata interface structures | |
1247 | */ | |
1248 | static struct scsi_host_template sata_fsl_sht = { | |
68d1d07b | 1249 | ATA_NCQ_SHT("sata_fsl"), |
faf0b2e5 | 1250 | .can_queue = SATA_FSL_QUEUE_DEPTH, |
faf0b2e5 | 1251 | .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, |
faf0b2e5 | 1252 | .dma_boundary = ATA_DMA_BOUNDARY, |
faf0b2e5 LY |
1253 | }; |
1254 | ||
034d8e8f AK |
1255 | static struct ata_port_operations sata_fsl_ops = { |
1256 | .inherits = &sata_pmp_port_ops, | |
029cfd6b | 1257 | |
faf0b2e5 LY |
1258 | .qc_prep = sata_fsl_qc_prep, |
1259 | .qc_issue = sata_fsl_qc_issue, | |
4c9bf4e7 | 1260 | .qc_fill_rtf = sata_fsl_qc_fill_rtf, |
faf0b2e5 LY |
1261 | |
1262 | .scr_read = sata_fsl_scr_read, | |
1263 | .scr_write = sata_fsl_scr_write, | |
1264 | ||
1265 | .freeze = sata_fsl_freeze, | |
1266 | .thaw = sata_fsl_thaw, | |
45db2f6c | 1267 | .prereset = sata_fsl_prereset, |
a1efdaba | 1268 | .softreset = sata_fsl_softreset, |
034d8e8f AK |
1269 | .pmp_softreset = sata_fsl_softreset, |
1270 | .error_handler = sata_fsl_error_handler, | |
faf0b2e5 LY |
1271 | .post_internal_cmd = sata_fsl_post_internal_cmd, |
1272 | ||
1273 | .port_start = sata_fsl_port_start, | |
1274 | .port_stop = sata_fsl_port_stop, | |
034d8e8f AK |
1275 | |
1276 | .pmp_attach = sata_fsl_pmp_attach, | |
1277 | .pmp_detach = sata_fsl_pmp_detach, | |
faf0b2e5 LY |
1278 | }; |
1279 | ||
1280 | static const struct ata_port_info sata_fsl_port_info[] = { | |
1281 | { | |
1282 | .flags = SATA_FSL_HOST_FLAGS, | |
14bdef98 EIB |
1283 | .pio_mask = ATA_PIO4, |
1284 | .udma_mask = ATA_UDMA6, | |
faf0b2e5 LY |
1285 | .port_ops = &sata_fsl_ops, |
1286 | }, | |
1287 | }; | |
1288 | ||
1289 | static int sata_fsl_probe(struct of_device *ofdev, | |
1290 | const struct of_device_id *match) | |
1291 | { | |
e4ac522b | 1292 | int retval = -ENXIO; |
faf0b2e5 LY |
1293 | void __iomem *hcr_base = NULL; |
1294 | void __iomem *ssr_base = NULL; | |
1295 | void __iomem *csr_base = NULL; | |
1296 | struct sata_fsl_host_priv *host_priv = NULL; | |
faf0b2e5 LY |
1297 | int irq; |
1298 | struct ata_host *host; | |
1299 | ||
1300 | struct ata_port_info pi = sata_fsl_port_info[0]; | |
1301 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
1302 | ||
1303 | dev_printk(KERN_INFO, &ofdev->dev, | |
1304 | "Sata FSL Platform/CSB Driver init\n"); | |
1305 | ||
faf0b2e5 LY |
1306 | hcr_base = of_iomap(ofdev->node, 0); |
1307 | if (!hcr_base) | |
1308 | goto error_exit_with_cleanup; | |
1309 | ||
1310 | ssr_base = hcr_base + 0x100; | |
1311 | csr_base = hcr_base + 0x140; | |
1312 | ||
1313 | DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); | |
1314 | DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); | |
1315 | DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); | |
1316 | ||
1317 | host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); | |
1318 | if (!host_priv) | |
1319 | goto error_exit_with_cleanup; | |
1320 | ||
1321 | host_priv->hcr_base = hcr_base; | |
1322 | host_priv->ssr_base = ssr_base; | |
1323 | host_priv->csr_base = csr_base; | |
1324 | ||
1325 | irq = irq_of_parse_and_map(ofdev->node, 0); | |
1326 | if (irq < 0) { | |
1327 | dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n"); | |
1328 | goto error_exit_with_cleanup; | |
1329 | } | |
79b3edc9 | 1330 | host_priv->irq = irq; |
faf0b2e5 LY |
1331 | |
1332 | /* allocate host structure */ | |
1333 | host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); | |
1334 | ||
1335 | /* host->iomap is not used currently */ | |
1336 | host->private_data = host_priv; | |
1337 | ||
faf0b2e5 LY |
1338 | /* initialize host controller */ |
1339 | sata_fsl_init_controller(host); | |
1340 | ||
1341 | /* | |
1342 | * Now, register with libATA core, this will also initiate the | |
1343 | * device discovery process, invoking our port_start() handler & | |
1344 | * error_handler() to execute a dummy Softreset EH session | |
1345 | */ | |
1346 | ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, | |
1347 | &sata_fsl_sht); | |
1348 | ||
1349 | dev_set_drvdata(&ofdev->dev, host); | |
1350 | ||
1351 | return 0; | |
1352 | ||
1353 | error_exit_with_cleanup: | |
1354 | ||
1355 | if (hcr_base) | |
1356 | iounmap(hcr_base); | |
1357 | if (host_priv) | |
1358 | kfree(host_priv); | |
1359 | ||
1360 | return retval; | |
1361 | } | |
1362 | ||
1363 | static int sata_fsl_remove(struct of_device *ofdev) | |
1364 | { | |
1365 | struct ata_host *host = dev_get_drvdata(&ofdev->dev); | |
1366 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
1367 | ||
1368 | ata_host_detach(host); | |
1369 | ||
1370 | dev_set_drvdata(&ofdev->dev, NULL); | |
1371 | ||
79b3edc9 | 1372 | irq_dispose_mapping(host_priv->irq); |
faf0b2e5 LY |
1373 | iounmap(host_priv->hcr_base); |
1374 | kfree(host_priv); | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
1379 | static struct of_device_id fsl_sata_match[] = { | |
1380 | { | |
96ce1b6d | 1381 | .compatible = "fsl,pq-sata", |
faf0b2e5 LY |
1382 | }, |
1383 | {}, | |
1384 | }; | |
1385 | ||
1386 | MODULE_DEVICE_TABLE(of, fsl_sata_match); | |
1387 | ||
1388 | static struct of_platform_driver fsl_sata_driver = { | |
1389 | .name = "fsl-sata", | |
1390 | .match_table = fsl_sata_match, | |
1391 | .probe = sata_fsl_probe, | |
1392 | .remove = sata_fsl_remove, | |
1393 | }; | |
1394 | ||
1395 | static int __init sata_fsl_init(void) | |
1396 | { | |
1397 | of_register_platform_driver(&fsl_sata_driver); | |
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | static void __exit sata_fsl_exit(void) | |
1402 | { | |
1403 | of_unregister_platform_driver(&fsl_sata_driver); | |
1404 | } | |
1405 | ||
1406 | MODULE_LICENSE("GPL"); | |
1407 | MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); | |
1408 | MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); | |
1409 | MODULE_VERSION("1.10"); | |
1410 | ||
1411 | module_init(sata_fsl_init); | |
1412 | module_exit(sata_fsl_exit); |