]>
Commit | Line | Data |
---|---|---|
1fd7a697 TH |
1 | /* |
2 | * sata_inic162x.c - Driver for Initio 162x SATA controllers | |
3 | * | |
4 | * Copyright 2006 SUSE Linux Products GmbH | |
5 | * Copyright 2006 Tejun Heo <teheo@novell.com> | |
6 | * | |
7 | * This file is released under GPL v2. | |
8 | * | |
9 | * This controller is eccentric and easily locks up if something isn't | |
10 | * right. Documentation is available at initio's website but it only | |
11 | * documents registers (not programming model). | |
12 | * | |
13 | * - ATA disks work. | |
14 | * - Hotplug works. | |
15 | * - ATAPI read works but burning doesn't. This thing is really | |
16 | * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and | |
17 | * ATAPI DMA WRITE should be programmed. If you've got a clue, be | |
18 | * my guest. | |
19 | * - Both STR and STD work. | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/pci.h> | |
25 | #include <scsi/scsi_host.h> | |
26 | #include <linux/libata.h> | |
27 | #include <linux/blkdev.h> | |
28 | #include <scsi/scsi_device.h> | |
29 | ||
30 | #define DRV_NAME "sata_inic162x" | |
2a3103ce | 31 | #define DRV_VERSION "0.3" |
1fd7a697 TH |
32 | |
33 | enum { | |
34 | MMIO_BAR = 5, | |
35 | ||
36 | NR_PORTS = 2, | |
37 | ||
b0dd9b8e | 38 | HOST_ACTRL = 0x08, |
1fd7a697 TH |
39 | HOST_CTL = 0x7c, |
40 | HOST_STAT = 0x7e, | |
41 | HOST_IRQ_STAT = 0xbc, | |
42 | HOST_IRQ_MASK = 0xbe, | |
43 | ||
44 | PORT_SIZE = 0x40, | |
45 | ||
46 | /* registers for ATA TF operation */ | |
b0dd9b8e TH |
47 | PORT_TF_DATA = 0x00, |
48 | PORT_TF_FEATURE = 0x01, | |
49 | PORT_TF_NSECT = 0x02, | |
50 | PORT_TF_LBAL = 0x03, | |
51 | PORT_TF_LBAM = 0x04, | |
52 | PORT_TF_LBAH = 0x05, | |
53 | PORT_TF_DEVICE = 0x06, | |
54 | PORT_TF_COMMAND = 0x07, | |
55 | PORT_TF_ALT_STAT = 0x08, | |
1fd7a697 TH |
56 | PORT_IRQ_STAT = 0x09, |
57 | PORT_IRQ_MASK = 0x0a, | |
58 | PORT_PRD_CTL = 0x0b, | |
59 | PORT_PRD_ADDR = 0x0c, | |
60 | PORT_PRD_XFERLEN = 0x10, | |
b0dd9b8e TH |
61 | PORT_CPB_CPBLAR = 0x18, |
62 | PORT_CPB_PTQFIFO = 0x1c, | |
1fd7a697 TH |
63 | |
64 | /* IDMA register */ | |
65 | PORT_IDMA_CTL = 0x14, | |
b0dd9b8e TH |
66 | PORT_IDMA_STAT = 0x16, |
67 | ||
68 | PORT_RPQ_FIFO = 0x1e, | |
69 | PORT_RPQ_CNT = 0x1f, | |
1fd7a697 TH |
70 | |
71 | PORT_SCR = 0x20, | |
72 | ||
73 | /* HOST_CTL bits */ | |
74 | HCTL_IRQOFF = (1 << 8), /* global IRQ off */ | |
b0dd9b8e TH |
75 | HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */ |
76 | HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/ | |
77 | HCTL_PWRDWN = (1 << 12), /* power down PHYs */ | |
1fd7a697 TH |
78 | HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */ |
79 | HCTL_RPGSEL = (1 << 15), /* register page select */ | |
80 | ||
81 | HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST | | |
82 | HCTL_RPGSEL, | |
83 | ||
84 | /* HOST_IRQ_(STAT|MASK) bits */ | |
85 | HIRQ_PORT0 = (1 << 0), | |
86 | HIRQ_PORT1 = (1 << 1), | |
87 | HIRQ_SOFT = (1 << 14), | |
88 | HIRQ_GLOBAL = (1 << 15), /* STAT only */ | |
89 | ||
90 | /* PORT_IRQ_(STAT|MASK) bits */ | |
91 | PIRQ_OFFLINE = (1 << 0), /* device unplugged */ | |
92 | PIRQ_ONLINE = (1 << 1), /* device plugged */ | |
93 | PIRQ_COMPLETE = (1 << 2), /* completion interrupt */ | |
94 | PIRQ_FATAL = (1 << 3), /* fatal error */ | |
95 | PIRQ_ATA = (1 << 4), /* ATA interrupt */ | |
96 | PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */ | |
97 | PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */ | |
98 | ||
99 | PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL, | |
100 | ||
101 | PIRQ_MASK_DMA_READ = PIRQ_REPLY | PIRQ_ATA, | |
102 | PIRQ_MASK_OTHER = PIRQ_REPLY | PIRQ_COMPLETE, | |
103 | PIRQ_MASK_FREEZE = 0xff, | |
104 | ||
105 | /* PORT_PRD_CTL bits */ | |
106 | PRD_CTL_START = (1 << 0), | |
107 | PRD_CTL_WR = (1 << 3), | |
108 | PRD_CTL_DMAEN = (1 << 7), /* DMA enable */ | |
109 | ||
110 | /* PORT_IDMA_CTL bits */ | |
111 | IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */ | |
112 | IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */ | |
113 | IDMA_CTL_GO = (1 << 7), /* IDMA mode go */ | |
114 | IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */ | |
b0dd9b8e TH |
115 | |
116 | /* PORT_IDMA_STAT bits */ | |
117 | IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */ | |
118 | IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */ | |
119 | IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */ | |
120 | IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */ | |
121 | IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */ | |
122 | IDMA_STAT_PSD = (1 << 6), /* ADMA pause */ | |
123 | IDMA_STAT_DONE = (1 << 7), /* ADMA done */ | |
124 | ||
125 | IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR, | |
126 | ||
127 | /* CPB Control Flags*/ | |
128 | CPB_CTL_VALID = (1 << 0), /* CPB valid */ | |
129 | CPB_CTL_QUEUED = (1 << 1), /* queued command */ | |
130 | CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */ | |
131 | CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */ | |
132 | CPB_CTL_DEVDIR = (1 << 4), /* device direction control */ | |
133 | ||
134 | /* CPB Response Flags */ | |
135 | CPB_RESP_DONE = (1 << 0), /* ATA command complete */ | |
136 | CPB_RESP_REL = (1 << 1), /* ATA release */ | |
137 | CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */ | |
138 | CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */ | |
139 | CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */ | |
140 | CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */ | |
141 | CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */ | |
142 | CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */ | |
143 | ||
144 | /* PRD Control Flags */ | |
145 | PRD_DRAIN = (1 << 1), /* ignore data excess */ | |
146 | PRD_CDB = (1 << 2), /* atapi packet command pointer */ | |
147 | PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */ | |
148 | PRD_DMA = (1 << 4), /* data transfer method */ | |
149 | PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */ | |
150 | PRD_IOM = (1 << 6), /* io/memory transfer */ | |
151 | PRD_END = (1 << 7), /* APRD chain end */ | |
1fd7a697 TH |
152 | }; |
153 | ||
154 | struct inic_host_priv { | |
36f674d9 | 155 | u16 cached_hctl; |
1fd7a697 TH |
156 | }; |
157 | ||
158 | struct inic_port_priv { | |
36f674d9 TH |
159 | u8 dfl_prdctl; |
160 | u8 cached_prdctl; | |
161 | u8 cached_pirq_mask; | |
1fd7a697 TH |
162 | }; |
163 | ||
1fd7a697 | 164 | static struct scsi_host_template inic_sht = { |
68d1d07b | 165 | ATA_BMDMA_SHT(DRV_NAME), |
1fd7a697 TH |
166 | }; |
167 | ||
168 | static const int scr_map[] = { | |
169 | [SCR_STATUS] = 0, | |
170 | [SCR_ERROR] = 1, | |
171 | [SCR_CONTROL] = 2, | |
172 | }; | |
173 | ||
5796d1c4 | 174 | static void __iomem *inic_port_base(struct ata_port *ap) |
1fd7a697 | 175 | { |
0d5ff566 | 176 | return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE; |
1fd7a697 TH |
177 | } |
178 | ||
179 | static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask) | |
180 | { | |
181 | void __iomem *port_base = inic_port_base(ap); | |
182 | struct inic_port_priv *pp = ap->private_data; | |
183 | ||
184 | writeb(mask, port_base + PORT_IRQ_MASK); | |
185 | pp->cached_pirq_mask = mask; | |
186 | } | |
187 | ||
188 | static void inic_set_pirq_mask(struct ata_port *ap, u8 mask) | |
189 | { | |
190 | struct inic_port_priv *pp = ap->private_data; | |
191 | ||
192 | if (pp->cached_pirq_mask != mask) | |
193 | __inic_set_pirq_mask(ap, mask); | |
194 | } | |
195 | ||
196 | static void inic_reset_port(void __iomem *port_base) | |
197 | { | |
198 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
199 | u16 ctl; | |
200 | ||
201 | ctl = readw(idma_ctl); | |
202 | ctl &= ~(IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN | IDMA_CTL_GO); | |
203 | ||
204 | /* mask IRQ and assert reset */ | |
205 | writew(ctl | IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN, idma_ctl); | |
206 | readw(idma_ctl); /* flush */ | |
207 | ||
208 | /* give it some time */ | |
209 | msleep(1); | |
210 | ||
211 | /* release reset */ | |
212 | writew(ctl | IDMA_CTL_ATA_NIEN, idma_ctl); | |
213 | ||
214 | /* clear irq */ | |
215 | writeb(0xff, port_base + PORT_IRQ_STAT); | |
216 | ||
217 | /* reenable ATA IRQ, turn off IDMA mode */ | |
218 | writew(ctl, idma_ctl); | |
219 | } | |
220 | ||
da3dbb17 | 221 | static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val) |
1fd7a697 | 222 | { |
59f99880 | 223 | void __iomem *scr_addr = ap->ioaddr.scr_addr; |
1fd7a697 | 224 | void __iomem *addr; |
1fd7a697 TH |
225 | |
226 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 227 | return -EINVAL; |
1fd7a697 TH |
228 | |
229 | addr = scr_addr + scr_map[sc_reg] * 4; | |
da3dbb17 | 230 | *val = readl(scr_addr + scr_map[sc_reg] * 4); |
1fd7a697 TH |
231 | |
232 | /* this controller has stuck DIAG.N, ignore it */ | |
233 | if (sc_reg == SCR_ERROR) | |
da3dbb17 TH |
234 | *val &= ~SERR_PHYRDY_CHG; |
235 | return 0; | |
1fd7a697 TH |
236 | } |
237 | ||
da3dbb17 | 238 | static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) |
1fd7a697 | 239 | { |
59f99880 | 240 | void __iomem *scr_addr = ap->ioaddr.scr_addr; |
1fd7a697 TH |
241 | |
242 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 243 | return -EINVAL; |
1fd7a697 | 244 | |
1fd7a697 | 245 | writel(val, scr_addr + scr_map[sc_reg] * 4); |
da3dbb17 | 246 | return 0; |
1fd7a697 TH |
247 | } |
248 | ||
249 | /* | |
250 | * In TF mode, inic162x is very similar to SFF device. TF registers | |
251 | * function the same. DMA engine behaves similary using the same PRD | |
252 | * format as BMDMA but different command register, interrupt and event | |
253 | * notification methods are used. The following inic_bmdma_*() | |
254 | * functions do the impedance matching. | |
255 | */ | |
256 | static void inic_bmdma_setup(struct ata_queued_cmd *qc) | |
257 | { | |
258 | struct ata_port *ap = qc->ap; | |
259 | struct inic_port_priv *pp = ap->private_data; | |
260 | void __iomem *port_base = inic_port_base(ap); | |
261 | int rw = qc->tf.flags & ATA_TFLAG_WRITE; | |
262 | ||
263 | /* make sure device sees PRD table writes */ | |
264 | wmb(); | |
265 | ||
266 | /* load transfer length */ | |
267 | writel(qc->nbytes, port_base + PORT_PRD_XFERLEN); | |
268 | ||
269 | /* turn on DMA and specify data direction */ | |
270 | pp->cached_prdctl = pp->dfl_prdctl | PRD_CTL_DMAEN; | |
271 | if (!rw) | |
272 | pp->cached_prdctl |= PRD_CTL_WR; | |
273 | writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL); | |
274 | ||
275 | /* issue r/w command */ | |
5682ed33 | 276 | ap->ops->sff_exec_command(ap, &qc->tf); |
1fd7a697 TH |
277 | } |
278 | ||
279 | static void inic_bmdma_start(struct ata_queued_cmd *qc) | |
280 | { | |
281 | struct ata_port *ap = qc->ap; | |
282 | struct inic_port_priv *pp = ap->private_data; | |
283 | void __iomem *port_base = inic_port_base(ap); | |
284 | ||
285 | /* start host DMA transaction */ | |
286 | pp->cached_prdctl |= PRD_CTL_START; | |
287 | writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL); | |
288 | } | |
289 | ||
290 | static void inic_bmdma_stop(struct ata_queued_cmd *qc) | |
291 | { | |
292 | struct ata_port *ap = qc->ap; | |
293 | struct inic_port_priv *pp = ap->private_data; | |
294 | void __iomem *port_base = inic_port_base(ap); | |
295 | ||
296 | /* stop DMA engine */ | |
297 | writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL); | |
298 | } | |
299 | ||
300 | static u8 inic_bmdma_status(struct ata_port *ap) | |
301 | { | |
302 | /* event is already verified by the interrupt handler */ | |
303 | return ATA_DMA_INTR; | |
304 | } | |
305 | ||
1fd7a697 TH |
306 | static void inic_host_intr(struct ata_port *ap) |
307 | { | |
308 | void __iomem *port_base = inic_port_base(ap); | |
9af5c9c9 | 309 | struct ata_eh_info *ehi = &ap->link.eh_info; |
1fd7a697 TH |
310 | u8 irq_stat; |
311 | ||
312 | /* fetch and clear irq */ | |
313 | irq_stat = readb(port_base + PORT_IRQ_STAT); | |
314 | writeb(irq_stat, port_base + PORT_IRQ_STAT); | |
315 | ||
316 | if (likely(!(irq_stat & PIRQ_ERR))) { | |
9af5c9c9 TH |
317 | struct ata_queued_cmd *qc = |
318 | ata_qc_from_tag(ap, ap->link.active_tag); | |
1fd7a697 TH |
319 | |
320 | if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { | |
5682ed33 | 321 | ap->ops->sff_check_status(ap); /* clear ATA interrupt */ |
1fd7a697 TH |
322 | return; |
323 | } | |
324 | ||
9363c382 | 325 | if (likely(ata_sff_host_intr(ap, qc))) |
1fd7a697 TH |
326 | return; |
327 | ||
5682ed33 | 328 | ap->ops->sff_check_status(ap); /* clear ATA interrupt */ |
1fd7a697 TH |
329 | ata_port_printk(ap, KERN_WARNING, "unhandled " |
330 | "interrupt, irq_stat=%x\n", irq_stat); | |
331 | return; | |
332 | } | |
333 | ||
334 | /* error */ | |
335 | ata_ehi_push_desc(ehi, "irq_stat=0x%x", irq_stat); | |
336 | ||
337 | if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) { | |
338 | ata_ehi_hotplugged(ehi); | |
339 | ata_port_freeze(ap); | |
340 | } else | |
341 | ata_port_abort(ap); | |
342 | } | |
343 | ||
344 | static irqreturn_t inic_interrupt(int irq, void *dev_instance) | |
345 | { | |
346 | struct ata_host *host = dev_instance; | |
0d5ff566 | 347 | void __iomem *mmio_base = host->iomap[MMIO_BAR]; |
1fd7a697 TH |
348 | u16 host_irq_stat; |
349 | int i, handled = 0;; | |
350 | ||
351 | host_irq_stat = readw(mmio_base + HOST_IRQ_STAT); | |
352 | ||
353 | if (unlikely(!(host_irq_stat & HIRQ_GLOBAL))) | |
354 | goto out; | |
355 | ||
356 | spin_lock(&host->lock); | |
357 | ||
358 | for (i = 0; i < NR_PORTS; i++) { | |
359 | struct ata_port *ap = host->ports[i]; | |
360 | ||
361 | if (!(host_irq_stat & (HIRQ_PORT0 << i))) | |
362 | continue; | |
363 | ||
364 | if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) { | |
365 | inic_host_intr(ap); | |
366 | handled++; | |
367 | } else { | |
368 | if (ata_ratelimit()) | |
369 | dev_printk(KERN_ERR, host->dev, "interrupt " | |
370 | "from disabled port %d (0x%x)\n", | |
371 | i, host_irq_stat); | |
372 | } | |
373 | } | |
374 | ||
375 | spin_unlock(&host->lock); | |
376 | ||
377 | out: | |
378 | return IRQ_RETVAL(handled); | |
379 | } | |
380 | ||
381 | static unsigned int inic_qc_issue(struct ata_queued_cmd *qc) | |
382 | { | |
383 | struct ata_port *ap = qc->ap; | |
384 | ||
385 | /* ATA IRQ doesn't wait for DMA transfer completion and vice | |
386 | * versa. Mask IRQ selectively to detect command completion. | |
387 | * Without it, ATA DMA read command can cause data corruption. | |
388 | * | |
389 | * Something similar might be needed for ATAPI writes. I | |
390 | * tried a lot of combinations but couldn't find the solution. | |
391 | */ | |
392 | if (qc->tf.protocol == ATA_PROT_DMA && | |
393 | !(qc->tf.flags & ATA_TFLAG_WRITE)) | |
394 | inic_set_pirq_mask(ap, PIRQ_MASK_DMA_READ); | |
395 | else | |
396 | inic_set_pirq_mask(ap, PIRQ_MASK_OTHER); | |
397 | ||
398 | /* Issuing a command to yet uninitialized port locks up the | |
399 | * controller. Most of the time, this happens for the first | |
400 | * command after reset which are ATA and ATAPI IDENTIFYs. | |
401 | * Fast fail if stat is 0x7f or 0xff for those commands. | |
402 | */ | |
403 | if (unlikely(qc->tf.command == ATA_CMD_ID_ATA || | |
404 | qc->tf.command == ATA_CMD_ID_ATAPI)) { | |
5682ed33 | 405 | u8 stat = ap->ops->sff_check_status(ap); |
1fd7a697 TH |
406 | if (stat == 0x7f || stat == 0xff) |
407 | return AC_ERR_HSM; | |
408 | } | |
409 | ||
9363c382 | 410 | return ata_sff_qc_issue(qc); |
1fd7a697 TH |
411 | } |
412 | ||
364fac0e TH |
413 | static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
414 | { | |
415 | void __iomem *port_base = inic_port_base(ap); | |
416 | ||
417 | tf->feature = readb(port_base + PORT_TF_FEATURE); | |
418 | tf->nsect = readb(port_base + PORT_TF_NSECT); | |
419 | tf->lbal = readb(port_base + PORT_TF_LBAL); | |
420 | tf->lbam = readb(port_base + PORT_TF_LBAM); | |
421 | tf->lbah = readb(port_base + PORT_TF_LBAH); | |
422 | tf->device = readb(port_base + PORT_TF_DEVICE); | |
423 | tf->command = readb(port_base + PORT_TF_COMMAND); | |
424 | } | |
425 | ||
426 | static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc) | |
427 | { | |
428 | struct ata_taskfile *rtf = &qc->result_tf; | |
429 | struct ata_taskfile tf; | |
430 | ||
431 | /* FIXME: Except for status and error, result TF access | |
432 | * doesn't work. I tried reading from BAR0/2, CPB and BAR5. | |
433 | * None works regardless of which command interface is used. | |
434 | * For now return true iff status indicates device error. | |
435 | * This means that we're reporting bogus sector for RW | |
436 | * failures. Eeekk.... | |
437 | */ | |
438 | inic_tf_read(qc->ap, &tf); | |
439 | ||
440 | if (!(tf.command & ATA_ERR)) | |
441 | return false; | |
442 | ||
443 | rtf->command = tf.command; | |
444 | rtf->feature = tf.feature; | |
445 | return true; | |
446 | } | |
447 | ||
1fd7a697 TH |
448 | static void inic_freeze(struct ata_port *ap) |
449 | { | |
450 | void __iomem *port_base = inic_port_base(ap); | |
451 | ||
452 | __inic_set_pirq_mask(ap, PIRQ_MASK_FREEZE); | |
453 | ||
5682ed33 | 454 | ap->ops->sff_check_status(ap); |
1fd7a697 | 455 | writeb(0xff, port_base + PORT_IRQ_STAT); |
1fd7a697 TH |
456 | } |
457 | ||
458 | static void inic_thaw(struct ata_port *ap) | |
459 | { | |
460 | void __iomem *port_base = inic_port_base(ap); | |
461 | ||
5682ed33 | 462 | ap->ops->sff_check_status(ap); |
1fd7a697 TH |
463 | writeb(0xff, port_base + PORT_IRQ_STAT); |
464 | ||
465 | __inic_set_pirq_mask(ap, PIRQ_MASK_OTHER); | |
1fd7a697 TH |
466 | } |
467 | ||
364fac0e TH |
468 | static int inic_check_ready(struct ata_link *link) |
469 | { | |
470 | void __iomem *port_base = inic_port_base(link->ap); | |
471 | ||
472 | return ata_check_ready(readb(port_base + PORT_TF_COMMAND)); | |
473 | } | |
474 | ||
1fd7a697 TH |
475 | /* |
476 | * SRST and SControl hardreset don't give valid signature on this | |
477 | * controller. Only controller specific hardreset mechanism works. | |
478 | */ | |
cc0680a5 | 479 | static int inic_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 480 | unsigned long deadline) |
1fd7a697 | 481 | { |
cc0680a5 | 482 | struct ata_port *ap = link->ap; |
1fd7a697 TH |
483 | void __iomem *port_base = inic_port_base(ap); |
484 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
cc0680a5 | 485 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
1fd7a697 TH |
486 | u16 val; |
487 | int rc; | |
488 | ||
489 | /* hammer it into sane state */ | |
490 | inic_reset_port(port_base); | |
491 | ||
1fd7a697 TH |
492 | val = readw(idma_ctl); |
493 | writew(val | IDMA_CTL_RST_ATA, idma_ctl); | |
494 | readw(idma_ctl); /* flush */ | |
495 | msleep(1); | |
496 | writew(val & ~IDMA_CTL_RST_ATA, idma_ctl); | |
497 | ||
cc0680a5 | 498 | rc = sata_link_resume(link, timing, deadline); |
1fd7a697 | 499 | if (rc) { |
cc0680a5 | 500 | ata_link_printk(link, KERN_WARNING, "failed to resume " |
fe334602 | 501 | "link after reset (errno=%d)\n", rc); |
1fd7a697 TH |
502 | return rc; |
503 | } | |
504 | ||
1fd7a697 | 505 | *class = ATA_DEV_NONE; |
cc0680a5 | 506 | if (ata_link_online(link)) { |
1fd7a697 TH |
507 | struct ata_taskfile tf; |
508 | ||
705e76be | 509 | /* wait for link to become ready */ |
364fac0e | 510 | rc = ata_wait_after_reset(link, deadline, inic_check_ready); |
9b89391c TH |
511 | /* link occupied, -ENODEV too is an error */ |
512 | if (rc) { | |
cc0680a5 | 513 | ata_link_printk(link, KERN_WARNING, "device not ready " |
d4b2bab4 TH |
514 | "after hardreset (errno=%d)\n", rc); |
515 | return rc; | |
1fd7a697 TH |
516 | } |
517 | ||
364fac0e | 518 | inic_tf_read(ap, &tf); |
1fd7a697 | 519 | *class = ata_dev_classify(&tf); |
1fd7a697 TH |
520 | } |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | static void inic_error_handler(struct ata_port *ap) | |
526 | { | |
527 | void __iomem *port_base = inic_port_base(ap); | |
528 | struct inic_port_priv *pp = ap->private_data; | |
529 | unsigned long flags; | |
530 | ||
531 | /* reset PIO HSM and stop DMA engine */ | |
532 | inic_reset_port(port_base); | |
533 | ||
534 | spin_lock_irqsave(ap->lock, flags); | |
535 | ap->hsm_task_state = HSM_ST_IDLE; | |
536 | writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL); | |
537 | spin_unlock_irqrestore(ap->lock, flags); | |
538 | ||
539 | /* PIO and DMA engines have been stopped, perform recovery */ | |
a1efdaba | 540 | ata_std_error_handler(ap); |
1fd7a697 TH |
541 | } |
542 | ||
543 | static void inic_post_internal_cmd(struct ata_queued_cmd *qc) | |
544 | { | |
545 | /* make DMA engine forget about the failed command */ | |
a51d644a | 546 | if (qc->flags & ATA_QCFLAG_FAILED) |
1fd7a697 TH |
547 | inic_reset_port(inic_port_base(qc->ap)); |
548 | } | |
549 | ||
cd0d3bbc | 550 | static void inic_dev_config(struct ata_device *dev) |
1fd7a697 TH |
551 | { |
552 | /* inic can only handle upto LBA28 max sectors */ | |
553 | if (dev->max_sectors > ATA_MAX_SECTORS) | |
554 | dev->max_sectors = ATA_MAX_SECTORS; | |
90c93785 TH |
555 | |
556 | if (dev->n_sectors >= 1 << 28) { | |
557 | ata_dev_printk(dev, KERN_ERR, | |
558 | "ERROR: This driver doesn't support LBA48 yet and may cause\n" | |
559 | " data corruption on such devices. Disabling.\n"); | |
560 | ata_dev_disable(dev); | |
561 | } | |
1fd7a697 TH |
562 | } |
563 | ||
564 | static void init_port(struct ata_port *ap) | |
565 | { | |
566 | void __iomem *port_base = inic_port_base(ap); | |
567 | ||
568 | /* Setup PRD address */ | |
569 | writel(ap->prd_dma, port_base + PORT_PRD_ADDR); | |
570 | } | |
571 | ||
572 | static int inic_port_resume(struct ata_port *ap) | |
573 | { | |
574 | init_port(ap); | |
575 | return 0; | |
576 | } | |
577 | ||
578 | static int inic_port_start(struct ata_port *ap) | |
579 | { | |
580 | void __iomem *port_base = inic_port_base(ap); | |
581 | struct inic_port_priv *pp; | |
582 | u8 tmp; | |
583 | int rc; | |
584 | ||
585 | /* alloc and initialize private data */ | |
24dc5f33 | 586 | pp = devm_kzalloc(ap->host->dev, sizeof(*pp), GFP_KERNEL); |
1fd7a697 TH |
587 | if (!pp) |
588 | return -ENOMEM; | |
589 | ap->private_data = pp; | |
590 | ||
591 | /* default PRD_CTL value, DMAEN, WR and START off */ | |
592 | tmp = readb(port_base + PORT_PRD_CTL); | |
593 | tmp &= ~(PRD_CTL_DMAEN | PRD_CTL_WR | PRD_CTL_START); | |
594 | pp->dfl_prdctl = tmp; | |
595 | ||
596 | /* Alloc resources */ | |
597 | rc = ata_port_start(ap); | |
36f674d9 | 598 | if (rc) |
1fd7a697 | 599 | return rc; |
1fd7a697 TH |
600 | |
601 | init_port(ap); | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
1fd7a697 | 606 | static struct ata_port_operations inic_port_ops = { |
029cfd6b | 607 | .inherits = &ata_sff_port_ops, |
1fd7a697 TH |
608 | |
609 | .bmdma_setup = inic_bmdma_setup, | |
610 | .bmdma_start = inic_bmdma_start, | |
611 | .bmdma_stop = inic_bmdma_stop, | |
612 | .bmdma_status = inic_bmdma_status, | |
1fd7a697 | 613 | .qc_issue = inic_qc_issue, |
364fac0e | 614 | .qc_fill_rtf = inic_qc_fill_rtf, |
1fd7a697 TH |
615 | |
616 | .freeze = inic_freeze, | |
617 | .thaw = inic_thaw, | |
a1efdaba TH |
618 | .softreset = ATA_OP_NULL, /* softreset is broken */ |
619 | .hardreset = inic_hardreset, | |
1fd7a697 TH |
620 | .error_handler = inic_error_handler, |
621 | .post_internal_cmd = inic_post_internal_cmd, | |
622 | .dev_config = inic_dev_config, | |
623 | ||
029cfd6b TH |
624 | .scr_read = inic_scr_read, |
625 | .scr_write = inic_scr_write, | |
1fd7a697 | 626 | |
029cfd6b | 627 | .port_resume = inic_port_resume, |
1fd7a697 | 628 | .port_start = inic_port_start, |
1fd7a697 TH |
629 | }; |
630 | ||
631 | static struct ata_port_info inic_port_info = { | |
0dc36888 | 632 | /* For some reason, ATAPI_PROT_PIO is broken on this |
1fd7a697 TH |
633 | * controller, and no, PIO_POLLING does't fix it. It somehow |
634 | * manages to report the wrong ireason and ignoring ireason | |
635 | * results in machine lock up. Tell libata to always prefer | |
636 | * DMA. | |
637 | */ | |
638 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, | |
639 | .pio_mask = 0x1f, /* pio0-4 */ | |
640 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 641 | .udma_mask = ATA_UDMA6, |
1fd7a697 TH |
642 | .port_ops = &inic_port_ops |
643 | }; | |
644 | ||
645 | static int init_controller(void __iomem *mmio_base, u16 hctl) | |
646 | { | |
647 | int i; | |
648 | u16 val; | |
649 | ||
650 | hctl &= ~HCTL_KNOWN_BITS; | |
651 | ||
652 | /* Soft reset whole controller. Spec says reset duration is 3 | |
653 | * PCI clocks, be generous and give it 10ms. | |
654 | */ | |
655 | writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); | |
656 | readw(mmio_base + HOST_CTL); /* flush */ | |
657 | ||
658 | for (i = 0; i < 10; i++) { | |
659 | msleep(1); | |
660 | val = readw(mmio_base + HOST_CTL); | |
661 | if (!(val & HCTL_SOFTRST)) | |
662 | break; | |
663 | } | |
664 | ||
665 | if (val & HCTL_SOFTRST) | |
666 | return -EIO; | |
667 | ||
668 | /* mask all interrupts and reset ports */ | |
669 | for (i = 0; i < NR_PORTS; i++) { | |
670 | void __iomem *port_base = mmio_base + i * PORT_SIZE; | |
671 | ||
672 | writeb(0xff, port_base + PORT_IRQ_MASK); | |
673 | inic_reset_port(port_base); | |
674 | } | |
675 | ||
676 | /* port IRQ is masked now, unmask global IRQ */ | |
677 | writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); | |
678 | val = readw(mmio_base + HOST_IRQ_MASK); | |
679 | val &= ~(HIRQ_PORT0 | HIRQ_PORT1); | |
680 | writew(val, mmio_base + HOST_IRQ_MASK); | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
438ac6d5 | 685 | #ifdef CONFIG_PM |
1fd7a697 TH |
686 | static int inic_pci_device_resume(struct pci_dev *pdev) |
687 | { | |
688 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
689 | struct inic_host_priv *hpriv = host->private_data; | |
0d5ff566 | 690 | void __iomem *mmio_base = host->iomap[MMIO_BAR]; |
1fd7a697 TH |
691 | int rc; |
692 | ||
5aea408d DM |
693 | rc = ata_pci_device_do_resume(pdev); |
694 | if (rc) | |
695 | return rc; | |
1fd7a697 TH |
696 | |
697 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
1fd7a697 TH |
698 | rc = init_controller(mmio_base, hpriv->cached_hctl); |
699 | if (rc) | |
700 | return rc; | |
701 | } | |
702 | ||
703 | ata_host_resume(host); | |
704 | ||
705 | return 0; | |
706 | } | |
438ac6d5 | 707 | #endif |
1fd7a697 TH |
708 | |
709 | static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
710 | { | |
711 | static int printed_version; | |
4447d351 TH |
712 | const struct ata_port_info *ppi[] = { &inic_port_info, NULL }; |
713 | struct ata_host *host; | |
1fd7a697 | 714 | struct inic_host_priv *hpriv; |
0d5ff566 | 715 | void __iomem * const *iomap; |
1fd7a697 TH |
716 | int i, rc; |
717 | ||
718 | if (!printed_version++) | |
719 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
720 | ||
4447d351 TH |
721 | /* alloc host */ |
722 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS); | |
723 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
724 | if (!host || !hpriv) | |
725 | return -ENOMEM; | |
726 | ||
727 | host->private_data = hpriv; | |
728 | ||
729 | /* acquire resources and fill host */ | |
24dc5f33 | 730 | rc = pcim_enable_device(pdev); |
1fd7a697 TH |
731 | if (rc) |
732 | return rc; | |
733 | ||
0d5ff566 TH |
734 | rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME); |
735 | if (rc) | |
736 | return rc; | |
4447d351 TH |
737 | host->iomap = iomap = pcim_iomap_table(pdev); |
738 | ||
739 | for (i = 0; i < NR_PORTS; i++) { | |
cbcdd875 TH |
740 | struct ata_port *ap = host->ports[i]; |
741 | struct ata_ioports *port = &ap->ioaddr; | |
742 | unsigned int offset = i * PORT_SIZE; | |
4447d351 TH |
743 | |
744 | port->cmd_addr = iomap[2 * i]; | |
745 | port->altstatus_addr = | |
746 | port->ctl_addr = (void __iomem *) | |
747 | ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS); | |
cbcdd875 | 748 | port->scr_addr = iomap[MMIO_BAR] + offset + PORT_SCR; |
4447d351 | 749 | |
9363c382 | 750 | ata_sff_std_ports(port); |
cbcdd875 TH |
751 | |
752 | ata_port_pbar_desc(ap, MMIO_BAR, -1, "mmio"); | |
753 | ata_port_pbar_desc(ap, MMIO_BAR, offset, "port"); | |
754 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", | |
755 | (unsigned long long)pci_resource_start(pdev, 2 * i), | |
756 | (unsigned long long)pci_resource_start(pdev, (2 * i + 1)) | | |
757 | ATA_PCI_CTL_OFS); | |
4447d351 TH |
758 | } |
759 | ||
760 | hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL); | |
1fd7a697 TH |
761 | |
762 | /* Set dma_mask. This devices doesn't support 64bit addressing. */ | |
763 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
764 | if (rc) { | |
765 | dev_printk(KERN_ERR, &pdev->dev, | |
766 | "32-bit DMA enable failed\n"); | |
24dc5f33 | 767 | return rc; |
1fd7a697 TH |
768 | } |
769 | ||
770 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
771 | if (rc) { | |
772 | dev_printk(KERN_ERR, &pdev->dev, | |
773 | "32-bit consistent DMA enable failed\n"); | |
24dc5f33 | 774 | return rc; |
1fd7a697 TH |
775 | } |
776 | ||
b7d8629f FT |
777 | /* |
778 | * This controller is braindamaged. dma_boundary is 0xffff | |
779 | * like others but it will lock up the whole machine HARD if | |
780 | * 65536 byte PRD entry is fed. Reduce maximum segment size. | |
781 | */ | |
782 | rc = pci_set_dma_max_seg_size(pdev, 65536 - 512); | |
783 | if (rc) { | |
784 | dev_printk(KERN_ERR, &pdev->dev, | |
785 | "failed to set the maximum segment size.\n"); | |
786 | return rc; | |
787 | } | |
788 | ||
0d5ff566 | 789 | rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl); |
1fd7a697 TH |
790 | if (rc) { |
791 | dev_printk(KERN_ERR, &pdev->dev, | |
792 | "failed to initialize controller\n"); | |
24dc5f33 | 793 | return rc; |
1fd7a697 TH |
794 | } |
795 | ||
796 | pci_set_master(pdev); | |
4447d351 TH |
797 | return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED, |
798 | &inic_sht); | |
1fd7a697 TH |
799 | } |
800 | ||
801 | static const struct pci_device_id inic_pci_tbl[] = { | |
802 | { PCI_VDEVICE(INIT, 0x1622), }, | |
803 | { }, | |
804 | }; | |
805 | ||
806 | static struct pci_driver inic_pci_driver = { | |
807 | .name = DRV_NAME, | |
808 | .id_table = inic_pci_tbl, | |
438ac6d5 | 809 | #ifdef CONFIG_PM |
1fd7a697 TH |
810 | .suspend = ata_pci_device_suspend, |
811 | .resume = inic_pci_device_resume, | |
438ac6d5 | 812 | #endif |
1fd7a697 TH |
813 | .probe = inic_init_one, |
814 | .remove = ata_pci_remove_one, | |
815 | }; | |
816 | ||
817 | static int __init inic_init(void) | |
818 | { | |
819 | return pci_register_driver(&inic_pci_driver); | |
820 | } | |
821 | ||
822 | static void __exit inic_exit(void) | |
823 | { | |
824 | pci_unregister_driver(&inic_pci_driver); | |
825 | } | |
826 | ||
827 | MODULE_AUTHOR("Tejun Heo"); | |
828 | MODULE_DESCRIPTION("low-level driver for Initio 162x SATA"); | |
829 | MODULE_LICENSE("GPL v2"); | |
830 | MODULE_DEVICE_TABLE(pci, inic_pci_tbl); | |
831 | MODULE_VERSION(DRV_VERSION); | |
832 | ||
833 | module_init(inic_init); | |
834 | module_exit(inic_exit); |