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1fd7a697 TH |
1 | /* |
2 | * sata_inic162x.c - Driver for Initio 162x SATA controllers | |
3 | * | |
4 | * Copyright 2006 SUSE Linux Products GmbH | |
5 | * Copyright 2006 Tejun Heo <teheo@novell.com> | |
6 | * | |
7 | * This file is released under GPL v2. | |
8 | * | |
9 | * This controller is eccentric and easily locks up if something isn't | |
10 | * right. Documentation is available at initio's website but it only | |
11 | * documents registers (not programming model). | |
12 | * | |
13 | * - ATA disks work. | |
14 | * - Hotplug works. | |
15 | * - ATAPI read works but burning doesn't. This thing is really | |
16 | * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and | |
17 | * ATAPI DMA WRITE should be programmed. If you've got a clue, be | |
18 | * my guest. | |
19 | * - Both STR and STD work. | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/pci.h> | |
25 | #include <scsi/scsi_host.h> | |
26 | #include <linux/libata.h> | |
27 | #include <linux/blkdev.h> | |
28 | #include <scsi/scsi_device.h> | |
29 | ||
30 | #define DRV_NAME "sata_inic162x" | |
2a3103ce | 31 | #define DRV_VERSION "0.3" |
1fd7a697 TH |
32 | |
33 | enum { | |
34 | MMIO_BAR = 5, | |
35 | ||
36 | NR_PORTS = 2, | |
37 | ||
38 | HOST_CTL = 0x7c, | |
39 | HOST_STAT = 0x7e, | |
40 | HOST_IRQ_STAT = 0xbc, | |
41 | HOST_IRQ_MASK = 0xbe, | |
42 | ||
43 | PORT_SIZE = 0x40, | |
44 | ||
45 | /* registers for ATA TF operation */ | |
46 | PORT_TF = 0x00, | |
47 | PORT_ALT_STAT = 0x08, | |
48 | PORT_IRQ_STAT = 0x09, | |
49 | PORT_IRQ_MASK = 0x0a, | |
50 | PORT_PRD_CTL = 0x0b, | |
51 | PORT_PRD_ADDR = 0x0c, | |
52 | PORT_PRD_XFERLEN = 0x10, | |
53 | ||
54 | /* IDMA register */ | |
55 | PORT_IDMA_CTL = 0x14, | |
56 | ||
57 | PORT_SCR = 0x20, | |
58 | ||
59 | /* HOST_CTL bits */ | |
60 | HCTL_IRQOFF = (1 << 8), /* global IRQ off */ | |
61 | HCTL_PWRDWN = (1 << 13), /* power down PHYs */ | |
62 | HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */ | |
63 | HCTL_RPGSEL = (1 << 15), /* register page select */ | |
64 | ||
65 | HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST | | |
66 | HCTL_RPGSEL, | |
67 | ||
68 | /* HOST_IRQ_(STAT|MASK) bits */ | |
69 | HIRQ_PORT0 = (1 << 0), | |
70 | HIRQ_PORT1 = (1 << 1), | |
71 | HIRQ_SOFT = (1 << 14), | |
72 | HIRQ_GLOBAL = (1 << 15), /* STAT only */ | |
73 | ||
74 | /* PORT_IRQ_(STAT|MASK) bits */ | |
75 | PIRQ_OFFLINE = (1 << 0), /* device unplugged */ | |
76 | PIRQ_ONLINE = (1 << 1), /* device plugged */ | |
77 | PIRQ_COMPLETE = (1 << 2), /* completion interrupt */ | |
78 | PIRQ_FATAL = (1 << 3), /* fatal error */ | |
79 | PIRQ_ATA = (1 << 4), /* ATA interrupt */ | |
80 | PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */ | |
81 | PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */ | |
82 | ||
83 | PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL, | |
84 | ||
85 | PIRQ_MASK_DMA_READ = PIRQ_REPLY | PIRQ_ATA, | |
86 | PIRQ_MASK_OTHER = PIRQ_REPLY | PIRQ_COMPLETE, | |
87 | PIRQ_MASK_FREEZE = 0xff, | |
88 | ||
89 | /* PORT_PRD_CTL bits */ | |
90 | PRD_CTL_START = (1 << 0), | |
91 | PRD_CTL_WR = (1 << 3), | |
92 | PRD_CTL_DMAEN = (1 << 7), /* DMA enable */ | |
93 | ||
94 | /* PORT_IDMA_CTL bits */ | |
95 | IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */ | |
96 | IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */ | |
97 | IDMA_CTL_GO = (1 << 7), /* IDMA mode go */ | |
98 | IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */ | |
99 | }; | |
100 | ||
101 | struct inic_host_priv { | |
36f674d9 | 102 | u16 cached_hctl; |
1fd7a697 TH |
103 | }; |
104 | ||
105 | struct inic_port_priv { | |
36f674d9 TH |
106 | u8 dfl_prdctl; |
107 | u8 cached_prdctl; | |
108 | u8 cached_pirq_mask; | |
1fd7a697 TH |
109 | }; |
110 | ||
1fd7a697 | 111 | static struct scsi_host_template inic_sht = { |
68d1d07b | 112 | ATA_BMDMA_SHT(DRV_NAME), |
1fd7a697 TH |
113 | }; |
114 | ||
115 | static const int scr_map[] = { | |
116 | [SCR_STATUS] = 0, | |
117 | [SCR_ERROR] = 1, | |
118 | [SCR_CONTROL] = 2, | |
119 | }; | |
120 | ||
5796d1c4 | 121 | static void __iomem *inic_port_base(struct ata_port *ap) |
1fd7a697 | 122 | { |
0d5ff566 | 123 | return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE; |
1fd7a697 TH |
124 | } |
125 | ||
126 | static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask) | |
127 | { | |
128 | void __iomem *port_base = inic_port_base(ap); | |
129 | struct inic_port_priv *pp = ap->private_data; | |
130 | ||
131 | writeb(mask, port_base + PORT_IRQ_MASK); | |
132 | pp->cached_pirq_mask = mask; | |
133 | } | |
134 | ||
135 | static void inic_set_pirq_mask(struct ata_port *ap, u8 mask) | |
136 | { | |
137 | struct inic_port_priv *pp = ap->private_data; | |
138 | ||
139 | if (pp->cached_pirq_mask != mask) | |
140 | __inic_set_pirq_mask(ap, mask); | |
141 | } | |
142 | ||
143 | static void inic_reset_port(void __iomem *port_base) | |
144 | { | |
145 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
146 | u16 ctl; | |
147 | ||
148 | ctl = readw(idma_ctl); | |
149 | ctl &= ~(IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN | IDMA_CTL_GO); | |
150 | ||
151 | /* mask IRQ and assert reset */ | |
152 | writew(ctl | IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN, idma_ctl); | |
153 | readw(idma_ctl); /* flush */ | |
154 | ||
155 | /* give it some time */ | |
156 | msleep(1); | |
157 | ||
158 | /* release reset */ | |
159 | writew(ctl | IDMA_CTL_ATA_NIEN, idma_ctl); | |
160 | ||
161 | /* clear irq */ | |
162 | writeb(0xff, port_base + PORT_IRQ_STAT); | |
163 | ||
164 | /* reenable ATA IRQ, turn off IDMA mode */ | |
165 | writew(ctl, idma_ctl); | |
166 | } | |
167 | ||
da3dbb17 | 168 | static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val) |
1fd7a697 | 169 | { |
59f99880 | 170 | void __iomem *scr_addr = ap->ioaddr.scr_addr; |
1fd7a697 | 171 | void __iomem *addr; |
1fd7a697 TH |
172 | |
173 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 174 | return -EINVAL; |
1fd7a697 TH |
175 | |
176 | addr = scr_addr + scr_map[sc_reg] * 4; | |
da3dbb17 | 177 | *val = readl(scr_addr + scr_map[sc_reg] * 4); |
1fd7a697 TH |
178 | |
179 | /* this controller has stuck DIAG.N, ignore it */ | |
180 | if (sc_reg == SCR_ERROR) | |
da3dbb17 TH |
181 | *val &= ~SERR_PHYRDY_CHG; |
182 | return 0; | |
1fd7a697 TH |
183 | } |
184 | ||
da3dbb17 | 185 | static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) |
1fd7a697 | 186 | { |
59f99880 | 187 | void __iomem *scr_addr = ap->ioaddr.scr_addr; |
1fd7a697 TH |
188 | |
189 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 190 | return -EINVAL; |
1fd7a697 | 191 | |
1fd7a697 | 192 | writel(val, scr_addr + scr_map[sc_reg] * 4); |
da3dbb17 | 193 | return 0; |
1fd7a697 TH |
194 | } |
195 | ||
196 | /* | |
197 | * In TF mode, inic162x is very similar to SFF device. TF registers | |
198 | * function the same. DMA engine behaves similary using the same PRD | |
199 | * format as BMDMA but different command register, interrupt and event | |
200 | * notification methods are used. The following inic_bmdma_*() | |
201 | * functions do the impedance matching. | |
202 | */ | |
203 | static void inic_bmdma_setup(struct ata_queued_cmd *qc) | |
204 | { | |
205 | struct ata_port *ap = qc->ap; | |
206 | struct inic_port_priv *pp = ap->private_data; | |
207 | void __iomem *port_base = inic_port_base(ap); | |
208 | int rw = qc->tf.flags & ATA_TFLAG_WRITE; | |
209 | ||
210 | /* make sure device sees PRD table writes */ | |
211 | wmb(); | |
212 | ||
213 | /* load transfer length */ | |
214 | writel(qc->nbytes, port_base + PORT_PRD_XFERLEN); | |
215 | ||
216 | /* turn on DMA and specify data direction */ | |
217 | pp->cached_prdctl = pp->dfl_prdctl | PRD_CTL_DMAEN; | |
218 | if (!rw) | |
219 | pp->cached_prdctl |= PRD_CTL_WR; | |
220 | writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL); | |
221 | ||
222 | /* issue r/w command */ | |
5682ed33 | 223 | ap->ops->sff_exec_command(ap, &qc->tf); |
1fd7a697 TH |
224 | } |
225 | ||
226 | static void inic_bmdma_start(struct ata_queued_cmd *qc) | |
227 | { | |
228 | struct ata_port *ap = qc->ap; | |
229 | struct inic_port_priv *pp = ap->private_data; | |
230 | void __iomem *port_base = inic_port_base(ap); | |
231 | ||
232 | /* start host DMA transaction */ | |
233 | pp->cached_prdctl |= PRD_CTL_START; | |
234 | writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL); | |
235 | } | |
236 | ||
237 | static void inic_bmdma_stop(struct ata_queued_cmd *qc) | |
238 | { | |
239 | struct ata_port *ap = qc->ap; | |
240 | struct inic_port_priv *pp = ap->private_data; | |
241 | void __iomem *port_base = inic_port_base(ap); | |
242 | ||
243 | /* stop DMA engine */ | |
244 | writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL); | |
245 | } | |
246 | ||
247 | static u8 inic_bmdma_status(struct ata_port *ap) | |
248 | { | |
249 | /* event is already verified by the interrupt handler */ | |
250 | return ATA_DMA_INTR; | |
251 | } | |
252 | ||
1fd7a697 TH |
253 | static void inic_host_intr(struct ata_port *ap) |
254 | { | |
255 | void __iomem *port_base = inic_port_base(ap); | |
9af5c9c9 | 256 | struct ata_eh_info *ehi = &ap->link.eh_info; |
1fd7a697 TH |
257 | u8 irq_stat; |
258 | ||
259 | /* fetch and clear irq */ | |
260 | irq_stat = readb(port_base + PORT_IRQ_STAT); | |
261 | writeb(irq_stat, port_base + PORT_IRQ_STAT); | |
262 | ||
263 | if (likely(!(irq_stat & PIRQ_ERR))) { | |
9af5c9c9 TH |
264 | struct ata_queued_cmd *qc = |
265 | ata_qc_from_tag(ap, ap->link.active_tag); | |
1fd7a697 TH |
266 | |
267 | if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { | |
5682ed33 | 268 | ap->ops->sff_check_status(ap); /* clear ATA interrupt */ |
1fd7a697 TH |
269 | return; |
270 | } | |
271 | ||
9363c382 | 272 | if (likely(ata_sff_host_intr(ap, qc))) |
1fd7a697 TH |
273 | return; |
274 | ||
5682ed33 | 275 | ap->ops->sff_check_status(ap); /* clear ATA interrupt */ |
1fd7a697 TH |
276 | ata_port_printk(ap, KERN_WARNING, "unhandled " |
277 | "interrupt, irq_stat=%x\n", irq_stat); | |
278 | return; | |
279 | } | |
280 | ||
281 | /* error */ | |
282 | ata_ehi_push_desc(ehi, "irq_stat=0x%x", irq_stat); | |
283 | ||
284 | if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) { | |
285 | ata_ehi_hotplugged(ehi); | |
286 | ata_port_freeze(ap); | |
287 | } else | |
288 | ata_port_abort(ap); | |
289 | } | |
290 | ||
291 | static irqreturn_t inic_interrupt(int irq, void *dev_instance) | |
292 | { | |
293 | struct ata_host *host = dev_instance; | |
0d5ff566 | 294 | void __iomem *mmio_base = host->iomap[MMIO_BAR]; |
1fd7a697 TH |
295 | u16 host_irq_stat; |
296 | int i, handled = 0;; | |
297 | ||
298 | host_irq_stat = readw(mmio_base + HOST_IRQ_STAT); | |
299 | ||
300 | if (unlikely(!(host_irq_stat & HIRQ_GLOBAL))) | |
301 | goto out; | |
302 | ||
303 | spin_lock(&host->lock); | |
304 | ||
305 | for (i = 0; i < NR_PORTS; i++) { | |
306 | struct ata_port *ap = host->ports[i]; | |
307 | ||
308 | if (!(host_irq_stat & (HIRQ_PORT0 << i))) | |
309 | continue; | |
310 | ||
311 | if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) { | |
312 | inic_host_intr(ap); | |
313 | handled++; | |
314 | } else { | |
315 | if (ata_ratelimit()) | |
316 | dev_printk(KERN_ERR, host->dev, "interrupt " | |
317 | "from disabled port %d (0x%x)\n", | |
318 | i, host_irq_stat); | |
319 | } | |
320 | } | |
321 | ||
322 | spin_unlock(&host->lock); | |
323 | ||
324 | out: | |
325 | return IRQ_RETVAL(handled); | |
326 | } | |
327 | ||
328 | static unsigned int inic_qc_issue(struct ata_queued_cmd *qc) | |
329 | { | |
330 | struct ata_port *ap = qc->ap; | |
331 | ||
332 | /* ATA IRQ doesn't wait for DMA transfer completion and vice | |
333 | * versa. Mask IRQ selectively to detect command completion. | |
334 | * Without it, ATA DMA read command can cause data corruption. | |
335 | * | |
336 | * Something similar might be needed for ATAPI writes. I | |
337 | * tried a lot of combinations but couldn't find the solution. | |
338 | */ | |
339 | if (qc->tf.protocol == ATA_PROT_DMA && | |
340 | !(qc->tf.flags & ATA_TFLAG_WRITE)) | |
341 | inic_set_pirq_mask(ap, PIRQ_MASK_DMA_READ); | |
342 | else | |
343 | inic_set_pirq_mask(ap, PIRQ_MASK_OTHER); | |
344 | ||
345 | /* Issuing a command to yet uninitialized port locks up the | |
346 | * controller. Most of the time, this happens for the first | |
347 | * command after reset which are ATA and ATAPI IDENTIFYs. | |
348 | * Fast fail if stat is 0x7f or 0xff for those commands. | |
349 | */ | |
350 | if (unlikely(qc->tf.command == ATA_CMD_ID_ATA || | |
351 | qc->tf.command == ATA_CMD_ID_ATAPI)) { | |
5682ed33 | 352 | u8 stat = ap->ops->sff_check_status(ap); |
1fd7a697 TH |
353 | if (stat == 0x7f || stat == 0xff) |
354 | return AC_ERR_HSM; | |
355 | } | |
356 | ||
9363c382 | 357 | return ata_sff_qc_issue(qc); |
1fd7a697 TH |
358 | } |
359 | ||
360 | static void inic_freeze(struct ata_port *ap) | |
361 | { | |
362 | void __iomem *port_base = inic_port_base(ap); | |
363 | ||
364 | __inic_set_pirq_mask(ap, PIRQ_MASK_FREEZE); | |
365 | ||
5682ed33 | 366 | ap->ops->sff_check_status(ap); |
1fd7a697 | 367 | writeb(0xff, port_base + PORT_IRQ_STAT); |
1fd7a697 TH |
368 | } |
369 | ||
370 | static void inic_thaw(struct ata_port *ap) | |
371 | { | |
372 | void __iomem *port_base = inic_port_base(ap); | |
373 | ||
5682ed33 | 374 | ap->ops->sff_check_status(ap); |
1fd7a697 TH |
375 | writeb(0xff, port_base + PORT_IRQ_STAT); |
376 | ||
377 | __inic_set_pirq_mask(ap, PIRQ_MASK_OTHER); | |
1fd7a697 TH |
378 | } |
379 | ||
380 | /* | |
381 | * SRST and SControl hardreset don't give valid signature on this | |
382 | * controller. Only controller specific hardreset mechanism works. | |
383 | */ | |
cc0680a5 | 384 | static int inic_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 385 | unsigned long deadline) |
1fd7a697 | 386 | { |
cc0680a5 | 387 | struct ata_port *ap = link->ap; |
1fd7a697 TH |
388 | void __iomem *port_base = inic_port_base(ap); |
389 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
cc0680a5 | 390 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
1fd7a697 TH |
391 | u16 val; |
392 | int rc; | |
393 | ||
394 | /* hammer it into sane state */ | |
395 | inic_reset_port(port_base); | |
396 | ||
1fd7a697 TH |
397 | val = readw(idma_ctl); |
398 | writew(val | IDMA_CTL_RST_ATA, idma_ctl); | |
399 | readw(idma_ctl); /* flush */ | |
400 | msleep(1); | |
401 | writew(val & ~IDMA_CTL_RST_ATA, idma_ctl); | |
402 | ||
cc0680a5 | 403 | rc = sata_link_resume(link, timing, deadline); |
1fd7a697 | 404 | if (rc) { |
cc0680a5 | 405 | ata_link_printk(link, KERN_WARNING, "failed to resume " |
fe334602 | 406 | "link after reset (errno=%d)\n", rc); |
1fd7a697 TH |
407 | return rc; |
408 | } | |
409 | ||
1fd7a697 | 410 | *class = ATA_DEV_NONE; |
cc0680a5 | 411 | if (ata_link_online(link)) { |
1fd7a697 TH |
412 | struct ata_taskfile tf; |
413 | ||
705e76be TH |
414 | /* wait for link to become ready */ |
415 | rc = ata_sff_wait_after_reset(link, 1, deadline); | |
9b89391c TH |
416 | /* link occupied, -ENODEV too is an error */ |
417 | if (rc) { | |
cc0680a5 | 418 | ata_link_printk(link, KERN_WARNING, "device not ready " |
d4b2bab4 TH |
419 | "after hardreset (errno=%d)\n", rc); |
420 | return rc; | |
1fd7a697 TH |
421 | } |
422 | ||
9363c382 | 423 | ata_sff_tf_read(ap, &tf); |
1fd7a697 | 424 | *class = ata_dev_classify(&tf); |
1fd7a697 TH |
425 | } |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | static void inic_error_handler(struct ata_port *ap) | |
431 | { | |
432 | void __iomem *port_base = inic_port_base(ap); | |
433 | struct inic_port_priv *pp = ap->private_data; | |
434 | unsigned long flags; | |
435 | ||
436 | /* reset PIO HSM and stop DMA engine */ | |
437 | inic_reset_port(port_base); | |
438 | ||
439 | spin_lock_irqsave(ap->lock, flags); | |
440 | ap->hsm_task_state = HSM_ST_IDLE; | |
441 | writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL); | |
442 | spin_unlock_irqrestore(ap->lock, flags); | |
443 | ||
444 | /* PIO and DMA engines have been stopped, perform recovery */ | |
a1efdaba | 445 | ata_std_error_handler(ap); |
1fd7a697 TH |
446 | } |
447 | ||
448 | static void inic_post_internal_cmd(struct ata_queued_cmd *qc) | |
449 | { | |
450 | /* make DMA engine forget about the failed command */ | |
a51d644a | 451 | if (qc->flags & ATA_QCFLAG_FAILED) |
1fd7a697 TH |
452 | inic_reset_port(inic_port_base(qc->ap)); |
453 | } | |
454 | ||
cd0d3bbc | 455 | static void inic_dev_config(struct ata_device *dev) |
1fd7a697 TH |
456 | { |
457 | /* inic can only handle upto LBA28 max sectors */ | |
458 | if (dev->max_sectors > ATA_MAX_SECTORS) | |
459 | dev->max_sectors = ATA_MAX_SECTORS; | |
90c93785 TH |
460 | |
461 | if (dev->n_sectors >= 1 << 28) { | |
462 | ata_dev_printk(dev, KERN_ERR, | |
463 | "ERROR: This driver doesn't support LBA48 yet and may cause\n" | |
464 | " data corruption on such devices. Disabling.\n"); | |
465 | ata_dev_disable(dev); | |
466 | } | |
1fd7a697 TH |
467 | } |
468 | ||
469 | static void init_port(struct ata_port *ap) | |
470 | { | |
471 | void __iomem *port_base = inic_port_base(ap); | |
472 | ||
473 | /* Setup PRD address */ | |
474 | writel(ap->prd_dma, port_base + PORT_PRD_ADDR); | |
475 | } | |
476 | ||
477 | static int inic_port_resume(struct ata_port *ap) | |
478 | { | |
479 | init_port(ap); | |
480 | return 0; | |
481 | } | |
482 | ||
483 | static int inic_port_start(struct ata_port *ap) | |
484 | { | |
485 | void __iomem *port_base = inic_port_base(ap); | |
486 | struct inic_port_priv *pp; | |
487 | u8 tmp; | |
488 | int rc; | |
489 | ||
490 | /* alloc and initialize private data */ | |
24dc5f33 | 491 | pp = devm_kzalloc(ap->host->dev, sizeof(*pp), GFP_KERNEL); |
1fd7a697 TH |
492 | if (!pp) |
493 | return -ENOMEM; | |
494 | ap->private_data = pp; | |
495 | ||
496 | /* default PRD_CTL value, DMAEN, WR and START off */ | |
497 | tmp = readb(port_base + PORT_PRD_CTL); | |
498 | tmp &= ~(PRD_CTL_DMAEN | PRD_CTL_WR | PRD_CTL_START); | |
499 | pp->dfl_prdctl = tmp; | |
500 | ||
501 | /* Alloc resources */ | |
502 | rc = ata_port_start(ap); | |
36f674d9 | 503 | if (rc) |
1fd7a697 | 504 | return rc; |
1fd7a697 TH |
505 | |
506 | init_port(ap); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
1fd7a697 | 511 | static struct ata_port_operations inic_port_ops = { |
029cfd6b | 512 | .inherits = &ata_sff_port_ops, |
1fd7a697 TH |
513 | |
514 | .bmdma_setup = inic_bmdma_setup, | |
515 | .bmdma_start = inic_bmdma_start, | |
516 | .bmdma_stop = inic_bmdma_stop, | |
517 | .bmdma_status = inic_bmdma_status, | |
1fd7a697 | 518 | .qc_issue = inic_qc_issue, |
1fd7a697 TH |
519 | |
520 | .freeze = inic_freeze, | |
521 | .thaw = inic_thaw, | |
a1efdaba TH |
522 | .softreset = ATA_OP_NULL, /* softreset is broken */ |
523 | .hardreset = inic_hardreset, | |
1fd7a697 TH |
524 | .error_handler = inic_error_handler, |
525 | .post_internal_cmd = inic_post_internal_cmd, | |
526 | .dev_config = inic_dev_config, | |
527 | ||
029cfd6b TH |
528 | .scr_read = inic_scr_read, |
529 | .scr_write = inic_scr_write, | |
1fd7a697 | 530 | |
029cfd6b | 531 | .port_resume = inic_port_resume, |
1fd7a697 | 532 | .port_start = inic_port_start, |
1fd7a697 TH |
533 | }; |
534 | ||
535 | static struct ata_port_info inic_port_info = { | |
0dc36888 | 536 | /* For some reason, ATAPI_PROT_PIO is broken on this |
1fd7a697 TH |
537 | * controller, and no, PIO_POLLING does't fix it. It somehow |
538 | * manages to report the wrong ireason and ignoring ireason | |
539 | * results in machine lock up. Tell libata to always prefer | |
540 | * DMA. | |
541 | */ | |
542 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, | |
543 | .pio_mask = 0x1f, /* pio0-4 */ | |
544 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 545 | .udma_mask = ATA_UDMA6, |
1fd7a697 TH |
546 | .port_ops = &inic_port_ops |
547 | }; | |
548 | ||
549 | static int init_controller(void __iomem *mmio_base, u16 hctl) | |
550 | { | |
551 | int i; | |
552 | u16 val; | |
553 | ||
554 | hctl &= ~HCTL_KNOWN_BITS; | |
555 | ||
556 | /* Soft reset whole controller. Spec says reset duration is 3 | |
557 | * PCI clocks, be generous and give it 10ms. | |
558 | */ | |
559 | writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); | |
560 | readw(mmio_base + HOST_CTL); /* flush */ | |
561 | ||
562 | for (i = 0; i < 10; i++) { | |
563 | msleep(1); | |
564 | val = readw(mmio_base + HOST_CTL); | |
565 | if (!(val & HCTL_SOFTRST)) | |
566 | break; | |
567 | } | |
568 | ||
569 | if (val & HCTL_SOFTRST) | |
570 | return -EIO; | |
571 | ||
572 | /* mask all interrupts and reset ports */ | |
573 | for (i = 0; i < NR_PORTS; i++) { | |
574 | void __iomem *port_base = mmio_base + i * PORT_SIZE; | |
575 | ||
576 | writeb(0xff, port_base + PORT_IRQ_MASK); | |
577 | inic_reset_port(port_base); | |
578 | } | |
579 | ||
580 | /* port IRQ is masked now, unmask global IRQ */ | |
581 | writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); | |
582 | val = readw(mmio_base + HOST_IRQ_MASK); | |
583 | val &= ~(HIRQ_PORT0 | HIRQ_PORT1); | |
584 | writew(val, mmio_base + HOST_IRQ_MASK); | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
438ac6d5 | 589 | #ifdef CONFIG_PM |
1fd7a697 TH |
590 | static int inic_pci_device_resume(struct pci_dev *pdev) |
591 | { | |
592 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
593 | struct inic_host_priv *hpriv = host->private_data; | |
0d5ff566 | 594 | void __iomem *mmio_base = host->iomap[MMIO_BAR]; |
1fd7a697 TH |
595 | int rc; |
596 | ||
5aea408d DM |
597 | rc = ata_pci_device_do_resume(pdev); |
598 | if (rc) | |
599 | return rc; | |
1fd7a697 TH |
600 | |
601 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
1fd7a697 TH |
602 | rc = init_controller(mmio_base, hpriv->cached_hctl); |
603 | if (rc) | |
604 | return rc; | |
605 | } | |
606 | ||
607 | ata_host_resume(host); | |
608 | ||
609 | return 0; | |
610 | } | |
438ac6d5 | 611 | #endif |
1fd7a697 TH |
612 | |
613 | static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
614 | { | |
615 | static int printed_version; | |
4447d351 TH |
616 | const struct ata_port_info *ppi[] = { &inic_port_info, NULL }; |
617 | struct ata_host *host; | |
1fd7a697 | 618 | struct inic_host_priv *hpriv; |
0d5ff566 | 619 | void __iomem * const *iomap; |
1fd7a697 TH |
620 | int i, rc; |
621 | ||
622 | if (!printed_version++) | |
623 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
624 | ||
4447d351 TH |
625 | /* alloc host */ |
626 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS); | |
627 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
628 | if (!host || !hpriv) | |
629 | return -ENOMEM; | |
630 | ||
631 | host->private_data = hpriv; | |
632 | ||
633 | /* acquire resources and fill host */ | |
24dc5f33 | 634 | rc = pcim_enable_device(pdev); |
1fd7a697 TH |
635 | if (rc) |
636 | return rc; | |
637 | ||
0d5ff566 TH |
638 | rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME); |
639 | if (rc) | |
640 | return rc; | |
4447d351 TH |
641 | host->iomap = iomap = pcim_iomap_table(pdev); |
642 | ||
643 | for (i = 0; i < NR_PORTS; i++) { | |
cbcdd875 TH |
644 | struct ata_port *ap = host->ports[i]; |
645 | struct ata_ioports *port = &ap->ioaddr; | |
646 | unsigned int offset = i * PORT_SIZE; | |
4447d351 TH |
647 | |
648 | port->cmd_addr = iomap[2 * i]; | |
649 | port->altstatus_addr = | |
650 | port->ctl_addr = (void __iomem *) | |
651 | ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS); | |
cbcdd875 | 652 | port->scr_addr = iomap[MMIO_BAR] + offset + PORT_SCR; |
4447d351 | 653 | |
9363c382 | 654 | ata_sff_std_ports(port); |
cbcdd875 TH |
655 | |
656 | ata_port_pbar_desc(ap, MMIO_BAR, -1, "mmio"); | |
657 | ata_port_pbar_desc(ap, MMIO_BAR, offset, "port"); | |
658 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", | |
659 | (unsigned long long)pci_resource_start(pdev, 2 * i), | |
660 | (unsigned long long)pci_resource_start(pdev, (2 * i + 1)) | | |
661 | ATA_PCI_CTL_OFS); | |
4447d351 TH |
662 | } |
663 | ||
664 | hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL); | |
1fd7a697 TH |
665 | |
666 | /* Set dma_mask. This devices doesn't support 64bit addressing. */ | |
667 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
668 | if (rc) { | |
669 | dev_printk(KERN_ERR, &pdev->dev, | |
670 | "32-bit DMA enable failed\n"); | |
24dc5f33 | 671 | return rc; |
1fd7a697 TH |
672 | } |
673 | ||
674 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
675 | if (rc) { | |
676 | dev_printk(KERN_ERR, &pdev->dev, | |
677 | "32-bit consistent DMA enable failed\n"); | |
24dc5f33 | 678 | return rc; |
1fd7a697 TH |
679 | } |
680 | ||
b7d8629f FT |
681 | /* |
682 | * This controller is braindamaged. dma_boundary is 0xffff | |
683 | * like others but it will lock up the whole machine HARD if | |
684 | * 65536 byte PRD entry is fed. Reduce maximum segment size. | |
685 | */ | |
686 | rc = pci_set_dma_max_seg_size(pdev, 65536 - 512); | |
687 | if (rc) { | |
688 | dev_printk(KERN_ERR, &pdev->dev, | |
689 | "failed to set the maximum segment size.\n"); | |
690 | return rc; | |
691 | } | |
692 | ||
0d5ff566 | 693 | rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl); |
1fd7a697 TH |
694 | if (rc) { |
695 | dev_printk(KERN_ERR, &pdev->dev, | |
696 | "failed to initialize controller\n"); | |
24dc5f33 | 697 | return rc; |
1fd7a697 TH |
698 | } |
699 | ||
700 | pci_set_master(pdev); | |
4447d351 TH |
701 | return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED, |
702 | &inic_sht); | |
1fd7a697 TH |
703 | } |
704 | ||
705 | static const struct pci_device_id inic_pci_tbl[] = { | |
706 | { PCI_VDEVICE(INIT, 0x1622), }, | |
707 | { }, | |
708 | }; | |
709 | ||
710 | static struct pci_driver inic_pci_driver = { | |
711 | .name = DRV_NAME, | |
712 | .id_table = inic_pci_tbl, | |
438ac6d5 | 713 | #ifdef CONFIG_PM |
1fd7a697 TH |
714 | .suspend = ata_pci_device_suspend, |
715 | .resume = inic_pci_device_resume, | |
438ac6d5 | 716 | #endif |
1fd7a697 TH |
717 | .probe = inic_init_one, |
718 | .remove = ata_pci_remove_one, | |
719 | }; | |
720 | ||
721 | static int __init inic_init(void) | |
722 | { | |
723 | return pci_register_driver(&inic_pci_driver); | |
724 | } | |
725 | ||
726 | static void __exit inic_exit(void) | |
727 | { | |
728 | pci_unregister_driver(&inic_pci_driver); | |
729 | } | |
730 | ||
731 | MODULE_AUTHOR("Tejun Heo"); | |
732 | MODULE_DESCRIPTION("low-level driver for Initio 162x SATA"); | |
733 | MODULE_LICENSE("GPL v2"); | |
734 | MODULE_DEVICE_TABLE(pci, inic_pci_tbl); | |
735 | MODULE_VERSION(DRV_VERSION); | |
736 | ||
737 | module_init(inic_init); | |
738 | module_exit(inic_exit); |