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1fd7a697 TH |
1 | /* |
2 | * sata_inic162x.c - Driver for Initio 162x SATA controllers | |
3 | * | |
4 | * Copyright 2006 SUSE Linux Products GmbH | |
5 | * Copyright 2006 Tejun Heo <teheo@novell.com> | |
6 | * | |
7 | * This file is released under GPL v2. | |
8 | * | |
9 | * This controller is eccentric and easily locks up if something isn't | |
10 | * right. Documentation is available at initio's website but it only | |
11 | * documents registers (not programming model). | |
12 | * | |
13 | * - ATA disks work. | |
14 | * - Hotplug works. | |
15 | * - ATAPI read works but burning doesn't. This thing is really | |
16 | * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and | |
17 | * ATAPI DMA WRITE should be programmed. If you've got a clue, be | |
18 | * my guest. | |
19 | * - Both STR and STD work. | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/pci.h> | |
25 | #include <scsi/scsi_host.h> | |
26 | #include <linux/libata.h> | |
27 | #include <linux/blkdev.h> | |
28 | #include <scsi/scsi_device.h> | |
29 | ||
30 | #define DRV_NAME "sata_inic162x" | |
2a3103ce | 31 | #define DRV_VERSION "0.3" |
1fd7a697 TH |
32 | |
33 | enum { | |
34 | MMIO_BAR = 5, | |
35 | ||
36 | NR_PORTS = 2, | |
37 | ||
38 | HOST_CTL = 0x7c, | |
39 | HOST_STAT = 0x7e, | |
40 | HOST_IRQ_STAT = 0xbc, | |
41 | HOST_IRQ_MASK = 0xbe, | |
42 | ||
43 | PORT_SIZE = 0x40, | |
44 | ||
45 | /* registers for ATA TF operation */ | |
46 | PORT_TF = 0x00, | |
47 | PORT_ALT_STAT = 0x08, | |
48 | PORT_IRQ_STAT = 0x09, | |
49 | PORT_IRQ_MASK = 0x0a, | |
50 | PORT_PRD_CTL = 0x0b, | |
51 | PORT_PRD_ADDR = 0x0c, | |
52 | PORT_PRD_XFERLEN = 0x10, | |
53 | ||
54 | /* IDMA register */ | |
55 | PORT_IDMA_CTL = 0x14, | |
56 | ||
57 | PORT_SCR = 0x20, | |
58 | ||
59 | /* HOST_CTL bits */ | |
60 | HCTL_IRQOFF = (1 << 8), /* global IRQ off */ | |
61 | HCTL_PWRDWN = (1 << 13), /* power down PHYs */ | |
62 | HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */ | |
63 | HCTL_RPGSEL = (1 << 15), /* register page select */ | |
64 | ||
65 | HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST | | |
66 | HCTL_RPGSEL, | |
67 | ||
68 | /* HOST_IRQ_(STAT|MASK) bits */ | |
69 | HIRQ_PORT0 = (1 << 0), | |
70 | HIRQ_PORT1 = (1 << 1), | |
71 | HIRQ_SOFT = (1 << 14), | |
72 | HIRQ_GLOBAL = (1 << 15), /* STAT only */ | |
73 | ||
74 | /* PORT_IRQ_(STAT|MASK) bits */ | |
75 | PIRQ_OFFLINE = (1 << 0), /* device unplugged */ | |
76 | PIRQ_ONLINE = (1 << 1), /* device plugged */ | |
77 | PIRQ_COMPLETE = (1 << 2), /* completion interrupt */ | |
78 | PIRQ_FATAL = (1 << 3), /* fatal error */ | |
79 | PIRQ_ATA = (1 << 4), /* ATA interrupt */ | |
80 | PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */ | |
81 | PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */ | |
82 | ||
83 | PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL, | |
84 | ||
85 | PIRQ_MASK_DMA_READ = PIRQ_REPLY | PIRQ_ATA, | |
86 | PIRQ_MASK_OTHER = PIRQ_REPLY | PIRQ_COMPLETE, | |
87 | PIRQ_MASK_FREEZE = 0xff, | |
88 | ||
89 | /* PORT_PRD_CTL bits */ | |
90 | PRD_CTL_START = (1 << 0), | |
91 | PRD_CTL_WR = (1 << 3), | |
92 | PRD_CTL_DMAEN = (1 << 7), /* DMA enable */ | |
93 | ||
94 | /* PORT_IDMA_CTL bits */ | |
95 | IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */ | |
96 | IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */ | |
97 | IDMA_CTL_GO = (1 << 7), /* IDMA mode go */ | |
98 | IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */ | |
99 | }; | |
100 | ||
101 | struct inic_host_priv { | |
102 | u16 cached_hctl; | |
103 | }; | |
104 | ||
105 | struct inic_port_priv { | |
106 | u8 dfl_prdctl; | |
107 | u8 cached_prdctl; | |
108 | u8 cached_pirq_mask; | |
109 | }; | |
110 | ||
1fd7a697 | 111 | static struct scsi_host_template inic_sht = { |
68d1d07b | 112 | ATA_BMDMA_SHT(DRV_NAME), |
1fd7a697 TH |
113 | }; |
114 | ||
115 | static const int scr_map[] = { | |
116 | [SCR_STATUS] = 0, | |
117 | [SCR_ERROR] = 1, | |
118 | [SCR_CONTROL] = 2, | |
119 | }; | |
120 | ||
5796d1c4 | 121 | static void __iomem *inic_port_base(struct ata_port *ap) |
1fd7a697 | 122 | { |
0d5ff566 | 123 | return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE; |
1fd7a697 TH |
124 | } |
125 | ||
126 | static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask) | |
127 | { | |
128 | void __iomem *port_base = inic_port_base(ap); | |
129 | struct inic_port_priv *pp = ap->private_data; | |
130 | ||
131 | writeb(mask, port_base + PORT_IRQ_MASK); | |
132 | pp->cached_pirq_mask = mask; | |
133 | } | |
134 | ||
135 | static void inic_set_pirq_mask(struct ata_port *ap, u8 mask) | |
136 | { | |
137 | struct inic_port_priv *pp = ap->private_data; | |
138 | ||
139 | if (pp->cached_pirq_mask != mask) | |
140 | __inic_set_pirq_mask(ap, mask); | |
141 | } | |
142 | ||
143 | static void inic_reset_port(void __iomem *port_base) | |
144 | { | |
145 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
146 | u16 ctl; | |
147 | ||
148 | ctl = readw(idma_ctl); | |
149 | ctl &= ~(IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN | IDMA_CTL_GO); | |
150 | ||
151 | /* mask IRQ and assert reset */ | |
152 | writew(ctl | IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN, idma_ctl); | |
153 | readw(idma_ctl); /* flush */ | |
154 | ||
155 | /* give it some time */ | |
156 | msleep(1); | |
157 | ||
158 | /* release reset */ | |
159 | writew(ctl | IDMA_CTL_ATA_NIEN, idma_ctl); | |
160 | ||
161 | /* clear irq */ | |
162 | writeb(0xff, port_base + PORT_IRQ_STAT); | |
163 | ||
164 | /* reenable ATA IRQ, turn off IDMA mode */ | |
165 | writew(ctl, idma_ctl); | |
166 | } | |
167 | ||
da3dbb17 | 168 | static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val) |
1fd7a697 | 169 | { |
59f99880 | 170 | void __iomem *scr_addr = ap->ioaddr.scr_addr; |
1fd7a697 | 171 | void __iomem *addr; |
1fd7a697 TH |
172 | |
173 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 174 | return -EINVAL; |
1fd7a697 TH |
175 | |
176 | addr = scr_addr + scr_map[sc_reg] * 4; | |
da3dbb17 | 177 | *val = readl(scr_addr + scr_map[sc_reg] * 4); |
1fd7a697 TH |
178 | |
179 | /* this controller has stuck DIAG.N, ignore it */ | |
180 | if (sc_reg == SCR_ERROR) | |
da3dbb17 TH |
181 | *val &= ~SERR_PHYRDY_CHG; |
182 | return 0; | |
1fd7a697 TH |
183 | } |
184 | ||
da3dbb17 | 185 | static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) |
1fd7a697 | 186 | { |
59f99880 | 187 | void __iomem *scr_addr = ap->ioaddr.scr_addr; |
1fd7a697 TH |
188 | void __iomem *addr; |
189 | ||
190 | if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) | |
da3dbb17 | 191 | return -EINVAL; |
1fd7a697 TH |
192 | |
193 | addr = scr_addr + scr_map[sc_reg] * 4; | |
194 | writel(val, scr_addr + scr_map[sc_reg] * 4); | |
da3dbb17 | 195 | return 0; |
1fd7a697 TH |
196 | } |
197 | ||
198 | /* | |
199 | * In TF mode, inic162x is very similar to SFF device. TF registers | |
200 | * function the same. DMA engine behaves similary using the same PRD | |
201 | * format as BMDMA but different command register, interrupt and event | |
202 | * notification methods are used. The following inic_bmdma_*() | |
203 | * functions do the impedance matching. | |
204 | */ | |
205 | static void inic_bmdma_setup(struct ata_queued_cmd *qc) | |
206 | { | |
207 | struct ata_port *ap = qc->ap; | |
208 | struct inic_port_priv *pp = ap->private_data; | |
209 | void __iomem *port_base = inic_port_base(ap); | |
210 | int rw = qc->tf.flags & ATA_TFLAG_WRITE; | |
211 | ||
212 | /* make sure device sees PRD table writes */ | |
213 | wmb(); | |
214 | ||
215 | /* load transfer length */ | |
216 | writel(qc->nbytes, port_base + PORT_PRD_XFERLEN); | |
217 | ||
218 | /* turn on DMA and specify data direction */ | |
219 | pp->cached_prdctl = pp->dfl_prdctl | PRD_CTL_DMAEN; | |
220 | if (!rw) | |
221 | pp->cached_prdctl |= PRD_CTL_WR; | |
222 | writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL); | |
223 | ||
224 | /* issue r/w command */ | |
225 | ap->ops->exec_command(ap, &qc->tf); | |
226 | } | |
227 | ||
228 | static void inic_bmdma_start(struct ata_queued_cmd *qc) | |
229 | { | |
230 | struct ata_port *ap = qc->ap; | |
231 | struct inic_port_priv *pp = ap->private_data; | |
232 | void __iomem *port_base = inic_port_base(ap); | |
233 | ||
234 | /* start host DMA transaction */ | |
235 | pp->cached_prdctl |= PRD_CTL_START; | |
236 | writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL); | |
237 | } | |
238 | ||
239 | static void inic_bmdma_stop(struct ata_queued_cmd *qc) | |
240 | { | |
241 | struct ata_port *ap = qc->ap; | |
242 | struct inic_port_priv *pp = ap->private_data; | |
243 | void __iomem *port_base = inic_port_base(ap); | |
244 | ||
245 | /* stop DMA engine */ | |
246 | writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL); | |
247 | } | |
248 | ||
249 | static u8 inic_bmdma_status(struct ata_port *ap) | |
250 | { | |
251 | /* event is already verified by the interrupt handler */ | |
252 | return ATA_DMA_INTR; | |
253 | } | |
254 | ||
1fd7a697 TH |
255 | static void inic_host_intr(struct ata_port *ap) |
256 | { | |
257 | void __iomem *port_base = inic_port_base(ap); | |
9af5c9c9 | 258 | struct ata_eh_info *ehi = &ap->link.eh_info; |
1fd7a697 TH |
259 | u8 irq_stat; |
260 | ||
261 | /* fetch and clear irq */ | |
262 | irq_stat = readb(port_base + PORT_IRQ_STAT); | |
263 | writeb(irq_stat, port_base + PORT_IRQ_STAT); | |
264 | ||
265 | if (likely(!(irq_stat & PIRQ_ERR))) { | |
9af5c9c9 TH |
266 | struct ata_queued_cmd *qc = |
267 | ata_qc_from_tag(ap, ap->link.active_tag); | |
1fd7a697 TH |
268 | |
269 | if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { | |
270 | ata_chk_status(ap); /* clear ATA interrupt */ | |
271 | return; | |
272 | } | |
273 | ||
274 | if (likely(ata_host_intr(ap, qc))) | |
275 | return; | |
276 | ||
277 | ata_chk_status(ap); /* clear ATA interrupt */ | |
278 | ata_port_printk(ap, KERN_WARNING, "unhandled " | |
279 | "interrupt, irq_stat=%x\n", irq_stat); | |
280 | return; | |
281 | } | |
282 | ||
283 | /* error */ | |
284 | ata_ehi_push_desc(ehi, "irq_stat=0x%x", irq_stat); | |
285 | ||
286 | if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) { | |
287 | ata_ehi_hotplugged(ehi); | |
288 | ata_port_freeze(ap); | |
289 | } else | |
290 | ata_port_abort(ap); | |
291 | } | |
292 | ||
293 | static irqreturn_t inic_interrupt(int irq, void *dev_instance) | |
294 | { | |
295 | struct ata_host *host = dev_instance; | |
0d5ff566 | 296 | void __iomem *mmio_base = host->iomap[MMIO_BAR]; |
1fd7a697 TH |
297 | u16 host_irq_stat; |
298 | int i, handled = 0;; | |
299 | ||
300 | host_irq_stat = readw(mmio_base + HOST_IRQ_STAT); | |
301 | ||
302 | if (unlikely(!(host_irq_stat & HIRQ_GLOBAL))) | |
303 | goto out; | |
304 | ||
305 | spin_lock(&host->lock); | |
306 | ||
307 | for (i = 0; i < NR_PORTS; i++) { | |
308 | struct ata_port *ap = host->ports[i]; | |
309 | ||
310 | if (!(host_irq_stat & (HIRQ_PORT0 << i))) | |
311 | continue; | |
312 | ||
313 | if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) { | |
314 | inic_host_intr(ap); | |
315 | handled++; | |
316 | } else { | |
317 | if (ata_ratelimit()) | |
318 | dev_printk(KERN_ERR, host->dev, "interrupt " | |
319 | "from disabled port %d (0x%x)\n", | |
320 | i, host_irq_stat); | |
321 | } | |
322 | } | |
323 | ||
324 | spin_unlock(&host->lock); | |
325 | ||
326 | out: | |
327 | return IRQ_RETVAL(handled); | |
328 | } | |
329 | ||
330 | static unsigned int inic_qc_issue(struct ata_queued_cmd *qc) | |
331 | { | |
332 | struct ata_port *ap = qc->ap; | |
333 | ||
334 | /* ATA IRQ doesn't wait for DMA transfer completion and vice | |
335 | * versa. Mask IRQ selectively to detect command completion. | |
336 | * Without it, ATA DMA read command can cause data corruption. | |
337 | * | |
338 | * Something similar might be needed for ATAPI writes. I | |
339 | * tried a lot of combinations but couldn't find the solution. | |
340 | */ | |
341 | if (qc->tf.protocol == ATA_PROT_DMA && | |
342 | !(qc->tf.flags & ATA_TFLAG_WRITE)) | |
343 | inic_set_pirq_mask(ap, PIRQ_MASK_DMA_READ); | |
344 | else | |
345 | inic_set_pirq_mask(ap, PIRQ_MASK_OTHER); | |
346 | ||
347 | /* Issuing a command to yet uninitialized port locks up the | |
348 | * controller. Most of the time, this happens for the first | |
349 | * command after reset which are ATA and ATAPI IDENTIFYs. | |
350 | * Fast fail if stat is 0x7f or 0xff for those commands. | |
351 | */ | |
352 | if (unlikely(qc->tf.command == ATA_CMD_ID_ATA || | |
353 | qc->tf.command == ATA_CMD_ID_ATAPI)) { | |
354 | u8 stat = ata_chk_status(ap); | |
355 | if (stat == 0x7f || stat == 0xff) | |
356 | return AC_ERR_HSM; | |
357 | } | |
358 | ||
359 | return ata_qc_issue_prot(qc); | |
360 | } | |
361 | ||
362 | static void inic_freeze(struct ata_port *ap) | |
363 | { | |
364 | void __iomem *port_base = inic_port_base(ap); | |
365 | ||
366 | __inic_set_pirq_mask(ap, PIRQ_MASK_FREEZE); | |
367 | ||
368 | ata_chk_status(ap); | |
369 | writeb(0xff, port_base + PORT_IRQ_STAT); | |
370 | ||
371 | readb(port_base + PORT_IRQ_STAT); /* flush */ | |
372 | } | |
373 | ||
374 | static void inic_thaw(struct ata_port *ap) | |
375 | { | |
376 | void __iomem *port_base = inic_port_base(ap); | |
377 | ||
378 | ata_chk_status(ap); | |
379 | writeb(0xff, port_base + PORT_IRQ_STAT); | |
380 | ||
381 | __inic_set_pirq_mask(ap, PIRQ_MASK_OTHER); | |
382 | ||
383 | readb(port_base + PORT_IRQ_STAT); /* flush */ | |
384 | } | |
385 | ||
386 | /* | |
387 | * SRST and SControl hardreset don't give valid signature on this | |
388 | * controller. Only controller specific hardreset mechanism works. | |
389 | */ | |
cc0680a5 | 390 | static int inic_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 391 | unsigned long deadline) |
1fd7a697 | 392 | { |
cc0680a5 | 393 | struct ata_port *ap = link->ap; |
1fd7a697 TH |
394 | void __iomem *port_base = inic_port_base(ap); |
395 | void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; | |
cc0680a5 | 396 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); |
1fd7a697 TH |
397 | u16 val; |
398 | int rc; | |
399 | ||
400 | /* hammer it into sane state */ | |
401 | inic_reset_port(port_base); | |
402 | ||
1fd7a697 TH |
403 | val = readw(idma_ctl); |
404 | writew(val | IDMA_CTL_RST_ATA, idma_ctl); | |
405 | readw(idma_ctl); /* flush */ | |
406 | msleep(1); | |
407 | writew(val & ~IDMA_CTL_RST_ATA, idma_ctl); | |
408 | ||
cc0680a5 | 409 | rc = sata_link_resume(link, timing, deadline); |
1fd7a697 | 410 | if (rc) { |
cc0680a5 | 411 | ata_link_printk(link, KERN_WARNING, "failed to resume " |
fe334602 | 412 | "link after reset (errno=%d)\n", rc); |
1fd7a697 TH |
413 | return rc; |
414 | } | |
415 | ||
1fd7a697 | 416 | *class = ATA_DEV_NONE; |
cc0680a5 | 417 | if (ata_link_online(link)) { |
1fd7a697 TH |
418 | struct ata_taskfile tf; |
419 | ||
fe334602 | 420 | /* wait a while before checking status */ |
88ff6eaf | 421 | ata_wait_after_reset(ap, deadline); |
fe334602 | 422 | |
d4b2bab4 | 423 | rc = ata_wait_ready(ap, deadline); |
9b89391c TH |
424 | /* link occupied, -ENODEV too is an error */ |
425 | if (rc) { | |
cc0680a5 | 426 | ata_link_printk(link, KERN_WARNING, "device not ready " |
d4b2bab4 TH |
427 | "after hardreset (errno=%d)\n", rc); |
428 | return rc; | |
1fd7a697 TH |
429 | } |
430 | ||
431 | ata_tf_read(ap, &tf); | |
432 | *class = ata_dev_classify(&tf); | |
433 | if (*class == ATA_DEV_UNKNOWN) | |
434 | *class = ATA_DEV_NONE; | |
435 | } | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
440 | static void inic_error_handler(struct ata_port *ap) | |
441 | { | |
442 | void __iomem *port_base = inic_port_base(ap); | |
443 | struct inic_port_priv *pp = ap->private_data; | |
444 | unsigned long flags; | |
445 | ||
446 | /* reset PIO HSM and stop DMA engine */ | |
447 | inic_reset_port(port_base); | |
448 | ||
449 | spin_lock_irqsave(ap->lock, flags); | |
450 | ap->hsm_task_state = HSM_ST_IDLE; | |
451 | writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL); | |
452 | spin_unlock_irqrestore(ap->lock, flags); | |
453 | ||
454 | /* PIO and DMA engines have been stopped, perform recovery */ | |
455 | ata_do_eh(ap, ata_std_prereset, NULL, inic_hardreset, | |
456 | ata_std_postreset); | |
457 | } | |
458 | ||
459 | static void inic_post_internal_cmd(struct ata_queued_cmd *qc) | |
460 | { | |
461 | /* make DMA engine forget about the failed command */ | |
a51d644a | 462 | if (qc->flags & ATA_QCFLAG_FAILED) |
1fd7a697 TH |
463 | inic_reset_port(inic_port_base(qc->ap)); |
464 | } | |
465 | ||
cd0d3bbc | 466 | static void inic_dev_config(struct ata_device *dev) |
1fd7a697 TH |
467 | { |
468 | /* inic can only handle upto LBA28 max sectors */ | |
469 | if (dev->max_sectors > ATA_MAX_SECTORS) | |
470 | dev->max_sectors = ATA_MAX_SECTORS; | |
90c93785 TH |
471 | |
472 | if (dev->n_sectors >= 1 << 28) { | |
473 | ata_dev_printk(dev, KERN_ERR, | |
474 | "ERROR: This driver doesn't support LBA48 yet and may cause\n" | |
475 | " data corruption on such devices. Disabling.\n"); | |
476 | ata_dev_disable(dev); | |
477 | } | |
1fd7a697 TH |
478 | } |
479 | ||
480 | static void init_port(struct ata_port *ap) | |
481 | { | |
482 | void __iomem *port_base = inic_port_base(ap); | |
483 | ||
484 | /* Setup PRD address */ | |
485 | writel(ap->prd_dma, port_base + PORT_PRD_ADDR); | |
486 | } | |
487 | ||
488 | static int inic_port_resume(struct ata_port *ap) | |
489 | { | |
490 | init_port(ap); | |
491 | return 0; | |
492 | } | |
493 | ||
494 | static int inic_port_start(struct ata_port *ap) | |
495 | { | |
496 | void __iomem *port_base = inic_port_base(ap); | |
497 | struct inic_port_priv *pp; | |
498 | u8 tmp; | |
499 | int rc; | |
500 | ||
501 | /* alloc and initialize private data */ | |
24dc5f33 | 502 | pp = devm_kzalloc(ap->host->dev, sizeof(*pp), GFP_KERNEL); |
1fd7a697 TH |
503 | if (!pp) |
504 | return -ENOMEM; | |
505 | ap->private_data = pp; | |
506 | ||
507 | /* default PRD_CTL value, DMAEN, WR and START off */ | |
508 | tmp = readb(port_base + PORT_PRD_CTL); | |
509 | tmp &= ~(PRD_CTL_DMAEN | PRD_CTL_WR | PRD_CTL_START); | |
510 | pp->dfl_prdctl = tmp; | |
511 | ||
512 | /* Alloc resources */ | |
513 | rc = ata_port_start(ap); | |
514 | if (rc) { | |
515 | kfree(pp); | |
516 | return rc; | |
517 | } | |
518 | ||
519 | init_port(ap); | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
1fd7a697 | 524 | static struct ata_port_operations inic_port_ops = { |
1fd7a697 TH |
525 | .tf_load = ata_tf_load, |
526 | .tf_read = ata_tf_read, | |
527 | .check_status = ata_check_status, | |
528 | .exec_command = ata_exec_command, | |
529 | .dev_select = ata_std_dev_select, | |
530 | ||
531 | .scr_read = inic_scr_read, | |
532 | .scr_write = inic_scr_write, | |
533 | ||
534 | .bmdma_setup = inic_bmdma_setup, | |
535 | .bmdma_start = inic_bmdma_start, | |
536 | .bmdma_stop = inic_bmdma_stop, | |
537 | .bmdma_status = inic_bmdma_status, | |
538 | ||
358f9a77 | 539 | .irq_clear = ata_noop_irq_clear, |
246ce3b6 | 540 | .irq_on = ata_irq_on, |
1fd7a697 TH |
541 | |
542 | .qc_prep = ata_qc_prep, | |
543 | .qc_issue = inic_qc_issue, | |
0d5ff566 | 544 | .data_xfer = ata_data_xfer, |
1fd7a697 TH |
545 | |
546 | .freeze = inic_freeze, | |
547 | .thaw = inic_thaw, | |
548 | .error_handler = inic_error_handler, | |
549 | .post_internal_cmd = inic_post_internal_cmd, | |
550 | .dev_config = inic_dev_config, | |
551 | ||
552 | .port_resume = inic_port_resume, | |
553 | ||
554 | .port_start = inic_port_start, | |
1fd7a697 TH |
555 | }; |
556 | ||
557 | static struct ata_port_info inic_port_info = { | |
0dc36888 | 558 | /* For some reason, ATAPI_PROT_PIO is broken on this |
1fd7a697 TH |
559 | * controller, and no, PIO_POLLING does't fix it. It somehow |
560 | * manages to report the wrong ireason and ignoring ireason | |
561 | * results in machine lock up. Tell libata to always prefer | |
562 | * DMA. | |
563 | */ | |
564 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, | |
565 | .pio_mask = 0x1f, /* pio0-4 */ | |
566 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 567 | .udma_mask = ATA_UDMA6, |
1fd7a697 TH |
568 | .port_ops = &inic_port_ops |
569 | }; | |
570 | ||
571 | static int init_controller(void __iomem *mmio_base, u16 hctl) | |
572 | { | |
573 | int i; | |
574 | u16 val; | |
575 | ||
576 | hctl &= ~HCTL_KNOWN_BITS; | |
577 | ||
578 | /* Soft reset whole controller. Spec says reset duration is 3 | |
579 | * PCI clocks, be generous and give it 10ms. | |
580 | */ | |
581 | writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); | |
582 | readw(mmio_base + HOST_CTL); /* flush */ | |
583 | ||
584 | for (i = 0; i < 10; i++) { | |
585 | msleep(1); | |
586 | val = readw(mmio_base + HOST_CTL); | |
587 | if (!(val & HCTL_SOFTRST)) | |
588 | break; | |
589 | } | |
590 | ||
591 | if (val & HCTL_SOFTRST) | |
592 | return -EIO; | |
593 | ||
594 | /* mask all interrupts and reset ports */ | |
595 | for (i = 0; i < NR_PORTS; i++) { | |
596 | void __iomem *port_base = mmio_base + i * PORT_SIZE; | |
597 | ||
598 | writeb(0xff, port_base + PORT_IRQ_MASK); | |
599 | inic_reset_port(port_base); | |
600 | } | |
601 | ||
602 | /* port IRQ is masked now, unmask global IRQ */ | |
603 | writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); | |
604 | val = readw(mmio_base + HOST_IRQ_MASK); | |
605 | val &= ~(HIRQ_PORT0 | HIRQ_PORT1); | |
606 | writew(val, mmio_base + HOST_IRQ_MASK); | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
438ac6d5 | 611 | #ifdef CONFIG_PM |
1fd7a697 TH |
612 | static int inic_pci_device_resume(struct pci_dev *pdev) |
613 | { | |
614 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
615 | struct inic_host_priv *hpriv = host->private_data; | |
0d5ff566 | 616 | void __iomem *mmio_base = host->iomap[MMIO_BAR]; |
1fd7a697 TH |
617 | int rc; |
618 | ||
5aea408d DM |
619 | rc = ata_pci_device_do_resume(pdev); |
620 | if (rc) | |
621 | return rc; | |
1fd7a697 TH |
622 | |
623 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
1fd7a697 TH |
624 | rc = init_controller(mmio_base, hpriv->cached_hctl); |
625 | if (rc) | |
626 | return rc; | |
627 | } | |
628 | ||
629 | ata_host_resume(host); | |
630 | ||
631 | return 0; | |
632 | } | |
438ac6d5 | 633 | #endif |
1fd7a697 TH |
634 | |
635 | static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
636 | { | |
637 | static int printed_version; | |
4447d351 TH |
638 | const struct ata_port_info *ppi[] = { &inic_port_info, NULL }; |
639 | struct ata_host *host; | |
1fd7a697 | 640 | struct inic_host_priv *hpriv; |
0d5ff566 | 641 | void __iomem * const *iomap; |
1fd7a697 TH |
642 | int i, rc; |
643 | ||
644 | if (!printed_version++) | |
645 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
646 | ||
4447d351 TH |
647 | /* alloc host */ |
648 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS); | |
649 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
650 | if (!host || !hpriv) | |
651 | return -ENOMEM; | |
652 | ||
653 | host->private_data = hpriv; | |
654 | ||
655 | /* acquire resources and fill host */ | |
24dc5f33 | 656 | rc = pcim_enable_device(pdev); |
1fd7a697 TH |
657 | if (rc) |
658 | return rc; | |
659 | ||
0d5ff566 TH |
660 | rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME); |
661 | if (rc) | |
662 | return rc; | |
4447d351 TH |
663 | host->iomap = iomap = pcim_iomap_table(pdev); |
664 | ||
665 | for (i = 0; i < NR_PORTS; i++) { | |
cbcdd875 TH |
666 | struct ata_port *ap = host->ports[i]; |
667 | struct ata_ioports *port = &ap->ioaddr; | |
668 | unsigned int offset = i * PORT_SIZE; | |
4447d351 TH |
669 | |
670 | port->cmd_addr = iomap[2 * i]; | |
671 | port->altstatus_addr = | |
672 | port->ctl_addr = (void __iomem *) | |
673 | ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS); | |
cbcdd875 | 674 | port->scr_addr = iomap[MMIO_BAR] + offset + PORT_SCR; |
4447d351 TH |
675 | |
676 | ata_std_ports(port); | |
cbcdd875 TH |
677 | |
678 | ata_port_pbar_desc(ap, MMIO_BAR, -1, "mmio"); | |
679 | ata_port_pbar_desc(ap, MMIO_BAR, offset, "port"); | |
680 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", | |
681 | (unsigned long long)pci_resource_start(pdev, 2 * i), | |
682 | (unsigned long long)pci_resource_start(pdev, (2 * i + 1)) | | |
683 | ATA_PCI_CTL_OFS); | |
4447d351 TH |
684 | } |
685 | ||
686 | hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL); | |
1fd7a697 TH |
687 | |
688 | /* Set dma_mask. This devices doesn't support 64bit addressing. */ | |
689 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
690 | if (rc) { | |
691 | dev_printk(KERN_ERR, &pdev->dev, | |
692 | "32-bit DMA enable failed\n"); | |
24dc5f33 | 693 | return rc; |
1fd7a697 TH |
694 | } |
695 | ||
696 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
697 | if (rc) { | |
698 | dev_printk(KERN_ERR, &pdev->dev, | |
699 | "32-bit consistent DMA enable failed\n"); | |
24dc5f33 | 700 | return rc; |
1fd7a697 TH |
701 | } |
702 | ||
b7d8629f FT |
703 | /* |
704 | * This controller is braindamaged. dma_boundary is 0xffff | |
705 | * like others but it will lock up the whole machine HARD if | |
706 | * 65536 byte PRD entry is fed. Reduce maximum segment size. | |
707 | */ | |
708 | rc = pci_set_dma_max_seg_size(pdev, 65536 - 512); | |
709 | if (rc) { | |
710 | dev_printk(KERN_ERR, &pdev->dev, | |
711 | "failed to set the maximum segment size.\n"); | |
712 | return rc; | |
713 | } | |
714 | ||
0d5ff566 | 715 | rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl); |
1fd7a697 TH |
716 | if (rc) { |
717 | dev_printk(KERN_ERR, &pdev->dev, | |
718 | "failed to initialize controller\n"); | |
24dc5f33 | 719 | return rc; |
1fd7a697 TH |
720 | } |
721 | ||
722 | pci_set_master(pdev); | |
4447d351 TH |
723 | return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED, |
724 | &inic_sht); | |
1fd7a697 TH |
725 | } |
726 | ||
727 | static const struct pci_device_id inic_pci_tbl[] = { | |
728 | { PCI_VDEVICE(INIT, 0x1622), }, | |
729 | { }, | |
730 | }; | |
731 | ||
732 | static struct pci_driver inic_pci_driver = { | |
733 | .name = DRV_NAME, | |
734 | .id_table = inic_pci_tbl, | |
438ac6d5 | 735 | #ifdef CONFIG_PM |
1fd7a697 TH |
736 | .suspend = ata_pci_device_suspend, |
737 | .resume = inic_pci_device_resume, | |
438ac6d5 | 738 | #endif |
1fd7a697 TH |
739 | .probe = inic_init_one, |
740 | .remove = ata_pci_remove_one, | |
741 | }; | |
742 | ||
743 | static int __init inic_init(void) | |
744 | { | |
745 | return pci_register_driver(&inic_pci_driver); | |
746 | } | |
747 | ||
748 | static void __exit inic_exit(void) | |
749 | { | |
750 | pci_unregister_driver(&inic_pci_driver); | |
751 | } | |
752 | ||
753 | MODULE_AUTHOR("Tejun Heo"); | |
754 | MODULE_DESCRIPTION("low-level driver for Initio 162x SATA"); | |
755 | MODULE_LICENSE("GPL v2"); | |
756 | MODULE_DEVICE_TABLE(pci, inic_pci_tbl); | |
757 | MODULE_VERSION(DRV_VERSION); | |
758 | ||
759 | module_init(inic_init); | |
760 | module_exit(inic_exit); |