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sata_mv: mv_fill_sg fixes v2
[mirror_ubuntu-artful-kernel.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
85afb934
ML		 36 * --> Develop a low-power-consumption strategy, and implement it.
37 *
38 * --> [Experiment, low priority] Investigate interrupt coalescing.
39 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
40 * the overhead reduced by interrupt mitigation is quite often not
41 * worth the latency cost.
42 *
43 * --> [Experiment, Marvell value added] Is it possible to use target
44 * mode to cross-connect two Linux boxes with Marvell cards? If so,
45 * creating LibATA target mode support would be very interesting.
46 *
47 * Target mode, for those without docs, is the ability to directly
48 * connect two SATA ports.
49 */
4a05e209 50
20f733e7
BR		 51#include <linux/kernel.h>
52#include <linux/module.h>
53#include <linux/pci.h>
54#include <linux/init.h>
55#include <linux/blkdev.h>
56#include <linux/delay.h>
57#include <linux/interrupt.h>
8d8b6004 58#include <linux/dmapool.h>
20f733e7 59#include <linux/dma-mapping.h>
a9524a76 60#include <linux/device.h>
f351b2d6
SB		 61#include <linux/platform_device.h>
62#include <linux/ata_platform.h>
15a32632 63#include <linux/mbus.h>
c46938cc 64#include <linux/bitops.h>
20f733e7 65#include <scsi/scsi_host.h>
193515d5 66#include <scsi/scsi_cmnd.h>
6c08772e 67#include <scsi/scsi_device.h>
20f733e7 68#include <linux/libata.h>
20f733e7
BR		 69
70#define DRV_NAME "sata_mv"
6d3c30ef 71#define DRV_VERSION "1.25"
20f733e7
BR		 72
73enum {
74 /* BAR's are enumerated in terms of pci_resource_start() terms */
75 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
76 MV_IO_BAR = 2, /* offset 0x18: IO space */
77 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
78
79 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
80 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
81
82 MV_PCI_REG_BASE = 0,
83 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 84 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
85 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
86 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
87 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
88 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
89
20f733e7 90 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 91 MV_FLASH_CTL_OFS = 0x1046c,
92 MV_GPIO_PORT_CTL_OFS = 0x104f0,
93 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 94
95 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
96 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
97 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
98 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
99
31961943
BR		 100 MV_MAX_Q_DEPTH = 32,
101 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
102
103 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
104 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 105 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
106 */
107 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
108 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 109 MV_MAX_SG_CT = 256,
31961943 110 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 111
352fab70 112 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 113 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 114 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
115 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
116 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 117
118 /* Host Flags */
119 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
120 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 121
c5d3e45a 122 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
91b1a84c 123 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
ad3aef51 124
91b1a84c 125 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
20f733e7 126
91b1a84c 127 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | MV_FLAG_IRQ_COALESCE |
ad3aef51 128 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
91b1a84c
ML		 129 ATA_FLAG_NCQ | ATA_FLAG_NO_ATAPI,
130
131 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
ad3aef51 132
31961943
BR		 133 CRQB_FLAG_READ = (1 << 0),
134 CRQB_TAG_SHIFT = 1,
c5d3e45a 135 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 136 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 137 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 138 CRQB_CMD_ADDR_SHIFT = 8,
139 CRQB_CMD_CS = (0x2 << 11),
140 CRQB_CMD_LAST = (1 << 15),
141
142 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 143 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
144 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 145
146 EPRD_FLAG_END_OF_TBL = (1 << 31),
147
20f733e7
BR		 148 /* PCI interface registers */
149
31961943 150 PCI_COMMAND_OFS = 0xc00,
8e7decdb 151 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 152
20f733e7
BR		 153 PCI_MAIN_CMD_STS_OFS = 0xd30,
154 STOP_PCI_MASTER = (1 << 2),
155 PCI_MASTER_EMPTY = (1 << 3),
156 GLOB_SFT_RST = (1 << 4),
157
8e7decdb
ML		 158 MV_PCI_MODE_OFS = 0xd00,
159 MV_PCI_MODE_MASK = 0x30,
160
522479fb
JG		 161 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
162 MV_PCI_DISC_TIMER = 0xd04,
163 MV_PCI_MSI_TRIGGER = 0xc38,
164 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 165 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 166 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
167 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
168 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
169 MV_PCI_ERR_COMMAND = 0x1d50,
170
02a121da
ML		 171 PCI_IRQ_CAUSE_OFS = 0x1d58,
172 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 173 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
174
02a121da
ML		 175 PCIE_IRQ_CAUSE_OFS = 0x1900,
176 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 177 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 178
7368f919
ML		 179 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
180 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
181 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
182 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
183 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 184 ERR_IRQ = (1 << 0), /* shift by port # */
185 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 186 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
187 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
188 PCI_ERR = (1 << 18),
189 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
190 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 191 PORTS_0_3_COAL_DONE = (1 << 8),
192 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 193 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
194 GPIO_INT = (1 << 22),
195 SELF_INT = (1 << 23),
196 TWSI_INT = (1 << 24),
197 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 198 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 199 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 200
201 /* SATAHC registers */
202 HC_CFG_OFS = 0,
203
204 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 205 DMA_IRQ = (1 << 0), /* shift by port # */
206 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 207 DEV_IRQ = (1 << 8), /* shift by port # */
208
209 /* Shadow block registers */
31961943
BR		 210 SHD_BLK_OFS = 0x100,
211 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 212
213 /* SATA registers */
214 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
215 SATA_ACTIVE_OFS = 0x350,
0c58912e 216 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
c443c500 217 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
17c5aab5 218
e12bef50 219 LTMODE_OFS = 0x30c,
17c5aab5
ML		 220 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
221
47c2b677 222 PHY_MODE3 = 0x310,
bca1c4eb 223 PHY_MODE4 = 0x314,
ba069e37
ML		 224 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
225 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
226 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
227 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
228
bca1c4eb 229 PHY_MODE2 = 0x330,
e12bef50 230 SATA_IFCTL_OFS = 0x344,
8e7decdb 231 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 234
8e7decdb
ML		 235 FISCFG_OFS = 0x360,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 238
c9d39130 239 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 243
244 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 245
246 /* Port registers */
247 EDMA_CFG_OFS = 0,
0c58912e
ML		 248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 255
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 272
6c1153e0 273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
278
6c1153e0 279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 280
6c1153e0 281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
287
6c1153e0 288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 289
6c1153e0 290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 293
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 297 EDMA_ERR_LNK_CTRL_TX,
646a4da5 298
bdd4ddde
JG		 299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
300 EDMA_ERR_PRD_PAR |
301 EDMA_ERR_DEV_DCON |
302 EDMA_ERR_DEV_CON |
303 EDMA_ERR_SERR |
304 EDMA_ERR_SELF_DIS |
6c1153e0 305 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 306 EDMA_ERR_CRPB_PAR |
307 EDMA_ERR_INTRL_PAR |
308 EDMA_ERR_IORDY |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
e12bef50 313
bdd4ddde
JG		 314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
315 EDMA_ERR_PRD_PAR |
316 EDMA_ERR_DEV_DCON |
317 EDMA_ERR_DEV_CON |
318 EDMA_ERR_OVERRUN_5 |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
6c1153e0 321 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 322 EDMA_ERR_CRPB_PAR |
323 EDMA_ERR_INTRL_PAR |
324 EDMA_ERR_IORDY,
20f733e7 325
31961943
BR		 326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 328
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
331
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 335 EDMA_RSP_Q_PTR_SHIFT = 3,
336
0ea9e179
JG		 337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
341
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 345
8e7decdb
ML		 346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
348
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 350
31961943
BR		 351 /* Host private flags (hp_flags) */
352 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 353 MV_HP_ERRATA_50XXB0 = (1 << 1),
354 MV_HP_ERRATA_50XXB2 = (1 << 2),
355 MV_HP_ERRATA_60X1B2 = (1 << 3),
356 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 357 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
358 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
359 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 360 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 361 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 362 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
20f733e7 363
31961943 364 /* Port private flags (pp_flags) */
0ea9e179 365 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 366 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 367 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 368 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
20f733e7
BR		 369};
370
ee9ccdf7
JG		 371#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
372#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 373#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 374#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 375#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 376
15a32632
LB		 377#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
378#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
379
095fec88 380enum {
baf14aa1
JG		 381 /* DMA boundary 0xffff is required by the s/g splitting
382 * we need on /length/ in mv_fill-sg().
383 */
384 MV_DMA_BOUNDARY = 0xffffU,
095fec88 385
0ea9e179
JG		 386 /* mask of register bits containing lower 32 bits
387 * of EDMA request queue DMA address
388 */
095fec88
JG		 389 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
390
0ea9e179 391 /* ditto, for response queue */
095fec88
JG		 392 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
393};
394
522479fb
JG		 395enum chip_type {
396 chip_504x,
397 chip_508x,
398 chip_5080,
399 chip_604x,
400 chip_608x,
e4e7b892
JG		 401 chip_6042,
402 chip_7042,
f351b2d6 403 chip_soc,
522479fb
JG		 404};
405
31961943
BR		 406/* Command ReQuest Block: 32B */
407struct mv_crqb {
e1469874
ML		 408 __le32 sg_addr;
409 __le32 sg_addr_hi;
410 __le16 ctrl_flags;
411 __le16 ata_cmd[11];
31961943 412};
20f733e7 413
e4e7b892 414struct mv_crqb_iie {
e1469874
ML		 415 __le32 addr;
416 __le32 addr_hi;
417 __le32 flags;
418 __le32 len;
419 __le32 ata_cmd[4];
e4e7b892
JG		 420};
421
31961943
BR		 422/* Command ResPonse Block: 8B */
423struct mv_crpb {
e1469874
ML		 424 __le16 id;
425 __le16 flags;
426 __le32 tmstmp;
20f733e7
BR		 427};
428
31961943
BR		 429/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
430struct mv_sg {
e1469874
ML		 431 __le32 addr;
432 __le32 flags_size;
433 __le32 addr_hi;
434 __le32 reserved;
31961943 435};
20f733e7 436
31961943
BR		 437struct mv_port_priv {
438 struct mv_crqb *crqb;
439 dma_addr_t crqb_dma;
440 struct mv_crpb *crpb;
441 dma_addr_t crpb_dma;
eb73d558
ML		 442 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
443 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 444
445 unsigned int req_idx;
446 unsigned int resp_idx;
447
31961943 448 u32 pp_flags;
29d187bb 449 unsigned int delayed_eh_pmp_map;
31961943
BR		 450};
451
bca1c4eb
JG		 452struct mv_port_signal {
453 u32 amps;
454 u32 pre;
455};
456
02a121da
ML		 457struct mv_host_priv {
458 u32 hp_flags;
96e2c487 459 u32 main_irq_mask;
02a121da
ML		 460 struct mv_port_signal signal[8];
461 const struct mv_hw_ops *ops;
f351b2d6
SB		 462 int n_ports;
463 void __iomem *base;
7368f919
ML		 464 void __iomem *main_irq_cause_addr;
465 void __iomem *main_irq_mask_addr;
02a121da
ML		 466 u32 irq_cause_ofs;
467 u32 irq_mask_ofs;
468 u32 unmask_all_irqs;
da2fa9ba
ML		 469 /*
470 * These consistent DMA memory pools give us guaranteed
471 * alignment for hardware-accessed data structures,
472 * and less memory waste in accomplishing the alignment.
473 */
474 struct dma_pool *crqb_pool;
475 struct dma_pool *crpb_pool;
476 struct dma_pool *sg_tbl_pool;
02a121da
ML		 477};
478
47c2b677 479struct mv_hw_ops {
2a47ce06
JG		 480 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
481 unsigned int port);
47c2b677
JG		 482 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
483 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
484 void __iomem *mmio);
c9d39130
JG		 485 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
486 unsigned int n_hc);
522479fb 487 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 488 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 489};
490
82ef04fb
TH		 491static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
492static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
493static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
494static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
31961943
BR		 495static int mv_port_start(struct ata_port *ap);
496static void mv_port_stop(struct ata_port *ap);
3e4a1391 497static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 498static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 499static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 500static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 501static int mv_hardreset(struct ata_link *link, unsigned int *class,
502 unsigned long deadline);
bdd4ddde
JG		 503static void mv_eh_freeze(struct ata_port *ap);
504static void mv_eh_thaw(struct ata_port *ap);
f273827e 505static void mv6_dev_config(struct ata_device *dev);
20f733e7 506
2a47ce06
JG		 507static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
508 unsigned int port);
47c2b677
JG		 509static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
510static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
511 void __iomem *mmio);
c9d39130
JG		 512static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
513 unsigned int n_hc);
522479fb 514static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 515static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 516
2a47ce06
JG		 517static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
518 unsigned int port);
47c2b677
JG		 519static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
520static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
521 void __iomem *mmio);
c9d39130
JG		 522static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
523 unsigned int n_hc);
522479fb 524static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 525static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
526 void __iomem *mmio);
527static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
528 void __iomem *mmio);
529static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
530 void __iomem *mmio, unsigned int n_hc);
531static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
532 void __iomem *mmio);
533static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 534static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 535static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 536 unsigned int port_no);
e12bef50 537static int mv_stop_edma(struct ata_port *ap);
b562468c 538static int mv_stop_edma_engine(void __iomem *port_mmio);
00b81235 539static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
47c2b677 540
e49856d8
ML		 541static void mv_pmp_select(struct ata_port *ap, int pmp);
542static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
543 unsigned long deadline);
544static int mv_softreset(struct ata_link *link, unsigned int *class,
545 unsigned long deadline);
29d187bb 546static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 547static void mv_process_crpb_entries(struct ata_port *ap,
548 struct mv_port_priv *pp);
47c2b677 549
eb73d558
ML		 550/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
551 * because we have to allow room for worst case splitting of
552 * PRDs for 64K boundaries in mv_fill_sg().
553 */
c5d3e45a 554static struct scsi_host_template mv5_sht = {
68d1d07b 555 ATA_BASE_SHT(DRV_NAME),
baf14aa1 556 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 557 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 558};
559
560static struct scsi_host_template mv6_sht = {
68d1d07b 561 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 562 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 563 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 564 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 565};
566
029cfd6b
TH		 567static struct ata_port_operations mv5_ops = {
568 .inherits = &ata_sff_port_ops,
c9d39130 569
3e4a1391 570 .qc_defer = mv_qc_defer,
c9d39130
JG		 571 .qc_prep = mv_qc_prep,
572 .qc_issue = mv_qc_issue,
c9d39130 573
bdd4ddde
JG		 574 .freeze = mv_eh_freeze,
575 .thaw = mv_eh_thaw,
a1efdaba 576 .hardreset = mv_hardreset,
a1efdaba 577 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 578 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 579
c9d39130
JG		 580 .scr_read = mv5_scr_read,
581 .scr_write = mv5_scr_write,
582
583 .port_start = mv_port_start,
584 .port_stop = mv_port_stop,
c9d39130
JG		 585};
586
029cfd6b
TH		 587static struct ata_port_operations mv6_ops = {
588 .inherits = &mv5_ops,
f273827e 589 .dev_config = mv6_dev_config,
20f733e7
BR		 590 .scr_read = mv_scr_read,
591 .scr_write = mv_scr_write,
592
e49856d8
ML		 593 .pmp_hardreset = mv_pmp_hardreset,
594 .pmp_softreset = mv_softreset,
595 .softreset = mv_softreset,
29d187bb 596 .error_handler = mv_pmp_error_handler,
20f733e7
BR		 597};
598
029cfd6b
TH		 599static struct ata_port_operations mv_iie_ops = {
600 .inherits = &mv6_ops,
601 .dev_config = ATA_OP_NULL,
e4e7b892 602 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 603};
604
98ac62de 605static const struct ata_port_info mv_port_info[] = {
20f733e7 606 { /* chip_504x */
91b1a84c 607 .flags = MV_GEN_I_FLAGS,
31961943 608 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 609 .udma_mask = ATA_UDMA6,
c9d39130 610 .port_ops = &mv5_ops,
20f733e7
BR		 611 },
612 { /* chip_508x */
91b1a84c 613 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
31961943 614 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 615 .udma_mask = ATA_UDMA6,
c9d39130 616 .port_ops = &mv5_ops,
20f733e7 617 },
47c2b677 618 { /* chip_5080 */
91b1a84c 619 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 620 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 621 .udma_mask = ATA_UDMA6,
c9d39130 622 .port_ops = &mv5_ops,
47c2b677 623 },
20f733e7 624 { /* chip_604x */
91b1a84c 625 .flags = MV_GEN_II_FLAGS,
31961943 626 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 627 .udma_mask = ATA_UDMA6,
c9d39130 628 .port_ops = &mv6_ops,
20f733e7
BR		 629 },
630 { /* chip_608x */
91b1a84c 631 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
31961943 632 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 633 .udma_mask = ATA_UDMA6,
c9d39130 634 .port_ops = &mv6_ops,
20f733e7 635 },
e4e7b892 636 { /* chip_6042 */
91b1a84c 637 .flags = MV_GEN_IIE_FLAGS,
e4e7b892 638 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 639 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 640 .port_ops = &mv_iie_ops,
641 },
642 { /* chip_7042 */
91b1a84c 643 .flags = MV_GEN_IIE_FLAGS,
e4e7b892 644 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 645 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 646 .port_ops = &mv_iie_ops,
647 },
f351b2d6 648 { /* chip_soc */
91b1a84c 649 .flags = MV_GEN_IIE_FLAGS,
17c5aab5
ML		 650 .pio_mask = 0x1f, /* pio0-4 */
651 .udma_mask = ATA_UDMA6,
652 .port_ops = &mv_iie_ops,
f351b2d6 653 },
20f733e7
BR		 654};
655
3b7d697d 656static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 657 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
658 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
659 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
660 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
46c5784c
ML		 661 /* RocketRAID 1720/174x have different identifiers */
662 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
4462254a
ML		 663 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
664 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
2d2744fc
JG		 665
666 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
667 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
668 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
669 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
670 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
671
672 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
673
d9f9c6bc
FA		 674 /* Adaptec 1430SA */
675 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
676
02a121da 677 /* Marvell 7042 support */
6a3d586d
MT		 678 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
679
02a121da
ML		 680 /* Highpoint RocketRAID PCIe series */
681 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
682 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
683
2d2744fc 684 { } /* terminate list */
20f733e7
BR		 685};
686
47c2b677
JG		 687static const struct mv_hw_ops mv5xxx_ops = {
688 .phy_errata = mv5_phy_errata,
689 .enable_leds = mv5_enable_leds,
690 .read_preamp = mv5_read_preamp,
691 .reset_hc = mv5_reset_hc,
522479fb
JG		 692 .reset_flash = mv5_reset_flash,
693 .reset_bus = mv5_reset_bus,
47c2b677
JG		 694};
695
696static const struct mv_hw_ops mv6xxx_ops = {
697 .phy_errata = mv6_phy_errata,
698 .enable_leds = mv6_enable_leds,
699 .read_preamp = mv6_read_preamp,
700 .reset_hc = mv6_reset_hc,
522479fb
JG		 701 .reset_flash = mv6_reset_flash,
702 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 703};
704
f351b2d6
SB		 705static const struct mv_hw_ops mv_soc_ops = {
706 .phy_errata = mv6_phy_errata,
707 .enable_leds = mv_soc_enable_leds,
708 .read_preamp = mv_soc_read_preamp,
709 .reset_hc = mv_soc_reset_hc,
710 .reset_flash = mv_soc_reset_flash,
711 .reset_bus = mv_soc_reset_bus,
712};
713
20f733e7
BR		 714/*
715 * Functions
716 */
717
718static inline void writelfl(unsigned long data, void __iomem *addr)
719{
720 writel(data, addr);
721 (void) readl(addr); /* flush to avoid PCI posted write */
722}
723
c9d39130
JG		 724static inline unsigned int mv_hc_from_port(unsigned int port)
725{
726 return port >> MV_PORT_HC_SHIFT;
727}
728
729static inline unsigned int mv_hardport_from_port(unsigned int port)
730{
731 return port & MV_PORT_MASK;
732}
733
1cfd19ae
ML		 734/*
735 * Consolidate some rather tricky bit shift calculations.
736 * This is hot-path stuff, so not a function.
737 * Simple code, with two return values, so macro rather than inline.
738 *
739 * port is the sole input, in range 0..7.
7368f919
ML		 740 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
741 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 742 *
743 * Note that port and hardport may be the same variable in some cases.
744 */
745#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
746{ \
747 shift = mv_hc_from_port(port) * HC_SHIFT; \
748 hardport = mv_hardport_from_port(port); \
749 shift += hardport * 2; \
750}
751
352fab70
ML		 752static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
753{
754 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
755}
756
c9d39130
JG		 757static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
758 unsigned int port)
759{
760 return mv_hc_base(base, mv_hc_from_port(port));
761}
762
20f733e7
BR		 763static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
764{
c9d39130 765 return mv_hc_base_from_port(base, port) +
8b260248 766 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 767 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 768}
769
e12bef50
ML		 770static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
771{
772 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
773 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
774
775 return hc_mmio + ofs;
776}
777
f351b2d6
SB		 778static inline void __iomem *mv_host_base(struct ata_host *host)
779{
780 struct mv_host_priv *hpriv = host->private_data;
781 return hpriv->base;
782}
783
20f733e7
BR		 784static inline void __iomem *mv_ap_base(struct ata_port *ap)
785{
f351b2d6 786 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 787}
788
cca3974e 789static inline int mv_get_hc_count(unsigned long port_flags)
31961943 790{
cca3974e 791 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 792}
793
c5d3e45a
JG		 794static void mv_set_edma_ptrs(void __iomem *port_mmio,
795 struct mv_host_priv *hpriv,
796 struct mv_port_priv *pp)
797{
bdd4ddde
JG		 798 u32 index;
799
c5d3e45a
JG		 800 /*
801 * initialize request queue
802 */
fcfb1f77
ML		 803 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
804 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 805
c5d3e45a
JG		 806 WARN_ON(pp->crqb_dma & 0x3ff);
807 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 808 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a 809 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
5cf73bfb 810 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 811
812 /*
813 * initialize response queue
814 */
fcfb1f77
ML		 815 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
816 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 817
c5d3e45a
JG		 818 WARN_ON(pp->crpb_dma & 0xff);
819 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
5cf73bfb 820 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
bdd4ddde 821 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 822 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 823}
824
c4de573b
ML		 825static void mv_set_main_irq_mask(struct ata_host *host,
826 u32 disable_bits, u32 enable_bits)
827{
828 struct mv_host_priv *hpriv = host->private_data;
829 u32 old_mask, new_mask;
830
96e2c487 831 old_mask = hpriv->main_irq_mask;
c4de573b 832 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 833 if (new_mask != old_mask) {
834 hpriv->main_irq_mask = new_mask;
c4de573b 835 writelfl(new_mask, hpriv->main_irq_mask_addr);
96e2c487 836 }
c4de573b
ML		 837}
838
839static void mv_enable_port_irqs(struct ata_port *ap,
840 unsigned int port_bits)
841{
842 unsigned int shift, hardport, port = ap->port_no;
843 u32 disable_bits, enable_bits;
844
845 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
846
847 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
848 enable_bits = port_bits << shift;
849 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
850}
851
00b81235
ML		 852static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
853 void __iomem *port_mmio,
854 unsigned int port_irqs)
855{
856 struct mv_host_priv *hpriv = ap->host->private_data;
857 int hardport = mv_hardport_from_port(ap->port_no);
858 void __iomem *hc_mmio = mv_hc_base_from_port(
859 mv_host_base(ap->host), ap->port_no);
860 u32 hc_irq_cause;
861
862 /* clear EDMA event indicators, if any */
863 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
864
865 /* clear pending irq events */
866 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
867 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
868
869 /* clear FIS IRQ Cause */
870 if (IS_GEN_IIE(hpriv))
871 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
872
873 mv_enable_port_irqs(ap, port_irqs);
874}
875
05b308e1 876/**
00b81235 877 * mv_start_edma - Enable eDMA engine
05b308e1
BR		 878 * @base: port base address
879 * @pp: port private data
880 *
beec7dbc
TH		 881 * Verify the local cache of the eDMA state is accurate with a
882 * WARN_ON.
05b308e1
BR		 883 *
884 * LOCKING:
885 * Inherited from caller.
886 */
00b81235 887static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
72109168 888 struct mv_port_priv *pp, u8 protocol)
20f733e7 889{
72109168
ML		 890 int want_ncq = (protocol == ATA_PROT_NCQ);
891
892 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
893 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
894 if (want_ncq != using_ncq)
b562468c 895 mv_stop_edma(ap);
72109168 896 }
c5d3e45a 897 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 898 struct mv_host_priv *hpriv = ap->host->private_data;
0c58912e 899
00b81235 900 mv_edma_cfg(ap, want_ncq, 1);
0c58912e 901
f630d562 902 mv_set_edma_ptrs(port_mmio, hpriv, pp);
00b81235 903 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
bdd4ddde 904
f630d562 905 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 906 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
907 }
20f733e7
BR		 908}
909
9b2c4e0b
ML		 910static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
911{
912 void __iomem *port_mmio = mv_ap_base(ap);
913 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
914 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
915 int i;
916
917 /*
918 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 919 * No idea what a good "timeout" value might be, but measurements
920 * indicate that it often requires hundreds of microseconds
921 * with two drives in-use. So we use the 15msec value above
922 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 923 */
924 for (i = 0; i < timeout; ++i) {
925 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
926 if ((edma_stat & empty_idle) == empty_idle)
927 break;
928 udelay(per_loop);
929 }
930 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
931}
932
05b308e1 933/**
e12bef50 934 * mv_stop_edma_engine - Disable eDMA engine
b562468c 935 * @port_mmio: io base address
05b308e1
BR		 936 *
937 * LOCKING:
938 * Inherited from caller.
939 */
b562468c 940static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 941{
b562468c 942 int i;
31961943 943
b562468c
ML		 944 /* Disable eDMA. The disable bit auto clears. */
945 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 946
b562468c
ML		 947 /* Wait for the chip to confirm eDMA is off. */
948 for (i = 10000; i > 0; i--) {
949 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 950 if (!(reg & EDMA_EN))
b562468c
ML		 951 return 0;
952 udelay(10);
31961943 953 }
b562468c 954 return -EIO;
20f733e7
BR		 955}
956
e12bef50 957static int mv_stop_edma(struct ata_port *ap)
0ea9e179 958{
b562468c
ML		 959 void __iomem *port_mmio = mv_ap_base(ap);
960 struct mv_port_priv *pp = ap->private_data;
0ea9e179 961
b562468c
ML		 962 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
963 return 0;
964 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 965 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 966 if (mv_stop_edma_engine(port_mmio)) {
967 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
968 return -EIO;
969 }
970 return 0;
0ea9e179
JG		 971}
972
8a70f8dc 973#ifdef ATA_DEBUG
31961943 974static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 975{
31961943
BR		 976 int b, w;
977 for (b = 0; b < bytes; ) {
978 DPRINTK("%p: ", start + b);
979 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 980 printk("%08x ", readl(start + b));
31961943
BR		 981 b += sizeof(u32);
982 }
983 printk("\n");
984 }
31961943 985}
8a70f8dc
JG		 986#endif
987
31961943
BR		 988static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
989{
990#ifdef ATA_DEBUG
991 int b, w;
992 u32 dw;
993 for (b = 0; b < bytes; ) {
994 DPRINTK("%02x: ", b);
995 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 996 (void) pci_read_config_dword(pdev, b, &dw);
997 printk("%08x ", dw);
31961943
BR		 998 b += sizeof(u32);
999 }
1000 printk("\n");
1001 }
1002#endif
1003}
1004static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1005 struct pci_dev *pdev)
1006{
1007#ifdef ATA_DEBUG
8b260248 1008 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1009 port >> MV_PORT_HC_SHIFT);
1010 void __iomem *port_base;
1011 int start_port, num_ports, p, start_hc, num_hcs, hc;
1012
1013 if (0 > port) {
1014 start_hc = start_port = 0;
1015 num_ports = 8; /* shld be benign for 4 port devs */
1016 num_hcs = 2;
1017 } else {
1018 start_hc = port >> MV_PORT_HC_SHIFT;
1019 start_port = port;
1020 num_ports = num_hcs = 1;
1021 }
8b260248 1022 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1023 num_ports > 1 ? num_ports - 1 : start_port);
1024
1025 if (NULL != pdev) {
1026 DPRINTK("PCI config space regs:\n");
1027 mv_dump_pci_cfg(pdev, 0x68);
1028 }
1029 DPRINTK("PCI regs:\n");
1030 mv_dump_mem(mmio_base+0xc00, 0x3c);
1031 mv_dump_mem(mmio_base+0xd00, 0x34);
1032 mv_dump_mem(mmio_base+0xf00, 0x4);
1033 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1034 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1035 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1036 DPRINTK("HC regs (HC %i):\n", hc);
1037 mv_dump_mem(hc_base, 0x1c);
1038 }
1039 for (p = start_port; p < start_port + num_ports; p++) {
1040 port_base = mv_port_base(mmio_base, p);
2dcb407e 1041 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1042 mv_dump_mem(port_base, 0x54);
2dcb407e 1043 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1044 mv_dump_mem(port_base+0x300, 0x60);
1045 }
1046#endif
20f733e7
BR		 1047}
1048
1049static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1050{
1051 unsigned int ofs;
1052
1053 switch (sc_reg_in) {
1054 case SCR_STATUS:
1055 case SCR_CONTROL:
1056 case SCR_ERROR:
1057 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1058 break;
1059 case SCR_ACTIVE:
1060 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1061 break;
1062 default:
1063 ofs = 0xffffffffU;
1064 break;
1065 }
1066 return ofs;
1067}
1068
82ef04fb 1069static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1070{
1071 unsigned int ofs = mv_scr_offset(sc_reg_in);
1072
da3dbb17 1073 if (ofs != 0xffffffffU) {
82ef04fb 1074 *val = readl(mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1075 return 0;
1076 } else
1077 return -EINVAL;
20f733e7
BR		 1078}
1079
82ef04fb 1080static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1081{
1082 unsigned int ofs = mv_scr_offset(sc_reg_in);
1083
da3dbb17 1084 if (ofs != 0xffffffffU) {
82ef04fb 1085 writelfl(val, mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1086 return 0;
1087 } else
1088 return -EINVAL;
20f733e7
BR		 1089}
1090
f273827e
ML		 1091static void mv6_dev_config(struct ata_device *adev)
1092{
1093 /*
e49856d8
ML		 1094 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1095 *
1096 * Gen-II does not support NCQ over a port multiplier
1097 * (no FIS-based switching).
f273827e 1098 */
e49856d8 1099 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1100 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1101 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1102 ata_dev_printk(adev, KERN_INFO,
1103 "NCQ disabled for command-based switching\n");
352fab70 1104 }
e49856d8 1105 }
f273827e
ML		 1106}
1107
3e4a1391
ML		 1108static int mv_qc_defer(struct ata_queued_cmd *qc)
1109{
1110 struct ata_link *link = qc->dev->link;
1111 struct ata_port *ap = link->ap;
1112 struct mv_port_priv *pp = ap->private_data;
1113
29d187bb
ML		 1114 /*
1115 * Don't allow new commands if we're in a delayed EH state
1116 * for NCQ and/or FIS-based switching.
1117 */
1118 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1119 return ATA_DEFER_PORT;
3e4a1391
ML		 1120 /*
1121 * If the port is completely idle, then allow the new qc.
1122 */
1123 if (ap->nr_active_links == 0)
1124 return 0;
1125
4bdee6c5
TH		 1126 /*
1127 * The port is operating in host queuing mode (EDMA) with NCQ
1128 * enabled, allow multiple NCQ commands. EDMA also allows
1129 * queueing multiple DMA commands but libata core currently
1130 * doesn't allow it.
1131 */
1132 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1133 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1134 return 0;
1135
3e4a1391
ML		 1136 return ATA_DEFER_PORT;
1137}
1138
00f42eab 1139static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
e49856d8 1140{
00f42eab
ML		 1141 u32 new_fiscfg, old_fiscfg;
1142 u32 new_ltmode, old_ltmode;
1143 u32 new_haltcond, old_haltcond;
1144
1145 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1146 old_ltmode = readl(port_mmio + LTMODE_OFS);
1147 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1148
1149 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1150 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1151 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1152
1153 if (want_fbs) {
1154 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1155 new_ltmode = old_ltmode | LTMODE_BIT8;
4c299ca3
ML		 1156 if (want_ncq)
1157 new_haltcond &= ~EDMA_ERR_DEV;
1158 else
1159 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
e49856d8 1160 }
00f42eab 1161
8e7decdb
ML		 1162 if (new_fiscfg != old_fiscfg)
1163 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1164 if (new_ltmode != old_ltmode)
1165 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
00f42eab
ML		 1166 if (new_haltcond != old_haltcond)
1167 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
f273827e
ML		 1168}
1169
dd2890f6
ML		 1170static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1171{
1172 struct mv_host_priv *hpriv = ap->host->private_data;
1173 u32 old, new;
1174
1175 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1176 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1177 if (want_ncq)
1178 new = old | (1 << 22);
1179 else
1180 new = old & ~(1 << 22);
1181 if (new != old)
1182 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1183}
1184
00b81235 1185static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
e4e7b892 1186{
0c58912e 1187 u32 cfg;
e12bef50
ML		 1188 struct mv_port_priv *pp = ap->private_data;
1189 struct mv_host_priv *hpriv = ap->host->private_data;
1190 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1191
1192 /* set up non-NCQ EDMA configuration */
0c58912e 1193 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
00b81235 1194 pp->pp_flags &= ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN);
e4e7b892 1195
0c58912e 1196 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1197 cfg |= (1 << 8); /* enab config burst size mask */
1198
dd2890f6 1199 else if (IS_GEN_II(hpriv)) {
e4e7b892 1200 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1201 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1202
dd2890f6 1203 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1204 int want_fbs = sata_pmp_attached(ap);
1205 /*
1206 * Possible future enhancement:
1207 *
1208 * The chip can use FBS with non-NCQ, if we allow it,
1209 * But first we need to have the error handling in place
1210 * for this mode (datasheet section 7.3.15.4.2.3).
1211 * So disallow non-NCQ FBS for now.
1212 */
1213 want_fbs &= want_ncq;
1214
1215 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1216
1217 if (want_fbs) {
1218 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1219 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1220 }
1221
e728eabe 1222 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
00b81235
ML		 1223 if (want_edma) {
1224 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1225 if (!IS_SOC(hpriv))
1226 cfg |= (1 << 18); /* enab early completion */
1227 }
616d4a98
ML		 1228 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1229 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e4e7b892
JG		 1230 }
1231
72109168
ML		 1232 if (want_ncq) {
1233 cfg |= EDMA_CFG_NCQ;
1234 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
00b81235 1235 }
72109168 1236
e4e7b892
JG		 1237 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1238}
1239
da2fa9ba
ML		 1240static void mv_port_free_dma_mem(struct ata_port *ap)
1241{
1242 struct mv_host_priv *hpriv = ap->host->private_data;
1243 struct mv_port_priv *pp = ap->private_data;
eb73d558 1244 int tag;
da2fa9ba
ML		 1245
1246 if (pp->crqb) {
1247 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1248 pp->crqb = NULL;
1249 }
1250 if (pp->crpb) {
1251 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1252 pp->crpb = NULL;
1253 }
eb73d558
ML		 1254 /*
1255 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1256 * For later hardware, we have one unique sg_tbl per NCQ tag.
1257 */
1258 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1259 if (pp->sg_tbl[tag]) {
1260 if (tag == 0 || !IS_GEN_I(hpriv))
1261 dma_pool_free(hpriv->sg_tbl_pool,
1262 pp->sg_tbl[tag],
1263 pp->sg_tbl_dma[tag]);
1264 pp->sg_tbl[tag] = NULL;
1265 }
da2fa9ba
ML		 1266 }
1267}
1268
05b308e1
BR		 1269/**
1270 * mv_port_start - Port specific init/start routine.
1271 * @ap: ATA channel to manipulate
1272 *
1273 * Allocate and point to DMA memory, init port private memory,
1274 * zero indices.
1275 *
1276 * LOCKING:
1277 * Inherited from caller.
1278 */
31961943
BR		 1279static int mv_port_start(struct ata_port *ap)
1280{
cca3974e
JG		 1281 struct device *dev = ap->host->dev;
1282 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1283 struct mv_port_priv *pp;
dde20207 1284 int tag;
31961943 1285
24dc5f33 1286 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1287 if (!pp)
24dc5f33 1288 return -ENOMEM;
da2fa9ba 1289 ap->private_data = pp;
31961943 1290
da2fa9ba
ML		 1291 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1292 if (!pp->crqb)
1293 return -ENOMEM;
1294 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1295
da2fa9ba
ML		 1296 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1297 if (!pp->crpb)
1298 goto out_port_free_dma_mem;
1299 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1300
3bd0a70e
ML		 1301 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1302 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1303 ap->flags |= ATA_FLAG_AN;
eb73d558
ML		 1304 /*
1305 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1306 * For later hardware, we need one unique sg_tbl per NCQ tag.
1307 */
1308 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1309 if (tag == 0 || !IS_GEN_I(hpriv)) {
1310 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1311 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1312 if (!pp->sg_tbl[tag])
1313 goto out_port_free_dma_mem;
1314 } else {
1315 pp->sg_tbl[tag] = pp->sg_tbl[0];
1316 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1317 }
1318 }
31961943 1319 return 0;
da2fa9ba
ML		 1320
1321out_port_free_dma_mem:
1322 mv_port_free_dma_mem(ap);
1323 return -ENOMEM;
31961943
BR		 1324}
1325
05b308e1
BR		 1326/**
1327 * mv_port_stop - Port specific cleanup/stop routine.
1328 * @ap: ATA channel to manipulate
1329 *
1330 * Stop DMA, cleanup port memory.
1331 *
1332 * LOCKING:
cca3974e 1333 * This routine uses the host lock to protect the DMA stop.
05b308e1 1334 */
31961943
BR		 1335static void mv_port_stop(struct ata_port *ap)
1336{
e12bef50 1337 mv_stop_edma(ap);
88e675e1 1338 mv_enable_port_irqs(ap, 0);
da2fa9ba 1339 mv_port_free_dma_mem(ap);
31961943
BR		 1340}
1341
05b308e1
BR		 1342/**
1343 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1344 * @qc: queued command whose SG list to source from
1345 *
1346 * Populate the SG list and mark the last entry.
1347 *
1348 * LOCKING:
1349 * Inherited from caller.
1350 */
6c08772e 1351static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1352{
1353 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1354 struct scatterlist *sg;
3be6cbd7 1355 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1356 unsigned int si;
31961943 1357
eb73d558 1358 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1359 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1360 dma_addr_t addr = sg_dma_address(sg);
1361 u32 sg_len = sg_dma_len(sg);
22374677 1362
4007b493
OJ		 1363 while (sg_len) {
1364 u32 offset = addr & 0xffff;
1365 u32 len = sg_len;
22374677 1366
32cd11a6 1367 if (offset + len > 0x10000)
4007b493
OJ		 1368 len = 0x10000 - offset;
1369
1370 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1371 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1372 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
32cd11a6 1373 mv_sg->reserved = 0;
4007b493
OJ		 1374
1375 sg_len -= len;
1376 addr += len;
1377
3be6cbd7 1378 last_sg = mv_sg;
4007b493 1379 mv_sg++;
4007b493 1380 }
31961943 1381 }
3be6cbd7
JG		 1382
1383 if (likely(last_sg))
1384 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
32cd11a6 1385 mb(); /* ensure data structure is visible to the chipset */
31961943
BR		 1386}
1387
5796d1c4 1388static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1389{
559eedad 1390 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1391 (last ? CRQB_CMD_LAST : 0);
559eedad 1392 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1393}
1394
05b308e1
BR		 1395/**
1396 * mv_qc_prep - Host specific command preparation.
1397 * @qc: queued command to prepare
1398 *
1399 * This routine simply redirects to the general purpose routine
1400 * if command is not DMA. Else, it handles prep of the CRQB
1401 * (command request block), does some sanity checking, and calls
1402 * the SG load routine.
1403 *
1404 * LOCKING:
1405 * Inherited from caller.
1406 */
31961943
BR		 1407static void mv_qc_prep(struct ata_queued_cmd *qc)
1408{
1409 struct ata_port *ap = qc->ap;
1410 struct mv_port_priv *pp = ap->private_data;
e1469874 1411 __le16 *cw;
31961943
BR		 1412 struct ata_taskfile *tf;
1413 u16 flags = 0;
a6432436 1414 unsigned in_index;
31961943 1415
138bfdd0
ML		 1416 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1417 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1418 return;
20f733e7 1419
31961943
BR		 1420 /* Fill in command request block
1421 */
e4e7b892 1422 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1423 flags |= CRQB_FLAG_READ;
beec7dbc 1424 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1425 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1426 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1427
bdd4ddde 1428 /* get current queue index from software */
fcfb1f77 1429 in_index = pp->req_idx;
a6432436
ML		 1430
1431 pp->crqb[in_index].sg_addr =
eb73d558 1432 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1433 pp->crqb[in_index].sg_addr_hi =
eb73d558 1434 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1435 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1436
a6432436 1437 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1438 tf = &qc->tf;
1439
1440 /* Sadly, the CRQB cannot accomodate all registers--there are
1441 * only 11 bytes...so we must pick and choose required
1442 * registers based on the command. So, we drop feature and
1443 * hob_feature for [RW] DMA commands, but they are needed for
cd12e1f7
ML		 1444 * NCQ. NCQ will drop hob_nsect, which is not needed there
1445 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
20f733e7 1446 */
31961943
BR		 1447 switch (tf->command) {
1448 case ATA_CMD_READ:
1449 case ATA_CMD_READ_EXT:
1450 case ATA_CMD_WRITE:
1451 case ATA_CMD_WRITE_EXT:
c15d85c8 1452 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1453 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1454 break;
31961943
BR		 1455 case ATA_CMD_FPDMA_READ:
1456 case ATA_CMD_FPDMA_WRITE:
8b260248 1457 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1458 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1459 break;
31961943
BR		 1460 default:
1461 /* The only other commands EDMA supports in non-queued and
1462 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1463 * of which are defined/used by Linux. If we get here, this
1464 * driver needs work.
1465 *
1466 * FIXME: modify libata to give qc_prep a return value and
1467 * return error here.
1468 */
1469 BUG_ON(tf->command);
1470 break;
1471 }
1472 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1473 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1474 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1475 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1476 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1477 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1478 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1479 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1480 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1481
e4e7b892
JG		 1482 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1483 return;
1484 mv_fill_sg(qc);
1485}
1486
1487/**
1488 * mv_qc_prep_iie - Host specific command preparation.
1489 * @qc: queued command to prepare
1490 *
1491 * This routine simply redirects to the general purpose routine
1492 * if command is not DMA. Else, it handles prep of the CRQB
1493 * (command request block), does some sanity checking, and calls
1494 * the SG load routine.
1495 *
1496 * LOCKING:
1497 * Inherited from caller.
1498 */
1499static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1500{
1501 struct ata_port *ap = qc->ap;
1502 struct mv_port_priv *pp = ap->private_data;
1503 struct mv_crqb_iie *crqb;
1504 struct ata_taskfile *tf;
a6432436 1505 unsigned in_index;
e4e7b892
JG		 1506 u32 flags = 0;
1507
138bfdd0
ML		 1508 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1509 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1510 return;
1511
e12bef50 1512 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1513 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1514 flags |= CRQB_FLAG_READ;
1515
beec7dbc 1516 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1517 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1518 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1519 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1520
bdd4ddde 1521 /* get current queue index from software */
fcfb1f77 1522 in_index = pp->req_idx;
a6432436
ML		 1523
1524 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1525 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1526 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1527 crqb->flags = cpu_to_le32(flags);
1528
1529 tf = &qc->tf;
1530 crqb->ata_cmd[0] = cpu_to_le32(
1531 (tf->command << 16) |
1532 (tf->feature << 24)
1533 );
1534 crqb->ata_cmd[1] = cpu_to_le32(
1535 (tf->lbal << 0) |
1536 (tf->lbam << 8) |
1537 (tf->lbah << 16) |
1538 (tf->device << 24)
1539 );
1540 crqb->ata_cmd[2] = cpu_to_le32(
1541 (tf->hob_lbal << 0) |
1542 (tf->hob_lbam << 8) |
1543 (tf->hob_lbah << 16) |
1544 (tf->hob_feature << 24)
1545 );
1546 crqb->ata_cmd[3] = cpu_to_le32(
1547 (tf->nsect << 0) |
1548 (tf->hob_nsect << 8)
1549 );
1550
1551 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1552 return;
31961943
BR		 1553 mv_fill_sg(qc);
1554}
1555
05b308e1
BR		 1556/**
1557 * mv_qc_issue - Initiate a command to the host
1558 * @qc: queued command to start
1559 *
1560 * This routine simply redirects to the general purpose routine
1561 * if command is not DMA. Else, it sanity checks our local
1562 * caches of the request producer/consumer indices then enables
1563 * DMA and bumps the request producer index.
1564 *
1565 * LOCKING:
1566 * Inherited from caller.
1567 */
9a3d9eb0 1568static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1569{
f48765cc 1570 static int limit_warnings = 10;
c5d3e45a
JG		 1571 struct ata_port *ap = qc->ap;
1572 void __iomem *port_mmio = mv_ap_base(ap);
1573 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1574 u32 in_index;
f48765cc
ML		 1575 unsigned int port_irqs = DONE_IRQ | ERR_IRQ;
1576
1577 switch (qc->tf.protocol) {
1578 case ATA_PROT_DMA:
1579 case ATA_PROT_NCQ:
1580 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
1581 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1582 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1583
1584 /* Write the request in pointer to kick the EDMA to life */
1585 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1586 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1587 return 0;
31961943 1588
f48765cc 1589 case ATA_PROT_PIO:
c6112bd8
ML		 1590 /*
1591 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1592 *
1593 * Someday, we might implement special polling workarounds
1594 * for these, but it all seems rather unnecessary since we
1595 * normally use only DMA for commands which transfer more
1596 * than a single block of data.
1597 *
1598 * Much of the time, this could just work regardless.
1599 * So for now, just log the incident, and allow the attempt.
1600 */
c7843e8f 1601 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
c6112bd8
ML		 1602 --limit_warnings;
1603 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1604 ": attempting PIO w/multiple DRQ: "
1605 "this may fail due to h/w errata\n");
1606 }
f48765cc
ML		 1607 /* drop through */
1608 case ATAPI_PROT_PIO:
1609 port_irqs = ERR_IRQ; /* leave DONE_IRQ masked for PIO */
1610 /* drop through */
1611 default:
17c5aab5
ML		 1612 /*
1613 * We're about to send a non-EDMA capable command to the
31961943
BR		 1614 * port. Turn off EDMA so there won't be problems accessing
1615 * shadow block, etc registers.
1616 */
b562468c 1617 mv_stop_edma(ap);
f48765cc
ML		 1618 mv_edma_cfg(ap, 0, 0);
1619 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
e49856d8 1620 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1621 return ata_sff_qc_issue(qc);
31961943 1622 }
31961943
BR		 1623}
1624
8f767f8a
ML		 1625static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1626{
1627 struct mv_port_priv *pp = ap->private_data;
1628 struct ata_queued_cmd *qc;
1629
1630 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1631 return NULL;
1632 qc = ata_qc_from_tag(ap, ap->link.active_tag);
95db5051
ML		 1633 if (qc) {
1634 if (qc->tf.flags & ATA_TFLAG_POLLING)
1635 qc = NULL;
1636 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
1637 qc = NULL;
1638 }
8f767f8a
ML		 1639 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1640 qc = NULL;
1641 return qc;
1642}
1643
29d187bb
ML		 1644static void mv_pmp_error_handler(struct ata_port *ap)
1645{
1646 unsigned int pmp, pmp_map;
1647 struct mv_port_priv *pp = ap->private_data;
1648
1649 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1650 /*
1651 * Perform NCQ error analysis on failed PMPs
1652 * before we freeze the port entirely.
1653 *
1654 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1655 */
1656 pmp_map = pp->delayed_eh_pmp_map;
1657 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1658 for (pmp = 0; pmp_map != 0; pmp++) {
1659 unsigned int this_pmp = (1 << pmp);
1660 if (pmp_map & this_pmp) {
1661 struct ata_link *link = &ap->pmp_link[pmp];
1662 pmp_map &= ~this_pmp;
1663 ata_eh_analyze_ncq_error(link);
1664 }
1665 }
1666 ata_port_freeze(ap);
1667 }
1668 sata_pmp_error_handler(ap);
1669}
1670
4c299ca3
ML		 1671static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1672{
1673 void __iomem *port_mmio = mv_ap_base(ap);
1674
1675 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1676}
1677
4c299ca3
ML		 1678static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1679{
1680 struct ata_eh_info *ehi;
1681 unsigned int pmp;
1682
1683 /*
1684 * Initialize EH info for PMPs which saw device errors
1685 */
1686 ehi = &ap->link.eh_info;
1687 for (pmp = 0; pmp_map != 0; pmp++) {
1688 unsigned int this_pmp = (1 << pmp);
1689 if (pmp_map & this_pmp) {
1690 struct ata_link *link = &ap->pmp_link[pmp];
1691
1692 pmp_map &= ~this_pmp;
1693 ehi = &link->eh_info;
1694 ata_ehi_clear_desc(ehi);
1695 ata_ehi_push_desc(ehi, "dev err");
1696 ehi->err_mask |= AC_ERR_DEV;
1697 ehi->action |= ATA_EH_RESET;
1698 ata_link_abort(link);
1699 }
1700 }
1701}
1702
06aaca3f
ML		 1703static int mv_req_q_empty(struct ata_port *ap)
1704{
1705 void __iomem *port_mmio = mv_ap_base(ap);
1706 u32 in_ptr, out_ptr;
1707
1708 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1709 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1710 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1711 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1712 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1713}
1714
4c299ca3
ML		 1715static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1716{
1717 struct mv_port_priv *pp = ap->private_data;
1718 int failed_links;
1719 unsigned int old_map, new_map;
1720
1721 /*
1722 * Device error during FBS+NCQ operation:
1723 *
1724 * Set a port flag to prevent further I/O being enqueued.
1725 * Leave the EDMA running to drain outstanding commands from this port.
1726 * Perform the post-mortem/EH only when all responses are complete.
1727 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1728 */
1729 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1730 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1731 pp->delayed_eh_pmp_map = 0;
1732 }
1733 old_map = pp->delayed_eh_pmp_map;
1734 new_map = old_map | mv_get_err_pmp_map(ap);
1735
1736 if (old_map != new_map) {
1737 pp->delayed_eh_pmp_map = new_map;
1738 mv_pmp_eh_prep(ap, new_map & ~old_map);
1739 }
c46938cc 1740 failed_links = hweight16(new_map);
4c299ca3
ML		 1741
1742 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1743 "failed_links=%d nr_active_links=%d\n",
1744 __func__, pp->delayed_eh_pmp_map,
1745 ap->qc_active, failed_links,
1746 ap->nr_active_links);
1747
06aaca3f 1748 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 1749 mv_process_crpb_entries(ap, pp);
1750 mv_stop_edma(ap);
1751 mv_eh_freeze(ap);
1752 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1753 return 1; /* handled */
1754 }
1755 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1756 return 1; /* handled */
1757}
1758
1759static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1760{
1761 /*
1762 * Possible future enhancement:
1763 *
1764 * FBS+non-NCQ operation is not yet implemented.
1765 * See related notes in mv_edma_cfg().
1766 *
1767 * Device error during FBS+non-NCQ operation:
1768 *
1769 * We need to snapshot the shadow registers for each failed command.
1770 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1771 */
1772 return 0; /* not handled */
1773}
1774
1775static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1776{
1777 struct mv_port_priv *pp = ap->private_data;
1778
1779 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1780 return 0; /* EDMA was not active: not handled */
1781 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1782 return 0; /* FBS was not active: not handled */
1783
1784 if (!(edma_err_cause & EDMA_ERR_DEV))
1785 return 0; /* non DEV error: not handled */
1786 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1787 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1788 return 0; /* other problems: not handled */
1789
1790 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1791 /*
1792 * EDMA should NOT have self-disabled for this case.
1793 * If it did, then something is wrong elsewhere,
1794 * and we cannot handle it here.
1795 */
1796 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1797 ata_port_printk(ap, KERN_WARNING,
1798 "%s: err_cause=0x%x pp_flags=0x%x\n",
1799 __func__, edma_err_cause, pp->pp_flags);
1800 return 0; /* not handled */
1801 }
1802 return mv_handle_fbs_ncq_dev_err(ap);
1803 } else {
1804 /*
1805 * EDMA should have self-disabled for this case.
1806 * If it did not, then something is wrong elsewhere,
1807 * and we cannot handle it here.
1808 */
1809 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1810 ata_port_printk(ap, KERN_WARNING,
1811 "%s: err_cause=0x%x pp_flags=0x%x\n",
1812 __func__, edma_err_cause, pp->pp_flags);
1813 return 0; /* not handled */
1814 }
1815 return mv_handle_fbs_non_ncq_dev_err(ap);
1816 }
1817 return 0; /* not handled */
1818}
1819
a9010329 1820static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 1821{
8f767f8a 1822 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 1823 char *when = "idle";
8f767f8a 1824
8f767f8a 1825 ata_ehi_clear_desc(ehi);
a9010329
ML		 1826 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1827 when = "disabled";
1828 } else if (edma_was_enabled) {
1829 when = "EDMA enabled";
8f767f8a
ML		 1830 } else {
1831 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1832 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 1833 when = "polling";
8f767f8a 1834 }
a9010329 1835 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 1836 ehi->err_mask |= AC_ERR_OTHER;
1837 ehi->action |= ATA_EH_RESET;
1838 ata_port_freeze(ap);
1839}
1840
05b308e1
BR		 1841/**
1842 * mv_err_intr - Handle error interrupts on the port
1843 * @ap: ATA channel to manipulate
1844 *
8d07379d
ML		 1845 * Most cases require a full reset of the chip's state machine,
1846 * which also performs a COMRESET.
1847 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1848 *
1849 * LOCKING:
1850 * Inherited from caller.
1851 */
37b9046a 1852static void mv_err_intr(struct ata_port *ap)
31961943
BR		 1853{
1854 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 1855 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 1856 u32 fis_cause = 0;
bdd4ddde
JG		 1857 struct mv_port_priv *pp = ap->private_data;
1858 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1859 unsigned int action = 0, err_mask = 0;
9af5c9c9 1860 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 1861 struct ata_queued_cmd *qc;
1862 int abort = 0;
20f733e7 1863
8d07379d 1864 /*
37b9046a 1865 * Read and clear the SError and err_cause bits.
e4006077
ML		 1866 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1867 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 1868 */
37b9046a
ML		 1869 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1870 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1871
bdd4ddde 1872 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
e4006077
ML		 1873 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1874 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1875 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1876 }
8d07379d 1877 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1878
4c299ca3
ML		 1879 if (edma_err_cause & EDMA_ERR_DEV) {
1880 /*
1881 * Device errors during FIS-based switching operation
1882 * require special handling.
1883 */
1884 if (mv_handle_dev_err(ap, edma_err_cause))
1885 return;
1886 }
1887
37b9046a
ML		 1888 qc = mv_get_active_qc(ap);
1889 ata_ehi_clear_desc(ehi);
1890 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1891 edma_err_cause, pp->pp_flags);
e4006077 1892
c443c500 1893 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 1894 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
c443c500
ML		 1895 if (fis_cause & SATA_FIS_IRQ_AN) {
1896 u32 ec = edma_err_cause &
1897 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1898 sata_async_notification(ap);
1899 if (!ec)
1900 return; /* Just an AN; no need for the nukes */
1901 ata_ehi_push_desc(ehi, "SDB notify");
1902 }
1903 }
bdd4ddde 1904 /*
352fab70 1905 * All generations share these EDMA error cause bits:
bdd4ddde 1906 */
37b9046a 1907 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 1908 err_mask |= AC_ERR_DEV;
37b9046a
ML		 1909 action |= ATA_EH_RESET;
1910 ata_ehi_push_desc(ehi, "dev error");
1911 }
bdd4ddde 1912 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1913 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1914 EDMA_ERR_INTRL_PAR)) {
1915 err_mask |= AC_ERR_ATA_BUS;
cf480626 1916 action |= ATA_EH_RESET;
b64bbc39 1917 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1918 }
1919 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1920 ata_ehi_hotplugged(ehi);
1921 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1922 "dev disconnect" : "dev connect");
cf480626 1923 action |= ATA_EH_RESET;
bdd4ddde
JG		 1924 }
1925
352fab70
ML		 1926 /*
1927 * Gen-I has a different SELF_DIS bit,
1928 * different FREEZE bits, and no SERR bit:
1929 */
ee9ccdf7 1930 if (IS_GEN_I(hpriv)) {
bdd4ddde 1931 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1932 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1933 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1934 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1935 }
1936 } else {
1937 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1938 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1939 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1940 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1941 }
bdd4ddde 1942 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1943 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1944 err_mask |= AC_ERR_ATA_BUS;
cf480626 1945 action |= ATA_EH_RESET;
bdd4ddde 1946 }
afb0edd9 1947 }
20f733e7 1948
bdd4ddde
JG		 1949 if (!err_mask) {
1950 err_mask = AC_ERR_OTHER;
cf480626 1951 action |= ATA_EH_RESET;
bdd4ddde
JG		 1952 }
1953
1954 ehi->serror |= serr;
1955 ehi->action |= action;
1956
1957 if (qc)
1958 qc->err_mask |= err_mask;
1959 else
1960 ehi->err_mask |= err_mask;
1961
37b9046a
ML		 1962 if (err_mask == AC_ERR_DEV) {
1963 /*
1964 * Cannot do ata_port_freeze() here,
1965 * because it would kill PIO access,
1966 * which is needed for further diagnosis.
1967 */
1968 mv_eh_freeze(ap);
1969 abort = 1;
1970 } else if (edma_err_cause & eh_freeze_mask) {
1971 /*
1972 * Note to self: ata_port_freeze() calls ata_port_abort()
1973 */
bdd4ddde 1974 ata_port_freeze(ap);
37b9046a
ML		 1975 } else {
1976 abort = 1;
1977 }
1978
1979 if (abort) {
1980 if (qc)
1981 ata_link_abort(qc->dev->link);
1982 else
1983 ata_port_abort(ap);
1984 }
bdd4ddde
JG		 1985}
1986
fcfb1f77
ML		 1987static void mv_process_crpb_response(struct ata_port *ap,
1988 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1989{
1990 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1991
1992 if (qc) {
1993 u8 ata_status;
1994 u16 edma_status = le16_to_cpu(response->flags);
1995 /*
1996 * edma_status from a response queue entry:
1997 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1998 * MSB is saved ATA status from command completion.
1999 */
2000 if (!ncq_enabled) {
2001 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2002 if (err_cause) {
2003 /*
2004 * Error will be seen/handled by mv_err_intr().
2005 * So do nothing at all here.
2006 */
2007 return;
2008 }
2009 }
2010 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 2011 if (!ac_err_mask(ata_status))
2012 ata_qc_complete(qc);
2013 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 2014 } else {
2015 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2016 __func__, tag);
2017 }
2018}
2019
2020static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2021{
2022 void __iomem *port_mmio = mv_ap_base(ap);
2023 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2024 u32 in_index;
bdd4ddde 2025 bool work_done = false;
fcfb1f77 2026 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2027
fcfb1f77 2028 /* Get the hardware queue position index */
bdd4ddde
JG		 2029 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2030 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2031
fcfb1f77
ML		 2032 /* Process new responses from since the last time we looked */
2033 while (in_index != pp->resp_idx) {
6c1153e0 2034 unsigned int tag;
fcfb1f77 2035 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2036
fcfb1f77 2037 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2038
fcfb1f77
ML		 2039 if (IS_GEN_I(hpriv)) {
2040 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2041 tag = ap->link.active_tag;
fcfb1f77
ML		 2042 } else {
2043 /* Gen II/IIE: get command tag from CRPB entry */
2044 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2045 }
fcfb1f77 2046 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2047 work_done = true;
bdd4ddde
JG		 2048 }
2049
352fab70 2050 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2051 if (work_done)
2052 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2053 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2054 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2055}
2056
a9010329
ML		 2057static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2058{
2059 struct mv_port_priv *pp;
2060 int edma_was_enabled;
2061
2062 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2063 mv_unexpected_intr(ap, 0);
2064 return;
2065 }
2066 /*
2067 * Grab a snapshot of the EDMA_EN flag setting,
2068 * so that we have a consistent view for this port,
2069 * even if something we call of our routines changes it.
2070 */
2071 pp = ap->private_data;
2072 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2073 /*
2074 * Process completed CRPB response(s) before other events.
2075 */
2076 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2077 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2078 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2079 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2080 }
2081 /*
2082 * Handle chip-reported errors, or continue on to handle PIO.
2083 */
2084 if (unlikely(port_cause & ERR_IRQ)) {
2085 mv_err_intr(ap);
2086 } else if (!edma_was_enabled) {
2087 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2088 if (qc)
2089 ata_sff_host_intr(ap, qc);
2090 else
2091 mv_unexpected_intr(ap, edma_was_enabled);
2092 }
2093}
2094
05b308e1
BR		 2095/**
2096 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2097 * @host: host specific structure
7368f919 2098 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2099 *
2100 * LOCKING:
2101 * Inherited from caller.
2102 */
7368f919 2103static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2104{
f351b2d6 2105 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2106 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2107 unsigned int handled = 0, port;
20f733e7 2108
a3718c1f 2109 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2110 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2111 unsigned int p, shift, hardport, port_cause;
2112
a3718c1f 2113 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2114 /*
eabd5eb1
ML		 2115 * Each hc within the host has its own hc_irq_cause register,
2116 * where the interrupting ports bits get ack'd.
a3718c1f 2117 */
eabd5eb1
ML		 2118 if (hardport == 0) { /* first port on this hc ? */
2119 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2120 u32 port_mask, ack_irqs;
2121 /*
2122 * Skip this entire hc if nothing pending for any ports
2123 */
2124 if (!hc_cause) {
2125 port += MV_PORTS_PER_HC - 1;
2126 continue;
2127 }
2128 /*
2129 * We don't need/want to read the hc_irq_cause register,
2130 * because doing so hurts performance, and
2131 * main_irq_cause already gives us everything we need.
2132 *
2133 * But we do have to *write* to the hc_irq_cause to ack
2134 * the ports that we are handling this time through.
2135 *
2136 * This requires that we create a bitmap for those
2137 * ports which interrupted us, and use that bitmap
2138 * to ack (only) those ports via hc_irq_cause.
2139 */
2140 ack_irqs = 0;
2141 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2142 if ((port + p) >= hpriv->n_ports)
2143 break;
2144 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2145 if (hc_cause & port_mask)
2146 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2147 }
a3718c1f 2148 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2149 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2150 handled = 1;
2151 }
8f767f8a 2152 /*
a9010329 2153 * Handle interrupts signalled for this port:
8f767f8a 2154 */
a9010329
ML		 2155 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2156 if (port_cause)
2157 mv_port_intr(ap, port_cause);
20f733e7 2158 }
a3718c1f 2159 return handled;
20f733e7
BR		 2160}
2161
a3718c1f 2162static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2163{
02a121da 2164 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2165 struct ata_port *ap;
2166 struct ata_queued_cmd *qc;
2167 struct ata_eh_info *ehi;
2168 unsigned int i, err_mask, printed = 0;
2169 u32 err_cause;
2170
02a121da 2171 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2172
2173 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2174 err_cause);
2175
2176 DPRINTK("All regs @ PCI error\n");
2177 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2178
02a121da 2179 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2180
2181 for (i = 0; i < host->n_ports; i++) {
2182 ap = host->ports[i];
936fd732 2183 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2184 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2185 ata_ehi_clear_desc(ehi);
2186 if (!printed++)
2187 ata_ehi_push_desc(ehi,
2188 "PCI err cause 0x%08x", err_cause);
2189 err_mask = AC_ERR_HOST_BUS;
cf480626 2190 ehi->action = ATA_EH_RESET;
9af5c9c9 2191 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2192 if (qc)
2193 qc->err_mask |= err_mask;
2194 else
2195 ehi->err_mask |= err_mask;
2196
2197 ata_port_freeze(ap);
2198 }
2199 }
a3718c1f 2200 return 1; /* handled */
bdd4ddde
JG		 2201}
2202
05b308e1 2203/**
c5d3e45a 2204 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2205 * @irq: unused
2206 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2207 *
2208 * Read the read only register to determine if any host
2209 * controllers have pending interrupts. If so, call lower level
2210 * routine to handle. Also check for PCI errors which are only
2211 * reported here.
2212 *
8b260248 2213 * LOCKING:
cca3974e 2214 * This routine holds the host lock while processing pending
05b308e1
BR		 2215 * interrupts.
2216 */
7d12e780 2217static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2218{
cca3974e 2219 struct ata_host *host = dev_instance;
f351b2d6 2220 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2221 unsigned int handled = 0;
6d3c30ef 2222 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
96e2c487 2223 u32 main_irq_cause, pending_irqs;
20f733e7 2224
646a4da5 2225 spin_lock(&host->lock);
6d3c30ef
ML		 2226
2227 /* for MSI: block new interrupts while in here */
2228 if (using_msi)
2229 writel(0, hpriv->main_irq_mask_addr);
2230
7368f919 2231 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2232 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2233 /*
2234 * Deal with cases where we either have nothing pending, or have read
2235 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2236 */
a44253d2 2237 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 2238 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 2239 handled = mv_pci_error(host, hpriv->base);
2240 else
a44253d2 2241 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2242 }
6d3c30ef
ML		 2243
2244 /* for MSI: unmask; interrupt cause bits will retrigger now */
2245 if (using_msi)
2246 writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr);
2247
9d51af7b
ML		 2248 spin_unlock(&host->lock);
2249
20f733e7
BR		 2250 return IRQ_RETVAL(handled);
2251}
2252
c9d39130
JG		 2253static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2254{
2255 unsigned int ofs;
2256
2257 switch (sc_reg_in) {
2258 case SCR_STATUS:
2259 case SCR_ERROR:
2260 case SCR_CONTROL:
2261 ofs = sc_reg_in * sizeof(u32);
2262 break;
2263 default:
2264 ofs = 0xffffffffU;
2265 break;
2266 }
2267 return ofs;
2268}
2269
82ef04fb 2270static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
c9d39130 2271{
82ef04fb 2272 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2273 void __iomem *mmio = hpriv->base;
82ef04fb 2274 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2275 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2276
da3dbb17
TH		 2277 if (ofs != 0xffffffffU) {
2278 *val = readl(addr + ofs);
2279 return 0;
2280 } else
2281 return -EINVAL;
c9d39130
JG		 2282}
2283
82ef04fb 2284static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
c9d39130 2285{
82ef04fb 2286 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2287 void __iomem *mmio = hpriv->base;
82ef04fb 2288 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2289 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2290
da3dbb17 2291 if (ofs != 0xffffffffU) {
0d5ff566 2292 writelfl(val, addr + ofs);
da3dbb17
TH		 2293 return 0;
2294 } else
2295 return -EINVAL;
c9d39130
JG		 2296}
2297
7bb3c529 2298static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2299{
7bb3c529 2300 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2301 int early_5080;
2302
44c10138 2303 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2304
2305 if (!early_5080) {
2306 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2307 tmp |= (1 << 0);
2308 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2309 }
2310
7bb3c529 2311 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2312}
2313
2314static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2315{
8e7decdb 2316 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2317}
2318
47c2b677 2319static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2320 void __iomem *mmio)
2321{
c9d39130
JG		 2322 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2323 u32 tmp;
2324
2325 tmp = readl(phy_mmio + MV5_PHY_MODE);
2326
2327 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2328 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2329}
2330
47c2b677 2331static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2332{
522479fb
JG		 2333 u32 tmp;
2334
8e7decdb 2335 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2336
2337 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2338
2339 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2340 tmp |= ~(1 << 0);
2341 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2342}
2343
2a47ce06
JG		 2344static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2345 unsigned int port)
bca1c4eb 2346{
c9d39130
JG		 2347 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2348 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2349 u32 tmp;
2350 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2351
2352 if (fix_apm_sq) {
8e7decdb 2353 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2354 tmp |= (1 << 19);
8e7decdb 2355 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2356
8e7decdb 2357 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2358 tmp &= ~0x3;
2359 tmp |= 0x1;
8e7decdb 2360 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2361 }
2362
2363 tmp = readl(phy_mmio + MV5_PHY_MODE);
2364 tmp &= ~mask;
2365 tmp |= hpriv->signal[port].pre;
2366 tmp |= hpriv->signal[port].amps;
2367 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2368}
2369
c9d39130
JG		 2370
2371#undef ZERO
2372#define ZERO(reg) writel(0, port_mmio + (reg))
2373static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2374 unsigned int port)
2375{
2376 void __iomem *port_mmio = mv_port_base(mmio, port);
2377
e12bef50 2378 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2379
2380 ZERO(0x028); /* command */
2381 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2382 ZERO(0x004); /* timer */
2383 ZERO(0x008); /* irq err cause */
2384 ZERO(0x00c); /* irq err mask */
2385 ZERO(0x010); /* rq bah */
2386 ZERO(0x014); /* rq inp */
2387 ZERO(0x018); /* rq outp */
2388 ZERO(0x01c); /* respq bah */
2389 ZERO(0x024); /* respq outp */
2390 ZERO(0x020); /* respq inp */
2391 ZERO(0x02c); /* test control */
8e7decdb 2392 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2393}
2394#undef ZERO
2395
2396#define ZERO(reg) writel(0, hc_mmio + (reg))
2397static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2398 unsigned int hc)
47c2b677 2399{
c9d39130
JG		 2400 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2401 u32 tmp;
2402
2403 ZERO(0x00c);
2404 ZERO(0x010);
2405 ZERO(0x014);
2406 ZERO(0x018);
2407
2408 tmp = readl(hc_mmio + 0x20);
2409 tmp &= 0x1c1c1c1c;
2410 tmp |= 0x03030303;
2411 writel(tmp, hc_mmio + 0x20);
2412}
2413#undef ZERO
2414
2415static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2416 unsigned int n_hc)
2417{
2418 unsigned int hc, port;
2419
2420 for (hc = 0; hc < n_hc; hc++) {
2421 for (port = 0; port < MV_PORTS_PER_HC; port++)
2422 mv5_reset_hc_port(hpriv, mmio,
2423 (hc * MV_PORTS_PER_HC) + port);
2424
2425 mv5_reset_one_hc(hpriv, mmio, hc);
2426 }
2427
2428 return 0;
47c2b677
JG		 2429}
2430
101ffae2
JG		 2431#undef ZERO
2432#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2433static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2434{
02a121da 2435 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2436 u32 tmp;
2437
8e7decdb 2438 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2439 tmp &= 0xff00ffff;
8e7decdb 2440 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2441
2442 ZERO(MV_PCI_DISC_TIMER);
2443 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2444 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
101ffae2 2445 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2446 ZERO(hpriv->irq_cause_ofs);
2447 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2448 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2449 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2450 ZERO(MV_PCI_ERR_ATTRIBUTE);
2451 ZERO(MV_PCI_ERR_COMMAND);
2452}
2453#undef ZERO
2454
2455static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2456{
2457 u32 tmp;
2458
2459 mv5_reset_flash(hpriv, mmio);
2460
8e7decdb 2461 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2462 tmp &= 0x3;
2463 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2464 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2465}
2466
2467/**
2468 * mv6_reset_hc - Perform the 6xxx global soft reset
2469 * @mmio: base address of the HBA
2470 *
2471 * This routine only applies to 6xxx parts.
2472 *
2473 * LOCKING:
2474 * Inherited from caller.
2475 */
c9d39130
JG		 2476static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2477 unsigned int n_hc)
101ffae2
JG		 2478{
2479 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2480 int i, rc = 0;
2481 u32 t;
2482
2483 /* Following procedure defined in PCI "main command and status
2484 * register" table.
2485 */
2486 t = readl(reg);
2487 writel(t | STOP_PCI_MASTER, reg);
2488
2489 for (i = 0; i < 1000; i++) {
2490 udelay(1);
2491 t = readl(reg);
2dcb407e 2492 if (PCI_MASTER_EMPTY & t)
101ffae2 2493 break;
101ffae2
JG		 2494 }
2495 if (!(PCI_MASTER_EMPTY & t)) {
2496 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2497 rc = 1;
2498 goto done;
2499 }
2500
2501 /* set reset */
2502 i = 5;
2503 do {
2504 writel(t | GLOB_SFT_RST, reg);
2505 t = readl(reg);
2506 udelay(1);
2507 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2508
2509 if (!(GLOB_SFT_RST & t)) {
2510 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2511 rc = 1;
2512 goto done;
2513 }
2514
2515 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2516 i = 5;
2517 do {
2518 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2519 t = readl(reg);
2520 udelay(1);
2521 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2522
2523 if (GLOB_SFT_RST & t) {
2524 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2525 rc = 1;
2526 }
2527done:
2528 return rc;
2529}
2530
47c2b677 2531static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2532 void __iomem *mmio)
2533{
2534 void __iomem *port_mmio;
2535 u32 tmp;
2536
8e7decdb 2537 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2538 if ((tmp & (1 << 0)) == 0) {
47c2b677 2539 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2540 hpriv->signal[idx].pre = 0x1 << 5;
2541 return;
2542 }
2543
2544 port_mmio = mv_port_base(mmio, idx);
2545 tmp = readl(port_mmio + PHY_MODE2);
2546
2547 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2548 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2549}
2550
47c2b677 2551static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2552{
8e7decdb 2553 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2554}
2555
c9d39130 2556static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2557 unsigned int port)
bca1c4eb 2558{
c9d39130
JG		 2559 void __iomem *port_mmio = mv_port_base(mmio, port);
2560
bca1c4eb 2561 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2562 int fix_phy_mode2 =
2563 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2564 int fix_phy_mode4 =
47c2b677 2565 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 2566 u32 m2, m3;
47c2b677
JG		 2567
2568 if (fix_phy_mode2) {
2569 m2 = readl(port_mmio + PHY_MODE2);
2570 m2 &= ~(1 << 16);
2571 m2 |= (1 << 31);
2572 writel(m2, port_mmio + PHY_MODE2);
2573
2574 udelay(200);
2575
2576 m2 = readl(port_mmio + PHY_MODE2);
2577 m2 &= ~((1 << 16) | (1 << 31));
2578 writel(m2, port_mmio + PHY_MODE2);
2579
2580 udelay(200);
2581 }
2582
8c30a8b9
ML		 2583 /*
2584 * Gen-II/IIe PHY_MODE3 errata RM#2:
2585 * Achieves better receiver noise performance than the h/w default:
2586 */
2587 m3 = readl(port_mmio + PHY_MODE3);
2588 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb 2589
0388a8c0
ML		 2590 /* Guideline 88F5182 (GL# SATA-S11) */
2591 if (IS_SOC(hpriv))
2592 m3 &= ~0x1c;
2593
bca1c4eb 2594 if (fix_phy_mode4) {
ba069e37
ML		 2595 u32 m4 = readl(port_mmio + PHY_MODE4);
2596 /*
2597 * Enforce reserved-bit restrictions on GenIIe devices only.
2598 * For earlier chipsets, force only the internal config field
2599 * (workaround for errata FEr SATA#10 part 1).
2600 */
8c30a8b9 2601 if (IS_GEN_IIE(hpriv))
ba069e37
ML		 2602 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
2603 else
2604 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
8c30a8b9 2605 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 2606 }
b406c7a6
ML		 2607 /*
2608 * Workaround for 60x1-B2 errata SATA#13:
2609 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2610 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2611 */
2612 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2613
2614 /* Revert values of pre-emphasis and signal amps to the saved ones */
2615 m2 = readl(port_mmio + PHY_MODE2);
2616
2617 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2618 m2 |= hpriv->signal[port].amps;
2619 m2 |= hpriv->signal[port].pre;
47c2b677 2620 m2 &= ~(1 << 16);
bca1c4eb 2621
e4e7b892
JG		 2622 /* according to mvSata 3.6.1, some IIE values are fixed */
2623 if (IS_GEN_IIE(hpriv)) {
2624 m2 &= ~0xC30FF01F;
2625 m2 |= 0x0000900F;
2626 }
2627
bca1c4eb
JG		 2628 writel(m2, port_mmio + PHY_MODE2);
2629}
2630
f351b2d6
SB		 2631/* TODO: use the generic LED interface to configure the SATA Presence */
2632/* & Acitivy LEDs on the board */
2633static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2634 void __iomem *mmio)
2635{
2636 return;
2637}
2638
2639static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2640 void __iomem *mmio)
2641{
2642 void __iomem *port_mmio;
2643 u32 tmp;
2644
2645 port_mmio = mv_port_base(mmio, idx);
2646 tmp = readl(port_mmio + PHY_MODE2);
2647
2648 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2649 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2650}
2651
2652#undef ZERO
2653#define ZERO(reg) writel(0, port_mmio + (reg))
2654static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2655 void __iomem *mmio, unsigned int port)
2656{
2657 void __iomem *port_mmio = mv_port_base(mmio, port);
2658
e12bef50 2659 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2660
2661 ZERO(0x028); /* command */
2662 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2663 ZERO(0x004); /* timer */
2664 ZERO(0x008); /* irq err cause */
2665 ZERO(0x00c); /* irq err mask */
2666 ZERO(0x010); /* rq bah */
2667 ZERO(0x014); /* rq inp */
2668 ZERO(0x018); /* rq outp */
2669 ZERO(0x01c); /* respq bah */
2670 ZERO(0x024); /* respq outp */
2671 ZERO(0x020); /* respq inp */
2672 ZERO(0x02c); /* test control */
8e7decdb 2673 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2674}
2675
2676#undef ZERO
2677
2678#define ZERO(reg) writel(0, hc_mmio + (reg))
2679static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2680 void __iomem *mmio)
2681{
2682 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2683
2684 ZERO(0x00c);
2685 ZERO(0x010);
2686 ZERO(0x014);
2687
2688}
2689
2690#undef ZERO
2691
2692static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2693 void __iomem *mmio, unsigned int n_hc)
2694{
2695 unsigned int port;
2696
2697 for (port = 0; port < hpriv->n_ports; port++)
2698 mv_soc_reset_hc_port(hpriv, mmio, port);
2699
2700 mv_soc_reset_one_hc(hpriv, mmio);
2701
2702 return 0;
2703}
2704
2705static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2706 void __iomem *mmio)
2707{
2708 return;
2709}
2710
2711static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2712{
2713 return;
2714}
2715
8e7decdb 2716static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2717{
8e7decdb 2718 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2719
8e7decdb 2720 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2721 if (want_gen2i)
8e7decdb
ML		 2722 ifcfg |= (1 << 7); /* enable gen2i speed */
2723 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2724}
2725
e12bef50 2726static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2727 unsigned int port_no)
2728{
2729 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2730
8e7decdb
ML		 2731 /*
2732 * The datasheet warns against setting EDMA_RESET when EDMA is active
2733 * (but doesn't say what the problem might be). So we first try
2734 * to disable the EDMA engine before doing the EDMA_RESET operation.
2735 */
0d8be5cb 2736 mv_stop_edma_engine(port_mmio);
8e7decdb 2737 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2738
b67a1064 2739 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2740 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2741 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2742 }
b67a1064 2743 /*
8e7decdb 2744 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2745 * link, and physical layers. It resets all SATA interface registers
2746 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2747 */
8e7decdb 2748 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2749 udelay(25); /* allow reset propagation */
c9d39130
JG		 2750 writelfl(0, port_mmio + EDMA_CMD_OFS);
2751
2752 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2753
ee9ccdf7 2754 if (IS_GEN_I(hpriv))
c9d39130
JG		 2755 mdelay(1);
2756}
2757
e49856d8 2758static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2759{
e49856d8
ML		 2760 if (sata_pmp_supported(ap)) {
2761 void __iomem *port_mmio = mv_ap_base(ap);
2762 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2763 int old = reg & 0xf;
22374677 2764
e49856d8
ML		 2765 if (old != pmp) {
2766 reg = (reg & ~0xf) | pmp;
2767 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2768 }
22374677 2769 }
20f733e7
BR		 2770}
2771
e49856d8
ML		 2772static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2773 unsigned long deadline)
22374677 2774{
e49856d8
ML		 2775 mv_pmp_select(link->ap, sata_srst_pmp(link));
2776 return sata_std_hardreset(link, class, deadline);
2777}
bdd4ddde 2778
e49856d8
ML		 2779static int mv_softreset(struct ata_link *link, unsigned int *class,
2780 unsigned long deadline)
2781{
2782 mv_pmp_select(link->ap, sata_srst_pmp(link));
2783 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2784}
2785
cc0680a5 2786static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2787 unsigned long deadline)
31961943 2788{
cc0680a5 2789 struct ata_port *ap = link->ap;
bdd4ddde 2790 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2791 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2792 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2793 int rc, attempts = 0, extra = 0;
2794 u32 sstatus;
2795 bool online;
31961943 2796
e12bef50 2797 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2798 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2799
0d8be5cb
ML		 2800 /* Workaround for errata FEr SATA#10 (part 2) */
2801 do {
17c5aab5
ML		 2802 const unsigned long *timing =
2803 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2804
17c5aab5
ML		 2805 rc = sata_link_hardreset(link, timing, deadline + extra,
2806 &online, NULL);
9dcffd99 2807 rc = online ? -EAGAIN : rc;
17c5aab5 2808 if (rc)
0d8be5cb 2809 return rc;
0d8be5cb
ML		 2810 sata_scr_read(link, SCR_STATUS, &sstatus);
2811 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2812 /* Force 1.5gb/s link speed and try again */
8e7decdb 2813 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2814 if (time_after(jiffies + HZ, deadline))
2815 extra = HZ; /* only extend it once, max */
2816 }
2817 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2818
17c5aab5 2819 return rc;
bdd4ddde
JG		 2820}
2821
bdd4ddde
JG		 2822static void mv_eh_freeze(struct ata_port *ap)
2823{
1cfd19ae 2824 mv_stop_edma(ap);
c4de573b 2825 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 2826}
2827
2828static void mv_eh_thaw(struct ata_port *ap)
2829{
f351b2d6 2830 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 2831 unsigned int port = ap->port_no;
2832 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 2833 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2834 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 2835 u32 hc_irq_cause;
bdd4ddde 2836
bdd4ddde
JG		 2837 /* clear EDMA errors on this port */
2838 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2839
2840 /* clear pending irq events */
cae6edc3 2841 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1cfd19ae 2842 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde 2843
88e675e1 2844 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 2845}
2846
05b308e1
BR		 2847/**
2848 * mv_port_init - Perform some early initialization on a single port.
2849 * @port: libata data structure storing shadow register addresses
2850 * @port_mmio: base address of the port
2851 *
2852 * Initialize shadow register mmio addresses, clear outstanding
2853 * interrupts on the port, and unmask interrupts for the future
2854 * start of the port.
2855 *
2856 * LOCKING:
2857 * Inherited from caller.
2858 */
31961943 2859static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2860{
0d5ff566 2861 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2862 unsigned serr_ofs;
2863
8b260248 2864 /* PIO related setup
31961943
BR		 2865 */
2866 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2867 port->error_addr =
31961943
BR		 2868 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2869 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2870 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2871 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2872 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2873 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2874 port->status_addr =
31961943
BR		 2875 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2876 /* special case: control/altstatus doesn't have ATA_REG_ address */
2877 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2878
2879 /* unused: */
8d9db2d2 2880 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2881
31961943
BR		 2882 /* Clear any currently outstanding port interrupt conditions */
2883 serr_ofs = mv_scr_offset(SCR_ERROR);
2884 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2885 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2886
646a4da5
ML		 2887 /* unmask all non-transient EDMA error interrupts */
2888 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2889
8b260248 2890 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2891 readl(port_mmio + EDMA_CFG_OFS),
2892 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2893 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2894}
2895
616d4a98
ML		 2896static unsigned int mv_in_pcix_mode(struct ata_host *host)
2897{
2898 struct mv_host_priv *hpriv = host->private_data;
2899 void __iomem *mmio = hpriv->base;
2900 u32 reg;
2901
1f398472 2902 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98
ML		 2903 return 0; /* not PCI-X capable */
2904 reg = readl(mmio + MV_PCI_MODE_OFS);
2905 if ((reg & MV_PCI_MODE_MASK) == 0)
2906 return 0; /* conventional PCI mode */
2907 return 1; /* chip is in PCI-X mode */
2908}
2909
2910static int mv_pci_cut_through_okay(struct ata_host *host)
2911{
2912 struct mv_host_priv *hpriv = host->private_data;
2913 void __iomem *mmio = hpriv->base;
2914 u32 reg;
2915
2916 if (!mv_in_pcix_mode(host)) {
2917 reg = readl(mmio + PCI_COMMAND_OFS);
2918 if (reg & PCI_COMMAND_MRDTRIG)
2919 return 0; /* not okay */
2920 }
2921 return 1; /* okay */
2922}
2923
4447d351 2924static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2925{
4447d351
TH		 2926 struct pci_dev *pdev = to_pci_dev(host->dev);
2927 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2928 u32 hp_flags = hpriv->hp_flags;
2929
5796d1c4 2930 switch (board_idx) {
47c2b677
JG		 2931 case chip_5080:
2932 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2933 hp_flags |= MV_HP_GEN_I;
47c2b677 2934
44c10138 2935 switch (pdev->revision) {
47c2b677
JG		 2936 case 0x1:
2937 hp_flags |= MV_HP_ERRATA_50XXB0;
2938 break;
2939 case 0x3:
2940 hp_flags |= MV_HP_ERRATA_50XXB2;
2941 break;
2942 default:
2943 dev_printk(KERN_WARNING, &pdev->dev,
2944 "Applying 50XXB2 workarounds to unknown rev\n");
2945 hp_flags |= MV_HP_ERRATA_50XXB2;
2946 break;
2947 }
2948 break;
2949
bca1c4eb
JG		 2950 case chip_504x:
2951 case chip_508x:
47c2b677 2952 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2953 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2954
44c10138 2955 switch (pdev->revision) {
47c2b677
JG		 2956 case 0x0:
2957 hp_flags |= MV_HP_ERRATA_50XXB0;
2958 break;
2959 case 0x3:
2960 hp_flags |= MV_HP_ERRATA_50XXB2;
2961 break;
2962 default:
2963 dev_printk(KERN_WARNING, &pdev->dev,
2964 "Applying B2 workarounds to unknown rev\n");
2965 hp_flags |= MV_HP_ERRATA_50XXB2;
2966 break;
bca1c4eb
JG		 2967 }
2968 break;
2969
2970 case chip_604x:
2971 case chip_608x:
47c2b677 2972 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2973 hp_flags |= MV_HP_GEN_II;
47c2b677 2974
44c10138 2975 switch (pdev->revision) {
47c2b677
JG		 2976 case 0x7:
2977 hp_flags |= MV_HP_ERRATA_60X1B2;
2978 break;
2979 case 0x9:
2980 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2981 break;
2982 default:
2983 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2984 "Applying B2 workarounds to unknown rev\n");
2985 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2986 break;
2987 }
2988 break;
2989
e4e7b892 2990 case chip_7042:
616d4a98 2991 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2992 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2993 (pdev->device == 0x2300 || pdev->device == 0x2310))
2994 {
4e520033
ML		 2995 /*
2996 * Highpoint RocketRAID PCIe 23xx series cards:
2997 *
2998 * Unconfigured drives are treated as "Legacy"
2999 * by the BIOS, and it overwrites sector 8 with
3000 * a "Lgcy" metadata block prior to Linux boot.
3001 *
3002 * Configured drives (RAID or JBOD) leave sector 8
3003 * alone, but instead overwrite a high numbered
3004 * sector for the RAID metadata. This sector can
3005 * be determined exactly, by truncating the physical
3006 * drive capacity to a nice even GB value.
3007 *
3008 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3009 *
3010 * Warn the user, lest they think we're just buggy.
3011 */
3012 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3013 " BIOS CORRUPTS DATA on all attached drives,"
3014 " regardless of if/how they are configured."
3015 " BEWARE!\n");
3016 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3017 " use sectors 8-9 on \"Legacy\" drives,"
3018 " and avoid the final two gigabytes on"
3019 " all RocketRAID BIOS initialized drives.\n");
306b30f7 3020 }
8e7decdb 3021 /* drop through */
e4e7b892
JG		 3022 case chip_6042:
3023 hpriv->ops = &mv6xxx_ops;
e4e7b892 3024 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 3025 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3026 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 3027
44c10138 3028 switch (pdev->revision) {
5cf73bfb 3029 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 3030 hp_flags |= MV_HP_ERRATA_60X1C0;
3031 break;
3032 default:
3033 dev_printk(KERN_WARNING, &pdev->dev,
3034 "Applying 60X1C0 workarounds to unknown rev\n");
3035 hp_flags |= MV_HP_ERRATA_60X1C0;
3036 break;
3037 }
3038 break;
f351b2d6
SB		 3039 case chip_soc:
3040 hpriv->ops = &mv_soc_ops;
eb3a55a9
SB		 3041 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3042 MV_HP_ERRATA_60X1C0;
f351b2d6 3043 break;
e4e7b892 3044
bca1c4eb 3045 default:
f351b2d6 3046 dev_printk(KERN_ERR, host->dev,
5796d1c4 3047 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3048 return 1;
3049 }
3050
3051 hpriv->hp_flags = hp_flags;
02a121da
ML		 3052 if (hp_flags & MV_HP_PCIE) {
3053 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3054 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3055 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3056 } else {
3057 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3058 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3059 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3060 }
bca1c4eb
JG		 3061
3062 return 0;
3063}
3064
05b308e1 3065/**
47c2b677 3066 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3067 * @host: ATA host to initialize
3068 * @board_idx: controller index
05b308e1
BR		 3069 *
3070 * If possible, do an early global reset of the host. Then do
3071 * our port init and clear/unmask all/relevant host interrupts.
3072 *
3073 * LOCKING:
3074 * Inherited from caller.
3075 */
4447d351 3076static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3077{
3078 int rc = 0, n_hc, port, hc;
4447d351 3079 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3080 void __iomem *mmio = hpriv->base;
47c2b677 3081
4447d351 3082 rc = mv_chip_id(host, board_idx);
bca1c4eb 3083 if (rc)
352fab70 3084 goto done;
f351b2d6 3085
1f398472 3086 if (IS_SOC(hpriv)) {
7368f919
ML		 3087 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3088 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
1f398472
ML		 3089 } else {
3090 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3091 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3092 }
352fab70 3093
5d0fb2e7
TR		 3094 /* initialize shadow irq mask with register's value */
3095 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3096
352fab70 3097 /* global interrupt mask: 0 == mask everything */
c4de573b 3098 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3099
4447d351 3100 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3101
4447d351 3102 for (port = 0; port < host->n_ports; port++)
47c2b677 3103 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3104
c9d39130 3105 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3106 if (rc)
20f733e7 3107 goto done;
20f733e7 3108
522479fb 3109 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3110 hpriv->ops->reset_bus(host, mmio);
47c2b677 3111 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3112
4447d351 3113 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3114 struct ata_port *ap = host->ports[port];
2a47ce06 3115 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3116
3117 mv_port_init(&ap->ioaddr, port_mmio);
3118
7bb3c529 3119#ifdef CONFIG_PCI
1f398472 3120 if (!IS_SOC(hpriv)) {
f351b2d6
SB		 3121 unsigned int offset = port_mmio - mmio;
3122 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3123 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3124 }
7bb3c529 3125#endif
20f733e7
BR		 3126 }
3127
3128 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3129 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3130
3131 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3132 "(before clear)=0x%08x\n", hc,
3133 readl(hc_mmio + HC_CFG_OFS),
3134 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3135
3136 /* Clear any currently outstanding hc interrupt conditions */
3137 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3138 }
3139
6be96ac1
ML		 3140 /* Clear any currently outstanding host interrupt conditions */
3141 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3142
6be96ac1
ML		 3143 /* and unmask interrupt generation for host regs */
3144 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
51de32d2 3145
6be96ac1
ML		 3146 /*
3147 * enable only global host interrupts for now.
3148 * The per-port interrupts get done later as ports are set up.
3149 */
3150 mv_set_main_irq_mask(host, 0, PCI_ERR);
f351b2d6
SB		 3151done:
3152 return rc;
3153}
fb621e2f 3154
fbf14e2f
BB		 3155static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3156{
3157 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3158 MV_CRQB_Q_SZ, 0);
3159 if (!hpriv->crqb_pool)
3160 return -ENOMEM;
3161
3162 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3163 MV_CRPB_Q_SZ, 0);
3164 if (!hpriv->crpb_pool)
3165 return -ENOMEM;
3166
3167 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3168 MV_SG_TBL_SZ, 0);
3169 if (!hpriv->sg_tbl_pool)
3170 return -ENOMEM;
3171
3172 return 0;
3173}
3174
15a32632
LB		 3175static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3176 struct mbus_dram_target_info *dram)
3177{
3178 int i;
3179
3180 for (i = 0; i < 4; i++) {
3181 writel(0, hpriv->base + WINDOW_CTRL(i));
3182 writel(0, hpriv->base + WINDOW_BASE(i));
3183 }
3184
3185 for (i = 0; i < dram->num_cs; i++) {
3186 struct mbus_dram_window *cs = dram->cs + i;
3187
3188 writel(((cs->size - 1) & 0xffff0000) |
3189 (cs->mbus_attr << 8) |
3190 (dram->mbus_dram_target_id << 4) | 1,
3191 hpriv->base + WINDOW_CTRL(i));
3192 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3193 }
3194}
3195
f351b2d6
SB		 3196/**
3197 * mv_platform_probe - handle a positive probe of an soc Marvell
3198 * host
3199 * @pdev: platform device found
3200 *
3201 * LOCKING:
3202 * Inherited from caller.
3203 */
3204static int mv_platform_probe(struct platform_device *pdev)
3205{
3206 static int printed_version;
3207 const struct mv_sata_platform_data *mv_platform_data;
3208 const struct ata_port_info *ppi[] =
3209 { &mv_port_info[chip_soc], NULL };
3210 struct ata_host *host;
3211 struct mv_host_priv *hpriv;
3212 struct resource *res;
3213 int n_ports, rc;
20f733e7 3214
f351b2d6
SB		 3215 if (!printed_version++)
3216 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3217
f351b2d6
SB		 3218 /*
3219 * Simple resource validation ..
3220 */
3221 if (unlikely(pdev->num_resources != 2)) {
3222 dev_err(&pdev->dev, "invalid number of resources\n");
3223 return -EINVAL;
3224 }
3225
3226 /*
3227 * Get the register base first
3228 */
3229 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3230 if (res == NULL)
3231 return -EINVAL;
3232
3233 /* allocate host */
3234 mv_platform_data = pdev->dev.platform_data;
3235 n_ports = mv_platform_data->n_ports;
3236
3237 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3238 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3239
3240 if (!host || !hpriv)
3241 return -ENOMEM;
3242 host->private_data = hpriv;
3243 hpriv->n_ports = n_ports;
3244
3245 host->iomap = NULL;
f1cb0ea1
SB		 3246 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3247 res->end - res->start + 1);
f351b2d6
SB		 3248 hpriv->base -= MV_SATAHC0_REG_BASE;
3249
15a32632
LB		 3250 /*
3251 * (Re-)program MBUS remapping windows if we are asked to.
3252 */
3253 if (mv_platform_data->dram != NULL)
3254 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3255
fbf14e2f
BB		 3256 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3257 if (rc)
3258 return rc;
3259
f351b2d6
SB		 3260 /* initialize adapter */
3261 rc = mv_init_host(host, chip_soc);
3262 if (rc)
3263 return rc;
3264
3265 dev_printk(KERN_INFO, &pdev->dev,
3266 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3267 host->n_ports);
3268
3269 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3270 IRQF_SHARED, &mv6_sht);
3271}
3272
3273/*
3274 *
3275 * mv_platform_remove - unplug a platform interface
3276 * @pdev: platform device
3277 *
3278 * A platform bus SATA device has been unplugged. Perform the needed
3279 * cleanup. Also called on module unload for any active devices.
3280 */
3281static int __devexit mv_platform_remove(struct platform_device *pdev)
3282{
3283 struct device *dev = &pdev->dev;
3284 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3285
3286 ata_host_detach(host);
f351b2d6 3287 return 0;
20f733e7
BR		 3288}
3289
f351b2d6
SB		 3290static struct platform_driver mv_platform_driver = {
3291 .probe = mv_platform_probe,
3292 .remove = __devexit_p(mv_platform_remove),
3293 .driver = {
3294 .name = DRV_NAME,
3295 .owner = THIS_MODULE,
3296 },
3297};
3298
3299
7bb3c529 3300#ifdef CONFIG_PCI
f351b2d6
SB		 3301static int mv_pci_init_one(struct pci_dev *pdev,
3302 const struct pci_device_id *ent);
3303
7bb3c529
SB		 3304
3305static struct pci_driver mv_pci_driver = {
3306 .name = DRV_NAME,
3307 .id_table = mv_pci_tbl,
f351b2d6 3308 .probe = mv_pci_init_one,
7bb3c529
SB		 3309 .remove = ata_pci_remove_one,
3310};
3311
3312/*
3313 * module options
3314 */
3315static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3316
3317
3318/* move to PCI layer or libata core? */
3319static int pci_go_64(struct pci_dev *pdev)
3320{
3321 int rc;
3322
3323 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3324 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3325 if (rc) {
3326 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3327 if (rc) {
3328 dev_printk(KERN_ERR, &pdev->dev,
3329 "64-bit DMA enable failed\n");
3330 return rc;
3331 }
3332 }
3333 } else {
3334 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3335 if (rc) {
3336 dev_printk(KERN_ERR, &pdev->dev,
3337 "32-bit DMA enable failed\n");
3338 return rc;
3339 }
3340 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3341 if (rc) {
3342 dev_printk(KERN_ERR, &pdev->dev,
3343 "32-bit consistent DMA enable failed\n");
3344 return rc;
3345 }
3346 }
3347
3348 return rc;
3349}
3350
05b308e1
BR		 3351/**
3352 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3353 * @host: ATA host to print info about
05b308e1
BR		 3354 *
3355 * FIXME: complete this.
3356 *
3357 * LOCKING:
3358 * Inherited from caller.
3359 */
4447d351 3360static void mv_print_info(struct ata_host *host)
31961943 3361{
4447d351
TH		 3362 struct pci_dev *pdev = to_pci_dev(host->dev);
3363 struct mv_host_priv *hpriv = host->private_data;
44c10138 3364 u8 scc;
c1e4fe71 3365 const char *scc_s, *gen;
31961943
BR		 3366
3367 /* Use this to determine the HW stepping of the chip so we know
3368 * what errata to workaround
3369 */
31961943
BR		 3370 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3371 if (scc == 0)
3372 scc_s = "SCSI";
3373 else if (scc == 0x01)
3374 scc_s = "RAID";
3375 else
c1e4fe71
JG		 3376 scc_s = "?";
3377
3378 if (IS_GEN_I(hpriv))
3379 gen = "I";
3380 else if (IS_GEN_II(hpriv))
3381 gen = "II";
3382 else if (IS_GEN_IIE(hpriv))
3383 gen = "IIE";
3384 else
3385 gen = "?";
31961943 3386
a9524a76 3387 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3388 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3389 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3390 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3391}
3392
05b308e1 3393/**
f351b2d6 3394 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3395 * @pdev: PCI device found
3396 * @ent: PCI device ID entry for the matched host
3397 *
3398 * LOCKING:
3399 * Inherited from caller.
3400 */
f351b2d6
SB		 3401static int mv_pci_init_one(struct pci_dev *pdev,
3402 const struct pci_device_id *ent)
20f733e7 3403{
2dcb407e 3404 static int printed_version;
20f733e7 3405 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3406 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3407 struct ata_host *host;
3408 struct mv_host_priv *hpriv;
3409 int n_ports, rc;
20f733e7 3410
a9524a76
JG		 3411 if (!printed_version++)
3412 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3413
4447d351
TH		 3414 /* allocate host */
3415 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3416
3417 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3418 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3419 if (!host || !hpriv)
3420 return -ENOMEM;
3421 host->private_data = hpriv;
f351b2d6 3422 hpriv->n_ports = n_ports;
4447d351
TH		 3423
3424 /* acquire resources */
24dc5f33
TH		 3425 rc = pcim_enable_device(pdev);
3426 if (rc)
20f733e7 3427 return rc;
20f733e7 3428
0d5ff566
TH		 3429 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3430 if (rc == -EBUSY)
24dc5f33 3431 pcim_pin_device(pdev);
0d5ff566 3432 if (rc)
24dc5f33 3433 return rc;
4447d351 3434 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3435 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3436
d88184fb
JG		 3437 rc = pci_go_64(pdev);
3438 if (rc)
3439 return rc;
3440
da2fa9ba
ML		 3441 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3442 if (rc)
3443 return rc;
3444
20f733e7 3445 /* initialize adapter */
4447d351 3446 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3447 if (rc)
3448 return rc;
20f733e7 3449
6d3c30ef
ML		 3450 /* Enable message-switched interrupts, if requested */
3451 if (msi && pci_enable_msi(pdev) == 0)
3452 hpriv->hp_flags |= MV_HP_FLAG_MSI;
20f733e7 3453
31961943 3454 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3455 mv_print_info(host);
20f733e7 3456
4447d351 3457 pci_set_master(pdev);
ea8b4db9 3458 pci_try_set_mwi(pdev);
4447d351 3459 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3460 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3461}
7bb3c529 3462#endif
20f733e7 3463
f351b2d6
SB		 3464static int mv_platform_probe(struct platform_device *pdev);
3465static int __devexit mv_platform_remove(struct platform_device *pdev);
3466
20f733e7
BR		 3467static int __init mv_init(void)
3468{
7bb3c529
SB		 3469 int rc = -ENODEV;
3470#ifdef CONFIG_PCI
3471 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3472 if (rc < 0)
3473 return rc;
3474#endif
3475 rc = platform_driver_register(&mv_platform_driver);
3476
3477#ifdef CONFIG_PCI
3478 if (rc < 0)
3479 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3480#endif
3481 return rc;
20f733e7
BR		 3482}
3483
3484static void __exit mv_exit(void)
3485{
7bb3c529 3486#ifdef CONFIG_PCI
20f733e7 3487 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3488#endif
f351b2d6 3489 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3490}
3491
3492MODULE_AUTHOR("Brett Russ");
3493MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3494MODULE_LICENSE("GPL");
3495MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3496MODULE_VERSION(DRV_VERSION);
17c5aab5 3497MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3498
7bb3c529 3499#ifdef CONFIG_PCI
ddef9bb3
JG		 3500module_param(msi, int, 0444);
3501MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3502#endif
ddef9bb3 3503
20f733e7
BR		 3504module_init(mv_init);
3505module_exit(mv_exit);
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