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libata: add another IRQ calls (core and headers)
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
8b260248 4 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 5 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/init.h>
28#include <linux/blkdev.h>
29#include <linux/delay.h>
30#include <linux/interrupt.h>
31#include <linux/sched.h>
32#include <linux/dma-mapping.h>
a9524a76 33#include <linux/device.h>
20f733e7 34#include <scsi/scsi_host.h>
193515d5 35#include <scsi/scsi_cmnd.h>
20f733e7 36#include <linux/libata.h>
20f733e7
BR		 37
38#define DRV_NAME "sata_mv"
63a25355 39#define DRV_VERSION "0.7"
20f733e7
BR		 40
41enum {
42 /* BAR's are enumerated in terms of pci_resource_start() terms */
43 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
44 MV_IO_BAR = 2, /* offset 0x18: IO space */
45 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
46
47 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
48 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
49
50 MV_PCI_REG_BASE = 0,
51 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 52 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
53 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
54 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
55 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
56 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
57
20f733e7 58 MV_SATAHC0_REG_BASE = 0x20000,
522479fb 59 MV_FLASH_CTL = 0x1046c,
bca1c4eb
JG		 60 MV_GPIO_PORT_CTL = 0x104f0,
61 MV_RESET_CFG = 0x180d8,
20f733e7
BR		 62
63 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
64 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
65 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
66 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
67
31961943 68 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
20f733e7 69
31961943
BR		 70 MV_MAX_Q_DEPTH = 32,
71 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
72
73 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
74 * CRPB needs alignment on a 256B boundary. Size == 256B
75 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
76 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
77 */
78 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
79 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
80 MV_MAX_SG_CT = 176,
81 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
82 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
83
20f733e7
BR		 84 MV_PORTS_PER_HC = 4,
85 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
86 MV_PORT_HC_SHIFT = 2,
31961943 87 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
20f733e7
BR		 88 MV_PORT_MASK = 3,
89
90 /* Host Flags */
91 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
92 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
31961943 93 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
50630195 94 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
1f3461a7 95 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
47c2b677 96 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 97
31961943
BR		 98 CRQB_FLAG_READ = (1 << 0),
99 CRQB_TAG_SHIFT = 1,
100 CRQB_CMD_ADDR_SHIFT = 8,
101 CRQB_CMD_CS = (0x2 << 11),
102 CRQB_CMD_LAST = (1 << 15),
103
104 CRPB_FLAG_STATUS_SHIFT = 8,
105
106 EPRD_FLAG_END_OF_TBL = (1 << 31),
107
20f733e7
BR		 108 /* PCI interface registers */
109
31961943
BR		 110 PCI_COMMAND_OFS = 0xc00,
111
20f733e7
BR		 112 PCI_MAIN_CMD_STS_OFS = 0xd30,
113 STOP_PCI_MASTER = (1 << 2),
114 PCI_MASTER_EMPTY = (1 << 3),
115 GLOB_SFT_RST = (1 << 4),
116
522479fb
JG		 117 MV_PCI_MODE = 0xd00,
118 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
119 MV_PCI_DISC_TIMER = 0xd04,
120 MV_PCI_MSI_TRIGGER = 0xc38,
121 MV_PCI_SERR_MASK = 0xc28,
122 MV_PCI_XBAR_TMOUT = 0x1d04,
123 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
124 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
125 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
126 MV_PCI_ERR_COMMAND = 0x1d50,
127
128 PCI_IRQ_CAUSE_OFS = 0x1d58,
129 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 130 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
131
132 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
133 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
134 PORT0_ERR = (1 << 0), /* shift by port # */
135 PORT0_DONE = (1 << 1), /* shift by port # */
136 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
137 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
138 PCI_ERR = (1 << 18),
139 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
140 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
141 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
142 GPIO_INT = (1 << 22),
143 SELF_INT = (1 << 23),
144 TWSI_INT = (1 << 24),
145 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
8b260248 146 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
20f733e7
BR		 147 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
148 HC_MAIN_RSVD),
149
150 /* SATAHC registers */
151 HC_CFG_OFS = 0,
152
153 HC_IRQ_CAUSE_OFS = 0x14,
31961943 154 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
20f733e7
BR		 155 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
156 DEV_IRQ = (1 << 8), /* shift by port # */
157
158 /* Shadow block registers */
31961943
BR		 159 SHD_BLK_OFS = 0x100,
160 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 161
162 /* SATA registers */
163 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
164 SATA_ACTIVE_OFS = 0x350,
47c2b677 165 PHY_MODE3 = 0x310,
bca1c4eb
JG		 166 PHY_MODE4 = 0x314,
167 PHY_MODE2 = 0x330,
c9d39130
JG		 168 MV5_PHY_MODE = 0x74,
169 MV5_LT_MODE = 0x30,
170 MV5_PHY_CTL = 0x0C,
bca1c4eb
JG		 171 SATA_INTERFACE_CTL = 0x050,
172
173 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 174
175 /* Port registers */
176 EDMA_CFG_OFS = 0,
31961943
BR		 177 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
178 EDMA_CFG_NCQ = (1 << 5),
179 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
180 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
181 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
20f733e7
BR		 182
183 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
184 EDMA_ERR_IRQ_MASK_OFS = 0xc,
185 EDMA_ERR_D_PAR = (1 << 0),
186 EDMA_ERR_PRD_PAR = (1 << 1),
187 EDMA_ERR_DEV = (1 << 2),
188 EDMA_ERR_DEV_DCON = (1 << 3),
189 EDMA_ERR_DEV_CON = (1 << 4),
190 EDMA_ERR_SERR = (1 << 5),
191 EDMA_ERR_SELF_DIS = (1 << 7),
192 EDMA_ERR_BIST_ASYNC = (1 << 8),
193 EDMA_ERR_CRBQ_PAR = (1 << 9),
194 EDMA_ERR_CRPB_PAR = (1 << 10),
195 EDMA_ERR_INTRL_PAR = (1 << 11),
196 EDMA_ERR_IORDY = (1 << 12),
197 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
198 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
199 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
200 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
201 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
202 EDMA_ERR_TRANS_PROTO = (1 << 31),
8b260248 203 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
20f733e7
BR		 204 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
205 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
8b260248 206 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
20f733e7 207 EDMA_ERR_LNK_DATA_RX |
8b260248 208 EDMA_ERR_LNK_DATA_TX |
20f733e7
BR		 209 EDMA_ERR_TRANS_PROTO),
210
31961943
BR		 211 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
212 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 213
214 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
215 EDMA_REQ_Q_PTR_SHIFT = 5,
216
217 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
218 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
219 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 220 EDMA_RSP_Q_PTR_SHIFT = 3,
221
20f733e7
BR		 222 EDMA_CMD_OFS = 0x28,
223 EDMA_EN = (1 << 0),
224 EDMA_DS = (1 << 1),
225 ATA_RST = (1 << 2),
226
c9d39130 227 EDMA_IORDY_TMOUT = 0x34,
bca1c4eb 228 EDMA_ARB_CFG = 0x38,
bca1c4eb 229
31961943
BR		 230 /* Host private flags (hp_flags) */
231 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 232 MV_HP_ERRATA_50XXB0 = (1 << 1),
233 MV_HP_ERRATA_50XXB2 = (1 << 2),
234 MV_HP_ERRATA_60X1B2 = (1 << 3),
235 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892
JG		 236 MV_HP_ERRATA_XX42A0 = (1 << 5),
237 MV_HP_50XX = (1 << 6),
238 MV_HP_GEN_IIE = (1 << 7),
20f733e7 239
31961943
BR		 240 /* Port private flags (pp_flags) */
241 MV_PP_FLAG_EDMA_EN = (1 << 0),
242 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
20f733e7
BR		 243};
244
c9d39130 245#define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
bca1c4eb 246#define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
e4e7b892
JG		 247#define IS_GEN_I(hpriv) IS_50XX(hpriv)
248#define IS_GEN_II(hpriv) IS_60XX(hpriv)
249#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
bca1c4eb 250
095fec88
JG		 251enum {
252 /* Our DMA boundary is determined by an ePRD being unable to handle
253 * anything larger than 64KB
254 */
255 MV_DMA_BOUNDARY = 0xffffU,
256
257 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
258
259 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
260};
261
522479fb
JG		 262enum chip_type {
263 chip_504x,
264 chip_508x,
265 chip_5080,
266 chip_604x,
267 chip_608x,
e4e7b892
JG		 268 chip_6042,
269 chip_7042,
522479fb
JG		 270};
271
31961943
BR		 272/* Command ReQuest Block: 32B */
273struct mv_crqb {
e1469874
ML		 274 __le32 sg_addr;
275 __le32 sg_addr_hi;
276 __le16 ctrl_flags;
277 __le16 ata_cmd[11];
31961943 278};
20f733e7 279
e4e7b892 280struct mv_crqb_iie {
e1469874
ML		 281 __le32 addr;
282 __le32 addr_hi;
283 __le32 flags;
284 __le32 len;
285 __le32 ata_cmd[4];
e4e7b892
JG		 286};
287
31961943
BR		 288/* Command ResPonse Block: 8B */
289struct mv_crpb {
e1469874
ML		 290 __le16 id;
291 __le16 flags;
292 __le32 tmstmp;
20f733e7
BR		 293};
294
31961943
BR		 295/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
296struct mv_sg {
e1469874
ML		 297 __le32 addr;
298 __le32 flags_size;
299 __le32 addr_hi;
300 __le32 reserved;
31961943 301};
20f733e7 302
31961943
BR		 303struct mv_port_priv {
304 struct mv_crqb *crqb;
305 dma_addr_t crqb_dma;
306 struct mv_crpb *crpb;
307 dma_addr_t crpb_dma;
308 struct mv_sg *sg_tbl;
309 dma_addr_t sg_tbl_dma;
31961943
BR		 310 u32 pp_flags;
311};
312
bca1c4eb
JG		 313struct mv_port_signal {
314 u32 amps;
315 u32 pre;
316};
317
47c2b677
JG		 318struct mv_host_priv;
319struct mv_hw_ops {
2a47ce06
JG		 320 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
321 unsigned int port);
47c2b677
JG		 322 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
323 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
324 void __iomem *mmio);
c9d39130
JG		 325 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
326 unsigned int n_hc);
522479fb
JG		 327 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
328 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
47c2b677
JG		 329};
330
31961943
BR		 331struct mv_host_priv {
332 u32 hp_flags;
bca1c4eb 333 struct mv_port_signal signal[8];
47c2b677 334 const struct mv_hw_ops *ops;
20f733e7
BR		 335};
336
337static void mv_irq_clear(struct ata_port *ap);
338static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
339static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
c9d39130
JG		 340static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
341static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
20f733e7 342static void mv_phy_reset(struct ata_port *ap);
22374677 343static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
31961943
BR		 344static int mv_port_start(struct ata_port *ap);
345static void mv_port_stop(struct ata_port *ap);
346static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 347static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 348static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
7d12e780 349static irqreturn_t mv_interrupt(int irq, void *dev_instance);
31961943 350static void mv_eng_timeout(struct ata_port *ap);
20f733e7
BR		 351static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
352
2a47ce06
JG		 353static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
354 unsigned int port);
47c2b677
JG		 355static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
356static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
357 void __iomem *mmio);
c9d39130
JG		 358static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
359 unsigned int n_hc);
522479fb
JG		 360static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
361static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
47c2b677 362
2a47ce06
JG		 363static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
364 unsigned int port);
47c2b677
JG		 365static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
366static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
367 void __iomem *mmio);
c9d39130
JG		 368static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
369 unsigned int n_hc);
522479fb
JG		 370static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
371static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
c9d39130
JG		 372static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
373 unsigned int port_no);
374static void mv_stop_and_reset(struct ata_port *ap);
47c2b677 375
193515d5 376static struct scsi_host_template mv_sht = {
20f733e7
BR		 377 .module = THIS_MODULE,
378 .name = DRV_NAME,
379 .ioctl = ata_scsi_ioctl,
380 .queuecommand = ata_scsi_queuecmd,
31961943 381 .can_queue = MV_USE_Q_DEPTH,
20f733e7 382 .this_id = ATA_SHT_THIS_ID,
22374677 383 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7
BR		 384 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
385 .emulated = ATA_SHT_EMULATED,
31961943 386 .use_clustering = ATA_SHT_USE_CLUSTERING,
20f733e7
BR		 387 .proc_name = DRV_NAME,
388 .dma_boundary = MV_DMA_BOUNDARY,
389 .slave_configure = ata_scsi_slave_config,
ccf68c34 390 .slave_destroy = ata_scsi_slave_destroy,
20f733e7 391 .bios_param = ata_std_bios_param,
20f733e7
BR		 392};
393
c9d39130
JG		 394static const struct ata_port_operations mv5_ops = {
395 .port_disable = ata_port_disable,
396
397 .tf_load = ata_tf_load,
398 .tf_read = ata_tf_read,
399 .check_status = ata_check_status,
400 .exec_command = ata_exec_command,
401 .dev_select = ata_std_dev_select,
402
403 .phy_reset = mv_phy_reset,
404
405 .qc_prep = mv_qc_prep,
406 .qc_issue = mv_qc_issue,
0d5ff566 407 .data_xfer = ata_data_xfer,
c9d39130
JG		 408
409 .eng_timeout = mv_eng_timeout,
410
411 .irq_handler = mv_interrupt,
412 .irq_clear = mv_irq_clear,
413
414 .scr_read = mv5_scr_read,
415 .scr_write = mv5_scr_write,
416
417 .port_start = mv_port_start,
418 .port_stop = mv_port_stop,
c9d39130
JG		 419};
420
421static const struct ata_port_operations mv6_ops = {
20f733e7
BR		 422 .port_disable = ata_port_disable,
423
424 .tf_load = ata_tf_load,
425 .tf_read = ata_tf_read,
426 .check_status = ata_check_status,
427 .exec_command = ata_exec_command,
428 .dev_select = ata_std_dev_select,
429
430 .phy_reset = mv_phy_reset,
431
31961943
BR		 432 .qc_prep = mv_qc_prep,
433 .qc_issue = mv_qc_issue,
0d5ff566 434 .data_xfer = ata_data_xfer,
20f733e7 435
31961943 436 .eng_timeout = mv_eng_timeout,
20f733e7
BR		 437
438 .irq_handler = mv_interrupt,
439 .irq_clear = mv_irq_clear,
440
441 .scr_read = mv_scr_read,
442 .scr_write = mv_scr_write,
443
31961943
BR		 444 .port_start = mv_port_start,
445 .port_stop = mv_port_stop,
20f733e7
BR		 446};
447
e4e7b892
JG		 448static const struct ata_port_operations mv_iie_ops = {
449 .port_disable = ata_port_disable,
450
451 .tf_load = ata_tf_load,
452 .tf_read = ata_tf_read,
453 .check_status = ata_check_status,
454 .exec_command = ata_exec_command,
455 .dev_select = ata_std_dev_select,
456
457 .phy_reset = mv_phy_reset,
458
459 .qc_prep = mv_qc_prep_iie,
460 .qc_issue = mv_qc_issue,
0d5ff566 461 .data_xfer = ata_data_xfer,
e4e7b892
JG		 462
463 .eng_timeout = mv_eng_timeout,
464
465 .irq_handler = mv_interrupt,
466 .irq_clear = mv_irq_clear,
467
468 .scr_read = mv_scr_read,
469 .scr_write = mv_scr_write,
470
471 .port_start = mv_port_start,
472 .port_stop = mv_port_stop,
e4e7b892
JG		 473};
474
98ac62de 475static const struct ata_port_info mv_port_info[] = {
20f733e7
BR		 476 { /* chip_504x */
477 .sht = &mv_sht,
cca3974e 478 .flags = MV_COMMON_FLAGS,
31961943 479 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 480 .udma_mask = 0x7f, /* udma0-6 */
481 .port_ops = &mv5_ops,
20f733e7
BR		 482 },
483 { /* chip_508x */
484 .sht = &mv_sht,
cca3974e 485 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
31961943 486 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 487 .udma_mask = 0x7f, /* udma0-6 */
488 .port_ops = &mv5_ops,
20f733e7 489 },
47c2b677
JG		 490 { /* chip_5080 */
491 .sht = &mv_sht,
cca3974e 492 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
47c2b677 493 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 494 .udma_mask = 0x7f, /* udma0-6 */
495 .port_ops = &mv5_ops,
47c2b677 496 },
20f733e7
BR		 497 { /* chip_604x */
498 .sht = &mv_sht,
cca3974e 499 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
31961943
BR		 500 .pio_mask = 0x1f, /* pio0-4 */
501 .udma_mask = 0x7f, /* udma0-6 */
c9d39130 502 .port_ops = &mv6_ops,
20f733e7
BR		 503 },
504 { /* chip_608x */
505 .sht = &mv_sht,
cca3974e 506 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
31961943
BR		 507 MV_FLAG_DUAL_HC),
508 .pio_mask = 0x1f, /* pio0-4 */
509 .udma_mask = 0x7f, /* udma0-6 */
c9d39130 510 .port_ops = &mv6_ops,
20f733e7 511 },
e4e7b892
JG		 512 { /* chip_6042 */
513 .sht = &mv_sht,
cca3974e 514 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
e4e7b892
JG		 515 .pio_mask = 0x1f, /* pio0-4 */
516 .udma_mask = 0x7f, /* udma0-6 */
517 .port_ops = &mv_iie_ops,
518 },
519 { /* chip_7042 */
520 .sht = &mv_sht,
e93f09dc 521 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
e4e7b892
JG		 522 .pio_mask = 0x1f, /* pio0-4 */
523 .udma_mask = 0x7f, /* udma0-6 */
524 .port_ops = &mv_iie_ops,
525 },
20f733e7
BR		 526};
527
3b7d697d 528static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 529 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
530 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
531 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
532 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
533
534 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
535 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
536 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
537 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
538 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
539
540 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
541
e93f09dc
OJ		 542 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
543
2d2744fc 544 { } /* terminate list */
20f733e7
BR		 545};
546
547static struct pci_driver mv_pci_driver = {
548 .name = DRV_NAME,
549 .id_table = mv_pci_tbl,
550 .probe = mv_init_one,
551 .remove = ata_pci_remove_one,
552};
553
47c2b677
JG		 554static const struct mv_hw_ops mv5xxx_ops = {
555 .phy_errata = mv5_phy_errata,
556 .enable_leds = mv5_enable_leds,
557 .read_preamp = mv5_read_preamp,
558 .reset_hc = mv5_reset_hc,
522479fb
JG		 559 .reset_flash = mv5_reset_flash,
560 .reset_bus = mv5_reset_bus,
47c2b677
JG		 561};
562
563static const struct mv_hw_ops mv6xxx_ops = {
564 .phy_errata = mv6_phy_errata,
565 .enable_leds = mv6_enable_leds,
566 .read_preamp = mv6_read_preamp,
567 .reset_hc = mv6_reset_hc,
522479fb
JG		 568 .reset_flash = mv6_reset_flash,
569 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 570};
571
ddef9bb3
JG		 572/*
573 * module options
574 */
575static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
576
577
20f733e7
BR		 578/*
579 * Functions
580 */
581
582static inline void writelfl(unsigned long data, void __iomem *addr)
583{
584 writel(data, addr);
585 (void) readl(addr); /* flush to avoid PCI posted write */
586}
587
20f733e7
BR		 588static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
589{
590 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
591}
592
c9d39130
JG		 593static inline unsigned int mv_hc_from_port(unsigned int port)
594{
595 return port >> MV_PORT_HC_SHIFT;
596}
597
598static inline unsigned int mv_hardport_from_port(unsigned int port)
599{
600 return port & MV_PORT_MASK;
601}
602
603static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
604 unsigned int port)
605{
606 return mv_hc_base(base, mv_hc_from_port(port));
607}
608
20f733e7
BR		 609static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
610{
c9d39130 611 return mv_hc_base_from_port(base, port) +
8b260248 612 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 613 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 614}
615
616static inline void __iomem *mv_ap_base(struct ata_port *ap)
617{
0d5ff566 618 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
20f733e7
BR		 619}
620
cca3974e 621static inline int mv_get_hc_count(unsigned long port_flags)
31961943 622{
cca3974e 623 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 624}
625
626static void mv_irq_clear(struct ata_port *ap)
20f733e7 627{
20f733e7
BR		 628}
629
05b308e1
BR		 630/**
631 * mv_start_dma - Enable eDMA engine
632 * @base: port base address
633 * @pp: port private data
634 *
beec7dbc
TH		 635 * Verify the local cache of the eDMA state is accurate with a
636 * WARN_ON.
05b308e1
BR		 637 *
638 * LOCKING:
639 * Inherited from caller.
640 */
afb0edd9 641static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
20f733e7 642{
afb0edd9
BR		 643 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
644 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
645 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
646 }
beec7dbc 647 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
20f733e7
BR		 648}
649
05b308e1
BR		 650/**
651 * mv_stop_dma - Disable eDMA engine
652 * @ap: ATA channel to manipulate
653 *
beec7dbc
TH		 654 * Verify the local cache of the eDMA state is accurate with a
655 * WARN_ON.
05b308e1
BR		 656 *
657 * LOCKING:
658 * Inherited from caller.
659 */
31961943 660static void mv_stop_dma(struct ata_port *ap)
20f733e7 661{
31961943
BR		 662 void __iomem *port_mmio = mv_ap_base(ap);
663 struct mv_port_priv *pp = ap->private_data;
31961943
BR		 664 u32 reg;
665 int i;
666
afb0edd9
BR		 667 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
668 /* Disable EDMA if active. The disable bit auto clears.
31961943 669 */
31961943
BR		 670 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
671 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
afb0edd9 672 } else {
beec7dbc 673 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
afb0edd9 674 }
8b260248 675
31961943
BR		 676 /* now properly wait for the eDMA to stop */
677 for (i = 1000; i > 0; i--) {
678 reg = readl(port_mmio + EDMA_CMD_OFS);
679 if (!(EDMA_EN & reg)) {
680 break;
681 }
682 udelay(100);
683 }
684
31961943 685 if (EDMA_EN & reg) {
f15a1daf 686 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
afb0edd9 687 /* FIXME: Consider doing a reset here to recover */
31961943 688 }
20f733e7
BR		 689}
690
8a70f8dc 691#ifdef ATA_DEBUG
31961943 692static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 693{
31961943
BR		 694 int b, w;
695 for (b = 0; b < bytes; ) {
696 DPRINTK("%p: ", start + b);
697 for (w = 0; b < bytes && w < 4; w++) {
698 printk("%08x ",readl(start + b));
699 b += sizeof(u32);
700 }
701 printk("\n");
702 }
31961943 703}
8a70f8dc
JG		 704#endif
705
31961943
BR		 706static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
707{
708#ifdef ATA_DEBUG
709 int b, w;
710 u32 dw;
711 for (b = 0; b < bytes; ) {
712 DPRINTK("%02x: ", b);
713 for (w = 0; b < bytes && w < 4; w++) {
714 (void) pci_read_config_dword(pdev,b,&dw);
715 printk("%08x ",dw);
716 b += sizeof(u32);
717 }
718 printk("\n");
719 }
720#endif
721}
722static void mv_dump_all_regs(void __iomem *mmio_base, int port,
723 struct pci_dev *pdev)
724{
725#ifdef ATA_DEBUG
8b260248 726 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 727 port >> MV_PORT_HC_SHIFT);
728 void __iomem *port_base;
729 int start_port, num_ports, p, start_hc, num_hcs, hc;
730
731 if (0 > port) {
732 start_hc = start_port = 0;
733 num_ports = 8; /* shld be benign for 4 port devs */
734 num_hcs = 2;
735 } else {
736 start_hc = port >> MV_PORT_HC_SHIFT;
737 start_port = port;
738 num_ports = num_hcs = 1;
739 }
8b260248 740 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 741 num_ports > 1 ? num_ports - 1 : start_port);
742
743 if (NULL != pdev) {
744 DPRINTK("PCI config space regs:\n");
745 mv_dump_pci_cfg(pdev, 0x68);
746 }
747 DPRINTK("PCI regs:\n");
748 mv_dump_mem(mmio_base+0xc00, 0x3c);
749 mv_dump_mem(mmio_base+0xd00, 0x34);
750 mv_dump_mem(mmio_base+0xf00, 0x4);
751 mv_dump_mem(mmio_base+0x1d00, 0x6c);
752 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 753 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 754 DPRINTK("HC regs (HC %i):\n", hc);
755 mv_dump_mem(hc_base, 0x1c);
756 }
757 for (p = start_port; p < start_port + num_ports; p++) {
758 port_base = mv_port_base(mmio_base, p);
759 DPRINTK("EDMA regs (port %i):\n",p);
760 mv_dump_mem(port_base, 0x54);
761 DPRINTK("SATA regs (port %i):\n",p);
762 mv_dump_mem(port_base+0x300, 0x60);
763 }
764#endif
20f733e7
BR		 765}
766
767static unsigned int mv_scr_offset(unsigned int sc_reg_in)
768{
769 unsigned int ofs;
770
771 switch (sc_reg_in) {
772 case SCR_STATUS:
773 case SCR_CONTROL:
774 case SCR_ERROR:
775 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
776 break;
777 case SCR_ACTIVE:
778 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
779 break;
780 default:
781 ofs = 0xffffffffU;
782 break;
783 }
784 return ofs;
785}
786
787static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
788{
789 unsigned int ofs = mv_scr_offset(sc_reg_in);
790
791 if (0xffffffffU != ofs) {
792 return readl(mv_ap_base(ap) + ofs);
793 } else {
794 return (u32) ofs;
795 }
796}
797
798static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
799{
800 unsigned int ofs = mv_scr_offset(sc_reg_in);
801
802 if (0xffffffffU != ofs) {
803 writelfl(val, mv_ap_base(ap) + ofs);
804 }
805}
806
e4e7b892
JG		 807static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
808{
809 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
810
811 /* set up non-NCQ EDMA configuration */
812 cfg &= ~0x1f; /* clear queue depth */
813 cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */
814 cfg &= ~(1 << 9); /* disable equeue */
815
816 if (IS_GEN_I(hpriv))
817 cfg |= (1 << 8); /* enab config burst size mask */
818
819 else if (IS_GEN_II(hpriv))
820 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
821
822 else if (IS_GEN_IIE(hpriv)) {
823 cfg |= (1 << 23); /* dis RX PM port mask */
824 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
825 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
826 cfg |= (1 << 18); /* enab early completion */
827 cfg |= (1 << 17); /* enab host q cache */
828 cfg |= (1 << 22); /* enab cutthrough */
829 }
830
831 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
832}
833
05b308e1
BR		 834/**
835 * mv_port_start - Port specific init/start routine.
836 * @ap: ATA channel to manipulate
837 *
838 * Allocate and point to DMA memory, init port private memory,
839 * zero indices.
840 *
841 * LOCKING:
842 * Inherited from caller.
843 */
31961943
BR		 844static int mv_port_start(struct ata_port *ap)
845{
cca3974e
JG		 846 struct device *dev = ap->host->dev;
847 struct mv_host_priv *hpriv = ap->host->private_data;
31961943
BR		 848 struct mv_port_priv *pp;
849 void __iomem *port_mmio = mv_ap_base(ap);
850 void *mem;
851 dma_addr_t mem_dma;
24dc5f33 852 int rc;
31961943 853
24dc5f33 854 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 855 if (!pp)
24dc5f33 856 return -ENOMEM;
31961943 857
24dc5f33
TH		 858 mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
859 GFP_KERNEL);
6037d6bb 860 if (!mem)
24dc5f33 861 return -ENOMEM;
31961943
BR		 862 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
863
6037d6bb
JG		 864 rc = ata_pad_alloc(ap, dev);
865 if (rc)
24dc5f33 866 return rc;
6037d6bb 867
8b260248 868 /* First item in chunk of DMA memory:
31961943
BR		 869 * 32-slot command request table (CRQB), 32 bytes each in size
870 */
871 pp->crqb = mem;
872 pp->crqb_dma = mem_dma;
873 mem += MV_CRQB_Q_SZ;
874 mem_dma += MV_CRQB_Q_SZ;
875
8b260248 876 /* Second item:
31961943
BR		 877 * 32-slot command response table (CRPB), 8 bytes each in size
878 */
879 pp->crpb = mem;
880 pp->crpb_dma = mem_dma;
881 mem += MV_CRPB_Q_SZ;
882 mem_dma += MV_CRPB_Q_SZ;
883
884 /* Third item:
885 * Table of scatter-gather descriptors (ePRD), 16 bytes each
886 */
887 pp->sg_tbl = mem;
888 pp->sg_tbl_dma = mem_dma;
889
e4e7b892 890 mv_edma_cfg(hpriv, port_mmio);
31961943
BR		 891
892 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
8b260248 893 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
31961943
BR		 894 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
895
e4e7b892
JG		 896 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
897 writelfl(pp->crqb_dma & 0xffffffff,
898 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
899 else
900 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
31961943
BR		 901
902 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
e4e7b892
JG		 903
904 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
905 writelfl(pp->crpb_dma & 0xffffffff,
906 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
907 else
908 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
909
8b260248 910 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
31961943
BR		 911 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
912
31961943
BR		 913 /* Don't turn on EDMA here...do it before DMA commands only. Else
914 * we'll be unable to send non-data, PIO, etc due to restricted access
915 * to shadow regs.
916 */
917 ap->private_data = pp;
918 return 0;
919}
920
05b308e1
BR		 921/**
922 * mv_port_stop - Port specific cleanup/stop routine.
923 * @ap: ATA channel to manipulate
924 *
925 * Stop DMA, cleanup port memory.
926 *
927 * LOCKING:
cca3974e 928 * This routine uses the host lock to protect the DMA stop.
05b308e1 929 */
31961943
BR		 930static void mv_port_stop(struct ata_port *ap)
931{
afb0edd9 932 unsigned long flags;
31961943 933
cca3974e 934 spin_lock_irqsave(&ap->host->lock, flags);
31961943 935 mv_stop_dma(ap);
cca3974e 936 spin_unlock_irqrestore(&ap->host->lock, flags);
31961943
BR		 937}
938
05b308e1
BR		 939/**
940 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
941 * @qc: queued command whose SG list to source from
942 *
943 * Populate the SG list and mark the last entry.
944 *
945 * LOCKING:
946 * Inherited from caller.
947 */
31961943
BR		 948static void mv_fill_sg(struct ata_queued_cmd *qc)
949{
950 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd
JG		 951 unsigned int i = 0;
952 struct scatterlist *sg;
31961943 953
972c26bd 954 ata_for_each_sg(sg, qc) {
31961943 955 dma_addr_t addr;
22374677 956 u32 sg_len, len, offset;
31961943 957
972c26bd
JG		 958 addr = sg_dma_address(sg);
959 sg_len = sg_dma_len(sg);
31961943 960
22374677
JG		 961 while (sg_len) {
962 offset = addr & MV_DMA_BOUNDARY;
963 len = sg_len;
964 if ((offset + sg_len) > 0x10000)
965 len = 0x10000 - offset;
972c26bd 966
22374677
JG		 967 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
968 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
63af2a5c 969 pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff);
22374677
JG		 970
971 sg_len -= len;
972 addr += len;
973
974 if (!sg_len && ata_sg_is_last(sg, qc))
975 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
976
977 i++;
978 }
31961943
BR		 979 }
980}
981
a6432436 982static inline unsigned mv_inc_q_index(unsigned index)
31961943 983{
a6432436 984 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
31961943
BR		 985}
986
e1469874 987static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 988{
559eedad 989 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 990 (last ? CRQB_CMD_LAST : 0);
559eedad 991 *cmdw = cpu_to_le16(tmp);
31961943
BR		 992}
993
05b308e1
BR		 994/**
995 * mv_qc_prep - Host specific command preparation.
996 * @qc: queued command to prepare
997 *
998 * This routine simply redirects to the general purpose routine
999 * if command is not DMA. Else, it handles prep of the CRQB
1000 * (command request block), does some sanity checking, and calls
1001 * the SG load routine.
1002 *
1003 * LOCKING:
1004 * Inherited from caller.
1005 */
31961943
BR		 1006static void mv_qc_prep(struct ata_queued_cmd *qc)
1007{
1008 struct ata_port *ap = qc->ap;
1009 struct mv_port_priv *pp = ap->private_data;
e1469874 1010 __le16 *cw;
31961943
BR		 1011 struct ata_taskfile *tf;
1012 u16 flags = 0;
a6432436 1013 unsigned in_index;
31961943 1014
e4e7b892 1015 if (ATA_PROT_DMA != qc->tf.protocol)
31961943 1016 return;
20f733e7 1017
31961943
BR		 1018 /* Fill in command request block
1019 */
e4e7b892 1020 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1021 flags |= CRQB_FLAG_READ;
beec7dbc 1022 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943
BR		 1023 flags |= qc->tag << CRQB_TAG_SHIFT;
1024
a6432436
ML		 1025 /* get current queue index from hardware */
1026 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1027 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1028
1029 pp->crqb[in_index].sg_addr =
31961943 1030 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
a6432436 1031 pp->crqb[in_index].sg_addr_hi =
31961943 1032 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
a6432436 1033 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1034
a6432436 1035 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1036 tf = &qc->tf;
1037
1038 /* Sadly, the CRQB cannot accomodate all registers--there are
1039 * only 11 bytes...so we must pick and choose required
1040 * registers based on the command. So, we drop feature and
1041 * hob_feature for [RW] DMA commands, but they are needed for
1042 * NCQ. NCQ will drop hob_nsect.
20f733e7 1043 */
31961943
BR		 1044 switch (tf->command) {
1045 case ATA_CMD_READ:
1046 case ATA_CMD_READ_EXT:
1047 case ATA_CMD_WRITE:
1048 case ATA_CMD_WRITE_EXT:
c15d85c8 1049 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1050 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1051 break;
1052#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1053 case ATA_CMD_FPDMA_READ:
1054 case ATA_CMD_FPDMA_WRITE:
8b260248 1055 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1056 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1057 break;
1058#endif /* FIXME: remove this line when NCQ added */
1059 default:
1060 /* The only other commands EDMA supports in non-queued and
1061 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1062 * of which are defined/used by Linux. If we get here, this
1063 * driver needs work.
1064 *
1065 * FIXME: modify libata to give qc_prep a return value and
1066 * return error here.
1067 */
1068 BUG_ON(tf->command);
1069 break;
1070 }
1071 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1072 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1073 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1074 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1075 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1076 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1077 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1078 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1079 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1080
e4e7b892
JG		 1081 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1082 return;
1083 mv_fill_sg(qc);
1084}
1085
1086/**
1087 * mv_qc_prep_iie - Host specific command preparation.
1088 * @qc: queued command to prepare
1089 *
1090 * This routine simply redirects to the general purpose routine
1091 * if command is not DMA. Else, it handles prep of the CRQB
1092 * (command request block), does some sanity checking, and calls
1093 * the SG load routine.
1094 *
1095 * LOCKING:
1096 * Inherited from caller.
1097 */
1098static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1099{
1100 struct ata_port *ap = qc->ap;
1101 struct mv_port_priv *pp = ap->private_data;
1102 struct mv_crqb_iie *crqb;
1103 struct ata_taskfile *tf;
a6432436 1104 unsigned in_index;
e4e7b892
JG		 1105 u32 flags = 0;
1106
1107 if (ATA_PROT_DMA != qc->tf.protocol)
1108 return;
1109
e4e7b892
JG		 1110 /* Fill in Gen IIE command request block
1111 */
1112 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1113 flags |= CRQB_FLAG_READ;
1114
beec7dbc 1115 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892
JG		 1116 flags |= qc->tag << CRQB_TAG_SHIFT;
1117
a6432436
ML		 1118 /* get current queue index from hardware */
1119 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1120 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1121
1122 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
e4e7b892
JG		 1123 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1124 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1125 crqb->flags = cpu_to_le32(flags);
1126
1127 tf = &qc->tf;
1128 crqb->ata_cmd[0] = cpu_to_le32(
1129 (tf->command << 16) |
1130 (tf->feature << 24)
1131 );
1132 crqb->ata_cmd[1] = cpu_to_le32(
1133 (tf->lbal << 0) |
1134 (tf->lbam << 8) |
1135 (tf->lbah << 16) |
1136 (tf->device << 24)
1137 );
1138 crqb->ata_cmd[2] = cpu_to_le32(
1139 (tf->hob_lbal << 0) |
1140 (tf->hob_lbam << 8) |
1141 (tf->hob_lbah << 16) |
1142 (tf->hob_feature << 24)
1143 );
1144 crqb->ata_cmd[3] = cpu_to_le32(
1145 (tf->nsect << 0) |
1146 (tf->hob_nsect << 8)
1147 );
1148
1149 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1150 return;
31961943
BR		 1151 mv_fill_sg(qc);
1152}
1153
05b308e1
BR		 1154/**
1155 * mv_qc_issue - Initiate a command to the host
1156 * @qc: queued command to start
1157 *
1158 * This routine simply redirects to the general purpose routine
1159 * if command is not DMA. Else, it sanity checks our local
1160 * caches of the request producer/consumer indices then enables
1161 * DMA and bumps the request producer index.
1162 *
1163 * LOCKING:
1164 * Inherited from caller.
1165 */
9a3d9eb0 1166static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943
BR		 1167{
1168 void __iomem *port_mmio = mv_ap_base(qc->ap);
1169 struct mv_port_priv *pp = qc->ap->private_data;
a6432436 1170 unsigned in_index;
31961943
BR		 1171 u32 in_ptr;
1172
1173 if (ATA_PROT_DMA != qc->tf.protocol) {
1174 /* We're about to send a non-EDMA capable command to the
1175 * port. Turn off EDMA so there won't be problems accessing
1176 * shadow block, etc registers.
1177 */
1178 mv_stop_dma(qc->ap);
1179 return ata_qc_issue_prot(qc);
1180 }
1181
a6432436
ML		 1182 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1183 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
31961943 1184
31961943 1185 /* until we do queuing, the queue should be empty at this point */
a6432436
ML		 1186 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1187 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
31961943 1188
a6432436 1189 in_index = mv_inc_q_index(in_index); /* now incr producer index */
31961943 1190
afb0edd9 1191 mv_start_dma(port_mmio, pp);
31961943
BR		 1192
1193 /* and write the request in pointer to kick the EDMA to life */
1194 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
a6432436 1195 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1196 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1197
1198 return 0;
1199}
1200
05b308e1
BR		 1201/**
1202 * mv_get_crpb_status - get status from most recently completed cmd
1203 * @ap: ATA channel to manipulate
1204 *
1205 * This routine is for use when the port is in DMA mode, when it
1206 * will be using the CRPB (command response block) method of
beec7dbc 1207 * returning command completion information. We check indices
05b308e1
BR		 1208 * are good, grab status, and bump the response consumer index to
1209 * prove that we're up to date.
1210 *
1211 * LOCKING:
1212 * Inherited from caller.
1213 */
31961943
BR		 1214static u8 mv_get_crpb_status(struct ata_port *ap)
1215{
1216 void __iomem *port_mmio = mv_ap_base(ap);
1217 struct mv_port_priv *pp = ap->private_data;
a6432436 1218 unsigned out_index;
31961943 1219 u32 out_ptr;
806a6e7a 1220 u8 ata_status;
31961943 1221
a6432436
ML		 1222 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1223 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
31961943 1224
a6432436
ML		 1225 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1226 >> CRPB_FLAG_STATUS_SHIFT;
806a6e7a 1227
31961943 1228 /* increment our consumer index... */
a6432436 1229 out_index = mv_inc_q_index(out_index);
8b260248 1230
31961943 1231 /* and, until we do NCQ, there should only be 1 CRPB waiting */
a6432436
ML		 1232 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1233 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
31961943
BR		 1234
1235 /* write out our inc'd consumer index so EDMA knows we're caught up */
1236 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
a6432436 1237 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
31961943
BR		 1238 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1239
1240 /* Return ATA status register for completed CRPB */
806a6e7a 1241 return ata_status;
31961943
BR		 1242}
1243
05b308e1
BR		 1244/**
1245 * mv_err_intr - Handle error interrupts on the port
1246 * @ap: ATA channel to manipulate
9b358e30 1247 * @reset_allowed: bool: 0 == don't trigger from reset here
05b308e1
BR		 1248 *
1249 * In most cases, just clear the interrupt and move on. However,
1250 * some cases require an eDMA reset, which is done right before
1251 * the COMRESET in mv_phy_reset(). The SERR case requires a
1252 * clear of pending errors in the SATA SERROR register. Finally,
1253 * if the port disabled DMA, update our cached copy to match.
1254 *
1255 * LOCKING:
1256 * Inherited from caller.
1257 */
9b358e30 1258static void mv_err_intr(struct ata_port *ap, int reset_allowed)
31961943
BR		 1259{
1260 void __iomem *port_mmio = mv_ap_base(ap);
1261 u32 edma_err_cause, serr = 0;
20f733e7
BR		 1262
1263 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1264
1265 if (EDMA_ERR_SERR & edma_err_cause) {
81952c54
TH		 1266 sata_scr_read(ap, SCR_ERROR, &serr);
1267 sata_scr_write_flush(ap, SCR_ERROR, serr);
20f733e7 1268 }
afb0edd9
BR		 1269 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1270 struct mv_port_priv *pp = ap->private_data;
1271 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1272 }
1273 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1274 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
20f733e7
BR		 1275
1276 /* Clear EDMA now that SERR cleanup done */
1277 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1278
1279 /* check for fatal here and recover if needed */
9b358e30 1280 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
c9d39130 1281 mv_stop_and_reset(ap);
20f733e7
BR		 1282}
1283
05b308e1
BR		 1284/**
1285 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 1286 * @host: host specific structure
05b308e1
BR		 1287 * @relevant: port error bits relevant to this host controller
1288 * @hc: which host controller we're to look at
1289 *
1290 * Read then write clear the HC interrupt status then walk each
1291 * port connected to the HC and see if it needs servicing. Port
1292 * success ints are reported in the HC interrupt status reg, the
1293 * port error ints are reported in the higher level main
1294 * interrupt status register and thus are passed in via the
1295 * 'relevant' argument.
1296 *
1297 * LOCKING:
1298 * Inherited from caller.
1299 */
cca3974e 1300static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
20f733e7 1301{
0d5ff566 1302 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
20f733e7 1303 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
20f733e7
BR		 1304 struct ata_queued_cmd *qc;
1305 u32 hc_irq_cause;
31961943 1306 int shift, port, port0, hard_port, handled;
a7dac447 1307 unsigned int err_mask;
20f733e7
BR		 1308
1309 if (hc == 0) {
1310 port0 = 0;
1311 } else {
1312 port0 = MV_PORTS_PER_HC;
1313 }
1314
1315 /* we'll need the HC success int register in most cases */
1316 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1317 if (hc_irq_cause) {
31961943 1318 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 1319 }
1320
1321 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1322 hc,relevant,hc_irq_cause);
1323
1324 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
cd85f6e2 1325 u8 ata_status = 0;
cca3974e 1326 struct ata_port *ap = host->ports[port];
63af2a5c 1327 struct mv_port_priv *pp = ap->private_data;
55d8ca4f 1328
e857f141 1329 hard_port = mv_hardport_from_port(port); /* range 0..3 */
31961943 1330 handled = 0; /* ensure ata_status is set if handled++ */
20f733e7 1331
63af2a5c 1332 /* Note that DEV_IRQ might happen spuriously during EDMA,
e857f141
ML		 1333 * and should be ignored in such cases.
1334 * The cause of this is still under investigation.
8190bdb9 1335 */
63af2a5c
ML		 1336 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1337 /* EDMA: check for response queue interrupt */
1338 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1339 ata_status = mv_get_crpb_status(ap);
1340 handled = 1;
1341 }
1342 } else {
1343 /* PIO: check for device (drive) interrupt */
1344 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
0d5ff566 1345 ata_status = readb(ap->ioaddr.status_addr);
63af2a5c 1346 handled = 1;
e857f141
ML		 1347 /* ignore spurious intr if drive still BUSY */
1348 if (ata_status & ATA_BUSY) {
1349 ata_status = 0;
1350 handled = 0;
1351 }
63af2a5c 1352 }
20f733e7
BR		 1353 }
1354
029f5468 1355 if (ap && (ap->flags & ATA_FLAG_DISABLED))
a2c91a88
JG		 1356 continue;
1357
a7dac447
JG		 1358 err_mask = ac_err_mask(ata_status);
1359
31961943 1360 shift = port << 1; /* (port * 2) */
20f733e7
BR		 1361 if (port >= MV_PORTS_PER_HC) {
1362 shift++; /* skip bit 8 in the HC Main IRQ reg */
1363 }
1364 if ((PORT0_ERR << shift) & relevant) {
9b358e30 1365 mv_err_intr(ap, 1);
a7dac447 1366 err_mask |= AC_ERR_OTHER;
63af2a5c 1367 handled = 1;
20f733e7 1368 }
8b260248 1369
63af2a5c 1370 if (handled) {
20f733e7 1371 qc = ata_qc_from_tag(ap, ap->active_tag);
63af2a5c 1372 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
20f733e7
BR		 1373 VPRINTK("port %u IRQ found for qc, "
1374 "ata_status 0x%x\n", port,ata_status);
20f733e7 1375 /* mark qc status appropriately */
701db69d 1376 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
a22e2eb0
AL		 1377 qc->err_mask |= err_mask;
1378 ata_qc_complete(qc);
1379 }
20f733e7
BR		 1380 }
1381 }
1382 }
1383 VPRINTK("EXIT\n");
1384}
1385
05b308e1 1386/**
8b260248 1387 * mv_interrupt -
05b308e1
BR		 1388 * @irq: unused
1389 * @dev_instance: private data; in this case the host structure
1390 * @regs: unused
1391 *
1392 * Read the read only register to determine if any host
1393 * controllers have pending interrupts. If so, call lower level
1394 * routine to handle. Also check for PCI errors which are only
1395 * reported here.
1396 *
8b260248 1397 * LOCKING:
cca3974e 1398 * This routine holds the host lock while processing pending
05b308e1
BR		 1399 * interrupts.
1400 */
7d12e780 1401static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 1402{
cca3974e 1403 struct ata_host *host = dev_instance;
20f733e7 1404 unsigned int hc, handled = 0, n_hcs;
0d5ff566 1405 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
615ab953 1406 struct mv_host_priv *hpriv;
20f733e7
BR		 1407 u32 irq_stat;
1408
20f733e7 1409 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
20f733e7
BR		 1410
1411 /* check the cases where we either have nothing pending or have read
1412 * a bogus register value which can indicate HW removal or PCI fault
1413 */
1414 if (!irq_stat || (0xffffffffU == irq_stat)) {
1415 return IRQ_NONE;
1416 }
1417
cca3974e
JG		 1418 n_hcs = mv_get_hc_count(host->ports[0]->flags);
1419 spin_lock(&host->lock);
20f733e7
BR		 1420
1421 for (hc = 0; hc < n_hcs; hc++) {
1422 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1423 if (relevant) {
cca3974e 1424 mv_host_intr(host, relevant, hc);
31961943 1425 handled++;
20f733e7
BR		 1426 }
1427 }
615ab953 1428
cca3974e 1429 hpriv = host->private_data;
615ab953
ML		 1430 if (IS_60XX(hpriv)) {
1431 /* deal with the interrupt coalescing bits */
1432 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1433 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1434 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1435 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1436 }
1437 }
1438
20f733e7 1439 if (PCI_ERR & irq_stat) {
31961943
BR		 1440 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1441 readl(mmio + PCI_IRQ_CAUSE_OFS));
1442
afb0edd9 1443 DPRINTK("All regs @ PCI error\n");
cca3974e 1444 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
20f733e7 1445
31961943
BR		 1446 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1447 handled++;
1448 }
cca3974e 1449 spin_unlock(&host->lock);
20f733e7
BR		 1450
1451 return IRQ_RETVAL(handled);
1452}
1453
c9d39130
JG		 1454static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1455{
1456 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1457 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1458
1459 return hc_mmio + ofs;
1460}
1461
1462static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1463{
1464 unsigned int ofs;
1465
1466 switch (sc_reg_in) {
1467 case SCR_STATUS:
1468 case SCR_ERROR:
1469 case SCR_CONTROL:
1470 ofs = sc_reg_in * sizeof(u32);
1471 break;
1472 default:
1473 ofs = 0xffffffffU;
1474 break;
1475 }
1476 return ofs;
1477}
1478
1479static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1480{
0d5ff566
TH		 1481 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1482 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1483 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1484
1485 if (ofs != 0xffffffffU)
0d5ff566 1486 return readl(addr + ofs);
c9d39130
JG		 1487 else
1488 return (u32) ofs;
1489}
1490
1491static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1492{
0d5ff566
TH		 1493 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1494 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1495 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1496
1497 if (ofs != 0xffffffffU)
0d5ff566 1498 writelfl(val, addr + ofs);
c9d39130
JG		 1499}
1500
522479fb
JG		 1501static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1502{
1503 u8 rev_id;
1504 int early_5080;
1505
1506 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1507
1508 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1509
1510 if (!early_5080) {
1511 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1512 tmp |= (1 << 0);
1513 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1514 }
1515
1516 mv_reset_pci_bus(pdev, mmio);
1517}
1518
1519static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1520{
1521 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1522}
1523
47c2b677 1524static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1525 void __iomem *mmio)
1526{
c9d39130
JG		 1527 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1528 u32 tmp;
1529
1530 tmp = readl(phy_mmio + MV5_PHY_MODE);
1531
1532 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1533 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 1534}
1535
47c2b677 1536static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1537{
522479fb
JG		 1538 u32 tmp;
1539
1540 writel(0, mmio + MV_GPIO_PORT_CTL);
1541
1542 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1543
1544 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1545 tmp |= ~(1 << 0);
1546 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 1547}
1548
2a47ce06
JG		 1549static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1550 unsigned int port)
bca1c4eb 1551{
c9d39130
JG		 1552 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1553 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1554 u32 tmp;
1555 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1556
1557 if (fix_apm_sq) {
1558 tmp = readl(phy_mmio + MV5_LT_MODE);
1559 tmp |= (1 << 19);
1560 writel(tmp, phy_mmio + MV5_LT_MODE);
1561
1562 tmp = readl(phy_mmio + MV5_PHY_CTL);
1563 tmp &= ~0x3;
1564 tmp |= 0x1;
1565 writel(tmp, phy_mmio + MV5_PHY_CTL);
1566 }
1567
1568 tmp = readl(phy_mmio + MV5_PHY_MODE);
1569 tmp &= ~mask;
1570 tmp |= hpriv->signal[port].pre;
1571 tmp |= hpriv->signal[port].amps;
1572 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 1573}
1574
c9d39130
JG		 1575
1576#undef ZERO
1577#define ZERO(reg) writel(0, port_mmio + (reg))
1578static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1579 unsigned int port)
1580{
1581 void __iomem *port_mmio = mv_port_base(mmio, port);
1582
1583 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1584
1585 mv_channel_reset(hpriv, mmio, port);
1586
1587 ZERO(0x028); /* command */
1588 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1589 ZERO(0x004); /* timer */
1590 ZERO(0x008); /* irq err cause */
1591 ZERO(0x00c); /* irq err mask */
1592 ZERO(0x010); /* rq bah */
1593 ZERO(0x014); /* rq inp */
1594 ZERO(0x018); /* rq outp */
1595 ZERO(0x01c); /* respq bah */
1596 ZERO(0x024); /* respq outp */
1597 ZERO(0x020); /* respq inp */
1598 ZERO(0x02c); /* test control */
1599 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1600}
1601#undef ZERO
1602
1603#define ZERO(reg) writel(0, hc_mmio + (reg))
1604static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1605 unsigned int hc)
47c2b677 1606{
c9d39130
JG		 1607 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1608 u32 tmp;
1609
1610 ZERO(0x00c);
1611 ZERO(0x010);
1612 ZERO(0x014);
1613 ZERO(0x018);
1614
1615 tmp = readl(hc_mmio + 0x20);
1616 tmp &= 0x1c1c1c1c;
1617 tmp |= 0x03030303;
1618 writel(tmp, hc_mmio + 0x20);
1619}
1620#undef ZERO
1621
1622static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1623 unsigned int n_hc)
1624{
1625 unsigned int hc, port;
1626
1627 for (hc = 0; hc < n_hc; hc++) {
1628 for (port = 0; port < MV_PORTS_PER_HC; port++)
1629 mv5_reset_hc_port(hpriv, mmio,
1630 (hc * MV_PORTS_PER_HC) + port);
1631
1632 mv5_reset_one_hc(hpriv, mmio, hc);
1633 }
1634
1635 return 0;
47c2b677
JG		 1636}
1637
101ffae2
JG		 1638#undef ZERO
1639#define ZERO(reg) writel(0, mmio + (reg))
1640static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1641{
1642 u32 tmp;
1643
1644 tmp = readl(mmio + MV_PCI_MODE);
1645 tmp &= 0xff00ffff;
1646 writel(tmp, mmio + MV_PCI_MODE);
1647
1648 ZERO(MV_PCI_DISC_TIMER);
1649 ZERO(MV_PCI_MSI_TRIGGER);
1650 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1651 ZERO(HC_MAIN_IRQ_MASK_OFS);
1652 ZERO(MV_PCI_SERR_MASK);
1653 ZERO(PCI_IRQ_CAUSE_OFS);
1654 ZERO(PCI_IRQ_MASK_OFS);
1655 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1656 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1657 ZERO(MV_PCI_ERR_ATTRIBUTE);
1658 ZERO(MV_PCI_ERR_COMMAND);
1659}
1660#undef ZERO
1661
1662static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1663{
1664 u32 tmp;
1665
1666 mv5_reset_flash(hpriv, mmio);
1667
1668 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1669 tmp &= 0x3;
1670 tmp |= (1 << 5) | (1 << 6);
1671 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1672}
1673
1674/**
1675 * mv6_reset_hc - Perform the 6xxx global soft reset
1676 * @mmio: base address of the HBA
1677 *
1678 * This routine only applies to 6xxx parts.
1679 *
1680 * LOCKING:
1681 * Inherited from caller.
1682 */
c9d39130
JG		 1683static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1684 unsigned int n_hc)
101ffae2
JG		 1685{
1686 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1687 int i, rc = 0;
1688 u32 t;
1689
1690 /* Following procedure defined in PCI "main command and status
1691 * register" table.
1692 */
1693 t = readl(reg);
1694 writel(t | STOP_PCI_MASTER, reg);
1695
1696 for (i = 0; i < 1000; i++) {
1697 udelay(1);
1698 t = readl(reg);
1699 if (PCI_MASTER_EMPTY & t) {
1700 break;
1701 }
1702 }
1703 if (!(PCI_MASTER_EMPTY & t)) {
1704 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1705 rc = 1;
1706 goto done;
1707 }
1708
1709 /* set reset */
1710 i = 5;
1711 do {
1712 writel(t | GLOB_SFT_RST, reg);
1713 t = readl(reg);
1714 udelay(1);
1715 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1716
1717 if (!(GLOB_SFT_RST & t)) {
1718 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1719 rc = 1;
1720 goto done;
1721 }
1722
1723 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1724 i = 5;
1725 do {
1726 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1727 t = readl(reg);
1728 udelay(1);
1729 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1730
1731 if (GLOB_SFT_RST & t) {
1732 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1733 rc = 1;
1734 }
1735done:
1736 return rc;
1737}
1738
47c2b677 1739static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1740 void __iomem *mmio)
1741{
1742 void __iomem *port_mmio;
1743 u32 tmp;
1744
ba3fe8fb
JG		 1745 tmp = readl(mmio + MV_RESET_CFG);
1746 if ((tmp & (1 << 0)) == 0) {
47c2b677 1747 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 1748 hpriv->signal[idx].pre = 0x1 << 5;
1749 return;
1750 }
1751
1752 port_mmio = mv_port_base(mmio, idx);
1753 tmp = readl(port_mmio + PHY_MODE2);
1754
1755 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1756 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1757}
1758
47c2b677 1759static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1760{
47c2b677 1761 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
ba3fe8fb
JG		 1762}
1763
c9d39130 1764static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 1765 unsigned int port)
bca1c4eb 1766{
c9d39130
JG		 1767 void __iomem *port_mmio = mv_port_base(mmio, port);
1768
bca1c4eb 1769 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 1770 int fix_phy_mode2 =
1771 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 1772 int fix_phy_mode4 =
47c2b677
JG		 1773 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1774 u32 m2, tmp;
1775
1776 if (fix_phy_mode2) {
1777 m2 = readl(port_mmio + PHY_MODE2);
1778 m2 &= ~(1 << 16);
1779 m2 |= (1 << 31);
1780 writel(m2, port_mmio + PHY_MODE2);
1781
1782 udelay(200);
1783
1784 m2 = readl(port_mmio + PHY_MODE2);
1785 m2 &= ~((1 << 16) | (1 << 31));
1786 writel(m2, port_mmio + PHY_MODE2);
1787
1788 udelay(200);
1789 }
1790
1791 /* who knows what this magic does */
1792 tmp = readl(port_mmio + PHY_MODE3);
1793 tmp &= ~0x7F800000;
1794 tmp |= 0x2A800000;
1795 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 1796
1797 if (fix_phy_mode4) {
47c2b677 1798 u32 m4;
bca1c4eb
JG		 1799
1800 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 1801
1802 if (hp_flags & MV_HP_ERRATA_60X1B2)
1803 tmp = readl(port_mmio + 0x310);
bca1c4eb
JG		 1804
1805 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1806
1807 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 1808
1809 if (hp_flags & MV_HP_ERRATA_60X1B2)
1810 writel(tmp, port_mmio + 0x310);
bca1c4eb
JG		 1811 }
1812
1813 /* Revert values of pre-emphasis and signal amps to the saved ones */
1814 m2 = readl(port_mmio + PHY_MODE2);
1815
1816 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 1817 m2 |= hpriv->signal[port].amps;
1818 m2 |= hpriv->signal[port].pre;
47c2b677 1819 m2 &= ~(1 << 16);
bca1c4eb 1820
e4e7b892
JG		 1821 /* according to mvSata 3.6.1, some IIE values are fixed */
1822 if (IS_GEN_IIE(hpriv)) {
1823 m2 &= ~0xC30FF01F;
1824 m2 |= 0x0000900F;
1825 }
1826
bca1c4eb
JG		 1827 writel(m2, port_mmio + PHY_MODE2);
1828}
1829
c9d39130
JG		 1830static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1831 unsigned int port_no)
1832{
1833 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1834
1835 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1836
1837 if (IS_60XX(hpriv)) {
1838 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
eb46d684
ML		 1839 ifctl |= (1 << 7); /* enable gen2i speed */
1840 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
c9d39130
JG		 1841 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1842 }
1843
1844 udelay(25); /* allow reset propagation */
1845
1846 /* Spec never mentions clearing the bit. Marvell's driver does
1847 * clear the bit, however.
1848 */
1849 writelfl(0, port_mmio + EDMA_CMD_OFS);
1850
1851 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1852
1853 if (IS_50XX(hpriv))
1854 mdelay(1);
1855}
1856
1857static void mv_stop_and_reset(struct ata_port *ap)
1858{
cca3974e 1859 struct mv_host_priv *hpriv = ap->host->private_data;
0d5ff566 1860 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
c9d39130
JG		 1861
1862 mv_stop_dma(ap);
1863
1864 mv_channel_reset(hpriv, mmio, ap->port_no);
1865
22374677
JG		 1866 __mv_phy_reset(ap, 0);
1867}
1868
1869static inline void __msleep(unsigned int msec, int can_sleep)
1870{
1871 if (can_sleep)
1872 msleep(msec);
1873 else
1874 mdelay(msec);
c9d39130
JG		 1875}
1876
05b308e1 1877/**
22374677 1878 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
05b308e1
BR		 1879 * @ap: ATA channel to manipulate
1880 *
1881 * Part of this is taken from __sata_phy_reset and modified to
1882 * not sleep since this routine gets called from interrupt level.
1883 *
1884 * LOCKING:
1885 * Inherited from caller. This is coded to safe to call at
1886 * interrupt level, i.e. it does not sleep.
31961943 1887 */
22374677 1888static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
20f733e7 1889{
095fec88 1890 struct mv_port_priv *pp = ap->private_data;
cca3974e 1891 struct mv_host_priv *hpriv = ap->host->private_data;
20f733e7
BR		 1892 void __iomem *port_mmio = mv_ap_base(ap);
1893 struct ata_taskfile tf;
1894 struct ata_device *dev = &ap->device[0];
31961943 1895 unsigned long timeout;
22374677
JG		 1896 int retry = 5;
1897 u32 sstatus;
20f733e7
BR		 1898
1899 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1900
095fec88 1901 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
31961943
BR		 1902 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1903 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
20f733e7 1904
22374677
JG		 1905 /* Issue COMRESET via SControl */
1906comreset_retry:
81952c54 1907 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
22374677
JG		 1908 __msleep(1, can_sleep);
1909
81952c54 1910 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
22374677
JG		 1911 __msleep(20, can_sleep);
1912
1913 timeout = jiffies + msecs_to_jiffies(200);
31961943 1914 do {
81952c54 1915 sata_scr_read(ap, SCR_STATUS, &sstatus);
62f1d0e6 1916 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
31961943 1917 break;
22374677
JG		 1918
1919 __msleep(1, can_sleep);
31961943 1920 } while (time_before(jiffies, timeout));
20f733e7 1921
22374677
JG		 1922 /* work around errata */
1923 if (IS_60XX(hpriv) &&
1924 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1925 (retry-- > 0))
1926 goto comreset_retry;
095fec88
JG		 1927
1928 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
31961943
BR		 1929 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1930 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1931
81952c54 1932 if (ata_port_online(ap)) {
31961943
BR		 1933 ata_port_probe(ap);
1934 } else {
81952c54 1935 sata_scr_read(ap, SCR_STATUS, &sstatus);
f15a1daf
TH		 1936 ata_port_printk(ap, KERN_INFO,
1937 "no device found (phy stat %08x)\n", sstatus);
31961943 1938 ata_port_disable(ap);
20f733e7
BR		 1939 return;
1940 }
31961943 1941 ap->cbl = ATA_CBL_SATA;
20f733e7 1942
22374677
JG		 1943 /* even after SStatus reflects that device is ready,
1944 * it seems to take a while for link to be fully
1945 * established (and thus Status no longer 0x80/0x7F),
1946 * so we poll a bit for that, here.
1947 */
1948 retry = 20;
1949 while (1) {
1950 u8 drv_stat = ata_check_status(ap);
1951 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1952 break;
1953 __msleep(500, can_sleep);
1954 if (retry-- <= 0)
1955 break;
1956 }
1957
0d5ff566
TH		 1958 tf.lbah = readb(ap->ioaddr.lbah_addr);
1959 tf.lbam = readb(ap->ioaddr.lbam_addr);
1960 tf.lbal = readb(ap->ioaddr.lbal_addr);
1961 tf.nsect = readb(ap->ioaddr.nsect_addr);
20f733e7
BR		 1962
1963 dev->class = ata_dev_classify(&tf);
e1211e3f 1964 if (!ata_dev_enabled(dev)) {
20f733e7
BR		 1965 VPRINTK("Port disabled post-sig: No device present.\n");
1966 ata_port_disable(ap);
1967 }
095fec88
JG		 1968
1969 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1970
1971 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1972
bca1c4eb 1973 VPRINTK("EXIT\n");
20f733e7
BR		 1974}
1975
22374677
JG		 1976static void mv_phy_reset(struct ata_port *ap)
1977{
1978 __mv_phy_reset(ap, 1);
1979}
1980
05b308e1
BR		 1981/**
1982 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1983 * @ap: ATA channel to manipulate
1984 *
1985 * Intent is to clear all pending error conditions, reset the
1986 * chip/bus, fail the command, and move on.
1987 *
1988 * LOCKING:
cca3974e 1989 * This routine holds the host lock while failing the command.
05b308e1 1990 */
31961943
BR		 1991static void mv_eng_timeout(struct ata_port *ap)
1992{
0d5ff566 1993 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
31961943 1994 struct ata_queued_cmd *qc;
2f9719b6 1995 unsigned long flags;
31961943 1996
f15a1daf 1997 ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
31961943 1998 DPRINTK("All regs @ start of eng_timeout\n");
0d5ff566 1999 mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
31961943
BR		 2000
2001 qc = ata_qc_from_tag(ap, ap->active_tag);
2002 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
0d5ff566 2003 mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
31961943 2004
cca3974e 2005 spin_lock_irqsave(&ap->host->lock, flags);
9b358e30 2006 mv_err_intr(ap, 0);
c9d39130 2007 mv_stop_and_reset(ap);
cca3974e 2008 spin_unlock_irqrestore(&ap->host->lock, flags);
31961943 2009
9b358e30
ML		 2010 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2011 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2012 qc->err_mask |= AC_ERR_TIMEOUT;
2013 ata_eh_qc_complete(qc);
2014 }
31961943
BR		 2015}
2016
05b308e1
BR		 2017/**
2018 * mv_port_init - Perform some early initialization on a single port.
2019 * @port: libata data structure storing shadow register addresses
2020 * @port_mmio: base address of the port
2021 *
2022 * Initialize shadow register mmio addresses, clear outstanding
2023 * interrupts on the port, and unmask interrupts for the future
2024 * start of the port.
2025 *
2026 * LOCKING:
2027 * Inherited from caller.
2028 */
31961943 2029static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2030{
0d5ff566 2031 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2032 unsigned serr_ofs;
2033
8b260248 2034 /* PIO related setup
31961943
BR		 2035 */
2036 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2037 port->error_addr =
31961943
BR		 2038 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2039 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2040 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2041 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2042 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2043 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2044 port->status_addr =
31961943
BR		 2045 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2046 /* special case: control/altstatus doesn't have ATA_REG_ address */
2047 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2048
2049 /* unused: */
20f733e7
BR		 2050 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
2051
31961943
BR		 2052 /* Clear any currently outstanding port interrupt conditions */
2053 serr_ofs = mv_scr_offset(SCR_ERROR);
2054 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2055 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2056
20f733e7 2057 /* unmask all EDMA error interrupts */
31961943 2058 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2059
8b260248 2060 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2061 readl(port_mmio + EDMA_CFG_OFS),
2062 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2063 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2064}
2065
47c2b677 2066static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
522479fb 2067 unsigned int board_idx)
bca1c4eb
JG		 2068{
2069 u8 rev_id;
2070 u32 hp_flags = hpriv->hp_flags;
2071
2072 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2073
2074 switch(board_idx) {
47c2b677
JG		 2075 case chip_5080:
2076 hpriv->ops = &mv5xxx_ops;
2077 hp_flags |= MV_HP_50XX;
2078
2079 switch (rev_id) {
2080 case 0x1:
2081 hp_flags |= MV_HP_ERRATA_50XXB0;
2082 break;
2083 case 0x3:
2084 hp_flags |= MV_HP_ERRATA_50XXB2;
2085 break;
2086 default:
2087 dev_printk(KERN_WARNING, &pdev->dev,
2088 "Applying 50XXB2 workarounds to unknown rev\n");
2089 hp_flags |= MV_HP_ERRATA_50XXB2;
2090 break;
2091 }
2092 break;
2093
bca1c4eb
JG		 2094 case chip_504x:
2095 case chip_508x:
47c2b677 2096 hpriv->ops = &mv5xxx_ops;
bca1c4eb
JG		 2097 hp_flags |= MV_HP_50XX;
2098
47c2b677
JG		 2099 switch (rev_id) {
2100 case 0x0:
2101 hp_flags |= MV_HP_ERRATA_50XXB0;
2102 break;
2103 case 0x3:
2104 hp_flags |= MV_HP_ERRATA_50XXB2;
2105 break;
2106 default:
2107 dev_printk(KERN_WARNING, &pdev->dev,
2108 "Applying B2 workarounds to unknown rev\n");
2109 hp_flags |= MV_HP_ERRATA_50XXB2;
2110 break;
bca1c4eb
JG		 2111 }
2112 break;
2113
2114 case chip_604x:
2115 case chip_608x:
47c2b677
JG		 2116 hpriv->ops = &mv6xxx_ops;
2117
bca1c4eb 2118 switch (rev_id) {
47c2b677
JG		 2119 case 0x7:
2120 hp_flags |= MV_HP_ERRATA_60X1B2;
2121 break;
2122 case 0x9:
2123 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2124 break;
2125 default:
2126 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2127 "Applying B2 workarounds to unknown rev\n");
2128 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2129 break;
2130 }
2131 break;
2132
e4e7b892
JG		 2133 case chip_7042:
2134 case chip_6042:
2135 hpriv->ops = &mv6xxx_ops;
2136
2137 hp_flags |= MV_HP_GEN_IIE;
2138
2139 switch (rev_id) {
2140 case 0x0:
2141 hp_flags |= MV_HP_ERRATA_XX42A0;
2142 break;
2143 case 0x1:
2144 hp_flags |= MV_HP_ERRATA_60X1C0;
2145 break;
2146 default:
2147 dev_printk(KERN_WARNING, &pdev->dev,
2148 "Applying 60X1C0 workarounds to unknown rev\n");
2149 hp_flags |= MV_HP_ERRATA_60X1C0;
2150 break;
2151 }
2152 break;
2153
bca1c4eb
JG		 2154 default:
2155 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2156 return 1;
2157 }
2158
2159 hpriv->hp_flags = hp_flags;
2160
2161 return 0;
2162}
2163
05b308e1 2164/**
47c2b677 2165 * mv_init_host - Perform some early initialization of the host.
bca1c4eb 2166 * @pdev: host PCI device
05b308e1
BR		 2167 * @probe_ent: early data struct representing the host
2168 *
2169 * If possible, do an early global reset of the host. Then do
2170 * our port init and clear/unmask all/relevant host interrupts.
2171 *
2172 * LOCKING:
2173 * Inherited from caller.
2174 */
47c2b677 2175static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
bca1c4eb 2176 unsigned int board_idx)
20f733e7
BR		 2177{
2178 int rc = 0, n_hc, port, hc;
0d5ff566 2179 void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR];
bca1c4eb
JG		 2180 struct mv_host_priv *hpriv = probe_ent->private_data;
2181
47c2b677
JG		 2182 /* global interrupt mask */
2183 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2184
2185 rc = mv_chip_id(pdev, hpriv, board_idx);
bca1c4eb
JG		 2186 if (rc)
2187 goto done;
2188
cca3974e 2189 n_hc = mv_get_hc_count(probe_ent->port_flags);
bca1c4eb
JG		 2190 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2191
47c2b677
JG		 2192 for (port = 0; port < probe_ent->n_ports; port++)
2193 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 2194
c9d39130 2195 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 2196 if (rc)
20f733e7 2197 goto done;
20f733e7 2198
522479fb
JG		 2199 hpriv->ops->reset_flash(hpriv, mmio);
2200 hpriv->ops->reset_bus(pdev, mmio);
47c2b677 2201 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7
BR		 2202
2203 for (port = 0; port < probe_ent->n_ports; port++) {
2a47ce06 2204 if (IS_60XX(hpriv)) {
c9d39130
JG		 2205 void __iomem *port_mmio = mv_port_base(mmio, port);
2206
2a47ce06 2207 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
eb46d684
ML		 2208 ifctl |= (1 << 7); /* enable gen2i speed */
2209 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2a47ce06
JG		 2210 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2211 }
2212
c9d39130 2213 hpriv->ops->phy_errata(hpriv, mmio, port);
2a47ce06
JG		 2214 }
2215
2216 for (port = 0; port < probe_ent->n_ports; port++) {
2217 void __iomem *port_mmio = mv_port_base(mmio, port);
31961943 2218 mv_port_init(&probe_ent->port[port], port_mmio);
20f733e7
BR		 2219 }
2220
2221 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 2222 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2223
2224 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2225 "(before clear)=0x%08x\n", hc,
2226 readl(hc_mmio + HC_CFG_OFS),
2227 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2228
2229 /* Clear any currently outstanding hc interrupt conditions */
2230 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 2231 }
2232
31961943
BR		 2233 /* Clear any currently outstanding host interrupt conditions */
2234 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2235
2236 /* and unmask interrupt generation for host regs */
2237 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2238 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
20f733e7
BR		 2239
2240 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
8b260248 2241 "PCI int cause/mask=0x%08x/0x%08x\n",
20f733e7
BR		 2242 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2243 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2244 readl(mmio + PCI_IRQ_CAUSE_OFS),
2245 readl(mmio + PCI_IRQ_MASK_OFS));
bca1c4eb 2246
31961943 2247done:
20f733e7
BR		 2248 return rc;
2249}
2250
05b308e1
BR		 2251/**
2252 * mv_print_info - Dump key info to kernel log for perusal.
2253 * @probe_ent: early data struct representing the host
2254 *
2255 * FIXME: complete this.
2256 *
2257 * LOCKING:
2258 * Inherited from caller.
2259 */
31961943
BR		 2260static void mv_print_info(struct ata_probe_ent *probe_ent)
2261{
2262 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2263 struct mv_host_priv *hpriv = probe_ent->private_data;
2264 u8 rev_id, scc;
2265 const char *scc_s;
2266
2267 /* Use this to determine the HW stepping of the chip so we know
2268 * what errata to workaround
2269 */
2270 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2271
2272 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2273 if (scc == 0)
2274 scc_s = "SCSI";
2275 else if (scc == 0x01)
2276 scc_s = "RAID";
2277 else
2278 scc_s = "unknown";
2279
a9524a76
JG		 2280 dev_printk(KERN_INFO, &pdev->dev,
2281 "%u slots %u ports %s mode IRQ via %s\n",
8b260248 2282 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
31961943
BR		 2283 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2284}
2285
05b308e1
BR		 2286/**
2287 * mv_init_one - handle a positive probe of a Marvell host
2288 * @pdev: PCI device found
2289 * @ent: PCI device ID entry for the matched host
2290 *
2291 * LOCKING:
2292 * Inherited from caller.
2293 */
20f733e7
BR		 2294static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2295{
2296 static int printed_version = 0;
24dc5f33
TH		 2297 struct device *dev = &pdev->dev;
2298 struct ata_probe_ent *probe_ent;
20f733e7
BR		 2299 struct mv_host_priv *hpriv;
2300 unsigned int board_idx = (unsigned int)ent->driver_data;
24dc5f33 2301 int rc;
20f733e7 2302
a9524a76
JG		 2303 if (!printed_version++)
2304 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 2305
24dc5f33
TH		 2306 rc = pcim_enable_device(pdev);
2307 if (rc)
20f733e7 2308 return rc;
eb46d684 2309 pci_set_master(pdev);
20f733e7 2310
0d5ff566
TH		 2311 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2312 if (rc == -EBUSY)
24dc5f33 2313 pcim_pin_device(pdev);
0d5ff566 2314 if (rc)
24dc5f33 2315 return rc;
20f733e7 2316
24dc5f33
TH		 2317 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
2318 if (probe_ent == NULL)
2319 return -ENOMEM;
20f733e7 2320
20f733e7
BR		 2321 probe_ent->dev = pci_dev_to_dev(pdev);
2322 INIT_LIST_HEAD(&probe_ent->node);
2323
24dc5f33
TH		 2324 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2325 if (!hpriv)
2326 return -ENOMEM;
20f733e7
BR		 2327
2328 probe_ent->sht = mv_port_info[board_idx].sht;
cca3974e 2329 probe_ent->port_flags = mv_port_info[board_idx].flags;
20f733e7
BR		 2330 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2331 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2332 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2333
2334 probe_ent->irq = pdev->irq;
1d6f359a 2335 probe_ent->irq_flags = IRQF_SHARED;
0d5ff566 2336 probe_ent->iomap = pcim_iomap_table(pdev);
20f733e7
BR		 2337 probe_ent->private_data = hpriv;
2338
2339 /* initialize adapter */
47c2b677 2340 rc = mv_init_host(pdev, probe_ent, board_idx);
24dc5f33
TH		 2341 if (rc)
2342 return rc;
20f733e7 2343
31961943 2344 /* Enable interrupts */
24dc5f33 2345 if (msi && !pci_enable_msi(pdev))
31961943 2346 pci_intx(pdev, 1);
20f733e7 2347
31961943
BR		 2348 mv_dump_pci_cfg(pdev, 0x68);
2349 mv_print_info(probe_ent);
2350
24dc5f33
TH		 2351 if (ata_device_add(probe_ent) == 0)
2352 return -ENODEV;
20f733e7 2353
24dc5f33 2354 devm_kfree(dev, probe_ent);
20f733e7 2355 return 0;
20f733e7
BR		 2356}
2357
2358static int __init mv_init(void)
2359{
b7887196 2360 return pci_register_driver(&mv_pci_driver);
20f733e7
BR		 2361}
2362
2363static void __exit mv_exit(void)
2364{
2365 pci_unregister_driver(&mv_pci_driver);
2366}
2367
2368MODULE_AUTHOR("Brett Russ");
2369MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2370MODULE_LICENSE("GPL");
2371MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2372MODULE_VERSION(DRV_VERSION);
2373
ddef9bb3
JG		 2374module_param(msi, int, 0444);
2375MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2376
20f733e7
BR		 2377module_init(mv_init);
2378module_exit(mv_exit);
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