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sata_mv: group genIIe flags
[mirror_ubuntu-zesty-kernel.git] / drivers / ata / sata_mv.c
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20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
4a05e209 54
20f733e7
BR		 55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
8d8b6004 62#include <linux/dmapool.h>
20f733e7 63#include <linux/dma-mapping.h>
a9524a76 64#include <linux/device.h>
f351b2d6
SB		 65#include <linux/platform_device.h>
66#include <linux/ata_platform.h>
15a32632 67#include <linux/mbus.h>
c46938cc 68#include <linux/bitops.h>
20f733e7 69#include <scsi/scsi_host.h>
193515d5 70#include <scsi/scsi_cmnd.h>
6c08772e 71#include <scsi/scsi_device.h>
20f733e7 72#include <linux/libata.h>
20f733e7
BR		 73
74#define DRV_NAME "sata_mv"
1fd2e1c2 75#define DRV_VERSION "1.20"
20f733e7
BR		 76
77enum {
78 /* BAR's are enumerated in terms of pci_resource_start() terms */
79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
80 MV_IO_BAR = 2, /* offset 0x18: IO space */
81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
82
83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
85
86 MV_PCI_REG_BASE = 0,
87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
93
20f733e7 94 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 95 MV_FLASH_CTL_OFS = 0x1046c,
96 MV_GPIO_PORT_CTL_OFS = 0x104f0,
97 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 98
99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
103
31961943
BR		 104 MV_MAX_Q_DEPTH = 32,
105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
106
107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
108 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
110 */
111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 113 MV_MAX_SG_CT = 256,
31961943 114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 115
352fab70 116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 117 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 121
122 /* Host Flags */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 125 /* SoC integrated controllers, no PCI interface */
e12bef50 126 MV_FLAG_SOC = (1 << 28),
7bb3c529 127
c5d3e45a 128 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 129 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
130 ATA_FLAG_PIO_POLLING,
ad3aef51 131
47c2b677 132 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 133
ad3aef51
ML		 134 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
135 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
136 ATA_FLAG_NCQ,
137
31961943
BR		 138 CRQB_FLAG_READ = (1 << 0),
139 CRQB_TAG_SHIFT = 1,
c5d3e45a 140 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 141 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 142 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 143 CRQB_CMD_ADDR_SHIFT = 8,
144 CRQB_CMD_CS = (0x2 << 11),
145 CRQB_CMD_LAST = (1 << 15),
146
147 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 148 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
149 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 150
151 EPRD_FLAG_END_OF_TBL = (1 << 31),
152
20f733e7
BR		 153 /* PCI interface registers */
154
31961943 155 PCI_COMMAND_OFS = 0xc00,
8e7decdb 156 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 157
20f733e7
BR		 158 PCI_MAIN_CMD_STS_OFS = 0xd30,
159 STOP_PCI_MASTER = (1 << 2),
160 PCI_MASTER_EMPTY = (1 << 3),
161 GLOB_SFT_RST = (1 << 4),
162
8e7decdb
ML		 163 MV_PCI_MODE_OFS = 0xd00,
164 MV_PCI_MODE_MASK = 0x30,
165
522479fb
JG		 166 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
167 MV_PCI_DISC_TIMER = 0xd04,
168 MV_PCI_MSI_TRIGGER = 0xc38,
169 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 170 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 171 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
172 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
173 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
174 MV_PCI_ERR_COMMAND = 0x1d50,
175
02a121da
ML		 176 PCI_IRQ_CAUSE_OFS = 0x1d58,
177 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 178 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
179
02a121da
ML		 180 PCIE_IRQ_CAUSE_OFS = 0x1900,
181 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 182 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 183
7368f919
ML		 184 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
185 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
186 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
187 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
188 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 189 ERR_IRQ = (1 << 0), /* shift by port # */
190 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 191 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
192 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
193 PCI_ERR = (1 << 18),
194 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
195 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 196 PORTS_0_3_COAL_DONE = (1 << 8),
197 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 198 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
199 GPIO_INT = (1 << 22),
200 SELF_INT = (1 << 23),
201 TWSI_INT = (1 << 24),
202 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 203 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 204 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
8b260248 205 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
f9f7fe01 206 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
20f733e7
BR		 207 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
208 HC_MAIN_RSVD),
fb621e2f
JG		 209 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
210 HC_MAIN_RSVD_5),
f351b2d6 211 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
20f733e7
BR		 212
213 /* SATAHC registers */
214 HC_CFG_OFS = 0,
215
216 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 217 DMA_IRQ = (1 << 0), /* shift by port # */
218 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 219 DEV_IRQ = (1 << 8), /* shift by port # */
220
221 /* Shadow block registers */
31961943
BR		 222 SHD_BLK_OFS = 0x100,
223 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 224
225 /* SATA registers */
226 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
227 SATA_ACTIVE_OFS = 0x350,
0c58912e 228 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
17c5aab5 229
e12bef50 230 LTMODE_OFS = 0x30c,
17c5aab5
ML		 231 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
232
47c2b677 233 PHY_MODE3 = 0x310,
bca1c4eb
JG		 234 PHY_MODE4 = 0x314,
235 PHY_MODE2 = 0x330,
e12bef50 236 SATA_IFCTL_OFS = 0x344,
8e7decdb 237 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 238 SATA_IFSTAT_OFS = 0x34c,
239 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 240
8e7decdb
ML		 241 FISCFG_OFS = 0x360,
242 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
243 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 244
c9d39130 245 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 246 MV5_LTMODE_OFS = 0x30,
247 MV5_PHY_CTL_OFS = 0x0C,
248 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 249
250 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 251
252 /* Port registers */
253 EDMA_CFG_OFS = 0,
0c58912e
ML		 254 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
255 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
256 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
257 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
258 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 259 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
260 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 261
262 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
263 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 264 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
265 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
266 EDMA_ERR_DEV = (1 << 2), /* device error */
267 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
268 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
269 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 270 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
271 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 272 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 273 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 274 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
275 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
276 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
277 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 278
6c1153e0 279 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 280 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
281 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
282 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
283 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
284
6c1153e0 285 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 286
6c1153e0 287 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 288 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
289 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
290 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
291 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
292 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
293
6c1153e0 294 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 295
6c1153e0 296 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 297 EDMA_ERR_OVERRUN_5 = (1 << 5),
298 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 299
300 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
301 EDMA_ERR_LNK_CTRL_RX_1 |
302 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 303 EDMA_ERR_LNK_CTRL_TX,
646a4da5 304
bdd4ddde
JG		 305 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
306 EDMA_ERR_PRD_PAR |
307 EDMA_ERR_DEV_DCON |
308 EDMA_ERR_DEV_CON |
309 EDMA_ERR_SERR |
310 EDMA_ERR_SELF_DIS |
6c1153e0 311 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 312 EDMA_ERR_CRPB_PAR |
313 EDMA_ERR_INTRL_PAR |
314 EDMA_ERR_IORDY |
315 EDMA_ERR_LNK_CTRL_RX_2 |
316 EDMA_ERR_LNK_DATA_RX |
317 EDMA_ERR_LNK_DATA_TX |
318 EDMA_ERR_TRANS_PROTO,
e12bef50 319
bdd4ddde
JG		 320 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
321 EDMA_ERR_PRD_PAR |
322 EDMA_ERR_DEV_DCON |
323 EDMA_ERR_DEV_CON |
324 EDMA_ERR_OVERRUN_5 |
325 EDMA_ERR_UNDERRUN_5 |
326 EDMA_ERR_SELF_DIS_5 |
6c1153e0 327 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 328 EDMA_ERR_CRPB_PAR |
329 EDMA_ERR_INTRL_PAR |
330 EDMA_ERR_IORDY,
20f733e7 331
31961943
BR		 332 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
333 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 334
335 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
336 EDMA_REQ_Q_PTR_SHIFT = 5,
337
338 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
339 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
340 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 341 EDMA_RSP_Q_PTR_SHIFT = 3,
342
0ea9e179
JG		 343 EDMA_CMD_OFS = 0x28, /* EDMA command register */
344 EDMA_EN = (1 << 0), /* enable EDMA */
345 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 346 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
347
348 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
349 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
350 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 351
8e7decdb
ML		 352 EDMA_IORDY_TMOUT_OFS = 0x34,
353 EDMA_ARB_CFG_OFS = 0x38,
354
355 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 356
352fab70
ML		 357 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
358
31961943
BR		 359 /* Host private flags (hp_flags) */
360 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 361 MV_HP_ERRATA_50XXB0 = (1 << 1),
362 MV_HP_ERRATA_50XXB2 = (1 << 2),
363 MV_HP_ERRATA_60X1B2 = (1 << 3),
364 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892 365 MV_HP_ERRATA_XX42A0 = (1 << 5),
0ea9e179
JG		 366 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
367 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
368 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 369 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 370 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
20f733e7 371
31961943 372 /* Port private flags (pp_flags) */
0ea9e179 373 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 374 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 375 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 376 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
20f733e7
BR		 377};
378
ee9ccdf7
JG		 379#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
380#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 381#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 382#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
7bb3c529 383#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
bca1c4eb 384
15a32632
LB		 385#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
386#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
387
095fec88 388enum {
baf14aa1
JG		 389 /* DMA boundary 0xffff is required by the s/g splitting
390 * we need on /length/ in mv_fill-sg().
391 */
392 MV_DMA_BOUNDARY = 0xffffU,
095fec88 393
0ea9e179
JG		 394 /* mask of register bits containing lower 32 bits
395 * of EDMA request queue DMA address
396 */
095fec88
JG		 397 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
398
0ea9e179 399 /* ditto, for response queue */
095fec88
JG		 400 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
401};
402
522479fb
JG		 403enum chip_type {
404 chip_504x,
405 chip_508x,
406 chip_5080,
407 chip_604x,
408 chip_608x,
e4e7b892
JG		 409 chip_6042,
410 chip_7042,
f351b2d6 411 chip_soc,
522479fb
JG		 412};
413
31961943
BR		 414/* Command ReQuest Block: 32B */
415struct mv_crqb {
e1469874
ML		 416 __le32 sg_addr;
417 __le32 sg_addr_hi;
418 __le16 ctrl_flags;
419 __le16 ata_cmd[11];
31961943 420};
20f733e7 421
e4e7b892 422struct mv_crqb_iie {
e1469874
ML		 423 __le32 addr;
424 __le32 addr_hi;
425 __le32 flags;
426 __le32 len;
427 __le32 ata_cmd[4];
e4e7b892
JG		 428};
429
31961943
BR		 430/* Command ResPonse Block: 8B */
431struct mv_crpb {
e1469874
ML		 432 __le16 id;
433 __le16 flags;
434 __le32 tmstmp;
20f733e7
BR		 435};
436
31961943
BR		 437/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
438struct mv_sg {
e1469874
ML		 439 __le32 addr;
440 __le32 flags_size;
441 __le32 addr_hi;
442 __le32 reserved;
31961943 443};
20f733e7 444
31961943
BR		 445struct mv_port_priv {
446 struct mv_crqb *crqb;
447 dma_addr_t crqb_dma;
448 struct mv_crpb *crpb;
449 dma_addr_t crpb_dma;
eb73d558
ML		 450 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
451 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 452
453 unsigned int req_idx;
454 unsigned int resp_idx;
455
31961943 456 u32 pp_flags;
29d187bb 457 unsigned int delayed_eh_pmp_map;
31961943
BR		 458};
459
bca1c4eb
JG		 460struct mv_port_signal {
461 u32 amps;
462 u32 pre;
463};
464
02a121da
ML		 465struct mv_host_priv {
466 u32 hp_flags;
467 struct mv_port_signal signal[8];
468 const struct mv_hw_ops *ops;
f351b2d6
SB		 469 int n_ports;
470 void __iomem *base;
7368f919
ML		 471 void __iomem *main_irq_cause_addr;
472 void __iomem *main_irq_mask_addr;
02a121da
ML		 473 u32 irq_cause_ofs;
474 u32 irq_mask_ofs;
475 u32 unmask_all_irqs;
da2fa9ba
ML		 476 /*
477 * These consistent DMA memory pools give us guaranteed
478 * alignment for hardware-accessed data structures,
479 * and less memory waste in accomplishing the alignment.
480 */
481 struct dma_pool *crqb_pool;
482 struct dma_pool *crpb_pool;
483 struct dma_pool *sg_tbl_pool;
02a121da
ML		 484};
485
47c2b677 486struct mv_hw_ops {
2a47ce06
JG		 487 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
488 unsigned int port);
47c2b677
JG		 489 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
490 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
491 void __iomem *mmio);
c9d39130
JG		 492 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
493 unsigned int n_hc);
522479fb 494 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 495 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 496};
497
da3dbb17
TH		 498static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
499static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
500static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
501static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 502static int mv_port_start(struct ata_port *ap);
503static void mv_port_stop(struct ata_port *ap);
3e4a1391 504static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 505static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 506static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 507static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 508static int mv_hardreset(struct ata_link *link, unsigned int *class,
509 unsigned long deadline);
bdd4ddde
JG		 510static void mv_eh_freeze(struct ata_port *ap);
511static void mv_eh_thaw(struct ata_port *ap);
f273827e 512static void mv6_dev_config(struct ata_device *dev);
20f733e7 513
2a47ce06
JG		 514static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
515 unsigned int port);
47c2b677
JG		 516static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
517static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
518 void __iomem *mmio);
c9d39130
JG		 519static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
520 unsigned int n_hc);
522479fb 521static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 522static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 523
2a47ce06
JG		 524static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
525 unsigned int port);
47c2b677
JG		 526static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
527static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
528 void __iomem *mmio);
c9d39130
JG		 529static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
530 unsigned int n_hc);
522479fb 531static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 532static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
533 void __iomem *mmio);
534static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
535 void __iomem *mmio);
536static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
537 void __iomem *mmio, unsigned int n_hc);
538static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
539 void __iomem *mmio);
540static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 541static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 542static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 543 unsigned int port_no);
e12bef50 544static int mv_stop_edma(struct ata_port *ap);
b562468c 545static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 546static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 547
e49856d8
ML		 548static void mv_pmp_select(struct ata_port *ap, int pmp);
549static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
550 unsigned long deadline);
551static int mv_softreset(struct ata_link *link, unsigned int *class,
552 unsigned long deadline);
29d187bb 553static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 554static void mv_process_crpb_entries(struct ata_port *ap,
555 struct mv_port_priv *pp);
47c2b677 556
eb73d558
ML		 557/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
558 * because we have to allow room for worst case splitting of
559 * PRDs for 64K boundaries in mv_fill_sg().
560 */
c5d3e45a 561static struct scsi_host_template mv5_sht = {
68d1d07b 562 ATA_BASE_SHT(DRV_NAME),
baf14aa1 563 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 564 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 565};
566
567static struct scsi_host_template mv6_sht = {
68d1d07b 568 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 569 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 570 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 571 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 572};
573
029cfd6b
TH		 574static struct ata_port_operations mv5_ops = {
575 .inherits = &ata_sff_port_ops,
c9d39130 576
3e4a1391 577 .qc_defer = mv_qc_defer,
c9d39130
JG		 578 .qc_prep = mv_qc_prep,
579 .qc_issue = mv_qc_issue,
c9d39130 580
bdd4ddde
JG		 581 .freeze = mv_eh_freeze,
582 .thaw = mv_eh_thaw,
a1efdaba 583 .hardreset = mv_hardreset,
a1efdaba 584 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 585 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 586
c9d39130
JG		 587 .scr_read = mv5_scr_read,
588 .scr_write = mv5_scr_write,
589
590 .port_start = mv_port_start,
591 .port_stop = mv_port_stop,
c9d39130
JG		 592};
593
029cfd6b
TH		 594static struct ata_port_operations mv6_ops = {
595 .inherits = &mv5_ops,
f273827e 596 .dev_config = mv6_dev_config,
20f733e7
BR		 597 .scr_read = mv_scr_read,
598 .scr_write = mv_scr_write,
599
e49856d8
ML		 600 .pmp_hardreset = mv_pmp_hardreset,
601 .pmp_softreset = mv_softreset,
602 .softreset = mv_softreset,
29d187bb 603 .error_handler = mv_pmp_error_handler,
20f733e7
BR		 604};
605
029cfd6b
TH		 606static struct ata_port_operations mv_iie_ops = {
607 .inherits = &mv6_ops,
608 .dev_config = ATA_OP_NULL,
e4e7b892 609 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 610};
611
98ac62de 612static const struct ata_port_info mv_port_info[] = {
20f733e7 613 { /* chip_504x */
cca3974e 614 .flags = MV_COMMON_FLAGS,
31961943 615 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 616 .udma_mask = ATA_UDMA6,
c9d39130 617 .port_ops = &mv5_ops,
20f733e7
BR		 618 },
619 { /* chip_508x */
c5d3e45a 620 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 621 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 622 .udma_mask = ATA_UDMA6,
c9d39130 623 .port_ops = &mv5_ops,
20f733e7 624 },
47c2b677 625 { /* chip_5080 */
c5d3e45a 626 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 627 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 628 .udma_mask = ATA_UDMA6,
c9d39130 629 .port_ops = &mv5_ops,
47c2b677 630 },
20f733e7 631 { /* chip_604x */
138bfdd0 632 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 633 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 634 ATA_FLAG_NCQ,
31961943 635 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 636 .udma_mask = ATA_UDMA6,
c9d39130 637 .port_ops = &mv6_ops,
20f733e7
BR		 638 },
639 { /* chip_608x */
c5d3e45a 640 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 641 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 642 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 643 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 644 .udma_mask = ATA_UDMA6,
c9d39130 645 .port_ops = &mv6_ops,
20f733e7 646 },
e4e7b892 647 { /* chip_6042 */
ad3aef51 648 .flags = MV_GENIIE_FLAGS,
e4e7b892 649 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 650 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 651 .port_ops = &mv_iie_ops,
652 },
653 { /* chip_7042 */
ad3aef51 654 .flags = MV_GENIIE_FLAGS,
e4e7b892 655 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 656 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 657 .port_ops = &mv_iie_ops,
658 },
f351b2d6 659 { /* chip_soc */
ad3aef51 660 .flags = MV_GENIIE_FLAGS | MV_FLAG_SOC,
17c5aab5
ML		 661 .pio_mask = 0x1f, /* pio0-4 */
662 .udma_mask = ATA_UDMA6,
663 .port_ops = &mv_iie_ops,
f351b2d6 664 },
20f733e7
BR		 665};
666
3b7d697d 667static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 668 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
669 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
670 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
671 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 672 /* RocketRAID 1740/174x have different identifiers */
673 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
674 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 675
676 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
677 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
678 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
679 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
680 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
681
682 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
683
d9f9c6bc
FA		 684 /* Adaptec 1430SA */
685 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
686
02a121da 687 /* Marvell 7042 support */
6a3d586d
MT		 688 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
689
02a121da
ML		 690 /* Highpoint RocketRAID PCIe series */
691 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
692 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
693
2d2744fc 694 { } /* terminate list */
20f733e7
BR		 695};
696
47c2b677
JG		 697static const struct mv_hw_ops mv5xxx_ops = {
698 .phy_errata = mv5_phy_errata,
699 .enable_leds = mv5_enable_leds,
700 .read_preamp = mv5_read_preamp,
701 .reset_hc = mv5_reset_hc,
522479fb
JG		 702 .reset_flash = mv5_reset_flash,
703 .reset_bus = mv5_reset_bus,
47c2b677
JG		 704};
705
706static const struct mv_hw_ops mv6xxx_ops = {
707 .phy_errata = mv6_phy_errata,
708 .enable_leds = mv6_enable_leds,
709 .read_preamp = mv6_read_preamp,
710 .reset_hc = mv6_reset_hc,
522479fb
JG		 711 .reset_flash = mv6_reset_flash,
712 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 713};
714
f351b2d6
SB		 715static const struct mv_hw_ops mv_soc_ops = {
716 .phy_errata = mv6_phy_errata,
717 .enable_leds = mv_soc_enable_leds,
718 .read_preamp = mv_soc_read_preamp,
719 .reset_hc = mv_soc_reset_hc,
720 .reset_flash = mv_soc_reset_flash,
721 .reset_bus = mv_soc_reset_bus,
722};
723
20f733e7
BR		 724/*
725 * Functions
726 */
727
728static inline void writelfl(unsigned long data, void __iomem *addr)
729{
730 writel(data, addr);
731 (void) readl(addr); /* flush to avoid PCI posted write */
732}
733
c9d39130
JG		 734static inline unsigned int mv_hc_from_port(unsigned int port)
735{
736 return port >> MV_PORT_HC_SHIFT;
737}
738
739static inline unsigned int mv_hardport_from_port(unsigned int port)
740{
741 return port & MV_PORT_MASK;
742}
743
1cfd19ae
ML		 744/*
745 * Consolidate some rather tricky bit shift calculations.
746 * This is hot-path stuff, so not a function.
747 * Simple code, with two return values, so macro rather than inline.
748 *
749 * port is the sole input, in range 0..7.
7368f919
ML		 750 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
751 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 752 *
753 * Note that port and hardport may be the same variable in some cases.
754 */
755#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
756{ \
757 shift = mv_hc_from_port(port) * HC_SHIFT; \
758 hardport = mv_hardport_from_port(port); \
759 shift += hardport * 2; \
760}
761
352fab70
ML		 762static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
763{
764 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
765}
766
c9d39130
JG		 767static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
768 unsigned int port)
769{
770 return mv_hc_base(base, mv_hc_from_port(port));
771}
772
20f733e7
BR		 773static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
774{
c9d39130 775 return mv_hc_base_from_port(base, port) +
8b260248 776 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 777 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 778}
779
e12bef50
ML		 780static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
781{
782 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
783 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
784
785 return hc_mmio + ofs;
786}
787
f351b2d6
SB		 788static inline void __iomem *mv_host_base(struct ata_host *host)
789{
790 struct mv_host_priv *hpriv = host->private_data;
791 return hpriv->base;
792}
793
20f733e7
BR		 794static inline void __iomem *mv_ap_base(struct ata_port *ap)
795{
f351b2d6 796 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 797}
798
cca3974e 799static inline int mv_get_hc_count(unsigned long port_flags)
31961943 800{
cca3974e 801 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 802}
803
c5d3e45a
JG		 804static void mv_set_edma_ptrs(void __iomem *port_mmio,
805 struct mv_host_priv *hpriv,
806 struct mv_port_priv *pp)
807{
bdd4ddde
JG		 808 u32 index;
809
c5d3e45a
JG		 810 /*
811 * initialize request queue
812 */
fcfb1f77
ML		 813 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
814 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 815
c5d3e45a
JG		 816 WARN_ON(pp->crqb_dma & 0x3ff);
817 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 818 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a
JG		 819 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
820
821 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 822 writelfl((pp->crqb_dma & 0xffffffff) | index,
c5d3e45a
JG		 823 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
824 else
bdd4ddde 825 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 826
827 /*
828 * initialize response queue
829 */
fcfb1f77
ML		 830 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
831 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 832
c5d3e45a
JG		 833 WARN_ON(pp->crpb_dma & 0xff);
834 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
835
836 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 837 writelfl((pp->crpb_dma & 0xffffffff) | index,
c5d3e45a
JG		 838 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
839 else
bdd4ddde 840 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
c5d3e45a 841
bdd4ddde 842 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 843 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 844}
845
05b308e1
BR		 846/**
847 * mv_start_dma - Enable eDMA engine
848 * @base: port base address
849 * @pp: port private data
850 *
beec7dbc
TH		 851 * Verify the local cache of the eDMA state is accurate with a
852 * WARN_ON.
05b308e1
BR		 853 *
854 * LOCKING:
855 * Inherited from caller.
856 */
0c58912e 857static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 858 struct mv_port_priv *pp, u8 protocol)
20f733e7 859{
72109168
ML		 860 int want_ncq = (protocol == ATA_PROT_NCQ);
861
862 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
863 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
864 if (want_ncq != using_ncq)
b562468c 865 mv_stop_edma(ap);
72109168 866 }
c5d3e45a 867 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 868 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 869 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 870 void __iomem *hc_mmio = mv_hc_base_from_port(
352fab70 871 mv_host_base(ap->host), hardport);
0c58912e
ML		 872 u32 hc_irq_cause, ipending;
873
bdd4ddde 874 /* clear EDMA event indicators, if any */
f630d562 875 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 876
0c58912e
ML		 877 /* clear EDMA interrupt indicator, if any */
878 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
352fab70 879 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
0c58912e
ML		 880 if (hc_irq_cause & ipending) {
881 writelfl(hc_irq_cause & ~ipending,
882 hc_mmio + HC_IRQ_CAUSE_OFS);
883 }
884
e12bef50 885 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 886
887 /* clear FIS IRQ Cause */
e4006077
ML		 888 if (IS_GEN_IIE(hpriv))
889 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
0c58912e 890
f630d562 891 mv_set_edma_ptrs(port_mmio, hpriv, pp);
bdd4ddde 892
f630d562 893 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 894 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
895 }
20f733e7
BR		 896}
897
9b2c4e0b
ML		 898static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
899{
900 void __iomem *port_mmio = mv_ap_base(ap);
901 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
902 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
903 int i;
904
905 /*
906 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 907 * No idea what a good "timeout" value might be, but measurements
908 * indicate that it often requires hundreds of microseconds
909 * with two drives in-use. So we use the 15msec value above
910 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 911 */
912 for (i = 0; i < timeout; ++i) {
913 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
914 if ((edma_stat & empty_idle) == empty_idle)
915 break;
916 udelay(per_loop);
917 }
918 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
919}
920
05b308e1 921/**
e12bef50 922 * mv_stop_edma_engine - Disable eDMA engine
b562468c 923 * @port_mmio: io base address
05b308e1
BR		 924 *
925 * LOCKING:
926 * Inherited from caller.
927 */
b562468c 928static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 929{
b562468c 930 int i;
31961943 931
b562468c
ML		 932 /* Disable eDMA. The disable bit auto clears. */
933 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 934
b562468c
ML		 935 /* Wait for the chip to confirm eDMA is off. */
936 for (i = 10000; i > 0; i--) {
937 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 938 if (!(reg & EDMA_EN))
b562468c
ML		 939 return 0;
940 udelay(10);
31961943 941 }
b562468c 942 return -EIO;
20f733e7
BR		 943}
944
e12bef50 945static int mv_stop_edma(struct ata_port *ap)
0ea9e179 946{
b562468c
ML		 947 void __iomem *port_mmio = mv_ap_base(ap);
948 struct mv_port_priv *pp = ap->private_data;
0ea9e179 949
b562468c
ML		 950 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
951 return 0;
952 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 953 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 954 if (mv_stop_edma_engine(port_mmio)) {
955 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
956 return -EIO;
957 }
958 return 0;
0ea9e179
JG		 959}
960
8a70f8dc 961#ifdef ATA_DEBUG
31961943 962static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 963{
31961943
BR		 964 int b, w;
965 for (b = 0; b < bytes; ) {
966 DPRINTK("%p: ", start + b);
967 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 968 printk("%08x ", readl(start + b));
31961943
BR		 969 b += sizeof(u32);
970 }
971 printk("\n");
972 }
31961943 973}
8a70f8dc
JG		 974#endif
975
31961943
BR		 976static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
977{
978#ifdef ATA_DEBUG
979 int b, w;
980 u32 dw;
981 for (b = 0; b < bytes; ) {
982 DPRINTK("%02x: ", b);
983 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 984 (void) pci_read_config_dword(pdev, b, &dw);
985 printk("%08x ", dw);
31961943
BR		 986 b += sizeof(u32);
987 }
988 printk("\n");
989 }
990#endif
991}
992static void mv_dump_all_regs(void __iomem *mmio_base, int port,
993 struct pci_dev *pdev)
994{
995#ifdef ATA_DEBUG
8b260248 996 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 997 port >> MV_PORT_HC_SHIFT);
998 void __iomem *port_base;
999 int start_port, num_ports, p, start_hc, num_hcs, hc;
1000
1001 if (0 > port) {
1002 start_hc = start_port = 0;
1003 num_ports = 8; /* shld be benign for 4 port devs */
1004 num_hcs = 2;
1005 } else {
1006 start_hc = port >> MV_PORT_HC_SHIFT;
1007 start_port = port;
1008 num_ports = num_hcs = 1;
1009 }
8b260248 1010 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1011 num_ports > 1 ? num_ports - 1 : start_port);
1012
1013 if (NULL != pdev) {
1014 DPRINTK("PCI config space regs:\n");
1015 mv_dump_pci_cfg(pdev, 0x68);
1016 }
1017 DPRINTK("PCI regs:\n");
1018 mv_dump_mem(mmio_base+0xc00, 0x3c);
1019 mv_dump_mem(mmio_base+0xd00, 0x34);
1020 mv_dump_mem(mmio_base+0xf00, 0x4);
1021 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1022 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1023 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1024 DPRINTK("HC regs (HC %i):\n", hc);
1025 mv_dump_mem(hc_base, 0x1c);
1026 }
1027 for (p = start_port; p < start_port + num_ports; p++) {
1028 port_base = mv_port_base(mmio_base, p);
2dcb407e 1029 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1030 mv_dump_mem(port_base, 0x54);
2dcb407e 1031 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1032 mv_dump_mem(port_base+0x300, 0x60);
1033 }
1034#endif
20f733e7
BR		 1035}
1036
1037static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1038{
1039 unsigned int ofs;
1040
1041 switch (sc_reg_in) {
1042 case SCR_STATUS:
1043 case SCR_CONTROL:
1044 case SCR_ERROR:
1045 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1046 break;
1047 case SCR_ACTIVE:
1048 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1049 break;
1050 default:
1051 ofs = 0xffffffffU;
1052 break;
1053 }
1054 return ofs;
1055}
1056
da3dbb17 1057static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1058{
1059 unsigned int ofs = mv_scr_offset(sc_reg_in);
1060
da3dbb17
TH		 1061 if (ofs != 0xffffffffU) {
1062 *val = readl(mv_ap_base(ap) + ofs);
1063 return 0;
1064 } else
1065 return -EINVAL;
20f733e7
BR		 1066}
1067
da3dbb17 1068static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1069{
1070 unsigned int ofs = mv_scr_offset(sc_reg_in);
1071
da3dbb17 1072 if (ofs != 0xffffffffU) {
20f733e7 1073 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1074 return 0;
1075 } else
1076 return -EINVAL;
20f733e7
BR		 1077}
1078
f273827e
ML		 1079static void mv6_dev_config(struct ata_device *adev)
1080{
1081 /*
e49856d8
ML		 1082 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1083 *
1084 * Gen-II does not support NCQ over a port multiplier
1085 * (no FIS-based switching).
1086 *
f273827e
ML		 1087 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1088 * See mv_qc_prep() for more info.
1089 */
e49856d8 1090 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1091 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1092 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1093 ata_dev_printk(adev, KERN_INFO,
1094 "NCQ disabled for command-based switching\n");
1095 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1096 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1097 ata_dev_printk(adev, KERN_INFO,
1098 "max_sectors limited to %u for NCQ\n",
1099 adev->max_sectors);
1100 }
e49856d8 1101 }
f273827e
ML		 1102}
1103
3e4a1391
ML		 1104static int mv_qc_defer(struct ata_queued_cmd *qc)
1105{
1106 struct ata_link *link = qc->dev->link;
1107 struct ata_port *ap = link->ap;
1108 struct mv_port_priv *pp = ap->private_data;
1109
29d187bb
ML		 1110 /*
1111 * Don't allow new commands if we're in a delayed EH state
1112 * for NCQ and/or FIS-based switching.
1113 */
1114 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1115 return ATA_DEFER_PORT;
3e4a1391
ML		 1116 /*
1117 * If the port is completely idle, then allow the new qc.
1118 */
1119 if (ap->nr_active_links == 0)
1120 return 0;
1121
1122 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1123 /*
1124 * The port is operating in host queuing mode (EDMA).
1125 * It can accomodate a new qc if the qc protocol
1126 * is compatible with the current host queue mode.
1127 */
1128 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1129 /*
1130 * The host queue (EDMA) is in NCQ mode.
1131 * If the new qc is also an NCQ command,
1132 * then allow the new qc.
1133 */
1134 if (qc->tf.protocol == ATA_PROT_NCQ)
1135 return 0;
1136 } else {
1137 /*
1138 * The host queue (EDMA) is in non-NCQ, DMA mode.
1139 * If the new qc is also a non-NCQ, DMA command,
1140 * then allow the new qc.
1141 */
1142 if (qc->tf.protocol == ATA_PROT_DMA)
1143 return 0;
1144 }
1145 }
1146 return ATA_DEFER_PORT;
1147}
1148
00f42eab 1149static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
e49856d8 1150{
00f42eab
ML		 1151 u32 new_fiscfg, old_fiscfg;
1152 u32 new_ltmode, old_ltmode;
1153 u32 new_haltcond, old_haltcond;
1154
1155 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1156 old_ltmode = readl(port_mmio + LTMODE_OFS);
1157 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1158
1159 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1160 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1161 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1162
1163 if (want_fbs) {
1164 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1165 new_ltmode = old_ltmode | LTMODE_BIT8;
4c299ca3
ML		 1166 if (want_ncq)
1167 new_haltcond &= ~EDMA_ERR_DEV;
1168 else
1169 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
e49856d8 1170 }
00f42eab 1171
8e7decdb
ML		 1172 if (new_fiscfg != old_fiscfg)
1173 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1174 if (new_ltmode != old_ltmode)
1175 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
00f42eab
ML		 1176 if (new_haltcond != old_haltcond)
1177 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
f273827e
ML		 1178}
1179
dd2890f6
ML		 1180static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1181{
1182 struct mv_host_priv *hpriv = ap->host->private_data;
1183 u32 old, new;
1184
1185 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1186 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1187 if (want_ncq)
1188 new = old | (1 << 22);
1189 else
1190 new = old & ~(1 << 22);
1191 if (new != old)
1192 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1193}
1194
e12bef50 1195static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1196{
0c58912e 1197 u32 cfg;
e12bef50
ML		 1198 struct mv_port_priv *pp = ap->private_data;
1199 struct mv_host_priv *hpriv = ap->host->private_data;
1200 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1201
1202 /* set up non-NCQ EDMA configuration */
0c58912e 1203 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
00f42eab 1204 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
e4e7b892 1205
0c58912e 1206 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1207 cfg |= (1 << 8); /* enab config burst size mask */
1208
dd2890f6 1209 else if (IS_GEN_II(hpriv)) {
e4e7b892 1210 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1211 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1212
dd2890f6 1213 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1214 int want_fbs = sata_pmp_attached(ap);
1215 /*
1216 * Possible future enhancement:
1217 *
1218 * The chip can use FBS with non-NCQ, if we allow it,
1219 * But first we need to have the error handling in place
1220 * for this mode (datasheet section 7.3.15.4.2.3).
1221 * So disallow non-NCQ FBS for now.
1222 */
1223 want_fbs &= want_ncq;
1224
1225 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1226
1227 if (want_fbs) {
1228 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1229 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1230 }
1231
e728eabe
JG		 1232 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1233 cfg |= (1 << 22); /* enab 4-entry host queue cache */
616d4a98
ML		 1234 if (HAS_PCI(ap->host))
1235 cfg |= (1 << 18); /* enab early completion */
1236 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1237 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e4e7b892
JG		 1238 }
1239
72109168
ML		 1240 if (want_ncq) {
1241 cfg |= EDMA_CFG_NCQ;
1242 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1243 } else
1244 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1245
e4e7b892
JG		 1246 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1247}
1248
da2fa9ba
ML		 1249static void mv_port_free_dma_mem(struct ata_port *ap)
1250{
1251 struct mv_host_priv *hpriv = ap->host->private_data;
1252 struct mv_port_priv *pp = ap->private_data;
eb73d558 1253 int tag;
da2fa9ba
ML		 1254
1255 if (pp->crqb) {
1256 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1257 pp->crqb = NULL;
1258 }
1259 if (pp->crpb) {
1260 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1261 pp->crpb = NULL;
1262 }
eb73d558
ML		 1263 /*
1264 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1265 * For later hardware, we have one unique sg_tbl per NCQ tag.
1266 */
1267 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1268 if (pp->sg_tbl[tag]) {
1269 if (tag == 0 || !IS_GEN_I(hpriv))
1270 dma_pool_free(hpriv->sg_tbl_pool,
1271 pp->sg_tbl[tag],
1272 pp->sg_tbl_dma[tag]);
1273 pp->sg_tbl[tag] = NULL;
1274 }
da2fa9ba
ML		 1275 }
1276}
1277
05b308e1
BR		 1278/**
1279 * mv_port_start - Port specific init/start routine.
1280 * @ap: ATA channel to manipulate
1281 *
1282 * Allocate and point to DMA memory, init port private memory,
1283 * zero indices.
1284 *
1285 * LOCKING:
1286 * Inherited from caller.
1287 */
31961943
BR		 1288static int mv_port_start(struct ata_port *ap)
1289{
cca3974e
JG		 1290 struct device *dev = ap->host->dev;
1291 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1292 struct mv_port_priv *pp;
dde20207 1293 int tag;
31961943 1294
24dc5f33 1295 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1296 if (!pp)
24dc5f33 1297 return -ENOMEM;
da2fa9ba 1298 ap->private_data = pp;
31961943 1299
da2fa9ba
ML		 1300 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1301 if (!pp->crqb)
1302 return -ENOMEM;
1303 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1304
da2fa9ba
ML		 1305 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1306 if (!pp->crpb)
1307 goto out_port_free_dma_mem;
1308 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1309
eb73d558
ML		 1310 /*
1311 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1312 * For later hardware, we need one unique sg_tbl per NCQ tag.
1313 */
1314 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1315 if (tag == 0 || !IS_GEN_I(hpriv)) {
1316 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1317 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1318 if (!pp->sg_tbl[tag])
1319 goto out_port_free_dma_mem;
1320 } else {
1321 pp->sg_tbl[tag] = pp->sg_tbl[0];
1322 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1323 }
1324 }
31961943 1325 return 0;
da2fa9ba
ML		 1326
1327out_port_free_dma_mem:
1328 mv_port_free_dma_mem(ap);
1329 return -ENOMEM;
31961943
BR		 1330}
1331
05b308e1
BR		 1332/**
1333 * mv_port_stop - Port specific cleanup/stop routine.
1334 * @ap: ATA channel to manipulate
1335 *
1336 * Stop DMA, cleanup port memory.
1337 *
1338 * LOCKING:
cca3974e 1339 * This routine uses the host lock to protect the DMA stop.
05b308e1 1340 */
31961943
BR		 1341static void mv_port_stop(struct ata_port *ap)
1342{
e12bef50 1343 mv_stop_edma(ap);
da2fa9ba 1344 mv_port_free_dma_mem(ap);
31961943
BR		 1345}
1346
05b308e1
BR		 1347/**
1348 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1349 * @qc: queued command whose SG list to source from
1350 *
1351 * Populate the SG list and mark the last entry.
1352 *
1353 * LOCKING:
1354 * Inherited from caller.
1355 */
6c08772e 1356static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1357{
1358 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1359 struct scatterlist *sg;
3be6cbd7 1360 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1361 unsigned int si;
31961943 1362
eb73d558 1363 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1364 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1365 dma_addr_t addr = sg_dma_address(sg);
1366 u32 sg_len = sg_dma_len(sg);
22374677 1367
4007b493
OJ		 1368 while (sg_len) {
1369 u32 offset = addr & 0xffff;
1370 u32 len = sg_len;
22374677 1371
4007b493
OJ		 1372 if ((offset + sg_len > 0x10000))
1373 len = 0x10000 - offset;
1374
1375 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1376 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1377 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1378
1379 sg_len -= len;
1380 addr += len;
1381
3be6cbd7 1382 last_sg = mv_sg;
4007b493 1383 mv_sg++;
4007b493 1384 }
31961943 1385 }
3be6cbd7
JG		 1386
1387 if (likely(last_sg))
1388 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1389}
1390
5796d1c4 1391static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1392{
559eedad 1393 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1394 (last ? CRQB_CMD_LAST : 0);
559eedad 1395 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1396}
1397
05b308e1
BR		 1398/**
1399 * mv_qc_prep - Host specific command preparation.
1400 * @qc: queued command to prepare
1401 *
1402 * This routine simply redirects to the general purpose routine
1403 * if command is not DMA. Else, it handles prep of the CRQB
1404 * (command request block), does some sanity checking, and calls
1405 * the SG load routine.
1406 *
1407 * LOCKING:
1408 * Inherited from caller.
1409 */
31961943
BR		 1410static void mv_qc_prep(struct ata_queued_cmd *qc)
1411{
1412 struct ata_port *ap = qc->ap;
1413 struct mv_port_priv *pp = ap->private_data;
e1469874 1414 __le16 *cw;
31961943
BR		 1415 struct ata_taskfile *tf;
1416 u16 flags = 0;
a6432436 1417 unsigned in_index;
31961943 1418
138bfdd0
ML		 1419 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1420 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1421 return;
20f733e7 1422
31961943
BR		 1423 /* Fill in command request block
1424 */
e4e7b892 1425 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1426 flags |= CRQB_FLAG_READ;
beec7dbc 1427 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1428 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1429 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1430
bdd4ddde 1431 /* get current queue index from software */
fcfb1f77 1432 in_index = pp->req_idx;
a6432436
ML		 1433
1434 pp->crqb[in_index].sg_addr =
eb73d558 1435 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1436 pp->crqb[in_index].sg_addr_hi =
eb73d558 1437 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1438 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1439
a6432436 1440 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1441 tf = &qc->tf;
1442
1443 /* Sadly, the CRQB cannot accomodate all registers--there are
1444 * only 11 bytes...so we must pick and choose required
1445 * registers based on the command. So, we drop feature and
1446 * hob_feature for [RW] DMA commands, but they are needed for
1447 * NCQ. NCQ will drop hob_nsect.
20f733e7 1448 */
31961943
BR		 1449 switch (tf->command) {
1450 case ATA_CMD_READ:
1451 case ATA_CMD_READ_EXT:
1452 case ATA_CMD_WRITE:
1453 case ATA_CMD_WRITE_EXT:
c15d85c8 1454 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1455 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1456 break;
31961943
BR		 1457 case ATA_CMD_FPDMA_READ:
1458 case ATA_CMD_FPDMA_WRITE:
8b260248 1459 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1460 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1461 break;
31961943
BR		 1462 default:
1463 /* The only other commands EDMA supports in non-queued and
1464 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1465 * of which are defined/used by Linux. If we get here, this
1466 * driver needs work.
1467 *
1468 * FIXME: modify libata to give qc_prep a return value and
1469 * return error here.
1470 */
1471 BUG_ON(tf->command);
1472 break;
1473 }
1474 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1475 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1476 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1477 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1478 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1479 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1480 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1481 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1482 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1483
e4e7b892
JG		 1484 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1485 return;
1486 mv_fill_sg(qc);
1487}
1488
1489/**
1490 * mv_qc_prep_iie - Host specific command preparation.
1491 * @qc: queued command to prepare
1492 *
1493 * This routine simply redirects to the general purpose routine
1494 * if command is not DMA. Else, it handles prep of the CRQB
1495 * (command request block), does some sanity checking, and calls
1496 * the SG load routine.
1497 *
1498 * LOCKING:
1499 * Inherited from caller.
1500 */
1501static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1502{
1503 struct ata_port *ap = qc->ap;
1504 struct mv_port_priv *pp = ap->private_data;
1505 struct mv_crqb_iie *crqb;
1506 struct ata_taskfile *tf;
a6432436 1507 unsigned in_index;
e4e7b892
JG		 1508 u32 flags = 0;
1509
138bfdd0
ML		 1510 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1511 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1512 return;
1513
e12bef50 1514 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1515 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1516 flags |= CRQB_FLAG_READ;
1517
beec7dbc 1518 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1519 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1520 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1521 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1522
bdd4ddde 1523 /* get current queue index from software */
fcfb1f77 1524 in_index = pp->req_idx;
a6432436
ML		 1525
1526 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1527 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1528 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1529 crqb->flags = cpu_to_le32(flags);
1530
1531 tf = &qc->tf;
1532 crqb->ata_cmd[0] = cpu_to_le32(
1533 (tf->command << 16) |
1534 (tf->feature << 24)
1535 );
1536 crqb->ata_cmd[1] = cpu_to_le32(
1537 (tf->lbal << 0) |
1538 (tf->lbam << 8) |
1539 (tf->lbah << 16) |
1540 (tf->device << 24)
1541 );
1542 crqb->ata_cmd[2] = cpu_to_le32(
1543 (tf->hob_lbal << 0) |
1544 (tf->hob_lbam << 8) |
1545 (tf->hob_lbah << 16) |
1546 (tf->hob_feature << 24)
1547 );
1548 crqb->ata_cmd[3] = cpu_to_le32(
1549 (tf->nsect << 0) |
1550 (tf->hob_nsect << 8)
1551 );
1552
1553 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1554 return;
31961943
BR		 1555 mv_fill_sg(qc);
1556}
1557
05b308e1
BR		 1558/**
1559 * mv_qc_issue - Initiate a command to the host
1560 * @qc: queued command to start
1561 *
1562 * This routine simply redirects to the general purpose routine
1563 * if command is not DMA. Else, it sanity checks our local
1564 * caches of the request producer/consumer indices then enables
1565 * DMA and bumps the request producer index.
1566 *
1567 * LOCKING:
1568 * Inherited from caller.
1569 */
9a3d9eb0 1570static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1571{
c5d3e45a
JG		 1572 struct ata_port *ap = qc->ap;
1573 void __iomem *port_mmio = mv_ap_base(ap);
1574 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1575 u32 in_index;
31961943 1576
138bfdd0
ML		 1577 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1578 (qc->tf.protocol != ATA_PROT_NCQ)) {
17c5aab5
ML		 1579 /*
1580 * We're about to send a non-EDMA capable command to the
31961943
BR		 1581 * port. Turn off EDMA so there won't be problems accessing
1582 * shadow block, etc registers.
1583 */
b562468c 1584 mv_stop_edma(ap);
e49856d8 1585 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1586 return ata_sff_qc_issue(qc);
31961943
BR		 1587 }
1588
72109168 1589 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1590
fcfb1f77
ML		 1591 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1592 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1593
1594 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1595 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1596 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1597
1598 return 0;
1599}
1600
8f767f8a
ML		 1601static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1602{
1603 struct mv_port_priv *pp = ap->private_data;
1604 struct ata_queued_cmd *qc;
1605
1606 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1607 return NULL;
1608 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1609 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1610 qc = NULL;
1611 return qc;
1612}
1613
29d187bb
ML		 1614static void mv_pmp_error_handler(struct ata_port *ap)
1615{
1616 unsigned int pmp, pmp_map;
1617 struct mv_port_priv *pp = ap->private_data;
1618
1619 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1620 /*
1621 * Perform NCQ error analysis on failed PMPs
1622 * before we freeze the port entirely.
1623 *
1624 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1625 */
1626 pmp_map = pp->delayed_eh_pmp_map;
1627 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1628 for (pmp = 0; pmp_map != 0; pmp++) {
1629 unsigned int this_pmp = (1 << pmp);
1630 if (pmp_map & this_pmp) {
1631 struct ata_link *link = &ap->pmp_link[pmp];
1632 pmp_map &= ~this_pmp;
1633 ata_eh_analyze_ncq_error(link);
1634 }
1635 }
1636 ata_port_freeze(ap);
1637 }
1638 sata_pmp_error_handler(ap);
1639}
1640
4c299ca3
ML		 1641static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1642{
1643 void __iomem *port_mmio = mv_ap_base(ap);
1644
1645 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1646}
1647
4c299ca3
ML		 1648static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1649{
1650 struct ata_eh_info *ehi;
1651 unsigned int pmp;
1652
1653 /*
1654 * Initialize EH info for PMPs which saw device errors
1655 */
1656 ehi = &ap->link.eh_info;
1657 for (pmp = 0; pmp_map != 0; pmp++) {
1658 unsigned int this_pmp = (1 << pmp);
1659 if (pmp_map & this_pmp) {
1660 struct ata_link *link = &ap->pmp_link[pmp];
1661
1662 pmp_map &= ~this_pmp;
1663 ehi = &link->eh_info;
1664 ata_ehi_clear_desc(ehi);
1665 ata_ehi_push_desc(ehi, "dev err");
1666 ehi->err_mask |= AC_ERR_DEV;
1667 ehi->action |= ATA_EH_RESET;
1668 ata_link_abort(link);
1669 }
1670 }
1671}
1672
1673static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1674{
1675 struct mv_port_priv *pp = ap->private_data;
1676 int failed_links;
1677 unsigned int old_map, new_map;
1678
1679 /*
1680 * Device error during FBS+NCQ operation:
1681 *
1682 * Set a port flag to prevent further I/O being enqueued.
1683 * Leave the EDMA running to drain outstanding commands from this port.
1684 * Perform the post-mortem/EH only when all responses are complete.
1685 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1686 */
1687 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1688 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1689 pp->delayed_eh_pmp_map = 0;
1690 }
1691 old_map = pp->delayed_eh_pmp_map;
1692 new_map = old_map | mv_get_err_pmp_map(ap);
1693
1694 if (old_map != new_map) {
1695 pp->delayed_eh_pmp_map = new_map;
1696 mv_pmp_eh_prep(ap, new_map & ~old_map);
1697 }
c46938cc 1698 failed_links = hweight16(new_map);
4c299ca3
ML		 1699
1700 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1701 "failed_links=%d nr_active_links=%d\n",
1702 __func__, pp->delayed_eh_pmp_map,
1703 ap->qc_active, failed_links,
1704 ap->nr_active_links);
1705
1706 if (ap->nr_active_links <= failed_links) {
1707 mv_process_crpb_entries(ap, pp);
1708 mv_stop_edma(ap);
1709 mv_eh_freeze(ap);
1710 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1711 return 1; /* handled */
1712 }
1713 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1714 return 1; /* handled */
1715}
1716
1717static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1718{
1719 /*
1720 * Possible future enhancement:
1721 *
1722 * FBS+non-NCQ operation is not yet implemented.
1723 * See related notes in mv_edma_cfg().
1724 *
1725 * Device error during FBS+non-NCQ operation:
1726 *
1727 * We need to snapshot the shadow registers for each failed command.
1728 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1729 */
1730 return 0; /* not handled */
1731}
1732
1733static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1734{
1735 struct mv_port_priv *pp = ap->private_data;
1736
1737 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1738 return 0; /* EDMA was not active: not handled */
1739 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1740 return 0; /* FBS was not active: not handled */
1741
1742 if (!(edma_err_cause & EDMA_ERR_DEV))
1743 return 0; /* non DEV error: not handled */
1744 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1745 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1746 return 0; /* other problems: not handled */
1747
1748 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1749 /*
1750 * EDMA should NOT have self-disabled for this case.
1751 * If it did, then something is wrong elsewhere,
1752 * and we cannot handle it here.
1753 */
1754 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1755 ata_port_printk(ap, KERN_WARNING,
1756 "%s: err_cause=0x%x pp_flags=0x%x\n",
1757 __func__, edma_err_cause, pp->pp_flags);
1758 return 0; /* not handled */
1759 }
1760 return mv_handle_fbs_ncq_dev_err(ap);
1761 } else {
1762 /*
1763 * EDMA should have self-disabled for this case.
1764 * If it did not, then something is wrong elsewhere,
1765 * and we cannot handle it here.
1766 */
1767 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1768 ata_port_printk(ap, KERN_WARNING,
1769 "%s: err_cause=0x%x pp_flags=0x%x\n",
1770 __func__, edma_err_cause, pp->pp_flags);
1771 return 0; /* not handled */
1772 }
1773 return mv_handle_fbs_non_ncq_dev_err(ap);
1774 }
1775 return 0; /* not handled */
1776}
1777
a9010329 1778static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 1779{
8f767f8a 1780 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 1781 char *when = "idle";
8f767f8a 1782
8f767f8a 1783 ata_ehi_clear_desc(ehi);
a9010329
ML		 1784 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1785 when = "disabled";
1786 } else if (edma_was_enabled) {
1787 when = "EDMA enabled";
8f767f8a
ML		 1788 } else {
1789 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1790 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 1791 when = "polling";
8f767f8a 1792 }
a9010329 1793 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 1794 ehi->err_mask |= AC_ERR_OTHER;
1795 ehi->action |= ATA_EH_RESET;
1796 ata_port_freeze(ap);
1797}
1798
05b308e1
BR		 1799/**
1800 * mv_err_intr - Handle error interrupts on the port
1801 * @ap: ATA channel to manipulate
8d07379d 1802 * @qc: affected command (non-NCQ), or NULL
05b308e1 1803 *
8d07379d
ML		 1804 * Most cases require a full reset of the chip's state machine,
1805 * which also performs a COMRESET.
1806 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1807 *
1808 * LOCKING:
1809 * Inherited from caller.
1810 */
37b9046a 1811static void mv_err_intr(struct ata_port *ap)
31961943
BR		 1812{
1813 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 1814 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 1815 u32 fis_cause = 0;
bdd4ddde
JG		 1816 struct mv_port_priv *pp = ap->private_data;
1817 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1818 unsigned int action = 0, err_mask = 0;
9af5c9c9 1819 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 1820 struct ata_queued_cmd *qc;
1821 int abort = 0;
20f733e7 1822
8d07379d 1823 /*
37b9046a 1824 * Read and clear the SError and err_cause bits.
e4006077
ML		 1825 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1826 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 1827 */
37b9046a
ML		 1828 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1829 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1830
bdd4ddde 1831 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
e4006077
ML		 1832 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1833 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1834 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1835 }
8d07379d 1836 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1837
4c299ca3
ML		 1838 if (edma_err_cause & EDMA_ERR_DEV) {
1839 /*
1840 * Device errors during FIS-based switching operation
1841 * require special handling.
1842 */
1843 if (mv_handle_dev_err(ap, edma_err_cause))
1844 return;
1845 }
1846
37b9046a
ML		 1847 qc = mv_get_active_qc(ap);
1848 ata_ehi_clear_desc(ehi);
1849 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1850 edma_err_cause, pp->pp_flags);
e4006077
ML		 1851
1852 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7))
1853 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
bdd4ddde 1854 /*
352fab70 1855 * All generations share these EDMA error cause bits:
bdd4ddde 1856 */
37b9046a 1857 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 1858 err_mask |= AC_ERR_DEV;
37b9046a
ML		 1859 action |= ATA_EH_RESET;
1860 ata_ehi_push_desc(ehi, "dev error");
1861 }
bdd4ddde 1862 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1863 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1864 EDMA_ERR_INTRL_PAR)) {
1865 err_mask |= AC_ERR_ATA_BUS;
cf480626 1866 action |= ATA_EH_RESET;
b64bbc39 1867 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1868 }
1869 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1870 ata_ehi_hotplugged(ehi);
1871 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1872 "dev disconnect" : "dev connect");
cf480626 1873 action |= ATA_EH_RESET;
bdd4ddde
JG		 1874 }
1875
352fab70
ML		 1876 /*
1877 * Gen-I has a different SELF_DIS bit,
1878 * different FREEZE bits, and no SERR bit:
1879 */
ee9ccdf7 1880 if (IS_GEN_I(hpriv)) {
bdd4ddde 1881 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1882 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1883 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1884 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1885 }
1886 } else {
1887 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1888 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1889 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1890 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1891 }
bdd4ddde 1892 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1893 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1894 err_mask |= AC_ERR_ATA_BUS;
cf480626 1895 action |= ATA_EH_RESET;
bdd4ddde 1896 }
afb0edd9 1897 }
20f733e7 1898
bdd4ddde
JG		 1899 if (!err_mask) {
1900 err_mask = AC_ERR_OTHER;
cf480626 1901 action |= ATA_EH_RESET;
bdd4ddde
JG		 1902 }
1903
1904 ehi->serror |= serr;
1905 ehi->action |= action;
1906
1907 if (qc)
1908 qc->err_mask |= err_mask;
1909 else
1910 ehi->err_mask |= err_mask;
1911
37b9046a
ML		 1912 if (err_mask == AC_ERR_DEV) {
1913 /*
1914 * Cannot do ata_port_freeze() here,
1915 * because it would kill PIO access,
1916 * which is needed for further diagnosis.
1917 */
1918 mv_eh_freeze(ap);
1919 abort = 1;
1920 } else if (edma_err_cause & eh_freeze_mask) {
1921 /*
1922 * Note to self: ata_port_freeze() calls ata_port_abort()
1923 */
bdd4ddde 1924 ata_port_freeze(ap);
37b9046a
ML		 1925 } else {
1926 abort = 1;
1927 }
1928
1929 if (abort) {
1930 if (qc)
1931 ata_link_abort(qc->dev->link);
1932 else
1933 ata_port_abort(ap);
1934 }
bdd4ddde
JG		 1935}
1936
fcfb1f77
ML		 1937static void mv_process_crpb_response(struct ata_port *ap,
1938 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1939{
1940 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1941
1942 if (qc) {
1943 u8 ata_status;
1944 u16 edma_status = le16_to_cpu(response->flags);
1945 /*
1946 * edma_status from a response queue entry:
1947 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1948 * MSB is saved ATA status from command completion.
1949 */
1950 if (!ncq_enabled) {
1951 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1952 if (err_cause) {
1953 /*
1954 * Error will be seen/handled by mv_err_intr().
1955 * So do nothing at all here.
1956 */
1957 return;
1958 }
1959 }
1960 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 1961 if (!ac_err_mask(ata_status))
1962 ata_qc_complete(qc);
1963 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 1964 } else {
1965 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1966 __func__, tag);
1967 }
1968}
1969
1970static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 1971{
1972 void __iomem *port_mmio = mv_ap_base(ap);
1973 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 1974 u32 in_index;
bdd4ddde 1975 bool work_done = false;
fcfb1f77 1976 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 1977
fcfb1f77 1978 /* Get the hardware queue position index */
bdd4ddde
JG		 1979 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1980 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1981
fcfb1f77
ML		 1982 /* Process new responses from since the last time we looked */
1983 while (in_index != pp->resp_idx) {
6c1153e0 1984 unsigned int tag;
fcfb1f77 1985 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 1986
fcfb1f77 1987 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 1988
fcfb1f77
ML		 1989 if (IS_GEN_I(hpriv)) {
1990 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 1991 tag = ap->link.active_tag;
fcfb1f77
ML		 1992 } else {
1993 /* Gen II/IIE: get command tag from CRPB entry */
1994 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 1995 }
fcfb1f77 1996 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 1997 work_done = true;
bdd4ddde
JG		 1998 }
1999
352fab70 2000 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2001 if (work_done)
2002 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2003 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2004 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2005}
2006
a9010329
ML		 2007static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2008{
2009 struct mv_port_priv *pp;
2010 int edma_was_enabled;
2011
2012 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2013 mv_unexpected_intr(ap, 0);
2014 return;
2015 }
2016 /*
2017 * Grab a snapshot of the EDMA_EN flag setting,
2018 * so that we have a consistent view for this port,
2019 * even if something we call of our routines changes it.
2020 */
2021 pp = ap->private_data;
2022 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2023 /*
2024 * Process completed CRPB response(s) before other events.
2025 */
2026 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2027 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2028 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2029 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2030 }
2031 /*
2032 * Handle chip-reported errors, or continue on to handle PIO.
2033 */
2034 if (unlikely(port_cause & ERR_IRQ)) {
2035 mv_err_intr(ap);
2036 } else if (!edma_was_enabled) {
2037 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2038 if (qc)
2039 ata_sff_host_intr(ap, qc);
2040 else
2041 mv_unexpected_intr(ap, edma_was_enabled);
2042 }
2043}
2044
05b308e1
BR		 2045/**
2046 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2047 * @host: host specific structure
7368f919 2048 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2049 *
2050 * LOCKING:
2051 * Inherited from caller.
2052 */
7368f919 2053static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2054{
f351b2d6 2055 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2056 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2057 unsigned int handled = 0, port;
20f733e7 2058
a3718c1f 2059 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2060 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2061 unsigned int p, shift, hardport, port_cause;
2062
a3718c1f 2063 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2064 /*
eabd5eb1
ML		 2065 * Each hc within the host has its own hc_irq_cause register,
2066 * where the interrupting ports bits get ack'd.
a3718c1f 2067 */
eabd5eb1
ML		 2068 if (hardport == 0) { /* first port on this hc ? */
2069 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2070 u32 port_mask, ack_irqs;
2071 /*
2072 * Skip this entire hc if nothing pending for any ports
2073 */
2074 if (!hc_cause) {
2075 port += MV_PORTS_PER_HC - 1;
2076 continue;
2077 }
2078 /*
2079 * We don't need/want to read the hc_irq_cause register,
2080 * because doing so hurts performance, and
2081 * main_irq_cause already gives us everything we need.
2082 *
2083 * But we do have to *write* to the hc_irq_cause to ack
2084 * the ports that we are handling this time through.
2085 *
2086 * This requires that we create a bitmap for those
2087 * ports which interrupted us, and use that bitmap
2088 * to ack (only) those ports via hc_irq_cause.
2089 */
2090 ack_irqs = 0;
2091 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2092 if ((port + p) >= hpriv->n_ports)
2093 break;
2094 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2095 if (hc_cause & port_mask)
2096 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2097 }
a3718c1f 2098 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2099 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2100 handled = 1;
2101 }
8f767f8a 2102 /*
a9010329 2103 * Handle interrupts signalled for this port:
8f767f8a 2104 */
a9010329
ML		 2105 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2106 if (port_cause)
2107 mv_port_intr(ap, port_cause);
20f733e7 2108 }
a3718c1f 2109 return handled;
20f733e7
BR		 2110}
2111
a3718c1f 2112static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2113{
02a121da 2114 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2115 struct ata_port *ap;
2116 struct ata_queued_cmd *qc;
2117 struct ata_eh_info *ehi;
2118 unsigned int i, err_mask, printed = 0;
2119 u32 err_cause;
2120
02a121da 2121 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2122
2123 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2124 err_cause);
2125
2126 DPRINTK("All regs @ PCI error\n");
2127 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2128
02a121da 2129 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2130
2131 for (i = 0; i < host->n_ports; i++) {
2132 ap = host->ports[i];
936fd732 2133 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2134 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2135 ata_ehi_clear_desc(ehi);
2136 if (!printed++)
2137 ata_ehi_push_desc(ehi,
2138 "PCI err cause 0x%08x", err_cause);
2139 err_mask = AC_ERR_HOST_BUS;
cf480626 2140 ehi->action = ATA_EH_RESET;
9af5c9c9 2141 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2142 if (qc)
2143 qc->err_mask |= err_mask;
2144 else
2145 ehi->err_mask |= err_mask;
2146
2147 ata_port_freeze(ap);
2148 }
2149 }
a3718c1f 2150 return 1; /* handled */
bdd4ddde
JG		 2151}
2152
05b308e1 2153/**
c5d3e45a 2154 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2155 * @irq: unused
2156 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2157 *
2158 * Read the read only register to determine if any host
2159 * controllers have pending interrupts. If so, call lower level
2160 * routine to handle. Also check for PCI errors which are only
2161 * reported here.
2162 *
8b260248 2163 * LOCKING:
cca3974e 2164 * This routine holds the host lock while processing pending
05b308e1
BR		 2165 * interrupts.
2166 */
7d12e780 2167static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2168{
cca3974e 2169 struct ata_host *host = dev_instance;
f351b2d6 2170 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2171 unsigned int handled = 0;
7368f919 2172 u32 main_irq_cause, main_irq_mask;
20f733e7 2173
646a4da5 2174 spin_lock(&host->lock);
7368f919
ML		 2175 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2176 main_irq_mask = readl(hpriv->main_irq_mask_addr);
352fab70
ML		 2177 /*
2178 * Deal with cases where we either have nothing pending, or have read
2179 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2180 */
7368f919
ML		 2181 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
2182 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
a3718c1f
ML		 2183 handled = mv_pci_error(host, hpriv->base);
2184 else
7368f919 2185 handled = mv_host_intr(host, main_irq_cause);
bdd4ddde 2186 }
cca3974e 2187 spin_unlock(&host->lock);
20f733e7
BR		 2188 return IRQ_RETVAL(handled);
2189}
2190
c9d39130
JG		 2191static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2192{
2193 unsigned int ofs;
2194
2195 switch (sc_reg_in) {
2196 case SCR_STATUS:
2197 case SCR_ERROR:
2198 case SCR_CONTROL:
2199 ofs = sc_reg_in * sizeof(u32);
2200 break;
2201 default:
2202 ofs = 0xffffffffU;
2203 break;
2204 }
2205 return ofs;
2206}
2207
da3dbb17 2208static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 2209{
f351b2d6
SB		 2210 struct mv_host_priv *hpriv = ap->host->private_data;
2211 void __iomem *mmio = hpriv->base;
0d5ff566 2212 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2213 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2214
da3dbb17
TH		 2215 if (ofs != 0xffffffffU) {
2216 *val = readl(addr + ofs);
2217 return 0;
2218 } else
2219 return -EINVAL;
c9d39130
JG		 2220}
2221
da3dbb17 2222static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 2223{
f351b2d6
SB		 2224 struct mv_host_priv *hpriv = ap->host->private_data;
2225 void __iomem *mmio = hpriv->base;
0d5ff566 2226 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2227 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2228
da3dbb17 2229 if (ofs != 0xffffffffU) {
0d5ff566 2230 writelfl(val, addr + ofs);
da3dbb17
TH		 2231 return 0;
2232 } else
2233 return -EINVAL;
c9d39130
JG		 2234}
2235
7bb3c529 2236static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2237{
7bb3c529 2238 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2239 int early_5080;
2240
44c10138 2241 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2242
2243 if (!early_5080) {
2244 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2245 tmp |= (1 << 0);
2246 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2247 }
2248
7bb3c529 2249 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2250}
2251
2252static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2253{
8e7decdb 2254 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2255}
2256
47c2b677 2257static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2258 void __iomem *mmio)
2259{
c9d39130
JG		 2260 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2261 u32 tmp;
2262
2263 tmp = readl(phy_mmio + MV5_PHY_MODE);
2264
2265 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2266 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2267}
2268
47c2b677 2269static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2270{
522479fb
JG		 2271 u32 tmp;
2272
8e7decdb 2273 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2274
2275 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2276
2277 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2278 tmp |= ~(1 << 0);
2279 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2280}
2281
2a47ce06
JG		 2282static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2283 unsigned int port)
bca1c4eb 2284{
c9d39130
JG		 2285 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2286 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2287 u32 tmp;
2288 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2289
2290 if (fix_apm_sq) {
8e7decdb 2291 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2292 tmp |= (1 << 19);
8e7decdb 2293 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2294
8e7decdb 2295 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2296 tmp &= ~0x3;
2297 tmp |= 0x1;
8e7decdb 2298 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2299 }
2300
2301 tmp = readl(phy_mmio + MV5_PHY_MODE);
2302 tmp &= ~mask;
2303 tmp |= hpriv->signal[port].pre;
2304 tmp |= hpriv->signal[port].amps;
2305 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2306}
2307
c9d39130
JG		 2308
2309#undef ZERO
2310#define ZERO(reg) writel(0, port_mmio + (reg))
2311static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2312 unsigned int port)
2313{
2314 void __iomem *port_mmio = mv_port_base(mmio, port);
2315
e12bef50 2316 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2317
2318 ZERO(0x028); /* command */
2319 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2320 ZERO(0x004); /* timer */
2321 ZERO(0x008); /* irq err cause */
2322 ZERO(0x00c); /* irq err mask */
2323 ZERO(0x010); /* rq bah */
2324 ZERO(0x014); /* rq inp */
2325 ZERO(0x018); /* rq outp */
2326 ZERO(0x01c); /* respq bah */
2327 ZERO(0x024); /* respq outp */
2328 ZERO(0x020); /* respq inp */
2329 ZERO(0x02c); /* test control */
8e7decdb 2330 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2331}
2332#undef ZERO
2333
2334#define ZERO(reg) writel(0, hc_mmio + (reg))
2335static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2336 unsigned int hc)
47c2b677 2337{
c9d39130
JG		 2338 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2339 u32 tmp;
2340
2341 ZERO(0x00c);
2342 ZERO(0x010);
2343 ZERO(0x014);
2344 ZERO(0x018);
2345
2346 tmp = readl(hc_mmio + 0x20);
2347 tmp &= 0x1c1c1c1c;
2348 tmp |= 0x03030303;
2349 writel(tmp, hc_mmio + 0x20);
2350}
2351#undef ZERO
2352
2353static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2354 unsigned int n_hc)
2355{
2356 unsigned int hc, port;
2357
2358 for (hc = 0; hc < n_hc; hc++) {
2359 for (port = 0; port < MV_PORTS_PER_HC; port++)
2360 mv5_reset_hc_port(hpriv, mmio,
2361 (hc * MV_PORTS_PER_HC) + port);
2362
2363 mv5_reset_one_hc(hpriv, mmio, hc);
2364 }
2365
2366 return 0;
47c2b677
JG		 2367}
2368
101ffae2
JG		 2369#undef ZERO
2370#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2371static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2372{
02a121da 2373 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2374 u32 tmp;
2375
8e7decdb 2376 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2377 tmp &= 0xff00ffff;
8e7decdb 2378 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2379
2380 ZERO(MV_PCI_DISC_TIMER);
2381 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2382 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
7368f919 2383 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
101ffae2 2384 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2385 ZERO(hpriv->irq_cause_ofs);
2386 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2387 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2388 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2389 ZERO(MV_PCI_ERR_ATTRIBUTE);
2390 ZERO(MV_PCI_ERR_COMMAND);
2391}
2392#undef ZERO
2393
2394static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2395{
2396 u32 tmp;
2397
2398 mv5_reset_flash(hpriv, mmio);
2399
8e7decdb 2400 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2401 tmp &= 0x3;
2402 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2403 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2404}
2405
2406/**
2407 * mv6_reset_hc - Perform the 6xxx global soft reset
2408 * @mmio: base address of the HBA
2409 *
2410 * This routine only applies to 6xxx parts.
2411 *
2412 * LOCKING:
2413 * Inherited from caller.
2414 */
c9d39130
JG		 2415static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2416 unsigned int n_hc)
101ffae2
JG		 2417{
2418 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2419 int i, rc = 0;
2420 u32 t;
2421
2422 /* Following procedure defined in PCI "main command and status
2423 * register" table.
2424 */
2425 t = readl(reg);
2426 writel(t | STOP_PCI_MASTER, reg);
2427
2428 for (i = 0; i < 1000; i++) {
2429 udelay(1);
2430 t = readl(reg);
2dcb407e 2431 if (PCI_MASTER_EMPTY & t)
101ffae2 2432 break;
101ffae2
JG		 2433 }
2434 if (!(PCI_MASTER_EMPTY & t)) {
2435 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2436 rc = 1;
2437 goto done;
2438 }
2439
2440 /* set reset */
2441 i = 5;
2442 do {
2443 writel(t | GLOB_SFT_RST, reg);
2444 t = readl(reg);
2445 udelay(1);
2446 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2447
2448 if (!(GLOB_SFT_RST & t)) {
2449 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2450 rc = 1;
2451 goto done;
2452 }
2453
2454 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2455 i = 5;
2456 do {
2457 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2458 t = readl(reg);
2459 udelay(1);
2460 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2461
2462 if (GLOB_SFT_RST & t) {
2463 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2464 rc = 1;
2465 }
2466done:
2467 return rc;
2468}
2469
47c2b677 2470static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2471 void __iomem *mmio)
2472{
2473 void __iomem *port_mmio;
2474 u32 tmp;
2475
8e7decdb 2476 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2477 if ((tmp & (1 << 0)) == 0) {
47c2b677 2478 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2479 hpriv->signal[idx].pre = 0x1 << 5;
2480 return;
2481 }
2482
2483 port_mmio = mv_port_base(mmio, idx);
2484 tmp = readl(port_mmio + PHY_MODE2);
2485
2486 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2487 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2488}
2489
47c2b677 2490static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2491{
8e7decdb 2492 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2493}
2494
c9d39130 2495static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2496 unsigned int port)
bca1c4eb 2497{
c9d39130
JG		 2498 void __iomem *port_mmio = mv_port_base(mmio, port);
2499
bca1c4eb 2500 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2501 int fix_phy_mode2 =
2502 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2503 int fix_phy_mode4 =
47c2b677
JG		 2504 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2505 u32 m2, tmp;
2506
2507 if (fix_phy_mode2) {
2508 m2 = readl(port_mmio + PHY_MODE2);
2509 m2 &= ~(1 << 16);
2510 m2 |= (1 << 31);
2511 writel(m2, port_mmio + PHY_MODE2);
2512
2513 udelay(200);
2514
2515 m2 = readl(port_mmio + PHY_MODE2);
2516 m2 &= ~((1 << 16) | (1 << 31));
2517 writel(m2, port_mmio + PHY_MODE2);
2518
2519 udelay(200);
2520 }
2521
2522 /* who knows what this magic does */
2523 tmp = readl(port_mmio + PHY_MODE3);
2524 tmp &= ~0x7F800000;
2525 tmp |= 0x2A800000;
2526 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2527
2528 if (fix_phy_mode4) {
47c2b677 2529 u32 m4;
bca1c4eb
JG		 2530
2531 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 2532
2533 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2534 tmp = readl(port_mmio + PHY_MODE3);
bca1c4eb 2535
e12bef50 2536 /* workaround for errata FEr SATA#10 (part 1) */
bca1c4eb
JG		 2537 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2538
2539 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 2540
2541 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2542 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2543 }
2544
2545 /* Revert values of pre-emphasis and signal amps to the saved ones */
2546 m2 = readl(port_mmio + PHY_MODE2);
2547
2548 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2549 m2 |= hpriv->signal[port].amps;
2550 m2 |= hpriv->signal[port].pre;
47c2b677 2551 m2 &= ~(1 << 16);
bca1c4eb 2552
e4e7b892
JG		 2553 /* according to mvSata 3.6.1, some IIE values are fixed */
2554 if (IS_GEN_IIE(hpriv)) {
2555 m2 &= ~0xC30FF01F;
2556 m2 |= 0x0000900F;
2557 }
2558
bca1c4eb
JG		 2559 writel(m2, port_mmio + PHY_MODE2);
2560}
2561
f351b2d6
SB		 2562/* TODO: use the generic LED interface to configure the SATA Presence */
2563/* & Acitivy LEDs on the board */
2564static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2565 void __iomem *mmio)
2566{
2567 return;
2568}
2569
2570static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2571 void __iomem *mmio)
2572{
2573 void __iomem *port_mmio;
2574 u32 tmp;
2575
2576 port_mmio = mv_port_base(mmio, idx);
2577 tmp = readl(port_mmio + PHY_MODE2);
2578
2579 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2580 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2581}
2582
2583#undef ZERO
2584#define ZERO(reg) writel(0, port_mmio + (reg))
2585static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2586 void __iomem *mmio, unsigned int port)
2587{
2588 void __iomem *port_mmio = mv_port_base(mmio, port);
2589
e12bef50 2590 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2591
2592 ZERO(0x028); /* command */
2593 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2594 ZERO(0x004); /* timer */
2595 ZERO(0x008); /* irq err cause */
2596 ZERO(0x00c); /* irq err mask */
2597 ZERO(0x010); /* rq bah */
2598 ZERO(0x014); /* rq inp */
2599 ZERO(0x018); /* rq outp */
2600 ZERO(0x01c); /* respq bah */
2601 ZERO(0x024); /* respq outp */
2602 ZERO(0x020); /* respq inp */
2603 ZERO(0x02c); /* test control */
8e7decdb 2604 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2605}
2606
2607#undef ZERO
2608
2609#define ZERO(reg) writel(0, hc_mmio + (reg))
2610static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2611 void __iomem *mmio)
2612{
2613 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2614
2615 ZERO(0x00c);
2616 ZERO(0x010);
2617 ZERO(0x014);
2618
2619}
2620
2621#undef ZERO
2622
2623static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2624 void __iomem *mmio, unsigned int n_hc)
2625{
2626 unsigned int port;
2627
2628 for (port = 0; port < hpriv->n_ports; port++)
2629 mv_soc_reset_hc_port(hpriv, mmio, port);
2630
2631 mv_soc_reset_one_hc(hpriv, mmio);
2632
2633 return 0;
2634}
2635
2636static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2637 void __iomem *mmio)
2638{
2639 return;
2640}
2641
2642static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2643{
2644 return;
2645}
2646
8e7decdb 2647static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2648{
8e7decdb 2649 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2650
8e7decdb 2651 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2652 if (want_gen2i)
8e7decdb
ML		 2653 ifcfg |= (1 << 7); /* enable gen2i speed */
2654 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2655}
2656
e12bef50 2657static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2658 unsigned int port_no)
2659{
2660 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2661
8e7decdb
ML		 2662 /*
2663 * The datasheet warns against setting EDMA_RESET when EDMA is active
2664 * (but doesn't say what the problem might be). So we first try
2665 * to disable the EDMA engine before doing the EDMA_RESET operation.
2666 */
0d8be5cb 2667 mv_stop_edma_engine(port_mmio);
8e7decdb 2668 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2669
b67a1064 2670 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2671 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2672 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2673 }
b67a1064 2674 /*
8e7decdb 2675 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2676 * link, and physical layers. It resets all SATA interface registers
2677 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2678 */
8e7decdb 2679 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2680 udelay(25); /* allow reset propagation */
c9d39130
JG		 2681 writelfl(0, port_mmio + EDMA_CMD_OFS);
2682
2683 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2684
ee9ccdf7 2685 if (IS_GEN_I(hpriv))
c9d39130
JG		 2686 mdelay(1);
2687}
2688
e49856d8 2689static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2690{
e49856d8
ML		 2691 if (sata_pmp_supported(ap)) {
2692 void __iomem *port_mmio = mv_ap_base(ap);
2693 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2694 int old = reg & 0xf;
22374677 2695
e49856d8
ML		 2696 if (old != pmp) {
2697 reg = (reg & ~0xf) | pmp;
2698 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2699 }
22374677 2700 }
20f733e7
BR		 2701}
2702
e49856d8
ML		 2703static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2704 unsigned long deadline)
22374677 2705{
e49856d8
ML		 2706 mv_pmp_select(link->ap, sata_srst_pmp(link));
2707 return sata_std_hardreset(link, class, deadline);
2708}
bdd4ddde 2709
e49856d8
ML		 2710static int mv_softreset(struct ata_link *link, unsigned int *class,
2711 unsigned long deadline)
2712{
2713 mv_pmp_select(link->ap, sata_srst_pmp(link));
2714 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2715}
2716
cc0680a5 2717static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2718 unsigned long deadline)
31961943 2719{
cc0680a5 2720 struct ata_port *ap = link->ap;
bdd4ddde 2721 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2722 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2723 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2724 int rc, attempts = 0, extra = 0;
2725 u32 sstatus;
2726 bool online;
31961943 2727
e12bef50 2728 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2729 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2730
0d8be5cb
ML		 2731 /* Workaround for errata FEr SATA#10 (part 2) */
2732 do {
17c5aab5
ML		 2733 const unsigned long *timing =
2734 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2735
17c5aab5
ML		 2736 rc = sata_link_hardreset(link, timing, deadline + extra,
2737 &online, NULL);
9dcffd99 2738 rc = online ? -EAGAIN : rc;
17c5aab5 2739 if (rc)
0d8be5cb 2740 return rc;
0d8be5cb
ML		 2741 sata_scr_read(link, SCR_STATUS, &sstatus);
2742 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2743 /* Force 1.5gb/s link speed and try again */
8e7decdb 2744 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2745 if (time_after(jiffies + HZ, deadline))
2746 extra = HZ; /* only extend it once, max */
2747 }
2748 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2749
17c5aab5 2750 return rc;
bdd4ddde
JG		 2751}
2752
bdd4ddde
JG		 2753static void mv_eh_freeze(struct ata_port *ap)
2754{
f351b2d6 2755 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae 2756 unsigned int shift, hardport, port = ap->port_no;
7368f919 2757 u32 main_irq_mask;
bdd4ddde
JG		 2758
2759 /* FIXME: handle coalescing completion events properly */
2760
1cfd19ae
ML		 2761 mv_stop_edma(ap);
2762 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2763
bdd4ddde 2764 /* disable assertion of portN err, done events */
7368f919
ML		 2765 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2766 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2767 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
bdd4ddde
JG		 2768}
2769
2770static void mv_eh_thaw(struct ata_port *ap)
2771{
f351b2d6 2772 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae
ML		 2773 unsigned int shift, hardport, port = ap->port_no;
2774 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2775 void __iomem *port_mmio = mv_ap_base(ap);
7368f919 2776 u32 main_irq_mask, hc_irq_cause;
bdd4ddde
JG		 2777
2778 /* FIXME: handle coalescing completion events properly */
2779
1cfd19ae 2780 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2781
bdd4ddde
JG		 2782 /* clear EDMA errors on this port */
2783 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2784
2785 /* clear pending irq events */
2786 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1cfd19ae
ML		 2787 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2788 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde
JG		 2789
2790 /* enable assertion of portN err, done events */
7368f919
ML		 2791 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2792 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2793 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
31961943
BR		 2794}
2795
05b308e1
BR		 2796/**
2797 * mv_port_init - Perform some early initialization on a single port.
2798 * @port: libata data structure storing shadow register addresses
2799 * @port_mmio: base address of the port
2800 *
2801 * Initialize shadow register mmio addresses, clear outstanding
2802 * interrupts on the port, and unmask interrupts for the future
2803 * start of the port.
2804 *
2805 * LOCKING:
2806 * Inherited from caller.
2807 */
31961943 2808static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2809{
0d5ff566 2810 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2811 unsigned serr_ofs;
2812
8b260248 2813 /* PIO related setup
31961943
BR		 2814 */
2815 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2816 port->error_addr =
31961943
BR		 2817 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2818 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2819 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2820 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2821 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2822 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2823 port->status_addr =
31961943
BR		 2824 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2825 /* special case: control/altstatus doesn't have ATA_REG_ address */
2826 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2827
2828 /* unused: */
8d9db2d2 2829 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2830
31961943
BR		 2831 /* Clear any currently outstanding port interrupt conditions */
2832 serr_ofs = mv_scr_offset(SCR_ERROR);
2833 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2834 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2835
646a4da5
ML		 2836 /* unmask all non-transient EDMA error interrupts */
2837 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2838
8b260248 2839 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2840 readl(port_mmio + EDMA_CFG_OFS),
2841 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2842 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2843}
2844
616d4a98
ML		 2845static unsigned int mv_in_pcix_mode(struct ata_host *host)
2846{
2847 struct mv_host_priv *hpriv = host->private_data;
2848 void __iomem *mmio = hpriv->base;
2849 u32 reg;
2850
2851 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2852 return 0; /* not PCI-X capable */
2853 reg = readl(mmio + MV_PCI_MODE_OFS);
2854 if ((reg & MV_PCI_MODE_MASK) == 0)
2855 return 0; /* conventional PCI mode */
2856 return 1; /* chip is in PCI-X mode */
2857}
2858
2859static int mv_pci_cut_through_okay(struct ata_host *host)
2860{
2861 struct mv_host_priv *hpriv = host->private_data;
2862 void __iomem *mmio = hpriv->base;
2863 u32 reg;
2864
2865 if (!mv_in_pcix_mode(host)) {
2866 reg = readl(mmio + PCI_COMMAND_OFS);
2867 if (reg & PCI_COMMAND_MRDTRIG)
2868 return 0; /* not okay */
2869 }
2870 return 1; /* okay */
2871}
2872
4447d351 2873static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2874{
4447d351
TH		 2875 struct pci_dev *pdev = to_pci_dev(host->dev);
2876 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2877 u32 hp_flags = hpriv->hp_flags;
2878
5796d1c4 2879 switch (board_idx) {
47c2b677
JG		 2880 case chip_5080:
2881 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2882 hp_flags |= MV_HP_GEN_I;
47c2b677 2883
44c10138 2884 switch (pdev->revision) {
47c2b677
JG		 2885 case 0x1:
2886 hp_flags |= MV_HP_ERRATA_50XXB0;
2887 break;
2888 case 0x3:
2889 hp_flags |= MV_HP_ERRATA_50XXB2;
2890 break;
2891 default:
2892 dev_printk(KERN_WARNING, &pdev->dev,
2893 "Applying 50XXB2 workarounds to unknown rev\n");
2894 hp_flags |= MV_HP_ERRATA_50XXB2;
2895 break;
2896 }
2897 break;
2898
bca1c4eb
JG		 2899 case chip_504x:
2900 case chip_508x:
47c2b677 2901 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2902 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2903
44c10138 2904 switch (pdev->revision) {
47c2b677
JG		 2905 case 0x0:
2906 hp_flags |= MV_HP_ERRATA_50XXB0;
2907 break;
2908 case 0x3:
2909 hp_flags |= MV_HP_ERRATA_50XXB2;
2910 break;
2911 default:
2912 dev_printk(KERN_WARNING, &pdev->dev,
2913 "Applying B2 workarounds to unknown rev\n");
2914 hp_flags |= MV_HP_ERRATA_50XXB2;
2915 break;
bca1c4eb
JG		 2916 }
2917 break;
2918
2919 case chip_604x:
2920 case chip_608x:
47c2b677 2921 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2922 hp_flags |= MV_HP_GEN_II;
47c2b677 2923
44c10138 2924 switch (pdev->revision) {
47c2b677
JG		 2925 case 0x7:
2926 hp_flags |= MV_HP_ERRATA_60X1B2;
2927 break;
2928 case 0x9:
2929 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2930 break;
2931 default:
2932 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2933 "Applying B2 workarounds to unknown rev\n");
2934 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2935 break;
2936 }
2937 break;
2938
e4e7b892 2939 case chip_7042:
616d4a98 2940 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2941 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2942 (pdev->device == 0x2300 || pdev->device == 0x2310))
2943 {
4e520033
ML		 2944 /*
2945 * Highpoint RocketRAID PCIe 23xx series cards:
2946 *
2947 * Unconfigured drives are treated as "Legacy"
2948 * by the BIOS, and it overwrites sector 8 with
2949 * a "Lgcy" metadata block prior to Linux boot.
2950 *
2951 * Configured drives (RAID or JBOD) leave sector 8
2952 * alone, but instead overwrite a high numbered
2953 * sector for the RAID metadata. This sector can
2954 * be determined exactly, by truncating the physical
2955 * drive capacity to a nice even GB value.
2956 *
2957 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2958 *
2959 * Warn the user, lest they think we're just buggy.
2960 */
2961 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2962 " BIOS CORRUPTS DATA on all attached drives,"
2963 " regardless of if/how they are configured."
2964 " BEWARE!\n");
2965 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2966 " use sectors 8-9 on \"Legacy\" drives,"
2967 " and avoid the final two gigabytes on"
2968 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2969 }
8e7decdb 2970 /* drop through */
e4e7b892
JG		 2971 case chip_6042:
2972 hpriv->ops = &mv6xxx_ops;
e4e7b892 2973 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 2974 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2975 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 2976
44c10138 2977 switch (pdev->revision) {
e4e7b892
JG		 2978 case 0x0:
2979 hp_flags |= MV_HP_ERRATA_XX42A0;
2980 break;
2981 case 0x1:
2982 hp_flags |= MV_HP_ERRATA_60X1C0;
2983 break;
2984 default:
2985 dev_printk(KERN_WARNING, &pdev->dev,
2986 "Applying 60X1C0 workarounds to unknown rev\n");
2987 hp_flags |= MV_HP_ERRATA_60X1C0;
2988 break;
2989 }
2990 break;
f351b2d6
SB		 2991 case chip_soc:
2992 hpriv->ops = &mv_soc_ops;
2993 hp_flags |= MV_HP_ERRATA_60X1C0;
2994 break;
e4e7b892 2995
bca1c4eb 2996 default:
f351b2d6 2997 dev_printk(KERN_ERR, host->dev,
5796d1c4 2998 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 2999 return 1;
3000 }
3001
3002 hpriv->hp_flags = hp_flags;
02a121da
ML		 3003 if (hp_flags & MV_HP_PCIE) {
3004 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3005 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3006 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3007 } else {
3008 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3009 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3010 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3011 }
bca1c4eb
JG		 3012
3013 return 0;
3014}
3015
05b308e1 3016/**
47c2b677 3017 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3018 * @host: ATA host to initialize
3019 * @board_idx: controller index
05b308e1
BR		 3020 *
3021 * If possible, do an early global reset of the host. Then do
3022 * our port init and clear/unmask all/relevant host interrupts.
3023 *
3024 * LOCKING:
3025 * Inherited from caller.
3026 */
4447d351 3027static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3028{
3029 int rc = 0, n_hc, port, hc;
4447d351 3030 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3031 void __iomem *mmio = hpriv->base;
47c2b677 3032
4447d351 3033 rc = mv_chip_id(host, board_idx);
bca1c4eb 3034 if (rc)
352fab70 3035 goto done;
f351b2d6
SB		 3036
3037 if (HAS_PCI(host)) {
7368f919
ML		 3038 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3039 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3040 } else {
7368f919
ML		 3041 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3042 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3043 }
352fab70
ML		 3044
3045 /* global interrupt mask: 0 == mask everything */
7368f919 3046 writel(0, hpriv->main_irq_mask_addr);
bca1c4eb 3047
4447d351 3048 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3049
4447d351 3050 for (port = 0; port < host->n_ports; port++)
47c2b677 3051 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3052
c9d39130 3053 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3054 if (rc)
20f733e7 3055 goto done;
20f733e7 3056
522479fb 3057 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3058 hpriv->ops->reset_bus(host, mmio);
47c2b677 3059 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3060
4447d351 3061 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3062 struct ata_port *ap = host->ports[port];
2a47ce06 3063 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3064
3065 mv_port_init(&ap->ioaddr, port_mmio);
3066
7bb3c529 3067#ifdef CONFIG_PCI
f351b2d6
SB		 3068 if (HAS_PCI(host)) {
3069 unsigned int offset = port_mmio - mmio;
3070 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3071 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3072 }
7bb3c529 3073#endif
20f733e7
BR		 3074 }
3075
3076 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3077 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3078
3079 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3080 "(before clear)=0x%08x\n", hc,
3081 readl(hc_mmio + HC_CFG_OFS),
3082 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3083
3084 /* Clear any currently outstanding hc interrupt conditions */
3085 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3086 }
3087
f351b2d6
SB		 3088 if (HAS_PCI(host)) {
3089 /* Clear any currently outstanding host interrupt conditions */
3090 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3091
f351b2d6
SB		 3092 /* and unmask interrupt generation for host regs */
3093 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3094 if (IS_GEN_I(hpriv))
3095 writelfl(~HC_MAIN_MASKED_IRQS_5,
7368f919 3096 hpriv->main_irq_mask_addr);
f351b2d6
SB		 3097 else
3098 writelfl(~HC_MAIN_MASKED_IRQS,
7368f919 3099 hpriv->main_irq_mask_addr);
f351b2d6
SB		 3100
3101 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
3102 "PCI int cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 3103 readl(hpriv->main_irq_cause_addr),
3104 readl(hpriv->main_irq_mask_addr),
f351b2d6
SB		 3105 readl(mmio + hpriv->irq_cause_ofs),
3106 readl(mmio + hpriv->irq_mask_ofs));
3107 } else {
3108 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
7368f919 3109 hpriv->main_irq_mask_addr);
f351b2d6 3110 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 3111 readl(hpriv->main_irq_cause_addr),
3112 readl(hpriv->main_irq_mask_addr));
f351b2d6
SB		 3113 }
3114done:
3115 return rc;
3116}
fb621e2f 3117
fbf14e2f
BB		 3118static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3119{
3120 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3121 MV_CRQB_Q_SZ, 0);
3122 if (!hpriv->crqb_pool)
3123 return -ENOMEM;
3124
3125 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3126 MV_CRPB_Q_SZ, 0);
3127 if (!hpriv->crpb_pool)
3128 return -ENOMEM;
3129
3130 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3131 MV_SG_TBL_SZ, 0);
3132 if (!hpriv->sg_tbl_pool)
3133 return -ENOMEM;
3134
3135 return 0;
3136}
3137
15a32632
LB		 3138static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3139 struct mbus_dram_target_info *dram)
3140{
3141 int i;
3142
3143 for (i = 0; i < 4; i++) {
3144 writel(0, hpriv->base + WINDOW_CTRL(i));
3145 writel(0, hpriv->base + WINDOW_BASE(i));
3146 }
3147
3148 for (i = 0; i < dram->num_cs; i++) {
3149 struct mbus_dram_window *cs = dram->cs + i;
3150
3151 writel(((cs->size - 1) & 0xffff0000) |
3152 (cs->mbus_attr << 8) |
3153 (dram->mbus_dram_target_id << 4) | 1,
3154 hpriv->base + WINDOW_CTRL(i));
3155 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3156 }
3157}
3158
f351b2d6
SB		 3159/**
3160 * mv_platform_probe - handle a positive probe of an soc Marvell
3161 * host
3162 * @pdev: platform device found
3163 *
3164 * LOCKING:
3165 * Inherited from caller.
3166 */
3167static int mv_platform_probe(struct platform_device *pdev)
3168{
3169 static int printed_version;
3170 const struct mv_sata_platform_data *mv_platform_data;
3171 const struct ata_port_info *ppi[] =
3172 { &mv_port_info[chip_soc], NULL };
3173 struct ata_host *host;
3174 struct mv_host_priv *hpriv;
3175 struct resource *res;
3176 int n_ports, rc;
20f733e7 3177
f351b2d6
SB		 3178 if (!printed_version++)
3179 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3180
f351b2d6
SB		 3181 /*
3182 * Simple resource validation ..
3183 */
3184 if (unlikely(pdev->num_resources != 2)) {
3185 dev_err(&pdev->dev, "invalid number of resources\n");
3186 return -EINVAL;
3187 }
3188
3189 /*
3190 * Get the register base first
3191 */
3192 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3193 if (res == NULL)
3194 return -EINVAL;
3195
3196 /* allocate host */
3197 mv_platform_data = pdev->dev.platform_data;
3198 n_ports = mv_platform_data->n_ports;
3199
3200 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3201 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3202
3203 if (!host || !hpriv)
3204 return -ENOMEM;
3205 host->private_data = hpriv;
3206 hpriv->n_ports = n_ports;
3207
3208 host->iomap = NULL;
f1cb0ea1
SB		 3209 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3210 res->end - res->start + 1);
f351b2d6
SB		 3211 hpriv->base -= MV_SATAHC0_REG_BASE;
3212
15a32632
LB		 3213 /*
3214 * (Re-)program MBUS remapping windows if we are asked to.
3215 */
3216 if (mv_platform_data->dram != NULL)
3217 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3218
fbf14e2f
BB		 3219 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3220 if (rc)
3221 return rc;
3222
f351b2d6
SB		 3223 /* initialize adapter */
3224 rc = mv_init_host(host, chip_soc);
3225 if (rc)
3226 return rc;
3227
3228 dev_printk(KERN_INFO, &pdev->dev,
3229 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3230 host->n_ports);
3231
3232 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3233 IRQF_SHARED, &mv6_sht);
3234}
3235
3236/*
3237 *
3238 * mv_platform_remove - unplug a platform interface
3239 * @pdev: platform device
3240 *
3241 * A platform bus SATA device has been unplugged. Perform the needed
3242 * cleanup. Also called on module unload for any active devices.
3243 */
3244static int __devexit mv_platform_remove(struct platform_device *pdev)
3245{
3246 struct device *dev = &pdev->dev;
3247 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3248
3249 ata_host_detach(host);
f351b2d6 3250 return 0;
20f733e7
BR		 3251}
3252
f351b2d6
SB		 3253static struct platform_driver mv_platform_driver = {
3254 .probe = mv_platform_probe,
3255 .remove = __devexit_p(mv_platform_remove),
3256 .driver = {
3257 .name = DRV_NAME,
3258 .owner = THIS_MODULE,
3259 },
3260};
3261
3262
7bb3c529 3263#ifdef CONFIG_PCI
f351b2d6
SB		 3264static int mv_pci_init_one(struct pci_dev *pdev,
3265 const struct pci_device_id *ent);
3266
7bb3c529
SB		 3267
3268static struct pci_driver mv_pci_driver = {
3269 .name = DRV_NAME,
3270 .id_table = mv_pci_tbl,
f351b2d6 3271 .probe = mv_pci_init_one,
7bb3c529
SB		 3272 .remove = ata_pci_remove_one,
3273};
3274
3275/*
3276 * module options
3277 */
3278static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3279
3280
3281/* move to PCI layer or libata core? */
3282static int pci_go_64(struct pci_dev *pdev)
3283{
3284 int rc;
3285
3286 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3287 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3288 if (rc) {
3289 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3290 if (rc) {
3291 dev_printk(KERN_ERR, &pdev->dev,
3292 "64-bit DMA enable failed\n");
3293 return rc;
3294 }
3295 }
3296 } else {
3297 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3298 if (rc) {
3299 dev_printk(KERN_ERR, &pdev->dev,
3300 "32-bit DMA enable failed\n");
3301 return rc;
3302 }
3303 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3304 if (rc) {
3305 dev_printk(KERN_ERR, &pdev->dev,
3306 "32-bit consistent DMA enable failed\n");
3307 return rc;
3308 }
3309 }
3310
3311 return rc;
3312}
3313
05b308e1
BR		 3314/**
3315 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3316 * @host: ATA host to print info about
05b308e1
BR		 3317 *
3318 * FIXME: complete this.
3319 *
3320 * LOCKING:
3321 * Inherited from caller.
3322 */
4447d351 3323static void mv_print_info(struct ata_host *host)
31961943 3324{
4447d351
TH		 3325 struct pci_dev *pdev = to_pci_dev(host->dev);
3326 struct mv_host_priv *hpriv = host->private_data;
44c10138 3327 u8 scc;
c1e4fe71 3328 const char *scc_s, *gen;
31961943
BR		 3329
3330 /* Use this to determine the HW stepping of the chip so we know
3331 * what errata to workaround
3332 */
31961943
BR		 3333 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3334 if (scc == 0)
3335 scc_s = "SCSI";
3336 else if (scc == 0x01)
3337 scc_s = "RAID";
3338 else
c1e4fe71
JG		 3339 scc_s = "?";
3340
3341 if (IS_GEN_I(hpriv))
3342 gen = "I";
3343 else if (IS_GEN_II(hpriv))
3344 gen = "II";
3345 else if (IS_GEN_IIE(hpriv))
3346 gen = "IIE";
3347 else
3348 gen = "?";
31961943 3349
a9524a76 3350 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3351 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3352 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3353 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3354}
3355
05b308e1 3356/**
f351b2d6 3357 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3358 * @pdev: PCI device found
3359 * @ent: PCI device ID entry for the matched host
3360 *
3361 * LOCKING:
3362 * Inherited from caller.
3363 */
f351b2d6
SB		 3364static int mv_pci_init_one(struct pci_dev *pdev,
3365 const struct pci_device_id *ent)
20f733e7 3366{
2dcb407e 3367 static int printed_version;
20f733e7 3368 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3369 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3370 struct ata_host *host;
3371 struct mv_host_priv *hpriv;
3372 int n_ports, rc;
20f733e7 3373
a9524a76
JG		 3374 if (!printed_version++)
3375 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3376
4447d351
TH		 3377 /* allocate host */
3378 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3379
3380 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3381 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3382 if (!host || !hpriv)
3383 return -ENOMEM;
3384 host->private_data = hpriv;
f351b2d6 3385 hpriv->n_ports = n_ports;
4447d351
TH		 3386
3387 /* acquire resources */
24dc5f33
TH		 3388 rc = pcim_enable_device(pdev);
3389 if (rc)
20f733e7 3390 return rc;
20f733e7 3391
0d5ff566
TH		 3392 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3393 if (rc == -EBUSY)
24dc5f33 3394 pcim_pin_device(pdev);
0d5ff566 3395 if (rc)
24dc5f33 3396 return rc;
4447d351 3397 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3398 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3399
d88184fb
JG		 3400 rc = pci_go_64(pdev);
3401 if (rc)
3402 return rc;
3403
da2fa9ba
ML		 3404 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3405 if (rc)
3406 return rc;
3407
20f733e7 3408 /* initialize adapter */
4447d351 3409 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3410 if (rc)
3411 return rc;
20f733e7 3412
31961943 3413 /* Enable interrupts */
6a59dcf8 3414 if (msi && pci_enable_msi(pdev))
31961943 3415 pci_intx(pdev, 1);
20f733e7 3416
31961943 3417 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3418 mv_print_info(host);
20f733e7 3419
4447d351 3420 pci_set_master(pdev);
ea8b4db9 3421 pci_try_set_mwi(pdev);
4447d351 3422 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3423 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3424}
7bb3c529 3425#endif
20f733e7 3426
f351b2d6
SB		 3427static int mv_platform_probe(struct platform_device *pdev);
3428static int __devexit mv_platform_remove(struct platform_device *pdev);
3429
20f733e7
BR		 3430static int __init mv_init(void)
3431{
7bb3c529
SB		 3432 int rc = -ENODEV;
3433#ifdef CONFIG_PCI
3434 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3435 if (rc < 0)
3436 return rc;
3437#endif
3438 rc = platform_driver_register(&mv_platform_driver);
3439
3440#ifdef CONFIG_PCI
3441 if (rc < 0)
3442 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3443#endif
3444 return rc;
20f733e7
BR		 3445}
3446
3447static void __exit mv_exit(void)
3448{
7bb3c529 3449#ifdef CONFIG_PCI
20f733e7 3450 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3451#endif
f351b2d6 3452 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3453}
3454
3455MODULE_AUTHOR("Brett Russ");
3456MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3457MODULE_LICENSE("GPL");
3458MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3459MODULE_VERSION(DRV_VERSION);
17c5aab5 3460MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3461
7bb3c529 3462#ifdef CONFIG_PCI
ddef9bb3
JG		 3463module_param(msi, int, 0444);
3464MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3465#endif
ddef9bb3 3466
20f733e7
BR		 3467module_init(mv_init);
3468module_exit(mv_exit);
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