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sata_mv: workaround for 60x1 errata sata13
[mirror_ubuntu-artful-kernel.git] / drivers / ata / sata_mv.c
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20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
4a05e209 54
20f733e7
BR		 55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
8d8b6004 62#include <linux/dmapool.h>
20f733e7 63#include <linux/dma-mapping.h>
a9524a76 64#include <linux/device.h>
f351b2d6
SB		 65#include <linux/platform_device.h>
66#include <linux/ata_platform.h>
15a32632 67#include <linux/mbus.h>
c46938cc 68#include <linux/bitops.h>
20f733e7 69#include <scsi/scsi_host.h>
193515d5 70#include <scsi/scsi_cmnd.h>
6c08772e 71#include <scsi/scsi_device.h>
20f733e7 72#include <linux/libata.h>
20f733e7
BR		 73
74#define DRV_NAME "sata_mv"
b406c7a6 75#define DRV_VERSION "1.23"
20f733e7
BR		 76
77enum {
78 /* BAR's are enumerated in terms of pci_resource_start() terms */
79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
80 MV_IO_BAR = 2, /* offset 0x18: IO space */
81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
82
83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
85
86 MV_PCI_REG_BASE = 0,
87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
93
20f733e7 94 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 95 MV_FLASH_CTL_OFS = 0x1046c,
96 MV_GPIO_PORT_CTL_OFS = 0x104f0,
97 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 98
99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
103
31961943
BR		 104 MV_MAX_Q_DEPTH = 32,
105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
106
107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
108 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
110 */
111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 113 MV_MAX_SG_CT = 256,
31961943 114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 115
352fab70 116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 117 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 121
122 /* Host Flags */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 125
c5d3e45a 126 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 127 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
128 ATA_FLAG_PIO_POLLING,
ad3aef51 129
47c2b677 130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 131
ad3aef51
ML		 132 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
133 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
c443c500 134 ATA_FLAG_NCQ | ATA_FLAG_AN,
ad3aef51 135
31961943
BR		 136 CRQB_FLAG_READ = (1 << 0),
137 CRQB_TAG_SHIFT = 1,
c5d3e45a 138 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 139 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 140 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 141 CRQB_CMD_ADDR_SHIFT = 8,
142 CRQB_CMD_CS = (0x2 << 11),
143 CRQB_CMD_LAST = (1 << 15),
144
145 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 146 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
147 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 148
149 EPRD_FLAG_END_OF_TBL = (1 << 31),
150
20f733e7
BR		 151 /* PCI interface registers */
152
31961943 153 PCI_COMMAND_OFS = 0xc00,
8e7decdb 154 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 155
20f733e7
BR		 156 PCI_MAIN_CMD_STS_OFS = 0xd30,
157 STOP_PCI_MASTER = (1 << 2),
158 PCI_MASTER_EMPTY = (1 << 3),
159 GLOB_SFT_RST = (1 << 4),
160
8e7decdb
ML		 161 MV_PCI_MODE_OFS = 0xd00,
162 MV_PCI_MODE_MASK = 0x30,
163
522479fb
JG		 164 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
165 MV_PCI_DISC_TIMER = 0xd04,
166 MV_PCI_MSI_TRIGGER = 0xc38,
167 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 168 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 169 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
170 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
171 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
172 MV_PCI_ERR_COMMAND = 0x1d50,
173
02a121da
ML		 174 PCI_IRQ_CAUSE_OFS = 0x1d58,
175 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 176 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
177
02a121da
ML		 178 PCIE_IRQ_CAUSE_OFS = 0x1900,
179 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 180 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 181
7368f919
ML		 182 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
183 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
184 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
185 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
186 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 187 ERR_IRQ = (1 << 0), /* shift by port # */
188 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 189 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
190 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
191 PCI_ERR = (1 << 18),
192 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
193 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 194 PORTS_0_3_COAL_DONE = (1 << 8),
195 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 196 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
197 GPIO_INT = (1 << 22),
198 SELF_INT = (1 << 23),
199 TWSI_INT = (1 << 24),
200 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 201 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 202 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 203
204 /* SATAHC registers */
205 HC_CFG_OFS = 0,
206
207 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 208 DMA_IRQ = (1 << 0), /* shift by port # */
209 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 210 DEV_IRQ = (1 << 8), /* shift by port # */
211
212 /* Shadow block registers */
31961943
BR		 213 SHD_BLK_OFS = 0x100,
214 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 215
216 /* SATA registers */
217 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
218 SATA_ACTIVE_OFS = 0x350,
0c58912e 219 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
c443c500 220 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
17c5aab5 221
e12bef50 222 LTMODE_OFS = 0x30c,
17c5aab5
ML		 223 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
224
47c2b677 225 PHY_MODE3 = 0x310,
bca1c4eb
JG		 226 PHY_MODE4 = 0x314,
227 PHY_MODE2 = 0x330,
e12bef50 228 SATA_IFCTL_OFS = 0x344,
8e7decdb 229 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 230 SATA_IFSTAT_OFS = 0x34c,
231 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 232
8e7decdb
ML		 233 FISCFG_OFS = 0x360,
234 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
235 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 236
c9d39130 237 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 238 MV5_LTMODE_OFS = 0x30,
239 MV5_PHY_CTL_OFS = 0x0C,
240 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 241
242 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 243
244 /* Port registers */
245 EDMA_CFG_OFS = 0,
0c58912e
ML		 246 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
247 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
248 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
249 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
250 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 251 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
252 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 253
254 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
255 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 256 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
257 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
258 EDMA_ERR_DEV = (1 << 2), /* device error */
259 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
260 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
261 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 262 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
263 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 264 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 265 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 266 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
267 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
268 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
269 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 270
6c1153e0 271 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 272 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
273 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
274 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
275 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
276
6c1153e0 277 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 278
6c1153e0 279 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 280 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
281 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
282 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
283 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
284 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
285
6c1153e0 286 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 287
6c1153e0 288 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 289 EDMA_ERR_OVERRUN_5 = (1 << 5),
290 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 291
292 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
293 EDMA_ERR_LNK_CTRL_RX_1 |
294 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 295 EDMA_ERR_LNK_CTRL_TX,
646a4da5 296
bdd4ddde
JG		 297 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
298 EDMA_ERR_PRD_PAR |
299 EDMA_ERR_DEV_DCON |
300 EDMA_ERR_DEV_CON |
301 EDMA_ERR_SERR |
302 EDMA_ERR_SELF_DIS |
6c1153e0 303 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 304 EDMA_ERR_CRPB_PAR |
305 EDMA_ERR_INTRL_PAR |
306 EDMA_ERR_IORDY |
307 EDMA_ERR_LNK_CTRL_RX_2 |
308 EDMA_ERR_LNK_DATA_RX |
309 EDMA_ERR_LNK_DATA_TX |
310 EDMA_ERR_TRANS_PROTO,
e12bef50 311
bdd4ddde
JG		 312 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
313 EDMA_ERR_PRD_PAR |
314 EDMA_ERR_DEV_DCON |
315 EDMA_ERR_DEV_CON |
316 EDMA_ERR_OVERRUN_5 |
317 EDMA_ERR_UNDERRUN_5 |
318 EDMA_ERR_SELF_DIS_5 |
6c1153e0 319 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 320 EDMA_ERR_CRPB_PAR |
321 EDMA_ERR_INTRL_PAR |
322 EDMA_ERR_IORDY,
20f733e7 323
31961943
BR		 324 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
325 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 326
327 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
328 EDMA_REQ_Q_PTR_SHIFT = 5,
329
330 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
331 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
332 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 333 EDMA_RSP_Q_PTR_SHIFT = 3,
334
0ea9e179
JG		 335 EDMA_CMD_OFS = 0x28, /* EDMA command register */
336 EDMA_EN = (1 << 0), /* enable EDMA */
337 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 338 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
339
340 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
341 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
342 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 343
8e7decdb
ML		 344 EDMA_IORDY_TMOUT_OFS = 0x34,
345 EDMA_ARB_CFG_OFS = 0x38,
346
347 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 348
352fab70
ML		 349 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
350
31961943
BR		 351 /* Host private flags (hp_flags) */
352 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 353 MV_HP_ERRATA_50XXB0 = (1 << 1),
354 MV_HP_ERRATA_50XXB2 = (1 << 2),
355 MV_HP_ERRATA_60X1B2 = (1 << 3),
356 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 357 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
358 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
359 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 360 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 361 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 362 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
20f733e7 363
31961943 364 /* Port private flags (pp_flags) */
0ea9e179 365 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 366 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 367 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 368 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
20f733e7
BR		 369};
370
ee9ccdf7
JG		 371#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
372#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 373#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 374#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 375#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 376
15a32632
LB		 377#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
378#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
379
095fec88 380enum {
baf14aa1
JG		 381 /* DMA boundary 0xffff is required by the s/g splitting
382 * we need on /length/ in mv_fill-sg().
383 */
384 MV_DMA_BOUNDARY = 0xffffU,
095fec88 385
0ea9e179
JG		 386 /* mask of register bits containing lower 32 bits
387 * of EDMA request queue DMA address
388 */
095fec88
JG		 389 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
390
0ea9e179 391 /* ditto, for response queue */
095fec88
JG		 392 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
393};
394
522479fb
JG		 395enum chip_type {
396 chip_504x,
397 chip_508x,
398 chip_5080,
399 chip_604x,
400 chip_608x,
e4e7b892
JG		 401 chip_6042,
402 chip_7042,
f351b2d6 403 chip_soc,
522479fb
JG		 404};
405
31961943
BR		 406/* Command ReQuest Block: 32B */
407struct mv_crqb {
e1469874
ML		 408 __le32 sg_addr;
409 __le32 sg_addr_hi;
410 __le16 ctrl_flags;
411 __le16 ata_cmd[11];
31961943 412};
20f733e7 413
e4e7b892 414struct mv_crqb_iie {
e1469874
ML		 415 __le32 addr;
416 __le32 addr_hi;
417 __le32 flags;
418 __le32 len;
419 __le32 ata_cmd[4];
e4e7b892
JG		 420};
421
31961943
BR		 422/* Command ResPonse Block: 8B */
423struct mv_crpb {
e1469874
ML		 424 __le16 id;
425 __le16 flags;
426 __le32 tmstmp;
20f733e7
BR		 427};
428
31961943
BR		 429/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
430struct mv_sg {
e1469874
ML		 431 __le32 addr;
432 __le32 flags_size;
433 __le32 addr_hi;
434 __le32 reserved;
31961943 435};
20f733e7 436
31961943
BR		 437struct mv_port_priv {
438 struct mv_crqb *crqb;
439 dma_addr_t crqb_dma;
440 struct mv_crpb *crpb;
441 dma_addr_t crpb_dma;
eb73d558
ML		 442 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
443 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 444
445 unsigned int req_idx;
446 unsigned int resp_idx;
447
31961943 448 u32 pp_flags;
29d187bb 449 unsigned int delayed_eh_pmp_map;
31961943
BR		 450};
451
bca1c4eb
JG		 452struct mv_port_signal {
453 u32 amps;
454 u32 pre;
455};
456
02a121da
ML		 457struct mv_host_priv {
458 u32 hp_flags;
96e2c487 459 u32 main_irq_mask;
02a121da
ML		 460 struct mv_port_signal signal[8];
461 const struct mv_hw_ops *ops;
f351b2d6
SB		 462 int n_ports;
463 void __iomem *base;
7368f919
ML		 464 void __iomem *main_irq_cause_addr;
465 void __iomem *main_irq_mask_addr;
02a121da
ML		 466 u32 irq_cause_ofs;
467 u32 irq_mask_ofs;
468 u32 unmask_all_irqs;
da2fa9ba
ML		 469 /*
470 * These consistent DMA memory pools give us guaranteed
471 * alignment for hardware-accessed data structures,
472 * and less memory waste in accomplishing the alignment.
473 */
474 struct dma_pool *crqb_pool;
475 struct dma_pool *crpb_pool;
476 struct dma_pool *sg_tbl_pool;
02a121da
ML		 477};
478
47c2b677 479struct mv_hw_ops {
2a47ce06
JG		 480 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
481 unsigned int port);
47c2b677
JG		 482 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
483 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
484 void __iomem *mmio);
c9d39130
JG		 485 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
486 unsigned int n_hc);
522479fb 487 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 488 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 489};
490
da3dbb17
TH		 491static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
492static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
493static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
494static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 495static int mv_port_start(struct ata_port *ap);
496static void mv_port_stop(struct ata_port *ap);
3e4a1391 497static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 498static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 499static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 500static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 501static int mv_hardreset(struct ata_link *link, unsigned int *class,
502 unsigned long deadline);
bdd4ddde
JG		 503static void mv_eh_freeze(struct ata_port *ap);
504static void mv_eh_thaw(struct ata_port *ap);
f273827e 505static void mv6_dev_config(struct ata_device *dev);
20f733e7 506
2a47ce06
JG		 507static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
508 unsigned int port);
47c2b677
JG		 509static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
510static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
511 void __iomem *mmio);
c9d39130
JG		 512static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
513 unsigned int n_hc);
522479fb 514static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 515static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 516
2a47ce06
JG		 517static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
518 unsigned int port);
47c2b677
JG		 519static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
520static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
521 void __iomem *mmio);
c9d39130
JG		 522static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
523 unsigned int n_hc);
522479fb 524static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 525static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
526 void __iomem *mmio);
527static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
528 void __iomem *mmio);
529static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
530 void __iomem *mmio, unsigned int n_hc);
531static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
532 void __iomem *mmio);
533static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 534static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 535static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 536 unsigned int port_no);
e12bef50 537static int mv_stop_edma(struct ata_port *ap);
b562468c 538static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 539static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 540
e49856d8
ML		 541static void mv_pmp_select(struct ata_port *ap, int pmp);
542static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
543 unsigned long deadline);
544static int mv_softreset(struct ata_link *link, unsigned int *class,
545 unsigned long deadline);
29d187bb 546static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 547static void mv_process_crpb_entries(struct ata_port *ap,
548 struct mv_port_priv *pp);
47c2b677 549
eb73d558
ML		 550/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
551 * because we have to allow room for worst case splitting of
552 * PRDs for 64K boundaries in mv_fill_sg().
553 */
c5d3e45a 554static struct scsi_host_template mv5_sht = {
68d1d07b 555 ATA_BASE_SHT(DRV_NAME),
baf14aa1 556 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 557 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 558};
559
560static struct scsi_host_template mv6_sht = {
68d1d07b 561 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 562 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 563 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 564 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 565};
566
029cfd6b
TH		 567static struct ata_port_operations mv5_ops = {
568 .inherits = &ata_sff_port_ops,
c9d39130 569
3e4a1391 570 .qc_defer = mv_qc_defer,
c9d39130
JG		 571 .qc_prep = mv_qc_prep,
572 .qc_issue = mv_qc_issue,
c9d39130 573
bdd4ddde
JG		 574 .freeze = mv_eh_freeze,
575 .thaw = mv_eh_thaw,
a1efdaba 576 .hardreset = mv_hardreset,
a1efdaba 577 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 578 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 579
c9d39130
JG		 580 .scr_read = mv5_scr_read,
581 .scr_write = mv5_scr_write,
582
583 .port_start = mv_port_start,
584 .port_stop = mv_port_stop,
c9d39130
JG		 585};
586
029cfd6b
TH		 587static struct ata_port_operations mv6_ops = {
588 .inherits = &mv5_ops,
f273827e 589 .dev_config = mv6_dev_config,
20f733e7
BR		 590 .scr_read = mv_scr_read,
591 .scr_write = mv_scr_write,
592
e49856d8
ML		 593 .pmp_hardreset = mv_pmp_hardreset,
594 .pmp_softreset = mv_softreset,
595 .softreset = mv_softreset,
29d187bb 596 .error_handler = mv_pmp_error_handler,
20f733e7
BR		 597};
598
029cfd6b
TH		 599static struct ata_port_operations mv_iie_ops = {
600 .inherits = &mv6_ops,
601 .dev_config = ATA_OP_NULL,
e4e7b892 602 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 603};
604
98ac62de 605static const struct ata_port_info mv_port_info[] = {
20f733e7 606 { /* chip_504x */
cca3974e 607 .flags = MV_COMMON_FLAGS,
31961943 608 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 609 .udma_mask = ATA_UDMA6,
c9d39130 610 .port_ops = &mv5_ops,
20f733e7
BR		 611 },
612 { /* chip_508x */
c5d3e45a 613 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 614 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 615 .udma_mask = ATA_UDMA6,
c9d39130 616 .port_ops = &mv5_ops,
20f733e7 617 },
47c2b677 618 { /* chip_5080 */
c5d3e45a 619 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 620 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 621 .udma_mask = ATA_UDMA6,
c9d39130 622 .port_ops = &mv5_ops,
47c2b677 623 },
20f733e7 624 { /* chip_604x */
138bfdd0 625 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 626 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 627 ATA_FLAG_NCQ,
31961943 628 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 629 .udma_mask = ATA_UDMA6,
c9d39130 630 .port_ops = &mv6_ops,
20f733e7
BR		 631 },
632 { /* chip_608x */
c5d3e45a 633 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 634 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 635 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 636 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 637 .udma_mask = ATA_UDMA6,
c9d39130 638 .port_ops = &mv6_ops,
20f733e7 639 },
e4e7b892 640 { /* chip_6042 */
ad3aef51 641 .flags = MV_GENIIE_FLAGS,
e4e7b892 642 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 643 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 644 .port_ops = &mv_iie_ops,
645 },
646 { /* chip_7042 */
ad3aef51 647 .flags = MV_GENIIE_FLAGS,
e4e7b892 648 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 649 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 650 .port_ops = &mv_iie_ops,
651 },
f351b2d6 652 { /* chip_soc */
1f398472 653 .flags = MV_GENIIE_FLAGS,
17c5aab5
ML		 654 .pio_mask = 0x1f, /* pio0-4 */
655 .udma_mask = ATA_UDMA6,
656 .port_ops = &mv_iie_ops,
f351b2d6 657 },
20f733e7
BR		 658};
659
3b7d697d 660static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 661 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
662 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
664 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 665 /* RocketRAID 1740/174x have different identifiers */
666 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
667 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 668
669 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
670 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
671 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
672 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
673 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
674
675 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
676
d9f9c6bc
FA		 677 /* Adaptec 1430SA */
678 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
679
02a121da 680 /* Marvell 7042 support */
6a3d586d
MT		 681 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
682
02a121da
ML		 683 /* Highpoint RocketRAID PCIe series */
684 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
685 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
686
2d2744fc 687 { } /* terminate list */
20f733e7
BR		 688};
689
47c2b677
JG		 690static const struct mv_hw_ops mv5xxx_ops = {
691 .phy_errata = mv5_phy_errata,
692 .enable_leds = mv5_enable_leds,
693 .read_preamp = mv5_read_preamp,
694 .reset_hc = mv5_reset_hc,
522479fb
JG		 695 .reset_flash = mv5_reset_flash,
696 .reset_bus = mv5_reset_bus,
47c2b677
JG		 697};
698
699static const struct mv_hw_ops mv6xxx_ops = {
700 .phy_errata = mv6_phy_errata,
701 .enable_leds = mv6_enable_leds,
702 .read_preamp = mv6_read_preamp,
703 .reset_hc = mv6_reset_hc,
522479fb
JG		 704 .reset_flash = mv6_reset_flash,
705 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 706};
707
f351b2d6
SB		 708static const struct mv_hw_ops mv_soc_ops = {
709 .phy_errata = mv6_phy_errata,
710 .enable_leds = mv_soc_enable_leds,
711 .read_preamp = mv_soc_read_preamp,
712 .reset_hc = mv_soc_reset_hc,
713 .reset_flash = mv_soc_reset_flash,
714 .reset_bus = mv_soc_reset_bus,
715};
716
20f733e7
BR		 717/*
718 * Functions
719 */
720
721static inline void writelfl(unsigned long data, void __iomem *addr)
722{
723 writel(data, addr);
724 (void) readl(addr); /* flush to avoid PCI posted write */
725}
726
c9d39130
JG		 727static inline unsigned int mv_hc_from_port(unsigned int port)
728{
729 return port >> MV_PORT_HC_SHIFT;
730}
731
732static inline unsigned int mv_hardport_from_port(unsigned int port)
733{
734 return port & MV_PORT_MASK;
735}
736
1cfd19ae
ML		 737/*
738 * Consolidate some rather tricky bit shift calculations.
739 * This is hot-path stuff, so not a function.
740 * Simple code, with two return values, so macro rather than inline.
741 *
742 * port is the sole input, in range 0..7.
7368f919
ML		 743 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
744 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 745 *
746 * Note that port and hardport may be the same variable in some cases.
747 */
748#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
749{ \
750 shift = mv_hc_from_port(port) * HC_SHIFT; \
751 hardport = mv_hardport_from_port(port); \
752 shift += hardport * 2; \
753}
754
352fab70
ML		 755static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
756{
757 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
758}
759
c9d39130
JG		 760static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
761 unsigned int port)
762{
763 return mv_hc_base(base, mv_hc_from_port(port));
764}
765
20f733e7
BR		 766static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
767{
c9d39130 768 return mv_hc_base_from_port(base, port) +
8b260248 769 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 770 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 771}
772
e12bef50
ML		 773static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
774{
775 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
776 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
777
778 return hc_mmio + ofs;
779}
780
f351b2d6
SB		 781static inline void __iomem *mv_host_base(struct ata_host *host)
782{
783 struct mv_host_priv *hpriv = host->private_data;
784 return hpriv->base;
785}
786
20f733e7
BR		 787static inline void __iomem *mv_ap_base(struct ata_port *ap)
788{
f351b2d6 789 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 790}
791
cca3974e 792static inline int mv_get_hc_count(unsigned long port_flags)
31961943 793{
cca3974e 794 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 795}
796
c5d3e45a
JG		 797static void mv_set_edma_ptrs(void __iomem *port_mmio,
798 struct mv_host_priv *hpriv,
799 struct mv_port_priv *pp)
800{
bdd4ddde
JG		 801 u32 index;
802
c5d3e45a
JG		 803 /*
804 * initialize request queue
805 */
fcfb1f77
ML		 806 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
807 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 808
c5d3e45a
JG		 809 WARN_ON(pp->crqb_dma & 0x3ff);
810 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 811 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a 812 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
5cf73bfb 813 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 814
815 /*
816 * initialize response queue
817 */
fcfb1f77
ML		 818 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
819 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 820
c5d3e45a
JG		 821 WARN_ON(pp->crpb_dma & 0xff);
822 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
5cf73bfb 823 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
bdd4ddde 824 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 825 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 826}
827
c4de573b
ML		 828static void mv_set_main_irq_mask(struct ata_host *host,
829 u32 disable_bits, u32 enable_bits)
830{
831 struct mv_host_priv *hpriv = host->private_data;
832 u32 old_mask, new_mask;
833
96e2c487 834 old_mask = hpriv->main_irq_mask;
c4de573b 835 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 836 if (new_mask != old_mask) {
837 hpriv->main_irq_mask = new_mask;
c4de573b 838 writelfl(new_mask, hpriv->main_irq_mask_addr);
96e2c487 839 }
c4de573b
ML		 840}
841
842static void mv_enable_port_irqs(struct ata_port *ap,
843 unsigned int port_bits)
844{
845 unsigned int shift, hardport, port = ap->port_no;
846 u32 disable_bits, enable_bits;
847
848 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
849
850 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
851 enable_bits = port_bits << shift;
852 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
853}
854
05b308e1
BR		 855/**
856 * mv_start_dma - Enable eDMA engine
857 * @base: port base address
858 * @pp: port private data
859 *
beec7dbc
TH		 860 * Verify the local cache of the eDMA state is accurate with a
861 * WARN_ON.
05b308e1
BR		 862 *
863 * LOCKING:
864 * Inherited from caller.
865 */
0c58912e 866static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 867 struct mv_port_priv *pp, u8 protocol)
20f733e7 868{
72109168
ML		 869 int want_ncq = (protocol == ATA_PROT_NCQ);
870
871 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
872 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
873 if (want_ncq != using_ncq)
b562468c 874 mv_stop_edma(ap);
72109168 875 }
c5d3e45a 876 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 877 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 878 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 879 void __iomem *hc_mmio = mv_hc_base_from_port(
352fab70 880 mv_host_base(ap->host), hardport);
0c58912e
ML		 881 u32 hc_irq_cause, ipending;
882
bdd4ddde 883 /* clear EDMA event indicators, if any */
f630d562 884 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 885
0c58912e
ML		 886 /* clear EDMA interrupt indicator, if any */
887 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
352fab70 888 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
0c58912e
ML		 889 if (hc_irq_cause & ipending) {
890 writelfl(hc_irq_cause & ~ipending,
891 hc_mmio + HC_IRQ_CAUSE_OFS);
892 }
893
e12bef50 894 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 895
896 /* clear FIS IRQ Cause */
e4006077
ML		 897 if (IS_GEN_IIE(hpriv))
898 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
0c58912e 899
f630d562 900 mv_set_edma_ptrs(port_mmio, hpriv, pp);
88e675e1 901 mv_enable_port_irqs(ap, DONE_IRQ|ERR_IRQ);
bdd4ddde 902
f630d562 903 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 904 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
905 }
20f733e7
BR		 906}
907
9b2c4e0b
ML		 908static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
909{
910 void __iomem *port_mmio = mv_ap_base(ap);
911 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
912 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
913 int i;
914
915 /*
916 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 917 * No idea what a good "timeout" value might be, but measurements
918 * indicate that it often requires hundreds of microseconds
919 * with two drives in-use. So we use the 15msec value above
920 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 921 */
922 for (i = 0; i < timeout; ++i) {
923 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
924 if ((edma_stat & empty_idle) == empty_idle)
925 break;
926 udelay(per_loop);
927 }
928 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
929}
930
05b308e1 931/**
e12bef50 932 * mv_stop_edma_engine - Disable eDMA engine
b562468c 933 * @port_mmio: io base address
05b308e1
BR		 934 *
935 * LOCKING:
936 * Inherited from caller.
937 */
b562468c 938static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 939{
b562468c 940 int i;
31961943 941
b562468c
ML		 942 /* Disable eDMA. The disable bit auto clears. */
943 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 944
b562468c
ML		 945 /* Wait for the chip to confirm eDMA is off. */
946 for (i = 10000; i > 0; i--) {
947 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 948 if (!(reg & EDMA_EN))
b562468c
ML		 949 return 0;
950 udelay(10);
31961943 951 }
b562468c 952 return -EIO;
20f733e7
BR		 953}
954
e12bef50 955static int mv_stop_edma(struct ata_port *ap)
0ea9e179 956{
b562468c
ML		 957 void __iomem *port_mmio = mv_ap_base(ap);
958 struct mv_port_priv *pp = ap->private_data;
0ea9e179 959
b562468c
ML		 960 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
961 return 0;
962 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 963 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 964 if (mv_stop_edma_engine(port_mmio)) {
965 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
966 return -EIO;
967 }
968 return 0;
0ea9e179
JG		 969}
970
8a70f8dc 971#ifdef ATA_DEBUG
31961943 972static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 973{
31961943
BR		 974 int b, w;
975 for (b = 0; b < bytes; ) {
976 DPRINTK("%p: ", start + b);
977 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 978 printk("%08x ", readl(start + b));
31961943
BR		 979 b += sizeof(u32);
980 }
981 printk("\n");
982 }
31961943 983}
8a70f8dc
JG		 984#endif
985
31961943
BR		 986static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
987{
988#ifdef ATA_DEBUG
989 int b, w;
990 u32 dw;
991 for (b = 0; b < bytes; ) {
992 DPRINTK("%02x: ", b);
993 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 994 (void) pci_read_config_dword(pdev, b, &dw);
995 printk("%08x ", dw);
31961943
BR		 996 b += sizeof(u32);
997 }
998 printk("\n");
999 }
1000#endif
1001}
1002static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1003 struct pci_dev *pdev)
1004{
1005#ifdef ATA_DEBUG
8b260248 1006 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1007 port >> MV_PORT_HC_SHIFT);
1008 void __iomem *port_base;
1009 int start_port, num_ports, p, start_hc, num_hcs, hc;
1010
1011 if (0 > port) {
1012 start_hc = start_port = 0;
1013 num_ports = 8; /* shld be benign for 4 port devs */
1014 num_hcs = 2;
1015 } else {
1016 start_hc = port >> MV_PORT_HC_SHIFT;
1017 start_port = port;
1018 num_ports = num_hcs = 1;
1019 }
8b260248 1020 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1021 num_ports > 1 ? num_ports - 1 : start_port);
1022
1023 if (NULL != pdev) {
1024 DPRINTK("PCI config space regs:\n");
1025 mv_dump_pci_cfg(pdev, 0x68);
1026 }
1027 DPRINTK("PCI regs:\n");
1028 mv_dump_mem(mmio_base+0xc00, 0x3c);
1029 mv_dump_mem(mmio_base+0xd00, 0x34);
1030 mv_dump_mem(mmio_base+0xf00, 0x4);
1031 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1032 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1033 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1034 DPRINTK("HC regs (HC %i):\n", hc);
1035 mv_dump_mem(hc_base, 0x1c);
1036 }
1037 for (p = start_port; p < start_port + num_ports; p++) {
1038 port_base = mv_port_base(mmio_base, p);
2dcb407e 1039 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1040 mv_dump_mem(port_base, 0x54);
2dcb407e 1041 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1042 mv_dump_mem(port_base+0x300, 0x60);
1043 }
1044#endif
20f733e7
BR		 1045}
1046
1047static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1048{
1049 unsigned int ofs;
1050
1051 switch (sc_reg_in) {
1052 case SCR_STATUS:
1053 case SCR_CONTROL:
1054 case SCR_ERROR:
1055 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1056 break;
1057 case SCR_ACTIVE:
1058 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1059 break;
1060 default:
1061 ofs = 0xffffffffU;
1062 break;
1063 }
1064 return ofs;
1065}
1066
da3dbb17 1067static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1068{
1069 unsigned int ofs = mv_scr_offset(sc_reg_in);
1070
da3dbb17
TH		 1071 if (ofs != 0xffffffffU) {
1072 *val = readl(mv_ap_base(ap) + ofs);
1073 return 0;
1074 } else
1075 return -EINVAL;
20f733e7
BR		 1076}
1077
da3dbb17 1078static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1079{
1080 unsigned int ofs = mv_scr_offset(sc_reg_in);
1081
da3dbb17 1082 if (ofs != 0xffffffffU) {
20f733e7 1083 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1084 return 0;
1085 } else
1086 return -EINVAL;
20f733e7
BR		 1087}
1088
f273827e
ML		 1089static void mv6_dev_config(struct ata_device *adev)
1090{
1091 /*
e49856d8
ML		 1092 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1093 *
1094 * Gen-II does not support NCQ over a port multiplier
1095 * (no FIS-based switching).
1096 *
f273827e
ML		 1097 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1098 * See mv_qc_prep() for more info.
1099 */
e49856d8 1100 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1101 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1102 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1103 ata_dev_printk(adev, KERN_INFO,
1104 "NCQ disabled for command-based switching\n");
1105 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1106 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1107 ata_dev_printk(adev, KERN_INFO,
1108 "max_sectors limited to %u for NCQ\n",
1109 adev->max_sectors);
1110 }
e49856d8 1111 }
f273827e
ML		 1112}
1113
3e4a1391
ML		 1114static int mv_qc_defer(struct ata_queued_cmd *qc)
1115{
1116 struct ata_link *link = qc->dev->link;
1117 struct ata_port *ap = link->ap;
1118 struct mv_port_priv *pp = ap->private_data;
1119
29d187bb
ML		 1120 /*
1121 * Don't allow new commands if we're in a delayed EH state
1122 * for NCQ and/or FIS-based switching.
1123 */
1124 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1125 return ATA_DEFER_PORT;
3e4a1391
ML		 1126 /*
1127 * If the port is completely idle, then allow the new qc.
1128 */
1129 if (ap->nr_active_links == 0)
1130 return 0;
1131
1132 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1133 /*
1134 * The port is operating in host queuing mode (EDMA).
1135 * It can accomodate a new qc if the qc protocol
1136 * is compatible with the current host queue mode.
1137 */
1138 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1139 /*
1140 * The host queue (EDMA) is in NCQ mode.
1141 * If the new qc is also an NCQ command,
1142 * then allow the new qc.
1143 */
1144 if (qc->tf.protocol == ATA_PROT_NCQ)
1145 return 0;
1146 } else {
1147 /*
1148 * The host queue (EDMA) is in non-NCQ, DMA mode.
1149 * If the new qc is also a non-NCQ, DMA command,
1150 * then allow the new qc.
1151 */
1152 if (qc->tf.protocol == ATA_PROT_DMA)
1153 return 0;
1154 }
1155 }
1156 return ATA_DEFER_PORT;
1157}
1158
00f42eab 1159static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
e49856d8 1160{
00f42eab
ML		 1161 u32 new_fiscfg, old_fiscfg;
1162 u32 new_ltmode, old_ltmode;
1163 u32 new_haltcond, old_haltcond;
1164
1165 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1166 old_ltmode = readl(port_mmio + LTMODE_OFS);
1167 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1168
1169 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1170 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1171 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1172
1173 if (want_fbs) {
1174 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1175 new_ltmode = old_ltmode | LTMODE_BIT8;
4c299ca3
ML		 1176 if (want_ncq)
1177 new_haltcond &= ~EDMA_ERR_DEV;
1178 else
1179 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
e49856d8 1180 }
00f42eab 1181
8e7decdb
ML		 1182 if (new_fiscfg != old_fiscfg)
1183 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1184 if (new_ltmode != old_ltmode)
1185 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
00f42eab
ML		 1186 if (new_haltcond != old_haltcond)
1187 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
f273827e
ML		 1188}
1189
dd2890f6
ML		 1190static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1191{
1192 struct mv_host_priv *hpriv = ap->host->private_data;
1193 u32 old, new;
1194
1195 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1196 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1197 if (want_ncq)
1198 new = old | (1 << 22);
1199 else
1200 new = old & ~(1 << 22);
1201 if (new != old)
1202 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1203}
1204
e12bef50 1205static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1206{
0c58912e 1207 u32 cfg;
e12bef50
ML		 1208 struct mv_port_priv *pp = ap->private_data;
1209 struct mv_host_priv *hpriv = ap->host->private_data;
1210 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1211
1212 /* set up non-NCQ EDMA configuration */
0c58912e 1213 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
00f42eab 1214 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
e4e7b892 1215
0c58912e 1216 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1217 cfg |= (1 << 8); /* enab config burst size mask */
1218
dd2890f6 1219 else if (IS_GEN_II(hpriv)) {
e4e7b892 1220 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1221 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1222
dd2890f6 1223 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1224 int want_fbs = sata_pmp_attached(ap);
1225 /*
1226 * Possible future enhancement:
1227 *
1228 * The chip can use FBS with non-NCQ, if we allow it,
1229 * But first we need to have the error handling in place
1230 * for this mode (datasheet section 7.3.15.4.2.3).
1231 * So disallow non-NCQ FBS for now.
1232 */
1233 want_fbs &= want_ncq;
1234
1235 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1236
1237 if (want_fbs) {
1238 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1239 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1240 }
1241
e728eabe
JG		 1242 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1243 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1f398472 1244 if (!IS_SOC(hpriv))
616d4a98
ML		 1245 cfg |= (1 << 18); /* enab early completion */
1246 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1247 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e4e7b892
JG		 1248 }
1249
72109168
ML		 1250 if (want_ncq) {
1251 cfg |= EDMA_CFG_NCQ;
1252 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1253 } else
1254 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1255
e4e7b892
JG		 1256 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1257}
1258
da2fa9ba
ML		 1259static void mv_port_free_dma_mem(struct ata_port *ap)
1260{
1261 struct mv_host_priv *hpriv = ap->host->private_data;
1262 struct mv_port_priv *pp = ap->private_data;
eb73d558 1263 int tag;
da2fa9ba
ML		 1264
1265 if (pp->crqb) {
1266 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1267 pp->crqb = NULL;
1268 }
1269 if (pp->crpb) {
1270 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1271 pp->crpb = NULL;
1272 }
eb73d558
ML		 1273 /*
1274 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1275 * For later hardware, we have one unique sg_tbl per NCQ tag.
1276 */
1277 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1278 if (pp->sg_tbl[tag]) {
1279 if (tag == 0 || !IS_GEN_I(hpriv))
1280 dma_pool_free(hpriv->sg_tbl_pool,
1281 pp->sg_tbl[tag],
1282 pp->sg_tbl_dma[tag]);
1283 pp->sg_tbl[tag] = NULL;
1284 }
da2fa9ba
ML		 1285 }
1286}
1287
05b308e1
BR		 1288/**
1289 * mv_port_start - Port specific init/start routine.
1290 * @ap: ATA channel to manipulate
1291 *
1292 * Allocate and point to DMA memory, init port private memory,
1293 * zero indices.
1294 *
1295 * LOCKING:
1296 * Inherited from caller.
1297 */
31961943
BR		 1298static int mv_port_start(struct ata_port *ap)
1299{
cca3974e
JG		 1300 struct device *dev = ap->host->dev;
1301 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1302 struct mv_port_priv *pp;
dde20207 1303 int tag;
31961943 1304
24dc5f33 1305 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1306 if (!pp)
24dc5f33 1307 return -ENOMEM;
da2fa9ba 1308 ap->private_data = pp;
31961943 1309
da2fa9ba
ML		 1310 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1311 if (!pp->crqb)
1312 return -ENOMEM;
1313 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1314
da2fa9ba
ML		 1315 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1316 if (!pp->crpb)
1317 goto out_port_free_dma_mem;
1318 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1319
eb73d558
ML		 1320 /*
1321 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1322 * For later hardware, we need one unique sg_tbl per NCQ tag.
1323 */
1324 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1325 if (tag == 0 || !IS_GEN_I(hpriv)) {
1326 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1327 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1328 if (!pp->sg_tbl[tag])
1329 goto out_port_free_dma_mem;
1330 } else {
1331 pp->sg_tbl[tag] = pp->sg_tbl[0];
1332 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1333 }
1334 }
31961943 1335 return 0;
da2fa9ba
ML		 1336
1337out_port_free_dma_mem:
1338 mv_port_free_dma_mem(ap);
1339 return -ENOMEM;
31961943
BR		 1340}
1341
05b308e1
BR		 1342/**
1343 * mv_port_stop - Port specific cleanup/stop routine.
1344 * @ap: ATA channel to manipulate
1345 *
1346 * Stop DMA, cleanup port memory.
1347 *
1348 * LOCKING:
cca3974e 1349 * This routine uses the host lock to protect the DMA stop.
05b308e1 1350 */
31961943
BR		 1351static void mv_port_stop(struct ata_port *ap)
1352{
e12bef50 1353 mv_stop_edma(ap);
88e675e1 1354 mv_enable_port_irqs(ap, 0);
da2fa9ba 1355 mv_port_free_dma_mem(ap);
31961943
BR		 1356}
1357
05b308e1
BR		 1358/**
1359 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1360 * @qc: queued command whose SG list to source from
1361 *
1362 * Populate the SG list and mark the last entry.
1363 *
1364 * LOCKING:
1365 * Inherited from caller.
1366 */
6c08772e 1367static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1368{
1369 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1370 struct scatterlist *sg;
3be6cbd7 1371 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1372 unsigned int si;
31961943 1373
eb73d558 1374 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1375 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1376 dma_addr_t addr = sg_dma_address(sg);
1377 u32 sg_len = sg_dma_len(sg);
22374677 1378
4007b493
OJ		 1379 while (sg_len) {
1380 u32 offset = addr & 0xffff;
1381 u32 len = sg_len;
22374677 1382
4007b493
OJ		 1383 if ((offset + sg_len > 0x10000))
1384 len = 0x10000 - offset;
1385
1386 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1387 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1388 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1389
1390 sg_len -= len;
1391 addr += len;
1392
3be6cbd7 1393 last_sg = mv_sg;
4007b493 1394 mv_sg++;
4007b493 1395 }
31961943 1396 }
3be6cbd7
JG		 1397
1398 if (likely(last_sg))
1399 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1400}
1401
5796d1c4 1402static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1403{
559eedad 1404 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1405 (last ? CRQB_CMD_LAST : 0);
559eedad 1406 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1407}
1408
05b308e1
BR		 1409/**
1410 * mv_qc_prep - Host specific command preparation.
1411 * @qc: queued command to prepare
1412 *
1413 * This routine simply redirects to the general purpose routine
1414 * if command is not DMA. Else, it handles prep of the CRQB
1415 * (command request block), does some sanity checking, and calls
1416 * the SG load routine.
1417 *
1418 * LOCKING:
1419 * Inherited from caller.
1420 */
31961943
BR		 1421static void mv_qc_prep(struct ata_queued_cmd *qc)
1422{
1423 struct ata_port *ap = qc->ap;
1424 struct mv_port_priv *pp = ap->private_data;
e1469874 1425 __le16 *cw;
31961943
BR		 1426 struct ata_taskfile *tf;
1427 u16 flags = 0;
a6432436 1428 unsigned in_index;
31961943 1429
138bfdd0
ML		 1430 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1431 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1432 return;
20f733e7 1433
31961943
BR		 1434 /* Fill in command request block
1435 */
e4e7b892 1436 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1437 flags |= CRQB_FLAG_READ;
beec7dbc 1438 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1439 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1440 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1441
bdd4ddde 1442 /* get current queue index from software */
fcfb1f77 1443 in_index = pp->req_idx;
a6432436
ML		 1444
1445 pp->crqb[in_index].sg_addr =
eb73d558 1446 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1447 pp->crqb[in_index].sg_addr_hi =
eb73d558 1448 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1449 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1450
a6432436 1451 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1452 tf = &qc->tf;
1453
1454 /* Sadly, the CRQB cannot accomodate all registers--there are
1455 * only 11 bytes...so we must pick and choose required
1456 * registers based on the command. So, we drop feature and
1457 * hob_feature for [RW] DMA commands, but they are needed for
1458 * NCQ. NCQ will drop hob_nsect.
20f733e7 1459 */
31961943
BR		 1460 switch (tf->command) {
1461 case ATA_CMD_READ:
1462 case ATA_CMD_READ_EXT:
1463 case ATA_CMD_WRITE:
1464 case ATA_CMD_WRITE_EXT:
c15d85c8 1465 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1466 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1467 break;
31961943
BR		 1468 case ATA_CMD_FPDMA_READ:
1469 case ATA_CMD_FPDMA_WRITE:
8b260248 1470 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1471 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1472 break;
31961943
BR		 1473 default:
1474 /* The only other commands EDMA supports in non-queued and
1475 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1476 * of which are defined/used by Linux. If we get here, this
1477 * driver needs work.
1478 *
1479 * FIXME: modify libata to give qc_prep a return value and
1480 * return error here.
1481 */
1482 BUG_ON(tf->command);
1483 break;
1484 }
1485 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1486 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1487 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1488 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1489 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1490 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1491 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1492 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1493 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1494
e4e7b892
JG		 1495 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1496 return;
1497 mv_fill_sg(qc);
1498}
1499
1500/**
1501 * mv_qc_prep_iie - Host specific command preparation.
1502 * @qc: queued command to prepare
1503 *
1504 * This routine simply redirects to the general purpose routine
1505 * if command is not DMA. Else, it handles prep of the CRQB
1506 * (command request block), does some sanity checking, and calls
1507 * the SG load routine.
1508 *
1509 * LOCKING:
1510 * Inherited from caller.
1511 */
1512static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1513{
1514 struct ata_port *ap = qc->ap;
1515 struct mv_port_priv *pp = ap->private_data;
1516 struct mv_crqb_iie *crqb;
1517 struct ata_taskfile *tf;
a6432436 1518 unsigned in_index;
e4e7b892
JG		 1519 u32 flags = 0;
1520
138bfdd0
ML		 1521 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1522 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1523 return;
1524
e12bef50 1525 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1526 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1527 flags |= CRQB_FLAG_READ;
1528
beec7dbc 1529 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1530 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1531 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1532 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1533
bdd4ddde 1534 /* get current queue index from software */
fcfb1f77 1535 in_index = pp->req_idx;
a6432436
ML		 1536
1537 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1538 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1539 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1540 crqb->flags = cpu_to_le32(flags);
1541
1542 tf = &qc->tf;
1543 crqb->ata_cmd[0] = cpu_to_le32(
1544 (tf->command << 16) |
1545 (tf->feature << 24)
1546 );
1547 crqb->ata_cmd[1] = cpu_to_le32(
1548 (tf->lbal << 0) |
1549 (tf->lbam << 8) |
1550 (tf->lbah << 16) |
1551 (tf->device << 24)
1552 );
1553 crqb->ata_cmd[2] = cpu_to_le32(
1554 (tf->hob_lbal << 0) |
1555 (tf->hob_lbam << 8) |
1556 (tf->hob_lbah << 16) |
1557 (tf->hob_feature << 24)
1558 );
1559 crqb->ata_cmd[3] = cpu_to_le32(
1560 (tf->nsect << 0) |
1561 (tf->hob_nsect << 8)
1562 );
1563
1564 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1565 return;
31961943
BR		 1566 mv_fill_sg(qc);
1567}
1568
05b308e1
BR		 1569/**
1570 * mv_qc_issue - Initiate a command to the host
1571 * @qc: queued command to start
1572 *
1573 * This routine simply redirects to the general purpose routine
1574 * if command is not DMA. Else, it sanity checks our local
1575 * caches of the request producer/consumer indices then enables
1576 * DMA and bumps the request producer index.
1577 *
1578 * LOCKING:
1579 * Inherited from caller.
1580 */
9a3d9eb0 1581static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1582{
c5d3e45a
JG		 1583 struct ata_port *ap = qc->ap;
1584 void __iomem *port_mmio = mv_ap_base(ap);
1585 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1586 u32 in_index;
31961943 1587
138bfdd0
ML		 1588 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1589 (qc->tf.protocol != ATA_PROT_NCQ)) {
17c5aab5
ML		 1590 /*
1591 * We're about to send a non-EDMA capable command to the
31961943
BR		 1592 * port. Turn off EDMA so there won't be problems accessing
1593 * shadow block, etc registers.
1594 */
b562468c 1595 mv_stop_edma(ap);
88e675e1 1596 mv_enable_port_irqs(ap, ERR_IRQ);
e49856d8 1597 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1598 return ata_sff_qc_issue(qc);
31961943
BR		 1599 }
1600
72109168 1601 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1602
fcfb1f77
ML		 1603 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1604 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1605
1606 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1607 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1608 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1609
1610 return 0;
1611}
1612
8f767f8a
ML		 1613static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1614{
1615 struct mv_port_priv *pp = ap->private_data;
1616 struct ata_queued_cmd *qc;
1617
1618 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1619 return NULL;
1620 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1621 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1622 qc = NULL;
1623 return qc;
1624}
1625
29d187bb
ML		 1626static void mv_pmp_error_handler(struct ata_port *ap)
1627{
1628 unsigned int pmp, pmp_map;
1629 struct mv_port_priv *pp = ap->private_data;
1630
1631 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1632 /*
1633 * Perform NCQ error analysis on failed PMPs
1634 * before we freeze the port entirely.
1635 *
1636 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1637 */
1638 pmp_map = pp->delayed_eh_pmp_map;
1639 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1640 for (pmp = 0; pmp_map != 0; pmp++) {
1641 unsigned int this_pmp = (1 << pmp);
1642 if (pmp_map & this_pmp) {
1643 struct ata_link *link = &ap->pmp_link[pmp];
1644 pmp_map &= ~this_pmp;
1645 ata_eh_analyze_ncq_error(link);
1646 }
1647 }
1648 ata_port_freeze(ap);
1649 }
1650 sata_pmp_error_handler(ap);
1651}
1652
4c299ca3
ML		 1653static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1654{
1655 void __iomem *port_mmio = mv_ap_base(ap);
1656
1657 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1658}
1659
4c299ca3
ML		 1660static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1661{
1662 struct ata_eh_info *ehi;
1663 unsigned int pmp;
1664
1665 /*
1666 * Initialize EH info for PMPs which saw device errors
1667 */
1668 ehi = &ap->link.eh_info;
1669 for (pmp = 0; pmp_map != 0; pmp++) {
1670 unsigned int this_pmp = (1 << pmp);
1671 if (pmp_map & this_pmp) {
1672 struct ata_link *link = &ap->pmp_link[pmp];
1673
1674 pmp_map &= ~this_pmp;
1675 ehi = &link->eh_info;
1676 ata_ehi_clear_desc(ehi);
1677 ata_ehi_push_desc(ehi, "dev err");
1678 ehi->err_mask |= AC_ERR_DEV;
1679 ehi->action |= ATA_EH_RESET;
1680 ata_link_abort(link);
1681 }
1682 }
1683}
1684
06aaca3f
ML		 1685static int mv_req_q_empty(struct ata_port *ap)
1686{
1687 void __iomem *port_mmio = mv_ap_base(ap);
1688 u32 in_ptr, out_ptr;
1689
1690 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1691 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1692 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1693 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1694 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1695}
1696
4c299ca3
ML		 1697static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1698{
1699 struct mv_port_priv *pp = ap->private_data;
1700 int failed_links;
1701 unsigned int old_map, new_map;
1702
1703 /*
1704 * Device error during FBS+NCQ operation:
1705 *
1706 * Set a port flag to prevent further I/O being enqueued.
1707 * Leave the EDMA running to drain outstanding commands from this port.
1708 * Perform the post-mortem/EH only when all responses are complete.
1709 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1710 */
1711 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1712 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1713 pp->delayed_eh_pmp_map = 0;
1714 }
1715 old_map = pp->delayed_eh_pmp_map;
1716 new_map = old_map | mv_get_err_pmp_map(ap);
1717
1718 if (old_map != new_map) {
1719 pp->delayed_eh_pmp_map = new_map;
1720 mv_pmp_eh_prep(ap, new_map & ~old_map);
1721 }
c46938cc 1722 failed_links = hweight16(new_map);
4c299ca3
ML		 1723
1724 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1725 "failed_links=%d nr_active_links=%d\n",
1726 __func__, pp->delayed_eh_pmp_map,
1727 ap->qc_active, failed_links,
1728 ap->nr_active_links);
1729
06aaca3f 1730 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 1731 mv_process_crpb_entries(ap, pp);
1732 mv_stop_edma(ap);
1733 mv_eh_freeze(ap);
1734 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1735 return 1; /* handled */
1736 }
1737 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1738 return 1; /* handled */
1739}
1740
1741static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1742{
1743 /*
1744 * Possible future enhancement:
1745 *
1746 * FBS+non-NCQ operation is not yet implemented.
1747 * See related notes in mv_edma_cfg().
1748 *
1749 * Device error during FBS+non-NCQ operation:
1750 *
1751 * We need to snapshot the shadow registers for each failed command.
1752 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1753 */
1754 return 0; /* not handled */
1755}
1756
1757static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1758{
1759 struct mv_port_priv *pp = ap->private_data;
1760
1761 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1762 return 0; /* EDMA was not active: not handled */
1763 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1764 return 0; /* FBS was not active: not handled */
1765
1766 if (!(edma_err_cause & EDMA_ERR_DEV))
1767 return 0; /* non DEV error: not handled */
1768 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1769 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1770 return 0; /* other problems: not handled */
1771
1772 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1773 /*
1774 * EDMA should NOT have self-disabled for this case.
1775 * If it did, then something is wrong elsewhere,
1776 * and we cannot handle it here.
1777 */
1778 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1779 ata_port_printk(ap, KERN_WARNING,
1780 "%s: err_cause=0x%x pp_flags=0x%x\n",
1781 __func__, edma_err_cause, pp->pp_flags);
1782 return 0; /* not handled */
1783 }
1784 return mv_handle_fbs_ncq_dev_err(ap);
1785 } else {
1786 /*
1787 * EDMA should have self-disabled for this case.
1788 * If it did not, then something is wrong elsewhere,
1789 * and we cannot handle it here.
1790 */
1791 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1792 ata_port_printk(ap, KERN_WARNING,
1793 "%s: err_cause=0x%x pp_flags=0x%x\n",
1794 __func__, edma_err_cause, pp->pp_flags);
1795 return 0; /* not handled */
1796 }
1797 return mv_handle_fbs_non_ncq_dev_err(ap);
1798 }
1799 return 0; /* not handled */
1800}
1801
a9010329 1802static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 1803{
8f767f8a 1804 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 1805 char *when = "idle";
8f767f8a 1806
8f767f8a 1807 ata_ehi_clear_desc(ehi);
a9010329
ML		 1808 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1809 when = "disabled";
1810 } else if (edma_was_enabled) {
1811 when = "EDMA enabled";
8f767f8a
ML		 1812 } else {
1813 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1814 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 1815 when = "polling";
8f767f8a 1816 }
a9010329 1817 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 1818 ehi->err_mask |= AC_ERR_OTHER;
1819 ehi->action |= ATA_EH_RESET;
1820 ata_port_freeze(ap);
1821}
1822
05b308e1
BR		 1823/**
1824 * mv_err_intr - Handle error interrupts on the port
1825 * @ap: ATA channel to manipulate
8d07379d 1826 * @qc: affected command (non-NCQ), or NULL
05b308e1 1827 *
8d07379d
ML		 1828 * Most cases require a full reset of the chip's state machine,
1829 * which also performs a COMRESET.
1830 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1831 *
1832 * LOCKING:
1833 * Inherited from caller.
1834 */
37b9046a 1835static void mv_err_intr(struct ata_port *ap)
31961943
BR		 1836{
1837 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 1838 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 1839 u32 fis_cause = 0;
bdd4ddde
JG		 1840 struct mv_port_priv *pp = ap->private_data;
1841 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1842 unsigned int action = 0, err_mask = 0;
9af5c9c9 1843 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 1844 struct ata_queued_cmd *qc;
1845 int abort = 0;
20f733e7 1846
8d07379d 1847 /*
37b9046a 1848 * Read and clear the SError and err_cause bits.
e4006077
ML		 1849 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1850 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 1851 */
37b9046a
ML		 1852 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1853 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1854
bdd4ddde 1855 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
e4006077
ML		 1856 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1857 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1858 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1859 }
8d07379d 1860 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1861
4c299ca3
ML		 1862 if (edma_err_cause & EDMA_ERR_DEV) {
1863 /*
1864 * Device errors during FIS-based switching operation
1865 * require special handling.
1866 */
1867 if (mv_handle_dev_err(ap, edma_err_cause))
1868 return;
1869 }
1870
37b9046a
ML		 1871 qc = mv_get_active_qc(ap);
1872 ata_ehi_clear_desc(ehi);
1873 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1874 edma_err_cause, pp->pp_flags);
e4006077 1875
c443c500 1876 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 1877 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
c443c500
ML		 1878 if (fis_cause & SATA_FIS_IRQ_AN) {
1879 u32 ec = edma_err_cause &
1880 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1881 sata_async_notification(ap);
1882 if (!ec)
1883 return; /* Just an AN; no need for the nukes */
1884 ata_ehi_push_desc(ehi, "SDB notify");
1885 }
1886 }
bdd4ddde 1887 /*
352fab70 1888 * All generations share these EDMA error cause bits:
bdd4ddde 1889 */
37b9046a 1890 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 1891 err_mask |= AC_ERR_DEV;
37b9046a
ML		 1892 action |= ATA_EH_RESET;
1893 ata_ehi_push_desc(ehi, "dev error");
1894 }
bdd4ddde 1895 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1896 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1897 EDMA_ERR_INTRL_PAR)) {
1898 err_mask |= AC_ERR_ATA_BUS;
cf480626 1899 action |= ATA_EH_RESET;
b64bbc39 1900 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1901 }
1902 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1903 ata_ehi_hotplugged(ehi);
1904 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1905 "dev disconnect" : "dev connect");
cf480626 1906 action |= ATA_EH_RESET;
bdd4ddde
JG		 1907 }
1908
352fab70
ML		 1909 /*
1910 * Gen-I has a different SELF_DIS bit,
1911 * different FREEZE bits, and no SERR bit:
1912 */
ee9ccdf7 1913 if (IS_GEN_I(hpriv)) {
bdd4ddde 1914 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1915 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1916 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1917 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1918 }
1919 } else {
1920 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1921 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1922 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1923 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1924 }
bdd4ddde 1925 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1926 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1927 err_mask |= AC_ERR_ATA_BUS;
cf480626 1928 action |= ATA_EH_RESET;
bdd4ddde 1929 }
afb0edd9 1930 }
20f733e7 1931
bdd4ddde
JG		 1932 if (!err_mask) {
1933 err_mask = AC_ERR_OTHER;
cf480626 1934 action |= ATA_EH_RESET;
bdd4ddde
JG		 1935 }
1936
1937 ehi->serror |= serr;
1938 ehi->action |= action;
1939
1940 if (qc)
1941 qc->err_mask |= err_mask;
1942 else
1943 ehi->err_mask |= err_mask;
1944
37b9046a
ML		 1945 if (err_mask == AC_ERR_DEV) {
1946 /*
1947 * Cannot do ata_port_freeze() here,
1948 * because it would kill PIO access,
1949 * which is needed for further diagnosis.
1950 */
1951 mv_eh_freeze(ap);
1952 abort = 1;
1953 } else if (edma_err_cause & eh_freeze_mask) {
1954 /*
1955 * Note to self: ata_port_freeze() calls ata_port_abort()
1956 */
bdd4ddde 1957 ata_port_freeze(ap);
37b9046a
ML		 1958 } else {
1959 abort = 1;
1960 }
1961
1962 if (abort) {
1963 if (qc)
1964 ata_link_abort(qc->dev->link);
1965 else
1966 ata_port_abort(ap);
1967 }
bdd4ddde
JG		 1968}
1969
fcfb1f77
ML		 1970static void mv_process_crpb_response(struct ata_port *ap,
1971 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1972{
1973 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1974
1975 if (qc) {
1976 u8 ata_status;
1977 u16 edma_status = le16_to_cpu(response->flags);
1978 /*
1979 * edma_status from a response queue entry:
1980 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1981 * MSB is saved ATA status from command completion.
1982 */
1983 if (!ncq_enabled) {
1984 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1985 if (err_cause) {
1986 /*
1987 * Error will be seen/handled by mv_err_intr().
1988 * So do nothing at all here.
1989 */
1990 return;
1991 }
1992 }
1993 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 1994 if (!ac_err_mask(ata_status))
1995 ata_qc_complete(qc);
1996 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 1997 } else {
1998 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1999 __func__, tag);
2000 }
2001}
2002
2003static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2004{
2005 void __iomem *port_mmio = mv_ap_base(ap);
2006 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2007 u32 in_index;
bdd4ddde 2008 bool work_done = false;
fcfb1f77 2009 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2010
fcfb1f77 2011 /* Get the hardware queue position index */
bdd4ddde
JG		 2012 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2013 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2014
fcfb1f77
ML		 2015 /* Process new responses from since the last time we looked */
2016 while (in_index != pp->resp_idx) {
6c1153e0 2017 unsigned int tag;
fcfb1f77 2018 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2019
fcfb1f77 2020 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2021
fcfb1f77
ML		 2022 if (IS_GEN_I(hpriv)) {
2023 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2024 tag = ap->link.active_tag;
fcfb1f77
ML		 2025 } else {
2026 /* Gen II/IIE: get command tag from CRPB entry */
2027 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2028 }
fcfb1f77 2029 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2030 work_done = true;
bdd4ddde
JG		 2031 }
2032
352fab70 2033 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2034 if (work_done)
2035 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2036 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2037 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2038}
2039
a9010329
ML		 2040static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2041{
2042 struct mv_port_priv *pp;
2043 int edma_was_enabled;
2044
2045 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2046 mv_unexpected_intr(ap, 0);
2047 return;
2048 }
2049 /*
2050 * Grab a snapshot of the EDMA_EN flag setting,
2051 * so that we have a consistent view for this port,
2052 * even if something we call of our routines changes it.
2053 */
2054 pp = ap->private_data;
2055 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2056 /*
2057 * Process completed CRPB response(s) before other events.
2058 */
2059 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2060 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2061 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2062 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2063 }
2064 /*
2065 * Handle chip-reported errors, or continue on to handle PIO.
2066 */
2067 if (unlikely(port_cause & ERR_IRQ)) {
2068 mv_err_intr(ap);
2069 } else if (!edma_was_enabled) {
2070 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2071 if (qc)
2072 ata_sff_host_intr(ap, qc);
2073 else
2074 mv_unexpected_intr(ap, edma_was_enabled);
2075 }
2076}
2077
05b308e1
BR		 2078/**
2079 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2080 * @host: host specific structure
7368f919 2081 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2082 *
2083 * LOCKING:
2084 * Inherited from caller.
2085 */
7368f919 2086static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2087{
f351b2d6 2088 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2089 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2090 unsigned int handled = 0, port;
20f733e7 2091
a3718c1f 2092 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2093 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2094 unsigned int p, shift, hardport, port_cause;
2095
a3718c1f 2096 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2097 /*
eabd5eb1
ML		 2098 * Each hc within the host has its own hc_irq_cause register,
2099 * where the interrupting ports bits get ack'd.
a3718c1f 2100 */
eabd5eb1
ML		 2101 if (hardport == 0) { /* first port on this hc ? */
2102 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2103 u32 port_mask, ack_irqs;
2104 /*
2105 * Skip this entire hc if nothing pending for any ports
2106 */
2107 if (!hc_cause) {
2108 port += MV_PORTS_PER_HC - 1;
2109 continue;
2110 }
2111 /*
2112 * We don't need/want to read the hc_irq_cause register,
2113 * because doing so hurts performance, and
2114 * main_irq_cause already gives us everything we need.
2115 *
2116 * But we do have to *write* to the hc_irq_cause to ack
2117 * the ports that we are handling this time through.
2118 *
2119 * This requires that we create a bitmap for those
2120 * ports which interrupted us, and use that bitmap
2121 * to ack (only) those ports via hc_irq_cause.
2122 */
2123 ack_irqs = 0;
2124 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2125 if ((port + p) >= hpriv->n_ports)
2126 break;
2127 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2128 if (hc_cause & port_mask)
2129 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2130 }
a3718c1f 2131 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2132 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2133 handled = 1;
2134 }
8f767f8a 2135 /*
a9010329 2136 * Handle interrupts signalled for this port:
8f767f8a 2137 */
a9010329
ML		 2138 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2139 if (port_cause)
2140 mv_port_intr(ap, port_cause);
20f733e7 2141 }
a3718c1f 2142 return handled;
20f733e7
BR		 2143}
2144
a3718c1f 2145static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2146{
02a121da 2147 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2148 struct ata_port *ap;
2149 struct ata_queued_cmd *qc;
2150 struct ata_eh_info *ehi;
2151 unsigned int i, err_mask, printed = 0;
2152 u32 err_cause;
2153
02a121da 2154 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2155
2156 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2157 err_cause);
2158
2159 DPRINTK("All regs @ PCI error\n");
2160 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2161
02a121da 2162 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2163
2164 for (i = 0; i < host->n_ports; i++) {
2165 ap = host->ports[i];
936fd732 2166 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2167 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2168 ata_ehi_clear_desc(ehi);
2169 if (!printed++)
2170 ata_ehi_push_desc(ehi,
2171 "PCI err cause 0x%08x", err_cause);
2172 err_mask = AC_ERR_HOST_BUS;
cf480626 2173 ehi->action = ATA_EH_RESET;
9af5c9c9 2174 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2175 if (qc)
2176 qc->err_mask |= err_mask;
2177 else
2178 ehi->err_mask |= err_mask;
2179
2180 ata_port_freeze(ap);
2181 }
2182 }
a3718c1f 2183 return 1; /* handled */
bdd4ddde
JG		 2184}
2185
05b308e1 2186/**
c5d3e45a 2187 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2188 * @irq: unused
2189 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2190 *
2191 * Read the read only register to determine if any host
2192 * controllers have pending interrupts. If so, call lower level
2193 * routine to handle. Also check for PCI errors which are only
2194 * reported here.
2195 *
8b260248 2196 * LOCKING:
cca3974e 2197 * This routine holds the host lock while processing pending
05b308e1
BR		 2198 * interrupts.
2199 */
7d12e780 2200static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2201{
cca3974e 2202 struct ata_host *host = dev_instance;
f351b2d6 2203 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2204 unsigned int handled = 0;
96e2c487 2205 u32 main_irq_cause, pending_irqs;
20f733e7 2206
646a4da5 2207 spin_lock(&host->lock);
7368f919 2208 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2209 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2210 /*
2211 * Deal with cases where we either have nothing pending, or have read
2212 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2213 */
a44253d2 2214 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 2215 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 2216 handled = mv_pci_error(host, hpriv->base);
2217 else
a44253d2 2218 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2219 }
cca3974e 2220 spin_unlock(&host->lock);
20f733e7
BR		 2221 return IRQ_RETVAL(handled);
2222}
2223
c9d39130
JG		 2224static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2225{
2226 unsigned int ofs;
2227
2228 switch (sc_reg_in) {
2229 case SCR_STATUS:
2230 case SCR_ERROR:
2231 case SCR_CONTROL:
2232 ofs = sc_reg_in * sizeof(u32);
2233 break;
2234 default:
2235 ofs = 0xffffffffU;
2236 break;
2237 }
2238 return ofs;
2239}
2240
da3dbb17 2241static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 2242{
f351b2d6
SB		 2243 struct mv_host_priv *hpriv = ap->host->private_data;
2244 void __iomem *mmio = hpriv->base;
0d5ff566 2245 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2246 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2247
da3dbb17
TH		 2248 if (ofs != 0xffffffffU) {
2249 *val = readl(addr + ofs);
2250 return 0;
2251 } else
2252 return -EINVAL;
c9d39130
JG		 2253}
2254
da3dbb17 2255static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 2256{
f351b2d6
SB		 2257 struct mv_host_priv *hpriv = ap->host->private_data;
2258 void __iomem *mmio = hpriv->base;
0d5ff566 2259 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2260 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2261
da3dbb17 2262 if (ofs != 0xffffffffU) {
0d5ff566 2263 writelfl(val, addr + ofs);
da3dbb17
TH		 2264 return 0;
2265 } else
2266 return -EINVAL;
c9d39130
JG		 2267}
2268
7bb3c529 2269static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2270{
7bb3c529 2271 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2272 int early_5080;
2273
44c10138 2274 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2275
2276 if (!early_5080) {
2277 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2278 tmp |= (1 << 0);
2279 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2280 }
2281
7bb3c529 2282 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2283}
2284
2285static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2286{
8e7decdb 2287 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2288}
2289
47c2b677 2290static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2291 void __iomem *mmio)
2292{
c9d39130
JG		 2293 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2294 u32 tmp;
2295
2296 tmp = readl(phy_mmio + MV5_PHY_MODE);
2297
2298 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2299 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2300}
2301
47c2b677 2302static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2303{
522479fb
JG		 2304 u32 tmp;
2305
8e7decdb 2306 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2307
2308 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2309
2310 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2311 tmp |= ~(1 << 0);
2312 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2313}
2314
2a47ce06
JG		 2315static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2316 unsigned int port)
bca1c4eb 2317{
c9d39130
JG		 2318 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2319 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2320 u32 tmp;
2321 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2322
2323 if (fix_apm_sq) {
8e7decdb 2324 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2325 tmp |= (1 << 19);
8e7decdb 2326 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2327
8e7decdb 2328 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2329 tmp &= ~0x3;
2330 tmp |= 0x1;
8e7decdb 2331 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2332 }
2333
2334 tmp = readl(phy_mmio + MV5_PHY_MODE);
2335 tmp &= ~mask;
2336 tmp |= hpriv->signal[port].pre;
2337 tmp |= hpriv->signal[port].amps;
2338 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2339}
2340
c9d39130
JG		 2341
2342#undef ZERO
2343#define ZERO(reg) writel(0, port_mmio + (reg))
2344static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2345 unsigned int port)
2346{
2347 void __iomem *port_mmio = mv_port_base(mmio, port);
2348
e12bef50 2349 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2350
2351 ZERO(0x028); /* command */
2352 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2353 ZERO(0x004); /* timer */
2354 ZERO(0x008); /* irq err cause */
2355 ZERO(0x00c); /* irq err mask */
2356 ZERO(0x010); /* rq bah */
2357 ZERO(0x014); /* rq inp */
2358 ZERO(0x018); /* rq outp */
2359 ZERO(0x01c); /* respq bah */
2360 ZERO(0x024); /* respq outp */
2361 ZERO(0x020); /* respq inp */
2362 ZERO(0x02c); /* test control */
8e7decdb 2363 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2364}
2365#undef ZERO
2366
2367#define ZERO(reg) writel(0, hc_mmio + (reg))
2368static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2369 unsigned int hc)
47c2b677 2370{
c9d39130
JG		 2371 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2372 u32 tmp;
2373
2374 ZERO(0x00c);
2375 ZERO(0x010);
2376 ZERO(0x014);
2377 ZERO(0x018);
2378
2379 tmp = readl(hc_mmio + 0x20);
2380 tmp &= 0x1c1c1c1c;
2381 tmp |= 0x03030303;
2382 writel(tmp, hc_mmio + 0x20);
2383}
2384#undef ZERO
2385
2386static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2387 unsigned int n_hc)
2388{
2389 unsigned int hc, port;
2390
2391 for (hc = 0; hc < n_hc; hc++) {
2392 for (port = 0; port < MV_PORTS_PER_HC; port++)
2393 mv5_reset_hc_port(hpriv, mmio,
2394 (hc * MV_PORTS_PER_HC) + port);
2395
2396 mv5_reset_one_hc(hpriv, mmio, hc);
2397 }
2398
2399 return 0;
47c2b677
JG		 2400}
2401
101ffae2
JG		 2402#undef ZERO
2403#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2404static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2405{
02a121da 2406 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2407 u32 tmp;
2408
8e7decdb 2409 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2410 tmp &= 0xff00ffff;
8e7decdb 2411 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2412
2413 ZERO(MV_PCI_DISC_TIMER);
2414 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2415 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
101ffae2 2416 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2417 ZERO(hpriv->irq_cause_ofs);
2418 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2419 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2420 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2421 ZERO(MV_PCI_ERR_ATTRIBUTE);
2422 ZERO(MV_PCI_ERR_COMMAND);
2423}
2424#undef ZERO
2425
2426static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2427{
2428 u32 tmp;
2429
2430 mv5_reset_flash(hpriv, mmio);
2431
8e7decdb 2432 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2433 tmp &= 0x3;
2434 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2435 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2436}
2437
2438/**
2439 * mv6_reset_hc - Perform the 6xxx global soft reset
2440 * @mmio: base address of the HBA
2441 *
2442 * This routine only applies to 6xxx parts.
2443 *
2444 * LOCKING:
2445 * Inherited from caller.
2446 */
c9d39130
JG		 2447static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2448 unsigned int n_hc)
101ffae2
JG		 2449{
2450 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2451 int i, rc = 0;
2452 u32 t;
2453
2454 /* Following procedure defined in PCI "main command and status
2455 * register" table.
2456 */
2457 t = readl(reg);
2458 writel(t | STOP_PCI_MASTER, reg);
2459
2460 for (i = 0; i < 1000; i++) {
2461 udelay(1);
2462 t = readl(reg);
2dcb407e 2463 if (PCI_MASTER_EMPTY & t)
101ffae2 2464 break;
101ffae2
JG		 2465 }
2466 if (!(PCI_MASTER_EMPTY & t)) {
2467 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2468 rc = 1;
2469 goto done;
2470 }
2471
2472 /* set reset */
2473 i = 5;
2474 do {
2475 writel(t | GLOB_SFT_RST, reg);
2476 t = readl(reg);
2477 udelay(1);
2478 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2479
2480 if (!(GLOB_SFT_RST & t)) {
2481 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2482 rc = 1;
2483 goto done;
2484 }
2485
2486 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2487 i = 5;
2488 do {
2489 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2490 t = readl(reg);
2491 udelay(1);
2492 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2493
2494 if (GLOB_SFT_RST & t) {
2495 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2496 rc = 1;
2497 }
2498done:
2499 return rc;
2500}
2501
47c2b677 2502static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2503 void __iomem *mmio)
2504{
2505 void __iomem *port_mmio;
2506 u32 tmp;
2507
8e7decdb 2508 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2509 if ((tmp & (1 << 0)) == 0) {
47c2b677 2510 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2511 hpriv->signal[idx].pre = 0x1 << 5;
2512 return;
2513 }
2514
2515 port_mmio = mv_port_base(mmio, idx);
2516 tmp = readl(port_mmio + PHY_MODE2);
2517
2518 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2519 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2520}
2521
47c2b677 2522static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2523{
8e7decdb 2524 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2525}
2526
c9d39130 2527static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2528 unsigned int port)
bca1c4eb 2529{
c9d39130
JG		 2530 void __iomem *port_mmio = mv_port_base(mmio, port);
2531
bca1c4eb 2532 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2533 int fix_phy_mode2 =
2534 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2535 int fix_phy_mode4 =
47c2b677 2536 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 2537 u32 m2, m3;
47c2b677
JG		 2538
2539 if (fix_phy_mode2) {
2540 m2 = readl(port_mmio + PHY_MODE2);
2541 m2 &= ~(1 << 16);
2542 m2 |= (1 << 31);
2543 writel(m2, port_mmio + PHY_MODE2);
2544
2545 udelay(200);
2546
2547 m2 = readl(port_mmio + PHY_MODE2);
2548 m2 &= ~((1 << 16) | (1 << 31));
2549 writel(m2, port_mmio + PHY_MODE2);
2550
2551 udelay(200);
2552 }
2553
8c30a8b9
ML		 2554 /*
2555 * Gen-II/IIe PHY_MODE3 errata RM#2:
2556 * Achieves better receiver noise performance than the h/w default:
2557 */
2558 m3 = readl(port_mmio + PHY_MODE3);
2559 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb
JG		 2560
2561 if (fix_phy_mode4) {
47c2b677 2562 u32 m4;
bca1c4eb
JG		 2563
2564 m4 = readl(port_mmio + PHY_MODE4);
47c2b677 2565
e12bef50 2566 /* workaround for errata FEr SATA#10 (part 1) */
bca1c4eb
JG		 2567 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2568
8c30a8b9
ML		 2569 /* enforce bit restrictions on GenIIe devices */
2570 if (IS_GEN_IIE(hpriv))
2571 m4 = (m4 & ~0x5DE3FFFC) | (1 << 2);
47c2b677 2572
8c30a8b9 2573 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 2574 }
b406c7a6
ML		 2575 /*
2576 * Workaround for 60x1-B2 errata SATA#13:
2577 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2578 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2579 */
2580 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2581
2582 /* Revert values of pre-emphasis and signal amps to the saved ones */
2583 m2 = readl(port_mmio + PHY_MODE2);
2584
2585 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2586 m2 |= hpriv->signal[port].amps;
2587 m2 |= hpriv->signal[port].pre;
47c2b677 2588 m2 &= ~(1 << 16);
bca1c4eb 2589
e4e7b892
JG		 2590 /* according to mvSata 3.6.1, some IIE values are fixed */
2591 if (IS_GEN_IIE(hpriv)) {
2592 m2 &= ~0xC30FF01F;
2593 m2 |= 0x0000900F;
2594 }
2595
bca1c4eb
JG		 2596 writel(m2, port_mmio + PHY_MODE2);
2597}
2598
f351b2d6
SB		 2599/* TODO: use the generic LED interface to configure the SATA Presence */
2600/* & Acitivy LEDs on the board */
2601static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2602 void __iomem *mmio)
2603{
2604 return;
2605}
2606
2607static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2608 void __iomem *mmio)
2609{
2610 void __iomem *port_mmio;
2611 u32 tmp;
2612
2613 port_mmio = mv_port_base(mmio, idx);
2614 tmp = readl(port_mmio + PHY_MODE2);
2615
2616 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2617 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2618}
2619
2620#undef ZERO
2621#define ZERO(reg) writel(0, port_mmio + (reg))
2622static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2623 void __iomem *mmio, unsigned int port)
2624{
2625 void __iomem *port_mmio = mv_port_base(mmio, port);
2626
e12bef50 2627 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2628
2629 ZERO(0x028); /* command */
2630 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2631 ZERO(0x004); /* timer */
2632 ZERO(0x008); /* irq err cause */
2633 ZERO(0x00c); /* irq err mask */
2634 ZERO(0x010); /* rq bah */
2635 ZERO(0x014); /* rq inp */
2636 ZERO(0x018); /* rq outp */
2637 ZERO(0x01c); /* respq bah */
2638 ZERO(0x024); /* respq outp */
2639 ZERO(0x020); /* respq inp */
2640 ZERO(0x02c); /* test control */
8e7decdb 2641 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2642}
2643
2644#undef ZERO
2645
2646#define ZERO(reg) writel(0, hc_mmio + (reg))
2647static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2648 void __iomem *mmio)
2649{
2650 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2651
2652 ZERO(0x00c);
2653 ZERO(0x010);
2654 ZERO(0x014);
2655
2656}
2657
2658#undef ZERO
2659
2660static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2661 void __iomem *mmio, unsigned int n_hc)
2662{
2663 unsigned int port;
2664
2665 for (port = 0; port < hpriv->n_ports; port++)
2666 mv_soc_reset_hc_port(hpriv, mmio, port);
2667
2668 mv_soc_reset_one_hc(hpriv, mmio);
2669
2670 return 0;
2671}
2672
2673static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2674 void __iomem *mmio)
2675{
2676 return;
2677}
2678
2679static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2680{
2681 return;
2682}
2683
8e7decdb 2684static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2685{
8e7decdb 2686 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2687
8e7decdb 2688 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2689 if (want_gen2i)
8e7decdb
ML		 2690 ifcfg |= (1 << 7); /* enable gen2i speed */
2691 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2692}
2693
e12bef50 2694static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2695 unsigned int port_no)
2696{
2697 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2698
8e7decdb
ML		 2699 /*
2700 * The datasheet warns against setting EDMA_RESET when EDMA is active
2701 * (but doesn't say what the problem might be). So we first try
2702 * to disable the EDMA engine before doing the EDMA_RESET operation.
2703 */
0d8be5cb 2704 mv_stop_edma_engine(port_mmio);
8e7decdb 2705 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2706
b67a1064 2707 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2708 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2709 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2710 }
b67a1064 2711 /*
8e7decdb 2712 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2713 * link, and physical layers. It resets all SATA interface registers
2714 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2715 */
8e7decdb 2716 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2717 udelay(25); /* allow reset propagation */
c9d39130
JG		 2718 writelfl(0, port_mmio + EDMA_CMD_OFS);
2719
2720 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2721
ee9ccdf7 2722 if (IS_GEN_I(hpriv))
c9d39130
JG		 2723 mdelay(1);
2724}
2725
e49856d8 2726static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2727{
e49856d8
ML		 2728 if (sata_pmp_supported(ap)) {
2729 void __iomem *port_mmio = mv_ap_base(ap);
2730 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2731 int old = reg & 0xf;
22374677 2732
e49856d8
ML		 2733 if (old != pmp) {
2734 reg = (reg & ~0xf) | pmp;
2735 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2736 }
22374677 2737 }
20f733e7
BR		 2738}
2739
e49856d8
ML		 2740static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2741 unsigned long deadline)
22374677 2742{
e49856d8
ML		 2743 mv_pmp_select(link->ap, sata_srst_pmp(link));
2744 return sata_std_hardreset(link, class, deadline);
2745}
bdd4ddde 2746
e49856d8
ML		 2747static int mv_softreset(struct ata_link *link, unsigned int *class,
2748 unsigned long deadline)
2749{
2750 mv_pmp_select(link->ap, sata_srst_pmp(link));
2751 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2752}
2753
cc0680a5 2754static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2755 unsigned long deadline)
31961943 2756{
cc0680a5 2757 struct ata_port *ap = link->ap;
bdd4ddde 2758 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2759 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2760 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2761 int rc, attempts = 0, extra = 0;
2762 u32 sstatus;
2763 bool online;
31961943 2764
e12bef50 2765 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2766 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2767
0d8be5cb
ML		 2768 /* Workaround for errata FEr SATA#10 (part 2) */
2769 do {
17c5aab5
ML		 2770 const unsigned long *timing =
2771 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2772
17c5aab5
ML		 2773 rc = sata_link_hardreset(link, timing, deadline + extra,
2774 &online, NULL);
9dcffd99 2775 rc = online ? -EAGAIN : rc;
17c5aab5 2776 if (rc)
0d8be5cb 2777 return rc;
0d8be5cb
ML		 2778 sata_scr_read(link, SCR_STATUS, &sstatus);
2779 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2780 /* Force 1.5gb/s link speed and try again */
8e7decdb 2781 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2782 if (time_after(jiffies + HZ, deadline))
2783 extra = HZ; /* only extend it once, max */
2784 }
2785 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2786
17c5aab5 2787 return rc;
bdd4ddde
JG		 2788}
2789
bdd4ddde
JG		 2790static void mv_eh_freeze(struct ata_port *ap)
2791{
1cfd19ae 2792 mv_stop_edma(ap);
c4de573b 2793 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 2794}
2795
2796static void mv_eh_thaw(struct ata_port *ap)
2797{
f351b2d6 2798 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 2799 unsigned int port = ap->port_no;
2800 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 2801 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2802 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 2803 u32 hc_irq_cause;
bdd4ddde 2804
bdd4ddde
JG		 2805 /* clear EDMA errors on this port */
2806 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2807
2808 /* clear pending irq events */
2809 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1cfd19ae
ML		 2810 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2811 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde 2812
88e675e1 2813 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 2814}
2815
05b308e1
BR		 2816/**
2817 * mv_port_init - Perform some early initialization on a single port.
2818 * @port: libata data structure storing shadow register addresses
2819 * @port_mmio: base address of the port
2820 *
2821 * Initialize shadow register mmio addresses, clear outstanding
2822 * interrupts on the port, and unmask interrupts for the future
2823 * start of the port.
2824 *
2825 * LOCKING:
2826 * Inherited from caller.
2827 */
31961943 2828static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2829{
0d5ff566 2830 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2831 unsigned serr_ofs;
2832
8b260248 2833 /* PIO related setup
31961943
BR		 2834 */
2835 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2836 port->error_addr =
31961943
BR		 2837 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2838 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2839 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2840 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2841 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2842 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2843 port->status_addr =
31961943
BR		 2844 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2845 /* special case: control/altstatus doesn't have ATA_REG_ address */
2846 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2847
2848 /* unused: */
8d9db2d2 2849 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2850
31961943
BR		 2851 /* Clear any currently outstanding port interrupt conditions */
2852 serr_ofs = mv_scr_offset(SCR_ERROR);
2853 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2854 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2855
646a4da5
ML		 2856 /* unmask all non-transient EDMA error interrupts */
2857 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2858
8b260248 2859 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2860 readl(port_mmio + EDMA_CFG_OFS),
2861 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2862 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2863}
2864
616d4a98
ML		 2865static unsigned int mv_in_pcix_mode(struct ata_host *host)
2866{
2867 struct mv_host_priv *hpriv = host->private_data;
2868 void __iomem *mmio = hpriv->base;
2869 u32 reg;
2870
1f398472 2871 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98
ML		 2872 return 0; /* not PCI-X capable */
2873 reg = readl(mmio + MV_PCI_MODE_OFS);
2874 if ((reg & MV_PCI_MODE_MASK) == 0)
2875 return 0; /* conventional PCI mode */
2876 return 1; /* chip is in PCI-X mode */
2877}
2878
2879static int mv_pci_cut_through_okay(struct ata_host *host)
2880{
2881 struct mv_host_priv *hpriv = host->private_data;
2882 void __iomem *mmio = hpriv->base;
2883 u32 reg;
2884
2885 if (!mv_in_pcix_mode(host)) {
2886 reg = readl(mmio + PCI_COMMAND_OFS);
2887 if (reg & PCI_COMMAND_MRDTRIG)
2888 return 0; /* not okay */
2889 }
2890 return 1; /* okay */
2891}
2892
4447d351 2893static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2894{
4447d351
TH		 2895 struct pci_dev *pdev = to_pci_dev(host->dev);
2896 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2897 u32 hp_flags = hpriv->hp_flags;
2898
5796d1c4 2899 switch (board_idx) {
47c2b677
JG		 2900 case chip_5080:
2901 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2902 hp_flags |= MV_HP_GEN_I;
47c2b677 2903
44c10138 2904 switch (pdev->revision) {
47c2b677
JG		 2905 case 0x1:
2906 hp_flags |= MV_HP_ERRATA_50XXB0;
2907 break;
2908 case 0x3:
2909 hp_flags |= MV_HP_ERRATA_50XXB2;
2910 break;
2911 default:
2912 dev_printk(KERN_WARNING, &pdev->dev,
2913 "Applying 50XXB2 workarounds to unknown rev\n");
2914 hp_flags |= MV_HP_ERRATA_50XXB2;
2915 break;
2916 }
2917 break;
2918
bca1c4eb
JG		 2919 case chip_504x:
2920 case chip_508x:
47c2b677 2921 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2922 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2923
44c10138 2924 switch (pdev->revision) {
47c2b677
JG		 2925 case 0x0:
2926 hp_flags |= MV_HP_ERRATA_50XXB0;
2927 break;
2928 case 0x3:
2929 hp_flags |= MV_HP_ERRATA_50XXB2;
2930 break;
2931 default:
2932 dev_printk(KERN_WARNING, &pdev->dev,
2933 "Applying B2 workarounds to unknown rev\n");
2934 hp_flags |= MV_HP_ERRATA_50XXB2;
2935 break;
bca1c4eb
JG		 2936 }
2937 break;
2938
2939 case chip_604x:
2940 case chip_608x:
47c2b677 2941 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2942 hp_flags |= MV_HP_GEN_II;
47c2b677 2943
44c10138 2944 switch (pdev->revision) {
47c2b677
JG		 2945 case 0x7:
2946 hp_flags |= MV_HP_ERRATA_60X1B2;
2947 break;
2948 case 0x9:
2949 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2950 break;
2951 default:
2952 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2953 "Applying B2 workarounds to unknown rev\n");
2954 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2955 break;
2956 }
2957 break;
2958
e4e7b892 2959 case chip_7042:
616d4a98 2960 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2961 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2962 (pdev->device == 0x2300 || pdev->device == 0x2310))
2963 {
4e520033
ML		 2964 /*
2965 * Highpoint RocketRAID PCIe 23xx series cards:
2966 *
2967 * Unconfigured drives are treated as "Legacy"
2968 * by the BIOS, and it overwrites sector 8 with
2969 * a "Lgcy" metadata block prior to Linux boot.
2970 *
2971 * Configured drives (RAID or JBOD) leave sector 8
2972 * alone, but instead overwrite a high numbered
2973 * sector for the RAID metadata. This sector can
2974 * be determined exactly, by truncating the physical
2975 * drive capacity to a nice even GB value.
2976 *
2977 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2978 *
2979 * Warn the user, lest they think we're just buggy.
2980 */
2981 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2982 " BIOS CORRUPTS DATA on all attached drives,"
2983 " regardless of if/how they are configured."
2984 " BEWARE!\n");
2985 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2986 " use sectors 8-9 on \"Legacy\" drives,"
2987 " and avoid the final two gigabytes on"
2988 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2989 }
8e7decdb 2990 /* drop through */
e4e7b892
JG		 2991 case chip_6042:
2992 hpriv->ops = &mv6xxx_ops;
e4e7b892 2993 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 2994 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2995 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 2996
44c10138 2997 switch (pdev->revision) {
5cf73bfb 2998 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 2999 hp_flags |= MV_HP_ERRATA_60X1C0;
3000 break;
3001 default:
3002 dev_printk(KERN_WARNING, &pdev->dev,
3003 "Applying 60X1C0 workarounds to unknown rev\n");
3004 hp_flags |= MV_HP_ERRATA_60X1C0;
3005 break;
3006 }
3007 break;
f351b2d6
SB		 3008 case chip_soc:
3009 hpriv->ops = &mv_soc_ops;
1f398472 3010 hp_flags |= MV_HP_FLAG_SOC | MV_HP_ERRATA_60X1C0;
f351b2d6 3011 break;
e4e7b892 3012
bca1c4eb 3013 default:
f351b2d6 3014 dev_printk(KERN_ERR, host->dev,
5796d1c4 3015 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3016 return 1;
3017 }
3018
3019 hpriv->hp_flags = hp_flags;
02a121da
ML		 3020 if (hp_flags & MV_HP_PCIE) {
3021 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3022 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3023 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3024 } else {
3025 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3026 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3027 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3028 }
bca1c4eb
JG		 3029
3030 return 0;
3031}
3032
05b308e1 3033/**
47c2b677 3034 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3035 * @host: ATA host to initialize
3036 * @board_idx: controller index
05b308e1
BR		 3037 *
3038 * If possible, do an early global reset of the host. Then do
3039 * our port init and clear/unmask all/relevant host interrupts.
3040 *
3041 * LOCKING:
3042 * Inherited from caller.
3043 */
4447d351 3044static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3045{
3046 int rc = 0, n_hc, port, hc;
4447d351 3047 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3048 void __iomem *mmio = hpriv->base;
47c2b677 3049
4447d351 3050 rc = mv_chip_id(host, board_idx);
bca1c4eb 3051 if (rc)
352fab70 3052 goto done;
f351b2d6 3053
1f398472 3054 if (IS_SOC(hpriv)) {
7368f919
ML		 3055 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3056 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
1f398472
ML		 3057 } else {
3058 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3059 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3060 }
352fab70
ML		 3061
3062 /* global interrupt mask: 0 == mask everything */
c4de573b 3063 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3064
4447d351 3065 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3066
4447d351 3067 for (port = 0; port < host->n_ports; port++)
47c2b677 3068 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3069
c9d39130 3070 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3071 if (rc)
20f733e7 3072 goto done;
20f733e7 3073
522479fb 3074 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3075 hpriv->ops->reset_bus(host, mmio);
47c2b677 3076 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3077
4447d351 3078 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3079 struct ata_port *ap = host->ports[port];
2a47ce06 3080 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3081
3082 mv_port_init(&ap->ioaddr, port_mmio);
3083
7bb3c529 3084#ifdef CONFIG_PCI
1f398472 3085 if (!IS_SOC(hpriv)) {
f351b2d6
SB		 3086 unsigned int offset = port_mmio - mmio;
3087 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3088 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3089 }
7bb3c529 3090#endif
20f733e7
BR		 3091 }
3092
3093 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3094 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3095
3096 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3097 "(before clear)=0x%08x\n", hc,
3098 readl(hc_mmio + HC_CFG_OFS),
3099 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3100
3101 /* Clear any currently outstanding hc interrupt conditions */
3102 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3103 }
3104
1f398472 3105 if (!IS_SOC(hpriv)) {
f351b2d6
SB		 3106 /* Clear any currently outstanding host interrupt conditions */
3107 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3108
f351b2d6
SB		 3109 /* and unmask interrupt generation for host regs */
3110 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
51de32d2
ML		 3111
3112 /*
3113 * enable only global host interrupts for now.
3114 * The per-port interrupts get done later as ports are set up.
3115 */
c4de573b 3116 mv_set_main_irq_mask(host, 0, PCI_ERR);
f351b2d6
SB		 3117 }
3118done:
3119 return rc;
3120}
fb621e2f 3121
fbf14e2f
BB		 3122static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3123{
3124 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3125 MV_CRQB_Q_SZ, 0);
3126 if (!hpriv->crqb_pool)
3127 return -ENOMEM;
3128
3129 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3130 MV_CRPB_Q_SZ, 0);
3131 if (!hpriv->crpb_pool)
3132 return -ENOMEM;
3133
3134 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3135 MV_SG_TBL_SZ, 0);
3136 if (!hpriv->sg_tbl_pool)
3137 return -ENOMEM;
3138
3139 return 0;
3140}
3141
15a32632
LB		 3142static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3143 struct mbus_dram_target_info *dram)
3144{
3145 int i;
3146
3147 for (i = 0; i < 4; i++) {
3148 writel(0, hpriv->base + WINDOW_CTRL(i));
3149 writel(0, hpriv->base + WINDOW_BASE(i));
3150 }
3151
3152 for (i = 0; i < dram->num_cs; i++) {
3153 struct mbus_dram_window *cs = dram->cs + i;
3154
3155 writel(((cs->size - 1) & 0xffff0000) |
3156 (cs->mbus_attr << 8) |
3157 (dram->mbus_dram_target_id << 4) | 1,
3158 hpriv->base + WINDOW_CTRL(i));
3159 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3160 }
3161}
3162
f351b2d6
SB		 3163/**
3164 * mv_platform_probe - handle a positive probe of an soc Marvell
3165 * host
3166 * @pdev: platform device found
3167 *
3168 * LOCKING:
3169 * Inherited from caller.
3170 */
3171static int mv_platform_probe(struct platform_device *pdev)
3172{
3173 static int printed_version;
3174 const struct mv_sata_platform_data *mv_platform_data;
3175 const struct ata_port_info *ppi[] =
3176 { &mv_port_info[chip_soc], NULL };
3177 struct ata_host *host;
3178 struct mv_host_priv *hpriv;
3179 struct resource *res;
3180 int n_ports, rc;
20f733e7 3181
f351b2d6
SB		 3182 if (!printed_version++)
3183 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3184
f351b2d6
SB		 3185 /*
3186 * Simple resource validation ..
3187 */
3188 if (unlikely(pdev->num_resources != 2)) {
3189 dev_err(&pdev->dev, "invalid number of resources\n");
3190 return -EINVAL;
3191 }
3192
3193 /*
3194 * Get the register base first
3195 */
3196 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3197 if (res == NULL)
3198 return -EINVAL;
3199
3200 /* allocate host */
3201 mv_platform_data = pdev->dev.platform_data;
3202 n_ports = mv_platform_data->n_ports;
3203
3204 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3205 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3206
3207 if (!host || !hpriv)
3208 return -ENOMEM;
3209 host->private_data = hpriv;
3210 hpriv->n_ports = n_ports;
3211
3212 host->iomap = NULL;
f1cb0ea1
SB		 3213 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3214 res->end - res->start + 1);
f351b2d6
SB		 3215 hpriv->base -= MV_SATAHC0_REG_BASE;
3216
15a32632
LB		 3217 /*
3218 * (Re-)program MBUS remapping windows if we are asked to.
3219 */
3220 if (mv_platform_data->dram != NULL)
3221 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3222
fbf14e2f
BB		 3223 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3224 if (rc)
3225 return rc;
3226
f351b2d6
SB		 3227 /* initialize adapter */
3228 rc = mv_init_host(host, chip_soc);
3229 if (rc)
3230 return rc;
3231
3232 dev_printk(KERN_INFO, &pdev->dev,
3233 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3234 host->n_ports);
3235
3236 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3237 IRQF_SHARED, &mv6_sht);
3238}
3239
3240/*
3241 *
3242 * mv_platform_remove - unplug a platform interface
3243 * @pdev: platform device
3244 *
3245 * A platform bus SATA device has been unplugged. Perform the needed
3246 * cleanup. Also called on module unload for any active devices.
3247 */
3248static int __devexit mv_platform_remove(struct platform_device *pdev)
3249{
3250 struct device *dev = &pdev->dev;
3251 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3252
3253 ata_host_detach(host);
f351b2d6 3254 return 0;
20f733e7
BR		 3255}
3256
f351b2d6
SB		 3257static struct platform_driver mv_platform_driver = {
3258 .probe = mv_platform_probe,
3259 .remove = __devexit_p(mv_platform_remove),
3260 .driver = {
3261 .name = DRV_NAME,
3262 .owner = THIS_MODULE,
3263 },
3264};
3265
3266
7bb3c529 3267#ifdef CONFIG_PCI
f351b2d6
SB		 3268static int mv_pci_init_one(struct pci_dev *pdev,
3269 const struct pci_device_id *ent);
3270
7bb3c529
SB		 3271
3272static struct pci_driver mv_pci_driver = {
3273 .name = DRV_NAME,
3274 .id_table = mv_pci_tbl,
f351b2d6 3275 .probe = mv_pci_init_one,
7bb3c529
SB		 3276 .remove = ata_pci_remove_one,
3277};
3278
3279/*
3280 * module options
3281 */
3282static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3283
3284
3285/* move to PCI layer or libata core? */
3286static int pci_go_64(struct pci_dev *pdev)
3287{
3288 int rc;
3289
3290 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3291 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3292 if (rc) {
3293 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3294 if (rc) {
3295 dev_printk(KERN_ERR, &pdev->dev,
3296 "64-bit DMA enable failed\n");
3297 return rc;
3298 }
3299 }
3300 } else {
3301 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3302 if (rc) {
3303 dev_printk(KERN_ERR, &pdev->dev,
3304 "32-bit DMA enable failed\n");
3305 return rc;
3306 }
3307 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3308 if (rc) {
3309 dev_printk(KERN_ERR, &pdev->dev,
3310 "32-bit consistent DMA enable failed\n");
3311 return rc;
3312 }
3313 }
3314
3315 return rc;
3316}
3317
05b308e1
BR		 3318/**
3319 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3320 * @host: ATA host to print info about
05b308e1
BR		 3321 *
3322 * FIXME: complete this.
3323 *
3324 * LOCKING:
3325 * Inherited from caller.
3326 */
4447d351 3327static void mv_print_info(struct ata_host *host)
31961943 3328{
4447d351
TH		 3329 struct pci_dev *pdev = to_pci_dev(host->dev);
3330 struct mv_host_priv *hpriv = host->private_data;
44c10138 3331 u8 scc;
c1e4fe71 3332 const char *scc_s, *gen;
31961943
BR		 3333
3334 /* Use this to determine the HW stepping of the chip so we know
3335 * what errata to workaround
3336 */
31961943
BR		 3337 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3338 if (scc == 0)
3339 scc_s = "SCSI";
3340 else if (scc == 0x01)
3341 scc_s = "RAID";
3342 else
c1e4fe71
JG		 3343 scc_s = "?";
3344
3345 if (IS_GEN_I(hpriv))
3346 gen = "I";
3347 else if (IS_GEN_II(hpriv))
3348 gen = "II";
3349 else if (IS_GEN_IIE(hpriv))
3350 gen = "IIE";
3351 else
3352 gen = "?";
31961943 3353
a9524a76 3354 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3355 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3356 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3357 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3358}
3359
05b308e1 3360/**
f351b2d6 3361 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3362 * @pdev: PCI device found
3363 * @ent: PCI device ID entry for the matched host
3364 *
3365 * LOCKING:
3366 * Inherited from caller.
3367 */
f351b2d6
SB		 3368static int mv_pci_init_one(struct pci_dev *pdev,
3369 const struct pci_device_id *ent)
20f733e7 3370{
2dcb407e 3371 static int printed_version;
20f733e7 3372 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3373 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3374 struct ata_host *host;
3375 struct mv_host_priv *hpriv;
3376 int n_ports, rc;
20f733e7 3377
a9524a76
JG		 3378 if (!printed_version++)
3379 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3380
4447d351
TH		 3381 /* allocate host */
3382 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3383
3384 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3385 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3386 if (!host || !hpriv)
3387 return -ENOMEM;
3388 host->private_data = hpriv;
f351b2d6 3389 hpriv->n_ports = n_ports;
4447d351
TH		 3390
3391 /* acquire resources */
24dc5f33
TH		 3392 rc = pcim_enable_device(pdev);
3393 if (rc)
20f733e7 3394 return rc;
20f733e7 3395
0d5ff566
TH		 3396 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3397 if (rc == -EBUSY)
24dc5f33 3398 pcim_pin_device(pdev);
0d5ff566 3399 if (rc)
24dc5f33 3400 return rc;
4447d351 3401 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3402 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3403
d88184fb
JG		 3404 rc = pci_go_64(pdev);
3405 if (rc)
3406 return rc;
3407
da2fa9ba
ML		 3408 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3409 if (rc)
3410 return rc;
3411
20f733e7 3412 /* initialize adapter */
4447d351 3413 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3414 if (rc)
3415 return rc;
20f733e7 3416
31961943 3417 /* Enable interrupts */
6a59dcf8 3418 if (msi && pci_enable_msi(pdev))
31961943 3419 pci_intx(pdev, 1);
20f733e7 3420
31961943 3421 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3422 mv_print_info(host);
20f733e7 3423
4447d351 3424 pci_set_master(pdev);
ea8b4db9 3425 pci_try_set_mwi(pdev);
4447d351 3426 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3427 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3428}
7bb3c529 3429#endif
20f733e7 3430
f351b2d6
SB		 3431static int mv_platform_probe(struct platform_device *pdev);
3432static int __devexit mv_platform_remove(struct platform_device *pdev);
3433
20f733e7
BR		 3434static int __init mv_init(void)
3435{
7bb3c529
SB		 3436 int rc = -ENODEV;
3437#ifdef CONFIG_PCI
3438 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3439 if (rc < 0)
3440 return rc;
3441#endif
3442 rc = platform_driver_register(&mv_platform_driver);
3443
3444#ifdef CONFIG_PCI
3445 if (rc < 0)
3446 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3447#endif
3448 return rc;
20f733e7
BR		 3449}
3450
3451static void __exit mv_exit(void)
3452{
7bb3c529 3453#ifdef CONFIG_PCI
20f733e7 3454 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3455#endif
f351b2d6 3456 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3457}
3458
3459MODULE_AUTHOR("Brett Russ");
3460MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3461MODULE_LICENSE("GPL");
3462MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3463MODULE_VERSION(DRV_VERSION);
17c5aab5 3464MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3465
7bb3c529 3466#ifdef CONFIG_PCI
ddef9bb3
JG		 3467module_param(msi, int, 0444);
3468MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3469#endif
ddef9bb3 3470
20f733e7
BR		 3471module_init(mv_init);
3472module_exit(mv_exit);
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