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sata_mv ncq Ignore response status LSB on NCQ
[mirror_ubuntu-jammy-kernel.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
8b260248 4 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 5 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
4a05e209
JG		 24/*
25 sata_mv TODO list:
26
27 1) Needs a full errata audit for all chipsets. I implemented most
28 of the errata workarounds found in the Marvell vendor driver, but
29 I distinctly remember a couple workarounds (one related to PCI-X)
30 are still needed.
31
4a05e209
JG		 32 4) Add NCQ support (easy to intermediate, once new-EH support appears)
33
34 5) Investigate problems with PCI Message Signalled Interrupts (MSI).
35
36 6) Add port multiplier support (intermediate)
37
4a05e209
JG		 38 8) Develop a low-power-consumption strategy, and implement it.
39
40 9) [Experiment, low priority] See if ATAPI can be supported using
41 "unknown FIS" or "vendor-specific FIS" support, or something creative
42 like that.
43
44 10) [Experiment, low priority] Investigate interrupt coalescing.
45 Quite often, especially with PCI Message Signalled Interrupts (MSI),
46 the overhead reduced by interrupt mitigation is quite often not
47 worth the latency cost.
48
49 11) [Experiment, Marvell value added] Is it possible to use target
50 mode to cross-connect two Linux boxes with Marvell cards? If so,
51 creating LibATA target mode support would be very interesting.
52
53 Target mode, for those without docs, is the ability to directly
54 connect two SATA controllers.
55
56 13) Verify that 7042 is fully supported. I only have a 6042.
57
58*/
59
60
20f733e7
BR		 61#include <linux/kernel.h>
62#include <linux/module.h>
63#include <linux/pci.h>
64#include <linux/init.h>
65#include <linux/blkdev.h>
66#include <linux/delay.h>
67#include <linux/interrupt.h>
20f733e7 68#include <linux/dma-mapping.h>
a9524a76 69#include <linux/device.h>
20f733e7 70#include <scsi/scsi_host.h>
193515d5 71#include <scsi/scsi_cmnd.h>
6c08772e 72#include <scsi/scsi_device.h>
20f733e7 73#include <linux/libata.h>
20f733e7
BR		 74
75#define DRV_NAME "sata_mv"
6c08772e 76#define DRV_VERSION "1.01"
20f733e7
BR		 77
78enum {
79 /* BAR's are enumerated in terms of pci_resource_start() terms */
80 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
81 MV_IO_BAR = 2, /* offset 0x18: IO space */
82 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
83
84 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
85 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
86
87 MV_PCI_REG_BASE = 0,
88 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 89 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
90 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
91 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
92 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
93 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
94
20f733e7 95 MV_SATAHC0_REG_BASE = 0x20000,
522479fb 96 MV_FLASH_CTL = 0x1046c,
bca1c4eb
JG		 97 MV_GPIO_PORT_CTL = 0x104f0,
98 MV_RESET_CFG = 0x180d8,
20f733e7
BR		 99
100 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
101 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
102 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
103 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
104
31961943
BR		 105 MV_MAX_Q_DEPTH = 32,
106 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
107
108 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
109 * CRPB needs alignment on a 256B boundary. Size == 256B
110 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
111 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
112 */
113 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
114 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
115 MV_MAX_SG_CT = 176,
116 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
117 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
118
20f733e7
BR		 119 MV_PORTS_PER_HC = 4,
120 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
121 MV_PORT_HC_SHIFT = 2,
31961943 122 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
20f733e7
BR		 123 MV_PORT_MASK = 3,
124
125 /* Host Flags */
126 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
127 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
c5d3e45a 128 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 129 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
130 ATA_FLAG_PIO_POLLING,
47c2b677 131 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 132
31961943
BR		 133 CRQB_FLAG_READ = (1 << 0),
134 CRQB_TAG_SHIFT = 1,
c5d3e45a
JG		 135 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
136 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 137 CRQB_CMD_ADDR_SHIFT = 8,
138 CRQB_CMD_CS = (0x2 << 11),
139 CRQB_CMD_LAST = (1 << 15),
140
141 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 142 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 144
145 EPRD_FLAG_END_OF_TBL = (1 << 31),
146
20f733e7
BR		 147 /* PCI interface registers */
148
31961943
BR		 149 PCI_COMMAND_OFS = 0xc00,
150
20f733e7
BR		 151 PCI_MAIN_CMD_STS_OFS = 0xd30,
152 STOP_PCI_MASTER = (1 << 2),
153 PCI_MASTER_EMPTY = (1 << 3),
154 GLOB_SFT_RST = (1 << 4),
155
522479fb
JG		 156 MV_PCI_MODE = 0xd00,
157 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
158 MV_PCI_DISC_TIMER = 0xd04,
159 MV_PCI_MSI_TRIGGER = 0xc38,
160 MV_PCI_SERR_MASK = 0xc28,
161 MV_PCI_XBAR_TMOUT = 0x1d04,
162 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
163 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
164 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
165 MV_PCI_ERR_COMMAND = 0x1d50,
166
02a121da
ML		 167 PCI_IRQ_CAUSE_OFS = 0x1d58,
168 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 169 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
170
02a121da
ML		 171 PCIE_IRQ_CAUSE_OFS = 0x1900,
172 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 173 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 174
20f733e7
BR		 175 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
176 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
177 PORT0_ERR = (1 << 0), /* shift by port # */
178 PORT0_DONE = (1 << 1), /* shift by port # */
179 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
180 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
181 PCI_ERR = (1 << 18),
182 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
183 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 184 PORTS_0_3_COAL_DONE = (1 << 8),
185 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 186 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
187 GPIO_INT = (1 << 22),
188 SELF_INT = (1 << 23),
189 TWSI_INT = (1 << 24),
190 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 191 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
8b260248 192 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
20f733e7
BR		 193 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
194 HC_MAIN_RSVD),
fb621e2f
JG		 195 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
196 HC_MAIN_RSVD_5),
20f733e7
BR		 197
198 /* SATAHC registers */
199 HC_CFG_OFS = 0,
200
201 HC_IRQ_CAUSE_OFS = 0x14,
31961943 202 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
20f733e7
BR		 203 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
204 DEV_IRQ = (1 << 8), /* shift by port # */
205
206 /* Shadow block registers */
31961943
BR		 207 SHD_BLK_OFS = 0x100,
208 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 209
210 /* SATA registers */
211 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
212 SATA_ACTIVE_OFS = 0x350,
0c58912e 213 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
47c2b677 214 PHY_MODE3 = 0x310,
bca1c4eb
JG		 215 PHY_MODE4 = 0x314,
216 PHY_MODE2 = 0x330,
c9d39130
JG		 217 MV5_PHY_MODE = 0x74,
218 MV5_LT_MODE = 0x30,
219 MV5_PHY_CTL = 0x0C,
bca1c4eb
JG		 220 SATA_INTERFACE_CTL = 0x050,
221
222 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 223
224 /* Port registers */
225 EDMA_CFG_OFS = 0,
0c58912e
ML		 226 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
227 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
228 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
229 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
230 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
20f733e7
BR		 231
232 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
233 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 234 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
235 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
236 EDMA_ERR_DEV = (1 << 2), /* device error */
237 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
238 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
239 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 240 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
241 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 242 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 243 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 244 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
245 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
246 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
247 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 248
6c1153e0 249 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 250 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
251 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
252 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
253 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
254
6c1153e0 255 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 256
6c1153e0 257 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 258 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
259 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
260 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
261 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
262 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
263
6c1153e0 264 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 265
6c1153e0 266 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 267 EDMA_ERR_OVERRUN_5 = (1 << 5),
268 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 269
270 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
271 EDMA_ERR_LNK_CTRL_RX_1 |
272 EDMA_ERR_LNK_CTRL_RX_3 |
273 EDMA_ERR_LNK_CTRL_TX,
274
bdd4ddde
JG		 275 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
276 EDMA_ERR_PRD_PAR |
277 EDMA_ERR_DEV_DCON |
278 EDMA_ERR_DEV_CON |
279 EDMA_ERR_SERR |
280 EDMA_ERR_SELF_DIS |
6c1153e0 281 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 282 EDMA_ERR_CRPB_PAR |
283 EDMA_ERR_INTRL_PAR |
284 EDMA_ERR_IORDY |
285 EDMA_ERR_LNK_CTRL_RX_2 |
286 EDMA_ERR_LNK_DATA_RX |
287 EDMA_ERR_LNK_DATA_TX |
288 EDMA_ERR_TRANS_PROTO,
289 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
290 EDMA_ERR_PRD_PAR |
291 EDMA_ERR_DEV_DCON |
292 EDMA_ERR_DEV_CON |
293 EDMA_ERR_OVERRUN_5 |
294 EDMA_ERR_UNDERRUN_5 |
295 EDMA_ERR_SELF_DIS_5 |
6c1153e0 296 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 297 EDMA_ERR_CRPB_PAR |
298 EDMA_ERR_INTRL_PAR |
299 EDMA_ERR_IORDY,
20f733e7 300
31961943
BR		 301 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
302 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 303
304 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
305 EDMA_REQ_Q_PTR_SHIFT = 5,
306
307 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
308 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
309 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 310 EDMA_RSP_Q_PTR_SHIFT = 3,
311
0ea9e179
JG		 312 EDMA_CMD_OFS = 0x28, /* EDMA command register */
313 EDMA_EN = (1 << 0), /* enable EDMA */
314 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
315 ATA_RST = (1 << 2), /* reset trans/link/phy */
20f733e7 316
c9d39130 317 EDMA_IORDY_TMOUT = 0x34,
bca1c4eb 318 EDMA_ARB_CFG = 0x38,
bca1c4eb 319
31961943
BR		 320 /* Host private flags (hp_flags) */
321 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 322 MV_HP_ERRATA_50XXB0 = (1 << 1),
323 MV_HP_ERRATA_50XXB2 = (1 << 2),
324 MV_HP_ERRATA_60X1B2 = (1 << 3),
325 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892 326 MV_HP_ERRATA_XX42A0 = (1 << 5),
0ea9e179
JG		 327 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
328 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
329 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 330 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
20f733e7 331
31961943 332 /* Port private flags (pp_flags) */
0ea9e179 333 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 334 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
0ea9e179 335 MV_PP_FLAG_HAD_A_RESET = (1 << 2), /* 1st hard reset complete? */
20f733e7
BR		 336};
337
ee9ccdf7
JG		 338#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
339#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 340#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
bca1c4eb 341
095fec88 342enum {
baf14aa1
JG		 343 /* DMA boundary 0xffff is required by the s/g splitting
344 * we need on /length/ in mv_fill-sg().
345 */
346 MV_DMA_BOUNDARY = 0xffffU,
095fec88 347
0ea9e179
JG		 348 /* mask of register bits containing lower 32 bits
349 * of EDMA request queue DMA address
350 */
095fec88
JG		 351 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
352
0ea9e179 353 /* ditto, for response queue */
095fec88
JG		 354 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
355};
356
522479fb
JG		 357enum chip_type {
358 chip_504x,
359 chip_508x,
360 chip_5080,
361 chip_604x,
362 chip_608x,
e4e7b892
JG		 363 chip_6042,
364 chip_7042,
522479fb
JG		 365};
366
31961943
BR		 367/* Command ReQuest Block: 32B */
368struct mv_crqb {
e1469874
ML		 369 __le32 sg_addr;
370 __le32 sg_addr_hi;
371 __le16 ctrl_flags;
372 __le16 ata_cmd[11];
31961943 373};
20f733e7 374
e4e7b892 375struct mv_crqb_iie {
e1469874
ML		 376 __le32 addr;
377 __le32 addr_hi;
378 __le32 flags;
379 __le32 len;
380 __le32 ata_cmd[4];
e4e7b892
JG		 381};
382
31961943
BR		 383/* Command ResPonse Block: 8B */
384struct mv_crpb {
e1469874
ML		 385 __le16 id;
386 __le16 flags;
387 __le32 tmstmp;
20f733e7
BR		 388};
389
31961943
BR		 390/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
391struct mv_sg {
e1469874
ML		 392 __le32 addr;
393 __le32 flags_size;
394 __le32 addr_hi;
395 __le32 reserved;
31961943 396};
20f733e7 397
31961943
BR		 398struct mv_port_priv {
399 struct mv_crqb *crqb;
400 dma_addr_t crqb_dma;
401 struct mv_crpb *crpb;
402 dma_addr_t crpb_dma;
403 struct mv_sg *sg_tbl;
404 dma_addr_t sg_tbl_dma;
bdd4ddde
JG		 405
406 unsigned int req_idx;
407 unsigned int resp_idx;
408
31961943
BR		 409 u32 pp_flags;
410};
411
bca1c4eb
JG		 412struct mv_port_signal {
413 u32 amps;
414 u32 pre;
415};
416
02a121da
ML		 417struct mv_host_priv {
418 u32 hp_flags;
419 struct mv_port_signal signal[8];
420 const struct mv_hw_ops *ops;
421 u32 irq_cause_ofs;
422 u32 irq_mask_ofs;
423 u32 unmask_all_irqs;
424};
425
47c2b677 426struct mv_hw_ops {
2a47ce06
JG		 427 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
428 unsigned int port);
47c2b677
JG		 429 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
430 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
431 void __iomem *mmio);
c9d39130
JG		 432 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
433 unsigned int n_hc);
522479fb
JG		 434 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
435 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
47c2b677
JG		 436};
437
20f733e7 438static void mv_irq_clear(struct ata_port *ap);
da3dbb17
TH		 439static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
440static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
441static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
442static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 443static int mv_port_start(struct ata_port *ap);
444static void mv_port_stop(struct ata_port *ap);
445static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 446static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 447static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
bdd4ddde
JG		 448static void mv_error_handler(struct ata_port *ap);
449static void mv_post_int_cmd(struct ata_queued_cmd *qc);
450static void mv_eh_freeze(struct ata_port *ap);
451static void mv_eh_thaw(struct ata_port *ap);
20f733e7
BR		 452static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
453
2a47ce06
JG		 454static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
455 unsigned int port);
47c2b677
JG		 456static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
457static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
458 void __iomem *mmio);
c9d39130
JG		 459static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
460 unsigned int n_hc);
522479fb
JG		 461static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
462static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
47c2b677 463
2a47ce06
JG		 464static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
465 unsigned int port);
47c2b677
JG		 466static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
467static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
468 void __iomem *mmio);
c9d39130
JG		 469static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
470 unsigned int n_hc);
522479fb
JG		 471static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
472static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
c9d39130
JG		 473static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
474 unsigned int port_no);
72109168
ML		 475static void mv_edma_cfg(struct mv_port_priv *pp, struct mv_host_priv *hpriv,
476 void __iomem *port_mmio, int want_ncq);
477static int __mv_stop_dma(struct ata_port *ap);
47c2b677 478
c5d3e45a
JG		 479static struct scsi_host_template mv5_sht = {
480 .module = THIS_MODULE,
481 .name = DRV_NAME,
482 .ioctl = ata_scsi_ioctl,
483 .queuecommand = ata_scsi_queuecmd,
484 .can_queue = ATA_DEF_QUEUE,
485 .this_id = ATA_SHT_THIS_ID,
baf14aa1 486 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a
JG		 487 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
488 .emulated = ATA_SHT_EMULATED,
489 .use_clustering = 1,
490 .proc_name = DRV_NAME,
491 .dma_boundary = MV_DMA_BOUNDARY,
3be6cbd7 492 .slave_configure = ata_scsi_slave_config,
c5d3e45a
JG		 493 .slave_destroy = ata_scsi_slave_destroy,
494 .bios_param = ata_std_bios_param,
495};
496
497static struct scsi_host_template mv6_sht = {
20f733e7
BR		 498 .module = THIS_MODULE,
499 .name = DRV_NAME,
500 .ioctl = ata_scsi_ioctl,
501 .queuecommand = ata_scsi_queuecmd,
c5d3e45a 502 .can_queue = ATA_DEF_QUEUE,
20f733e7 503 .this_id = ATA_SHT_THIS_ID,
baf14aa1 504 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7
BR		 505 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
506 .emulated = ATA_SHT_EMULATED,
d88184fb 507 .use_clustering = 1,
20f733e7
BR		 508 .proc_name = DRV_NAME,
509 .dma_boundary = MV_DMA_BOUNDARY,
3be6cbd7 510 .slave_configure = ata_scsi_slave_config,
ccf68c34 511 .slave_destroy = ata_scsi_slave_destroy,
20f733e7 512 .bios_param = ata_std_bios_param,
20f733e7
BR		 513};
514
c9d39130 515static const struct ata_port_operations mv5_ops = {
c9d39130
JG		 516 .tf_load = ata_tf_load,
517 .tf_read = ata_tf_read,
518 .check_status = ata_check_status,
519 .exec_command = ata_exec_command,
520 .dev_select = ata_std_dev_select,
521
cffacd85 522 .cable_detect = ata_cable_sata,
c9d39130
JG		 523
524 .qc_prep = mv_qc_prep,
525 .qc_issue = mv_qc_issue,
0d5ff566 526 .data_xfer = ata_data_xfer,
c9d39130 527
c9d39130 528 .irq_clear = mv_irq_clear,
246ce3b6 529 .irq_on = ata_irq_on,
c9d39130 530
bdd4ddde
JG		 531 .error_handler = mv_error_handler,
532 .post_internal_cmd = mv_post_int_cmd,
533 .freeze = mv_eh_freeze,
534 .thaw = mv_eh_thaw,
535
c9d39130
JG		 536 .scr_read = mv5_scr_read,
537 .scr_write = mv5_scr_write,
538
539 .port_start = mv_port_start,
540 .port_stop = mv_port_stop,
c9d39130
JG		 541};
542
543static const struct ata_port_operations mv6_ops = {
20f733e7
BR		 544 .tf_load = ata_tf_load,
545 .tf_read = ata_tf_read,
546 .check_status = ata_check_status,
547 .exec_command = ata_exec_command,
548 .dev_select = ata_std_dev_select,
549
cffacd85 550 .cable_detect = ata_cable_sata,
20f733e7 551
31961943
BR		 552 .qc_prep = mv_qc_prep,
553 .qc_issue = mv_qc_issue,
0d5ff566 554 .data_xfer = ata_data_xfer,
20f733e7 555
20f733e7 556 .irq_clear = mv_irq_clear,
246ce3b6 557 .irq_on = ata_irq_on,
20f733e7 558
bdd4ddde
JG		 559 .error_handler = mv_error_handler,
560 .post_internal_cmd = mv_post_int_cmd,
561 .freeze = mv_eh_freeze,
562 .thaw = mv_eh_thaw,
563
20f733e7
BR		 564 .scr_read = mv_scr_read,
565 .scr_write = mv_scr_write,
566
31961943
BR		 567 .port_start = mv_port_start,
568 .port_stop = mv_port_stop,
20f733e7
BR		 569};
570
e4e7b892 571static const struct ata_port_operations mv_iie_ops = {
e4e7b892
JG		 572 .tf_load = ata_tf_load,
573 .tf_read = ata_tf_read,
574 .check_status = ata_check_status,
575 .exec_command = ata_exec_command,
576 .dev_select = ata_std_dev_select,
577
cffacd85 578 .cable_detect = ata_cable_sata,
e4e7b892
JG		 579
580 .qc_prep = mv_qc_prep_iie,
581 .qc_issue = mv_qc_issue,
0d5ff566 582 .data_xfer = ata_data_xfer,
e4e7b892 583
e4e7b892 584 .irq_clear = mv_irq_clear,
246ce3b6 585 .irq_on = ata_irq_on,
e4e7b892 586
bdd4ddde
JG		 587 .error_handler = mv_error_handler,
588 .post_internal_cmd = mv_post_int_cmd,
589 .freeze = mv_eh_freeze,
590 .thaw = mv_eh_thaw,
591
e4e7b892
JG		 592 .scr_read = mv_scr_read,
593 .scr_write = mv_scr_write,
594
595 .port_start = mv_port_start,
596 .port_stop = mv_port_stop,
e4e7b892
JG		 597};
598
98ac62de 599static const struct ata_port_info mv_port_info[] = {
20f733e7 600 { /* chip_504x */
cca3974e 601 .flags = MV_COMMON_FLAGS,
31961943 602 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 603 .udma_mask = ATA_UDMA6,
c9d39130 604 .port_ops = &mv5_ops,
20f733e7
BR		 605 },
606 { /* chip_508x */
c5d3e45a 607 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 608 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 609 .udma_mask = ATA_UDMA6,
c9d39130 610 .port_ops = &mv5_ops,
20f733e7 611 },
47c2b677 612 { /* chip_5080 */
c5d3e45a 613 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 614 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 615 .udma_mask = ATA_UDMA6,
c9d39130 616 .port_ops = &mv5_ops,
47c2b677 617 },
20f733e7 618 { /* chip_604x */
c5d3e45a 619 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS,
31961943 620 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 621 .udma_mask = ATA_UDMA6,
c9d39130 622 .port_ops = &mv6_ops,
20f733e7
BR		 623 },
624 { /* chip_608x */
c5d3e45a
JG		 625 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
626 MV_FLAG_DUAL_HC,
31961943 627 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 628 .udma_mask = ATA_UDMA6,
c9d39130 629 .port_ops = &mv6_ops,
20f733e7 630 },
e4e7b892 631 { /* chip_6042 */
c5d3e45a 632 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS,
e4e7b892 633 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 634 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 635 .port_ops = &mv_iie_ops,
636 },
637 { /* chip_7042 */
c5d3e45a 638 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS,
e4e7b892 639 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 640 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 641 .port_ops = &mv_iie_ops,
642 },
20f733e7
BR		 643};
644
3b7d697d 645static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 646 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
647 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
648 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
649 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 650 /* RocketRAID 1740/174x have different identifiers */
651 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
652 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 653
654 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
655 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
656 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
657 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
658 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
659
660 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
661
d9f9c6bc
FA		 662 /* Adaptec 1430SA */
663 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
664
02a121da 665 /* Marvell 7042 support */
6a3d586d
MT		 666 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
667
02a121da
ML		 668 /* Highpoint RocketRAID PCIe series */
669 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
670 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
671
2d2744fc 672 { } /* terminate list */
20f733e7
BR		 673};
674
675static struct pci_driver mv_pci_driver = {
676 .name = DRV_NAME,
677 .id_table = mv_pci_tbl,
678 .probe = mv_init_one,
679 .remove = ata_pci_remove_one,
680};
681
47c2b677
JG		 682static const struct mv_hw_ops mv5xxx_ops = {
683 .phy_errata = mv5_phy_errata,
684 .enable_leds = mv5_enable_leds,
685 .read_preamp = mv5_read_preamp,
686 .reset_hc = mv5_reset_hc,
522479fb
JG		 687 .reset_flash = mv5_reset_flash,
688 .reset_bus = mv5_reset_bus,
47c2b677
JG		 689};
690
691static const struct mv_hw_ops mv6xxx_ops = {
692 .phy_errata = mv6_phy_errata,
693 .enable_leds = mv6_enable_leds,
694 .read_preamp = mv6_read_preamp,
695 .reset_hc = mv6_reset_hc,
522479fb
JG		 696 .reset_flash = mv6_reset_flash,
697 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 698};
699
ddef9bb3
JG		 700/*
701 * module options
702 */
703static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
704
705
d88184fb
JG		 706/* move to PCI layer or libata core? */
707static int pci_go_64(struct pci_dev *pdev)
708{
709 int rc;
710
711 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
712 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
713 if (rc) {
714 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
715 if (rc) {
716 dev_printk(KERN_ERR, &pdev->dev,
717 "64-bit DMA enable failed\n");
718 return rc;
719 }
720 }
721 } else {
722 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
723 if (rc) {
724 dev_printk(KERN_ERR, &pdev->dev,
725 "32-bit DMA enable failed\n");
726 return rc;
727 }
728 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
729 if (rc) {
730 dev_printk(KERN_ERR, &pdev->dev,
731 "32-bit consistent DMA enable failed\n");
732 return rc;
733 }
734 }
735
736 return rc;
737}
738
20f733e7
BR		 739/*
740 * Functions
741 */
742
743static inline void writelfl(unsigned long data, void __iomem *addr)
744{
745 writel(data, addr);
746 (void) readl(addr); /* flush to avoid PCI posted write */
747}
748
20f733e7
BR		 749static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
750{
751 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
752}
753
c9d39130
JG		 754static inline unsigned int mv_hc_from_port(unsigned int port)
755{
756 return port >> MV_PORT_HC_SHIFT;
757}
758
759static inline unsigned int mv_hardport_from_port(unsigned int port)
760{
761 return port & MV_PORT_MASK;
762}
763
764static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
765 unsigned int port)
766{
767 return mv_hc_base(base, mv_hc_from_port(port));
768}
769
20f733e7
BR		 770static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
771{
c9d39130 772 return mv_hc_base_from_port(base, port) +
8b260248 773 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 774 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 775}
776
777static inline void __iomem *mv_ap_base(struct ata_port *ap)
778{
0d5ff566 779 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
20f733e7
BR		 780}
781
cca3974e 782static inline int mv_get_hc_count(unsigned long port_flags)
31961943 783{
cca3974e 784 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 785}
786
787static void mv_irq_clear(struct ata_port *ap)
20f733e7 788{
20f733e7
BR		 789}
790
c5d3e45a
JG		 791static void mv_set_edma_ptrs(void __iomem *port_mmio,
792 struct mv_host_priv *hpriv,
793 struct mv_port_priv *pp)
794{
bdd4ddde
JG		 795 u32 index;
796
c5d3e45a
JG		 797 /*
798 * initialize request queue
799 */
bdd4ddde
JG		 800 index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT;
801
c5d3e45a
JG		 802 WARN_ON(pp->crqb_dma & 0x3ff);
803 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 804 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a
JG		 805 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
806
807 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 808 writelfl((pp->crqb_dma & 0xffffffff) | index,
c5d3e45a
JG		 809 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
810 else
bdd4ddde 811 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 812
813 /*
814 * initialize response queue
815 */
bdd4ddde
JG		 816 index = (pp->resp_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_RSP_Q_PTR_SHIFT;
817
c5d3e45a
JG		 818 WARN_ON(pp->crpb_dma & 0xff);
819 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
820
821 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 822 writelfl((pp->crpb_dma & 0xffffffff) | index,
c5d3e45a
JG		 823 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
824 else
bdd4ddde 825 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
c5d3e45a 826
bdd4ddde 827 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 828 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 829}
830
05b308e1
BR		 831/**
832 * mv_start_dma - Enable eDMA engine
833 * @base: port base address
834 * @pp: port private data
835 *
beec7dbc
TH		 836 * Verify the local cache of the eDMA state is accurate with a
837 * WARN_ON.
05b308e1
BR		 838 *
839 * LOCKING:
840 * Inherited from caller.
841 */
0c58912e 842static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 843 struct mv_port_priv *pp, u8 protocol)
20f733e7 844{
72109168
ML		 845 int want_ncq = (protocol == ATA_PROT_NCQ);
846
847 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
848 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
849 if (want_ncq != using_ncq)
850 __mv_stop_dma(ap);
851 }
c5d3e45a 852 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e
ML		 853 struct mv_host_priv *hpriv = ap->host->private_data;
854 int hard_port = mv_hardport_from_port(ap->port_no);
855 void __iomem *hc_mmio = mv_hc_base_from_port(
856 ap->host->iomap[MV_PRIMARY_BAR], hard_port);
857 u32 hc_irq_cause, ipending;
858
bdd4ddde 859 /* clear EDMA event indicators, if any */
f630d562 860 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 861
0c58912e
ML		 862 /* clear EDMA interrupt indicator, if any */
863 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
864 ipending = (DEV_IRQ << hard_port) |
865 (CRPB_DMA_DONE << hard_port);
866 if (hc_irq_cause & ipending) {
867 writelfl(hc_irq_cause & ~ipending,
868 hc_mmio + HC_IRQ_CAUSE_OFS);
869 }
870
72109168 871 mv_edma_cfg(pp, hpriv, port_mmio, want_ncq);
0c58912e
ML		 872
873 /* clear FIS IRQ Cause */
874 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
875
f630d562 876 mv_set_edma_ptrs(port_mmio, hpriv, pp);
bdd4ddde 877
f630d562 878 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 879 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
880 }
f630d562 881 WARN_ON(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
20f733e7
BR		 882}
883
05b308e1 884/**
0ea9e179 885 * __mv_stop_dma - Disable eDMA engine
05b308e1
BR		 886 * @ap: ATA channel to manipulate
887 *
beec7dbc
TH		 888 * Verify the local cache of the eDMA state is accurate with a
889 * WARN_ON.
05b308e1
BR		 890 *
891 * LOCKING:
892 * Inherited from caller.
893 */
0ea9e179 894static int __mv_stop_dma(struct ata_port *ap)
20f733e7 895{
31961943
BR		 896 void __iomem *port_mmio = mv_ap_base(ap);
897 struct mv_port_priv *pp = ap->private_data;
31961943 898 u32 reg;
c5d3e45a 899 int i, err = 0;
31961943 900
4537deb5 901 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
afb0edd9 902 /* Disable EDMA if active. The disable bit auto clears.
31961943 903 */
31961943
BR		 904 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
905 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
afb0edd9 906 } else {
beec7dbc 907 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
2dcb407e 908 }
8b260248 909
31961943
BR		 910 /* now properly wait for the eDMA to stop */
911 for (i = 1000; i > 0; i--) {
912 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 913 if (!(reg & EDMA_EN))
31961943 914 break;
4537deb5 915
31961943
BR		 916 udelay(100);
917 }
918
c5d3e45a 919 if (reg & EDMA_EN) {
f15a1daf 920 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
c5d3e45a 921 err = -EIO;
31961943 922 }
c5d3e45a
JG		 923
924 return err;
20f733e7
BR		 925}
926
0ea9e179
JG		 927static int mv_stop_dma(struct ata_port *ap)
928{
929 unsigned long flags;
930 int rc;
931
932 spin_lock_irqsave(&ap->host->lock, flags);
933 rc = __mv_stop_dma(ap);
934 spin_unlock_irqrestore(&ap->host->lock, flags);
935
936 return rc;
937}
938
8a70f8dc 939#ifdef ATA_DEBUG
31961943 940static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 941{
31961943
BR		 942 int b, w;
943 for (b = 0; b < bytes; ) {
944 DPRINTK("%p: ", start + b);
945 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 946 printk("%08x ", readl(start + b));
31961943
BR		 947 b += sizeof(u32);
948 }
949 printk("\n");
950 }
31961943 951}
8a70f8dc
JG		 952#endif
953
31961943
BR		 954static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
955{
956#ifdef ATA_DEBUG
957 int b, w;
958 u32 dw;
959 for (b = 0; b < bytes; ) {
960 DPRINTK("%02x: ", b);
961 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 962 (void) pci_read_config_dword(pdev, b, &dw);
963 printk("%08x ", dw);
31961943
BR		 964 b += sizeof(u32);
965 }
966 printk("\n");
967 }
968#endif
969}
970static void mv_dump_all_regs(void __iomem *mmio_base, int port,
971 struct pci_dev *pdev)
972{
973#ifdef ATA_DEBUG
8b260248 974 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 975 port >> MV_PORT_HC_SHIFT);
976 void __iomem *port_base;
977 int start_port, num_ports, p, start_hc, num_hcs, hc;
978
979 if (0 > port) {
980 start_hc = start_port = 0;
981 num_ports = 8; /* shld be benign for 4 port devs */
982 num_hcs = 2;
983 } else {
984 start_hc = port >> MV_PORT_HC_SHIFT;
985 start_port = port;
986 num_ports = num_hcs = 1;
987 }
8b260248 988 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 989 num_ports > 1 ? num_ports - 1 : start_port);
990
991 if (NULL != pdev) {
992 DPRINTK("PCI config space regs:\n");
993 mv_dump_pci_cfg(pdev, 0x68);
994 }
995 DPRINTK("PCI regs:\n");
996 mv_dump_mem(mmio_base+0xc00, 0x3c);
997 mv_dump_mem(mmio_base+0xd00, 0x34);
998 mv_dump_mem(mmio_base+0xf00, 0x4);
999 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1000 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1001 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1002 DPRINTK("HC regs (HC %i):\n", hc);
1003 mv_dump_mem(hc_base, 0x1c);
1004 }
1005 for (p = start_port; p < start_port + num_ports; p++) {
1006 port_base = mv_port_base(mmio_base, p);
2dcb407e 1007 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1008 mv_dump_mem(port_base, 0x54);
2dcb407e 1009 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1010 mv_dump_mem(port_base+0x300, 0x60);
1011 }
1012#endif
20f733e7
BR		 1013}
1014
1015static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1016{
1017 unsigned int ofs;
1018
1019 switch (sc_reg_in) {
1020 case SCR_STATUS:
1021 case SCR_CONTROL:
1022 case SCR_ERROR:
1023 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1024 break;
1025 case SCR_ACTIVE:
1026 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1027 break;
1028 default:
1029 ofs = 0xffffffffU;
1030 break;
1031 }
1032 return ofs;
1033}
1034
da3dbb17 1035static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1036{
1037 unsigned int ofs = mv_scr_offset(sc_reg_in);
1038
da3dbb17
TH		 1039 if (ofs != 0xffffffffU) {
1040 *val = readl(mv_ap_base(ap) + ofs);
1041 return 0;
1042 } else
1043 return -EINVAL;
20f733e7
BR		 1044}
1045
da3dbb17 1046static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1047{
1048 unsigned int ofs = mv_scr_offset(sc_reg_in);
1049
da3dbb17 1050 if (ofs != 0xffffffffU) {
20f733e7 1051 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1052 return 0;
1053 } else
1054 return -EINVAL;
20f733e7
BR		 1055}
1056
72109168
ML		 1057static void mv_edma_cfg(struct mv_port_priv *pp, struct mv_host_priv *hpriv,
1058 void __iomem *port_mmio, int want_ncq)
e4e7b892 1059{
0c58912e 1060 u32 cfg;
e4e7b892
JG		 1061
1062 /* set up non-NCQ EDMA configuration */
0c58912e 1063 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
e4e7b892 1064
0c58912e 1065 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1066 cfg |= (1 << 8); /* enab config burst size mask */
1067
0c58912e 1068 else if (IS_GEN_II(hpriv))
e4e7b892
JG		 1069 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1070
1071 else if (IS_GEN_IIE(hpriv)) {
e728eabe
JG		 1072 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1073 cfg |= (1 << 22); /* enab 4-entry host queue cache */
e4e7b892 1074 cfg |= (1 << 18); /* enab early completion */
e728eabe 1075 cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
e4e7b892
JG		 1076 }
1077
72109168
ML		 1078 if (want_ncq) {
1079 cfg |= EDMA_CFG_NCQ;
1080 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1081 } else
1082 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1083
e4e7b892
JG		 1084 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1085}
1086
05b308e1
BR		 1087/**
1088 * mv_port_start - Port specific init/start routine.
1089 * @ap: ATA channel to manipulate
1090 *
1091 * Allocate and point to DMA memory, init port private memory,
1092 * zero indices.
1093 *
1094 * LOCKING:
1095 * Inherited from caller.
1096 */
31961943
BR		 1097static int mv_port_start(struct ata_port *ap)
1098{
cca3974e
JG		 1099 struct device *dev = ap->host->dev;
1100 struct mv_host_priv *hpriv = ap->host->private_data;
31961943
BR		 1101 struct mv_port_priv *pp;
1102 void __iomem *port_mmio = mv_ap_base(ap);
1103 void *mem;
1104 dma_addr_t mem_dma;
0ea9e179 1105 unsigned long flags;
24dc5f33 1106 int rc;
31961943 1107
24dc5f33 1108 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1109 if (!pp)
24dc5f33 1110 return -ENOMEM;
31961943 1111
24dc5f33
TH		 1112 mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
1113 GFP_KERNEL);
6037d6bb 1114 if (!mem)
24dc5f33 1115 return -ENOMEM;
31961943
BR		 1116 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
1117
6037d6bb
JG		 1118 rc = ata_pad_alloc(ap, dev);
1119 if (rc)
24dc5f33 1120 return rc;
6037d6bb 1121
8b260248 1122 /* First item in chunk of DMA memory:
31961943
BR		 1123 * 32-slot command request table (CRQB), 32 bytes each in size
1124 */
1125 pp->crqb = mem;
1126 pp->crqb_dma = mem_dma;
1127 mem += MV_CRQB_Q_SZ;
1128 mem_dma += MV_CRQB_Q_SZ;
1129
8b260248 1130 /* Second item:
31961943
BR		 1131 * 32-slot command response table (CRPB), 8 bytes each in size
1132 */
1133 pp->crpb = mem;
1134 pp->crpb_dma = mem_dma;
1135 mem += MV_CRPB_Q_SZ;
1136 mem_dma += MV_CRPB_Q_SZ;
1137
1138 /* Third item:
1139 * Table of scatter-gather descriptors (ePRD), 16 bytes each
1140 */
1141 pp->sg_tbl = mem;
1142 pp->sg_tbl_dma = mem_dma;
1143
0ea9e179
JG		 1144 spin_lock_irqsave(&ap->host->lock, flags);
1145
72109168 1146 mv_edma_cfg(pp, hpriv, port_mmio, 0);
e4e7b892 1147
c5d3e45a 1148 mv_set_edma_ptrs(port_mmio, hpriv, pp);
31961943 1149
0ea9e179
JG		 1150 spin_unlock_irqrestore(&ap->host->lock, flags);
1151
31961943
BR		 1152 /* Don't turn on EDMA here...do it before DMA commands only. Else
1153 * we'll be unable to send non-data, PIO, etc due to restricted access
1154 * to shadow regs.
1155 */
1156 ap->private_data = pp;
1157 return 0;
1158}
1159
05b308e1
BR		 1160/**
1161 * mv_port_stop - Port specific cleanup/stop routine.
1162 * @ap: ATA channel to manipulate
1163 *
1164 * Stop DMA, cleanup port memory.
1165 *
1166 * LOCKING:
cca3974e 1167 * This routine uses the host lock to protect the DMA stop.
05b308e1 1168 */
31961943
BR		 1169static void mv_port_stop(struct ata_port *ap)
1170{
31961943 1171 mv_stop_dma(ap);
31961943
BR		 1172}
1173
05b308e1
BR		 1174/**
1175 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1176 * @qc: queued command whose SG list to source from
1177 *
1178 * Populate the SG list and mark the last entry.
1179 *
1180 * LOCKING:
1181 * Inherited from caller.
1182 */
6c08772e 1183static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1184{
1185 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1186 struct scatterlist *sg;
3be6cbd7 1187 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1188 unsigned int si;
31961943 1189
d88184fb 1190 mv_sg = pp->sg_tbl;
ff2aeb1e 1191 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1192 dma_addr_t addr = sg_dma_address(sg);
1193 u32 sg_len = sg_dma_len(sg);
22374677 1194
4007b493
OJ		 1195 while (sg_len) {
1196 u32 offset = addr & 0xffff;
1197 u32 len = sg_len;
22374677 1198
4007b493
OJ		 1199 if ((offset + sg_len > 0x10000))
1200 len = 0x10000 - offset;
1201
1202 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1203 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1204 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1205
1206 sg_len -= len;
1207 addr += len;
1208
3be6cbd7 1209 last_sg = mv_sg;
4007b493 1210 mv_sg++;
4007b493 1211 }
31961943 1212 }
3be6cbd7
JG		 1213
1214 if (likely(last_sg))
1215 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1216}
1217
5796d1c4 1218static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1219{
559eedad 1220 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1221 (last ? CRQB_CMD_LAST : 0);
559eedad 1222 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1223}
1224
05b308e1
BR		 1225/**
1226 * mv_qc_prep - Host specific command preparation.
1227 * @qc: queued command to prepare
1228 *
1229 * This routine simply redirects to the general purpose routine
1230 * if command is not DMA. Else, it handles prep of the CRQB
1231 * (command request block), does some sanity checking, and calls
1232 * the SG load routine.
1233 *
1234 * LOCKING:
1235 * Inherited from caller.
1236 */
31961943
BR		 1237static void mv_qc_prep(struct ata_queued_cmd *qc)
1238{
1239 struct ata_port *ap = qc->ap;
1240 struct mv_port_priv *pp = ap->private_data;
e1469874 1241 __le16 *cw;
31961943
BR		 1242 struct ata_taskfile *tf;
1243 u16 flags = 0;
a6432436 1244 unsigned in_index;
31961943 1245
2dcb407e 1246 if (qc->tf.protocol != ATA_PROT_DMA)
31961943 1247 return;
20f733e7 1248
31961943
BR		 1249 /* Fill in command request block
1250 */
e4e7b892 1251 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1252 flags |= CRQB_FLAG_READ;
beec7dbc 1253 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943
BR		 1254 flags |= qc->tag << CRQB_TAG_SHIFT;
1255
bdd4ddde
JG		 1256 /* get current queue index from software */
1257 in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK;
a6432436
ML		 1258
1259 pp->crqb[in_index].sg_addr =
31961943 1260 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
a6432436 1261 pp->crqb[in_index].sg_addr_hi =
31961943 1262 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
a6432436 1263 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1264
a6432436 1265 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1266 tf = &qc->tf;
1267
1268 /* Sadly, the CRQB cannot accomodate all registers--there are
1269 * only 11 bytes...so we must pick and choose required
1270 * registers based on the command. So, we drop feature and
1271 * hob_feature for [RW] DMA commands, but they are needed for
1272 * NCQ. NCQ will drop hob_nsect.
20f733e7 1273 */
31961943
BR		 1274 switch (tf->command) {
1275 case ATA_CMD_READ:
1276 case ATA_CMD_READ_EXT:
1277 case ATA_CMD_WRITE:
1278 case ATA_CMD_WRITE_EXT:
c15d85c8 1279 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1280 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1281 break;
1282#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1283 case ATA_CMD_FPDMA_READ:
1284 case ATA_CMD_FPDMA_WRITE:
8b260248 1285 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1286 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1287 break;
1288#endif /* FIXME: remove this line when NCQ added */
1289 default:
1290 /* The only other commands EDMA supports in non-queued and
1291 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1292 * of which are defined/used by Linux. If we get here, this
1293 * driver needs work.
1294 *
1295 * FIXME: modify libata to give qc_prep a return value and
1296 * return error here.
1297 */
1298 BUG_ON(tf->command);
1299 break;
1300 }
1301 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1302 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1303 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1304 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1305 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1306 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1307 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1308 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1309 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1310
e4e7b892
JG		 1311 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1312 return;
1313 mv_fill_sg(qc);
1314}
1315
1316/**
1317 * mv_qc_prep_iie - Host specific command preparation.
1318 * @qc: queued command to prepare
1319 *
1320 * This routine simply redirects to the general purpose routine
1321 * if command is not DMA. Else, it handles prep of the CRQB
1322 * (command request block), does some sanity checking, and calls
1323 * the SG load routine.
1324 *
1325 * LOCKING:
1326 * Inherited from caller.
1327 */
1328static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1329{
1330 struct ata_port *ap = qc->ap;
1331 struct mv_port_priv *pp = ap->private_data;
1332 struct mv_crqb_iie *crqb;
1333 struct ata_taskfile *tf;
a6432436 1334 unsigned in_index;
e4e7b892
JG		 1335 u32 flags = 0;
1336
2dcb407e 1337 if (qc->tf.protocol != ATA_PROT_DMA)
e4e7b892
JG		 1338 return;
1339
e4e7b892
JG		 1340 /* Fill in Gen IIE command request block
1341 */
1342 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1343 flags |= CRQB_FLAG_READ;
1344
beec7dbc 1345 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1346 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1347 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e4e7b892 1348
bdd4ddde
JG		 1349 /* get current queue index from software */
1350 in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK;
a6432436
ML		 1351
1352 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
e4e7b892
JG		 1353 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1354 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1355 crqb->flags = cpu_to_le32(flags);
1356
1357 tf = &qc->tf;
1358 crqb->ata_cmd[0] = cpu_to_le32(
1359 (tf->command << 16) |
1360 (tf->feature << 24)
1361 );
1362 crqb->ata_cmd[1] = cpu_to_le32(
1363 (tf->lbal << 0) |
1364 (tf->lbam << 8) |
1365 (tf->lbah << 16) |
1366 (tf->device << 24)
1367 );
1368 crqb->ata_cmd[2] = cpu_to_le32(
1369 (tf->hob_lbal << 0) |
1370 (tf->hob_lbam << 8) |
1371 (tf->hob_lbah << 16) |
1372 (tf->hob_feature << 24)
1373 );
1374 crqb->ata_cmd[3] = cpu_to_le32(
1375 (tf->nsect << 0) |
1376 (tf->hob_nsect << 8)
1377 );
1378
1379 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1380 return;
31961943
BR		 1381 mv_fill_sg(qc);
1382}
1383
05b308e1
BR		 1384/**
1385 * mv_qc_issue - Initiate a command to the host
1386 * @qc: queued command to start
1387 *
1388 * This routine simply redirects to the general purpose routine
1389 * if command is not DMA. Else, it sanity checks our local
1390 * caches of the request producer/consumer indices then enables
1391 * DMA and bumps the request producer index.
1392 *
1393 * LOCKING:
1394 * Inherited from caller.
1395 */
9a3d9eb0 1396static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1397{
c5d3e45a
JG		 1398 struct ata_port *ap = qc->ap;
1399 void __iomem *port_mmio = mv_ap_base(ap);
1400 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1401 u32 in_index;
31961943 1402
c5d3e45a 1403 if (qc->tf.protocol != ATA_PROT_DMA) {
31961943
BR		 1404 /* We're about to send a non-EDMA capable command to the
1405 * port. Turn off EDMA so there won't be problems accessing
1406 * shadow block, etc registers.
1407 */
0ea9e179 1408 __mv_stop_dma(ap);
31961943
BR		 1409 return ata_qc_issue_prot(qc);
1410 }
1411
72109168 1412 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde
JG		 1413
1414 in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK;
31961943 1415
31961943 1416 /* until we do queuing, the queue should be empty at this point */
a6432436
ML		 1417 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1418 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
31961943 1419
bdd4ddde 1420 pp->req_idx++;
31961943 1421
bdd4ddde 1422 in_index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1423
1424 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1425 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1426 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1427
1428 return 0;
1429}
1430
05b308e1
BR		 1431/**
1432 * mv_err_intr - Handle error interrupts on the port
1433 * @ap: ATA channel to manipulate
9b358e30 1434 * @reset_allowed: bool: 0 == don't trigger from reset here
05b308e1
BR		 1435 *
1436 * In most cases, just clear the interrupt and move on. However,
1437 * some cases require an eDMA reset, which is done right before
1438 * the COMRESET in mv_phy_reset(). The SERR case requires a
1439 * clear of pending errors in the SATA SERROR register. Finally,
1440 * if the port disabled DMA, update our cached copy to match.
1441 *
1442 * LOCKING:
1443 * Inherited from caller.
1444 */
bdd4ddde 1445static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
31961943
BR		 1446{
1447 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde
JG		 1448 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1449 struct mv_port_priv *pp = ap->private_data;
1450 struct mv_host_priv *hpriv = ap->host->private_data;
1451 unsigned int edma_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
1452 unsigned int action = 0, err_mask = 0;
9af5c9c9 1453 struct ata_eh_info *ehi = &ap->link.eh_info;
20f733e7 1454
bdd4ddde 1455 ata_ehi_clear_desc(ehi);
20f733e7 1456
bdd4ddde
JG		 1457 if (!edma_enabled) {
1458 /* just a guess: do we need to do this? should we
1459 * expand this, and do it in all cases?
1460 */
936fd732
TH		 1461 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1462 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
20f733e7 1463 }
bdd4ddde
JG		 1464
1465 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1466
1467 ata_ehi_push_desc(ehi, "edma_err 0x%08x", edma_err_cause);
1468
1469 /*
1470 * all generations share these EDMA error cause bits
1471 */
1472
1473 if (edma_err_cause & EDMA_ERR_DEV)
1474 err_mask |= AC_ERR_DEV;
1475 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1476 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1477 EDMA_ERR_INTRL_PAR)) {
1478 err_mask |= AC_ERR_ATA_BUS;
1479 action |= ATA_EH_HARDRESET;
b64bbc39 1480 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1481 }
1482 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1483 ata_ehi_hotplugged(ehi);
1484 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1485 "dev disconnect" : "dev connect");
3606a380 1486 action |= ATA_EH_HARDRESET;
bdd4ddde
JG		 1487 }
1488
ee9ccdf7 1489 if (IS_GEN_I(hpriv)) {
bdd4ddde
JG		 1490 eh_freeze_mask = EDMA_EH_FREEZE_5;
1491
1492 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
1493 struct mv_port_priv *pp = ap->private_data;
1494 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1495 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1496 }
1497 } else {
1498 eh_freeze_mask = EDMA_EH_FREEZE;
1499
1500 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1501 struct mv_port_priv *pp = ap->private_data;
1502 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1503 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1504 }
1505
1506 if (edma_err_cause & EDMA_ERR_SERR) {
936fd732
TH		 1507 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1508 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
bdd4ddde
JG		 1509 err_mask = AC_ERR_ATA_BUS;
1510 action |= ATA_EH_HARDRESET;
1511 }
afb0edd9 1512 }
20f733e7
BR		 1513
1514 /* Clear EDMA now that SERR cleanup done */
3606a380 1515 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
20f733e7 1516
bdd4ddde
JG		 1517 if (!err_mask) {
1518 err_mask = AC_ERR_OTHER;
1519 action |= ATA_EH_HARDRESET;
1520 }
1521
1522 ehi->serror |= serr;
1523 ehi->action |= action;
1524
1525 if (qc)
1526 qc->err_mask |= err_mask;
1527 else
1528 ehi->err_mask |= err_mask;
1529
1530 if (edma_err_cause & eh_freeze_mask)
1531 ata_port_freeze(ap);
1532 else
1533 ata_port_abort(ap);
1534}
1535
1536static void mv_intr_pio(struct ata_port *ap)
1537{
1538 struct ata_queued_cmd *qc;
1539 u8 ata_status;
1540
1541 /* ignore spurious intr if drive still BUSY */
1542 ata_status = readb(ap->ioaddr.status_addr);
1543 if (unlikely(ata_status & ATA_BUSY))
1544 return;
1545
1546 /* get active ATA command */
9af5c9c9 1547 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 1548 if (unlikely(!qc)) /* no active tag */
1549 return;
1550 if (qc->tf.flags & ATA_TFLAG_POLLING) /* polling; we don't own qc */
1551 return;
1552
1553 /* and finally, complete the ATA command */
1554 qc->err_mask |= ac_err_mask(ata_status);
1555 ata_qc_complete(qc);
1556}
1557
1558static void mv_intr_edma(struct ata_port *ap)
1559{
1560 void __iomem *port_mmio = mv_ap_base(ap);
1561 struct mv_host_priv *hpriv = ap->host->private_data;
1562 struct mv_port_priv *pp = ap->private_data;
1563 struct ata_queued_cmd *qc;
1564 u32 out_index, in_index;
1565 bool work_done = false;
1566
1567 /* get h/w response queue pointer */
1568 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1569 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1570
1571 while (1) {
1572 u16 status;
6c1153e0 1573 unsigned int tag;
bdd4ddde
JG		 1574
1575 /* get s/w response queue last-read pointer, and compare */
1576 out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK;
1577 if (in_index == out_index)
1578 break;
1579
bdd4ddde 1580 /* 50xx: get active ATA command */
0ea9e179 1581 if (IS_GEN_I(hpriv))
9af5c9c9 1582 tag = ap->link.active_tag;
bdd4ddde 1583
6c1153e0
JG		 1584 /* Gen II/IIE: get active ATA command via tag, to enable
1585 * support for queueing. this works transparently for
1586 * queued and non-queued modes.
bdd4ddde 1587 */
8c0aeb4a
ML		 1588 else
1589 tag = le16_to_cpu(pp->crpb[out_index].id) & 0x1f;
bdd4ddde 1590
6c1153e0 1591 qc = ata_qc_from_tag(ap, tag);
bdd4ddde 1592
cb924419
ML		 1593 /* For non-NCQ mode, the lower 8 bits of status
1594 * are from EDMA_ERR_IRQ_CAUSE_OFS,
1595 * which should be zero if all went well.
bdd4ddde
JG		 1596 */
1597 status = le16_to_cpu(pp->crpb[out_index].flags);
cb924419 1598 if ((status & 0xff) && !(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
bdd4ddde
JG		 1599 mv_err_intr(ap, qc);
1600 return;
1601 }
1602
1603 /* and finally, complete the ATA command */
1604 if (qc) {
1605 qc->err_mask |=
1606 ac_err_mask(status >> CRPB_FLAG_STATUS_SHIFT);
1607 ata_qc_complete(qc);
1608 }
1609
0ea9e179 1610 /* advance software response queue pointer, to
bdd4ddde
JG		 1611 * indicate (after the loop completes) to hardware
1612 * that we have consumed a response queue entry.
1613 */
1614 work_done = true;
1615 pp->resp_idx++;
1616 }
1617
1618 if (work_done)
1619 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
1620 (out_index << EDMA_RSP_Q_PTR_SHIFT),
1621 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 1622}
1623
05b308e1
BR		 1624/**
1625 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 1626 * @host: host specific structure
05b308e1
BR		 1627 * @relevant: port error bits relevant to this host controller
1628 * @hc: which host controller we're to look at
1629 *
1630 * Read then write clear the HC interrupt status then walk each
1631 * port connected to the HC and see if it needs servicing. Port
1632 * success ints are reported in the HC interrupt status reg, the
1633 * port error ints are reported in the higher level main
1634 * interrupt status register and thus are passed in via the
1635 * 'relevant' argument.
1636 *
1637 * LOCKING:
1638 * Inherited from caller.
1639 */
cca3974e 1640static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
20f733e7 1641{
0d5ff566 1642 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
20f733e7 1643 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
20f733e7 1644 u32 hc_irq_cause;
c5d3e45a 1645 int port, port0;
20f733e7 1646
35177265 1647 if (hc == 0)
20f733e7 1648 port0 = 0;
35177265 1649 else
20f733e7 1650 port0 = MV_PORTS_PER_HC;
20f733e7
BR		 1651
1652 /* we'll need the HC success int register in most cases */
1653 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde
JG		 1654 if (!hc_irq_cause)
1655 return;
1656
1657 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 1658
1659 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
2dcb407e 1660 hc, relevant, hc_irq_cause);
20f733e7
BR		 1661
1662 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
cca3974e 1663 struct ata_port *ap = host->ports[port];
63af2a5c 1664 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1665 int have_err_bits, hard_port, shift;
55d8ca4f 1666
bdd4ddde 1667 if ((!ap) || (ap->flags & ATA_FLAG_DISABLED))
a2c91a88
JG		 1668 continue;
1669
31961943 1670 shift = port << 1; /* (port * 2) */
20f733e7
BR		 1671 if (port >= MV_PORTS_PER_HC) {
1672 shift++; /* skip bit 8 in the HC Main IRQ reg */
1673 }
bdd4ddde
JG		 1674 have_err_bits = ((PORT0_ERR << shift) & relevant);
1675
1676 if (unlikely(have_err_bits)) {
1677 struct ata_queued_cmd *qc;
8b260248 1678
9af5c9c9 1679 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 1680 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1681 continue;
1682
1683 mv_err_intr(ap, qc);
1684 continue;
1685 }
1686
1687 hard_port = mv_hardport_from_port(port); /* range 0..3 */
1688
1689 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1690 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause)
1691 mv_intr_edma(ap);
1692 } else {
1693 if ((DEV_IRQ << hard_port) & hc_irq_cause)
1694 mv_intr_pio(ap);
20f733e7
BR		 1695 }
1696 }
1697 VPRINTK("EXIT\n");
1698}
1699
bdd4ddde
JG		 1700static void mv_pci_error(struct ata_host *host, void __iomem *mmio)
1701{
02a121da 1702 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 1703 struct ata_port *ap;
1704 struct ata_queued_cmd *qc;
1705 struct ata_eh_info *ehi;
1706 unsigned int i, err_mask, printed = 0;
1707 u32 err_cause;
1708
02a121da 1709 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 1710
1711 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
1712 err_cause);
1713
1714 DPRINTK("All regs @ PCI error\n");
1715 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1716
02a121da 1717 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 1718
1719 for (i = 0; i < host->n_ports; i++) {
1720 ap = host->ports[i];
936fd732 1721 if (!ata_link_offline(&ap->link)) {
9af5c9c9 1722 ehi = &ap->link.eh_info;
bdd4ddde
JG		 1723 ata_ehi_clear_desc(ehi);
1724 if (!printed++)
1725 ata_ehi_push_desc(ehi,
1726 "PCI err cause 0x%08x", err_cause);
1727 err_mask = AC_ERR_HOST_BUS;
1728 ehi->action = ATA_EH_HARDRESET;
9af5c9c9 1729 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 1730 if (qc)
1731 qc->err_mask |= err_mask;
1732 else
1733 ehi->err_mask |= err_mask;
1734
1735 ata_port_freeze(ap);
1736 }
1737 }
1738}
1739
05b308e1 1740/**
c5d3e45a 1741 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 1742 * @irq: unused
1743 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 1744 *
1745 * Read the read only register to determine if any host
1746 * controllers have pending interrupts. If so, call lower level
1747 * routine to handle. Also check for PCI errors which are only
1748 * reported here.
1749 *
8b260248 1750 * LOCKING:
cca3974e 1751 * This routine holds the host lock while processing pending
05b308e1
BR		 1752 * interrupts.
1753 */
7d12e780 1754static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 1755{
cca3974e 1756 struct ata_host *host = dev_instance;
20f733e7 1757 unsigned int hc, handled = 0, n_hcs;
0d5ff566 1758 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
646a4da5 1759 u32 irq_stat, irq_mask;
20f733e7 1760
646a4da5 1761 spin_lock(&host->lock);
20f733e7 1762 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
646a4da5 1763 irq_mask = readl(mmio + HC_MAIN_IRQ_MASK_OFS);
20f733e7
BR		 1764
1765 /* check the cases where we either have nothing pending or have read
1766 * a bogus register value which can indicate HW removal or PCI fault
1767 */
646a4da5
ML		 1768 if (!(irq_stat & irq_mask) || (0xffffffffU == irq_stat))
1769 goto out_unlock;
20f733e7 1770
cca3974e 1771 n_hcs = mv_get_hc_count(host->ports[0]->flags);
20f733e7 1772
bdd4ddde
JG		 1773 if (unlikely(irq_stat & PCI_ERR)) {
1774 mv_pci_error(host, mmio);
1775 handled = 1;
1776 goto out_unlock; /* skip all other HC irq handling */
1777 }
1778
20f733e7
BR		 1779 for (hc = 0; hc < n_hcs; hc++) {
1780 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1781 if (relevant) {
cca3974e 1782 mv_host_intr(host, relevant, hc);
bdd4ddde 1783 handled = 1;
20f733e7
BR		 1784 }
1785 }
615ab953 1786
bdd4ddde 1787out_unlock:
cca3974e 1788 spin_unlock(&host->lock);
20f733e7
BR		 1789
1790 return IRQ_RETVAL(handled);
1791}
1792
c9d39130
JG		 1793static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1794{
1795 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1796 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1797
1798 return hc_mmio + ofs;
1799}
1800
1801static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1802{
1803 unsigned int ofs;
1804
1805 switch (sc_reg_in) {
1806 case SCR_STATUS:
1807 case SCR_ERROR:
1808 case SCR_CONTROL:
1809 ofs = sc_reg_in * sizeof(u32);
1810 break;
1811 default:
1812 ofs = 0xffffffffU;
1813 break;
1814 }
1815 return ofs;
1816}
1817
da3dbb17 1818static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 1819{
0d5ff566
TH		 1820 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1821 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1822 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1823
da3dbb17
TH		 1824 if (ofs != 0xffffffffU) {
1825 *val = readl(addr + ofs);
1826 return 0;
1827 } else
1828 return -EINVAL;
c9d39130
JG		 1829}
1830
da3dbb17 1831static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 1832{
0d5ff566
TH		 1833 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1834 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1835 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1836
da3dbb17 1837 if (ofs != 0xffffffffU) {
0d5ff566 1838 writelfl(val, addr + ofs);
da3dbb17
TH		 1839 return 0;
1840 } else
1841 return -EINVAL;
c9d39130
JG		 1842}
1843
522479fb
JG		 1844static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1845{
522479fb
JG		 1846 int early_5080;
1847
44c10138 1848 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 1849
1850 if (!early_5080) {
1851 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1852 tmp |= (1 << 0);
1853 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1854 }
1855
1856 mv_reset_pci_bus(pdev, mmio);
1857}
1858
1859static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1860{
1861 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1862}
1863
47c2b677 1864static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1865 void __iomem *mmio)
1866{
c9d39130
JG		 1867 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1868 u32 tmp;
1869
1870 tmp = readl(phy_mmio + MV5_PHY_MODE);
1871
1872 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1873 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 1874}
1875
47c2b677 1876static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1877{
522479fb
JG		 1878 u32 tmp;
1879
1880 writel(0, mmio + MV_GPIO_PORT_CTL);
1881
1882 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1883
1884 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1885 tmp |= ~(1 << 0);
1886 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 1887}
1888
2a47ce06
JG		 1889static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1890 unsigned int port)
bca1c4eb 1891{
c9d39130
JG		 1892 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1893 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1894 u32 tmp;
1895 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1896
1897 if (fix_apm_sq) {
1898 tmp = readl(phy_mmio + MV5_LT_MODE);
1899 tmp |= (1 << 19);
1900 writel(tmp, phy_mmio + MV5_LT_MODE);
1901
1902 tmp = readl(phy_mmio + MV5_PHY_CTL);
1903 tmp &= ~0x3;
1904 tmp |= 0x1;
1905 writel(tmp, phy_mmio + MV5_PHY_CTL);
1906 }
1907
1908 tmp = readl(phy_mmio + MV5_PHY_MODE);
1909 tmp &= ~mask;
1910 tmp |= hpriv->signal[port].pre;
1911 tmp |= hpriv->signal[port].amps;
1912 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 1913}
1914
c9d39130
JG		 1915
1916#undef ZERO
1917#define ZERO(reg) writel(0, port_mmio + (reg))
1918static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1919 unsigned int port)
1920{
1921 void __iomem *port_mmio = mv_port_base(mmio, port);
1922
1923 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1924
1925 mv_channel_reset(hpriv, mmio, port);
1926
1927 ZERO(0x028); /* command */
1928 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1929 ZERO(0x004); /* timer */
1930 ZERO(0x008); /* irq err cause */
1931 ZERO(0x00c); /* irq err mask */
1932 ZERO(0x010); /* rq bah */
1933 ZERO(0x014); /* rq inp */
1934 ZERO(0x018); /* rq outp */
1935 ZERO(0x01c); /* respq bah */
1936 ZERO(0x024); /* respq outp */
1937 ZERO(0x020); /* respq inp */
1938 ZERO(0x02c); /* test control */
1939 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1940}
1941#undef ZERO
1942
1943#define ZERO(reg) writel(0, hc_mmio + (reg))
1944static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1945 unsigned int hc)
47c2b677 1946{
c9d39130
JG		 1947 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1948 u32 tmp;
1949
1950 ZERO(0x00c);
1951 ZERO(0x010);
1952 ZERO(0x014);
1953 ZERO(0x018);
1954
1955 tmp = readl(hc_mmio + 0x20);
1956 tmp &= 0x1c1c1c1c;
1957 tmp |= 0x03030303;
1958 writel(tmp, hc_mmio + 0x20);
1959}
1960#undef ZERO
1961
1962static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1963 unsigned int n_hc)
1964{
1965 unsigned int hc, port;
1966
1967 for (hc = 0; hc < n_hc; hc++) {
1968 for (port = 0; port < MV_PORTS_PER_HC; port++)
1969 mv5_reset_hc_port(hpriv, mmio,
1970 (hc * MV_PORTS_PER_HC) + port);
1971
1972 mv5_reset_one_hc(hpriv, mmio, hc);
1973 }
1974
1975 return 0;
47c2b677
JG		 1976}
1977
101ffae2
JG		 1978#undef ZERO
1979#define ZERO(reg) writel(0, mmio + (reg))
1980static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1981{
02a121da
ML		 1982 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1983 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 1984 u32 tmp;
1985
1986 tmp = readl(mmio + MV_PCI_MODE);
1987 tmp &= 0xff00ffff;
1988 writel(tmp, mmio + MV_PCI_MODE);
1989
1990 ZERO(MV_PCI_DISC_TIMER);
1991 ZERO(MV_PCI_MSI_TRIGGER);
1992 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1993 ZERO(HC_MAIN_IRQ_MASK_OFS);
1994 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 1995 ZERO(hpriv->irq_cause_ofs);
1996 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 1997 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1998 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1999 ZERO(MV_PCI_ERR_ATTRIBUTE);
2000 ZERO(MV_PCI_ERR_COMMAND);
2001}
2002#undef ZERO
2003
2004static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2005{
2006 u32 tmp;
2007
2008 mv5_reset_flash(hpriv, mmio);
2009
2010 tmp = readl(mmio + MV_GPIO_PORT_CTL);
2011 tmp &= 0x3;
2012 tmp |= (1 << 5) | (1 << 6);
2013 writel(tmp, mmio + MV_GPIO_PORT_CTL);
2014}
2015
2016/**
2017 * mv6_reset_hc - Perform the 6xxx global soft reset
2018 * @mmio: base address of the HBA
2019 *
2020 * This routine only applies to 6xxx parts.
2021 *
2022 * LOCKING:
2023 * Inherited from caller.
2024 */
c9d39130
JG		 2025static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2026 unsigned int n_hc)
101ffae2
JG		 2027{
2028 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2029 int i, rc = 0;
2030 u32 t;
2031
2032 /* Following procedure defined in PCI "main command and status
2033 * register" table.
2034 */
2035 t = readl(reg);
2036 writel(t | STOP_PCI_MASTER, reg);
2037
2038 for (i = 0; i < 1000; i++) {
2039 udelay(1);
2040 t = readl(reg);
2dcb407e 2041 if (PCI_MASTER_EMPTY & t)
101ffae2 2042 break;
101ffae2
JG		 2043 }
2044 if (!(PCI_MASTER_EMPTY & t)) {
2045 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2046 rc = 1;
2047 goto done;
2048 }
2049
2050 /* set reset */
2051 i = 5;
2052 do {
2053 writel(t | GLOB_SFT_RST, reg);
2054 t = readl(reg);
2055 udelay(1);
2056 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2057
2058 if (!(GLOB_SFT_RST & t)) {
2059 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2060 rc = 1;
2061 goto done;
2062 }
2063
2064 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2065 i = 5;
2066 do {
2067 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2068 t = readl(reg);
2069 udelay(1);
2070 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2071
2072 if (GLOB_SFT_RST & t) {
2073 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2074 rc = 1;
2075 }
2076done:
2077 return rc;
2078}
2079
47c2b677 2080static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2081 void __iomem *mmio)
2082{
2083 void __iomem *port_mmio;
2084 u32 tmp;
2085
ba3fe8fb
JG		 2086 tmp = readl(mmio + MV_RESET_CFG);
2087 if ((tmp & (1 << 0)) == 0) {
47c2b677 2088 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2089 hpriv->signal[idx].pre = 0x1 << 5;
2090 return;
2091 }
2092
2093 port_mmio = mv_port_base(mmio, idx);
2094 tmp = readl(port_mmio + PHY_MODE2);
2095
2096 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2097 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2098}
2099
47c2b677 2100static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2101{
47c2b677 2102 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
ba3fe8fb
JG		 2103}
2104
c9d39130 2105static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2106 unsigned int port)
bca1c4eb 2107{
c9d39130
JG		 2108 void __iomem *port_mmio = mv_port_base(mmio, port);
2109
bca1c4eb 2110 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2111 int fix_phy_mode2 =
2112 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2113 int fix_phy_mode4 =
47c2b677
JG		 2114 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2115 u32 m2, tmp;
2116
2117 if (fix_phy_mode2) {
2118 m2 = readl(port_mmio + PHY_MODE2);
2119 m2 &= ~(1 << 16);
2120 m2 |= (1 << 31);
2121 writel(m2, port_mmio + PHY_MODE2);
2122
2123 udelay(200);
2124
2125 m2 = readl(port_mmio + PHY_MODE2);
2126 m2 &= ~((1 << 16) | (1 << 31));
2127 writel(m2, port_mmio + PHY_MODE2);
2128
2129 udelay(200);
2130 }
2131
2132 /* who knows what this magic does */
2133 tmp = readl(port_mmio + PHY_MODE3);
2134 tmp &= ~0x7F800000;
2135 tmp |= 0x2A800000;
2136 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2137
2138 if (fix_phy_mode4) {
47c2b677 2139 u32 m4;
bca1c4eb
JG		 2140
2141 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 2142
2143 if (hp_flags & MV_HP_ERRATA_60X1B2)
2144 tmp = readl(port_mmio + 0x310);
bca1c4eb
JG		 2145
2146 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2147
2148 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 2149
2150 if (hp_flags & MV_HP_ERRATA_60X1B2)
2151 writel(tmp, port_mmio + 0x310);
bca1c4eb
JG		 2152 }
2153
2154 /* Revert values of pre-emphasis and signal amps to the saved ones */
2155 m2 = readl(port_mmio + PHY_MODE2);
2156
2157 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2158 m2 |= hpriv->signal[port].amps;
2159 m2 |= hpriv->signal[port].pre;
47c2b677 2160 m2 &= ~(1 << 16);
bca1c4eb 2161
e4e7b892
JG		 2162 /* according to mvSata 3.6.1, some IIE values are fixed */
2163 if (IS_GEN_IIE(hpriv)) {
2164 m2 &= ~0xC30FF01F;
2165 m2 |= 0x0000900F;
2166 }
2167
bca1c4eb
JG		 2168 writel(m2, port_mmio + PHY_MODE2);
2169}
2170
c9d39130
JG		 2171static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
2172 unsigned int port_no)
2173{
2174 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2175
2176 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
2177
ee9ccdf7 2178 if (IS_GEN_II(hpriv)) {
c9d39130 2179 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
eb46d684
ML		 2180 ifctl |= (1 << 7); /* enable gen2i speed */
2181 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
c9d39130
JG		 2182 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2183 }
2184
2185 udelay(25); /* allow reset propagation */
2186
2187 /* Spec never mentions clearing the bit. Marvell's driver does
2188 * clear the bit, however.
2189 */
2190 writelfl(0, port_mmio + EDMA_CMD_OFS);
2191
2192 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2193
ee9ccdf7 2194 if (IS_GEN_I(hpriv))
c9d39130
JG		 2195 mdelay(1);
2196}
2197
05b308e1 2198/**
bdd4ddde 2199 * mv_phy_reset - Perform eDMA reset followed by COMRESET
05b308e1
BR		 2200 * @ap: ATA channel to manipulate
2201 *
2202 * Part of this is taken from __sata_phy_reset and modified to
2203 * not sleep since this routine gets called from interrupt level.
2204 *
2205 * LOCKING:
2206 * Inherited from caller. This is coded to safe to call at
2207 * interrupt level, i.e. it does not sleep.
31961943 2208 */
bdd4ddde
JG		 2209static void mv_phy_reset(struct ata_port *ap, unsigned int *class,
2210 unsigned long deadline)
20f733e7 2211{
095fec88 2212 struct mv_port_priv *pp = ap->private_data;
cca3974e 2213 struct mv_host_priv *hpriv = ap->host->private_data;
20f733e7 2214 void __iomem *port_mmio = mv_ap_base(ap);
22374677
JG		 2215 int retry = 5;
2216 u32 sstatus;
20f733e7
BR		 2217
2218 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
2219
da3dbb17
TH		 2220#ifdef DEBUG
2221 {
2222 u32 sstatus, serror, scontrol;
2223
2224 mv_scr_read(ap, SCR_STATUS, &sstatus);
2225 mv_scr_read(ap, SCR_ERROR, &serror);
2226 mv_scr_read(ap, SCR_CONTROL, &scontrol);
2227 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
2d79ab8f 2228 "SCtrl 0x%08x\n", sstatus, serror, scontrol);
da3dbb17
TH		 2229 }
2230#endif
20f733e7 2231
22374677
JG		 2232 /* Issue COMRESET via SControl */
2233comreset_retry:
936fd732 2234 sata_scr_write_flush(&ap->link, SCR_CONTROL, 0x301);
bdd4ddde 2235 msleep(1);
22374677 2236
936fd732 2237 sata_scr_write_flush(&ap->link, SCR_CONTROL, 0x300);
bdd4ddde 2238 msleep(20);
22374677 2239
31961943 2240 do {
936fd732 2241 sata_scr_read(&ap->link, SCR_STATUS, &sstatus);
62f1d0e6 2242 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
31961943 2243 break;
22374677 2244
bdd4ddde 2245 msleep(1);
c5d3e45a 2246 } while (time_before(jiffies, deadline));
20f733e7 2247
22374677 2248 /* work around errata */
ee9ccdf7 2249 if (IS_GEN_II(hpriv) &&
22374677
JG		 2250 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
2251 (retry-- > 0))
2252 goto comreset_retry;
095fec88 2253
da3dbb17
TH		 2254#ifdef DEBUG
2255 {
2256 u32 sstatus, serror, scontrol;
2257
2258 mv_scr_read(ap, SCR_STATUS, &sstatus);
2259 mv_scr_read(ap, SCR_ERROR, &serror);
2260 mv_scr_read(ap, SCR_CONTROL, &scontrol);
2261 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
2262 "SCtrl 0x%08x\n", sstatus, serror, scontrol);
2263 }
2264#endif
31961943 2265
936fd732 2266 if (ata_link_offline(&ap->link)) {
bdd4ddde 2267 *class = ATA_DEV_NONE;
20f733e7
BR		 2268 return;
2269 }
2270
22374677
JG		 2271 /* even after SStatus reflects that device is ready,
2272 * it seems to take a while for link to be fully
2273 * established (and thus Status no longer 0x80/0x7F),
2274 * so we poll a bit for that, here.
2275 */
2276 retry = 20;
2277 while (1) {
2278 u8 drv_stat = ata_check_status(ap);
2279 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
2280 break;
bdd4ddde 2281 msleep(500);
22374677
JG		 2282 if (retry-- <= 0)
2283 break;
bdd4ddde
JG		 2284 if (time_after(jiffies, deadline))
2285 break;
22374677
JG		 2286 }
2287
bdd4ddde
JG		 2288 /* FIXME: if we passed the deadline, the following
2289 * code probably produces an invalid result
2290 */
20f733e7 2291
bdd4ddde 2292 /* finally, read device signature from TF registers */
3f19859e 2293 *class = ata_dev_try_classify(ap->link.device, 1, NULL);
095fec88
JG		 2294
2295 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2296
bdd4ddde 2297 WARN_ON(pp->pp_flags & MV_PP_FLAG_EDMA_EN);
095fec88 2298
bca1c4eb 2299 VPRINTK("EXIT\n");
20f733e7
BR		 2300}
2301
cc0680a5 2302static int mv_prereset(struct ata_link *link, unsigned long deadline)
22374677 2303{
cc0680a5 2304 struct ata_port *ap = link->ap;
bdd4ddde 2305 struct mv_port_priv *pp = ap->private_data;
cc0680a5 2306 struct ata_eh_context *ehc = &link->eh_context;
bdd4ddde 2307 int rc;
0ea9e179 2308
bdd4ddde
JG		 2309 rc = mv_stop_dma(ap);
2310 if (rc)
2311 ehc->i.action |= ATA_EH_HARDRESET;
2312
2313 if (!(pp->pp_flags & MV_PP_FLAG_HAD_A_RESET)) {
2314 pp->pp_flags |= MV_PP_FLAG_HAD_A_RESET;
2315 ehc->i.action |= ATA_EH_HARDRESET;
2316 }
2317
2318 /* if we're about to do hardreset, nothing more to do */
2319 if (ehc->i.action & ATA_EH_HARDRESET)
2320 return 0;
2321
cc0680a5 2322 if (ata_link_online(link))
bdd4ddde
JG		 2323 rc = ata_wait_ready(ap, deadline);
2324 else
2325 rc = -ENODEV;
2326
2327 return rc;
22374677
JG		 2328}
2329
cc0680a5 2330static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2331 unsigned long deadline)
31961943 2332{
cc0680a5 2333 struct ata_port *ap = link->ap;
bdd4ddde 2334 struct mv_host_priv *hpriv = ap->host->private_data;
0d5ff566 2335 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
31961943 2336
bdd4ddde 2337 mv_stop_dma(ap);
31961943 2338
bdd4ddde 2339 mv_channel_reset(hpriv, mmio, ap->port_no);
31961943 2340
bdd4ddde
JG		 2341 mv_phy_reset(ap, class, deadline);
2342
2343 return 0;
2344}
2345
cc0680a5 2346static void mv_postreset(struct ata_link *link, unsigned int *classes)
bdd4ddde 2347{
cc0680a5 2348 struct ata_port *ap = link->ap;
bdd4ddde
JG		 2349 u32 serr;
2350
2351 /* print link status */
cc0680a5 2352 sata_print_link_status(link);
31961943 2353
bdd4ddde 2354 /* clear SError */
cc0680a5
TH		 2355 sata_scr_read(link, SCR_ERROR, &serr);
2356 sata_scr_write_flush(link, SCR_ERROR, serr);
bdd4ddde
JG		 2357
2358 /* bail out if no device is present */
2359 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2360 DPRINTK("EXIT, no device\n");
2361 return;
9b358e30 2362 }
bdd4ddde
JG		 2363
2364 /* set up device control */
2365 iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
2366}
2367
2368static void mv_error_handler(struct ata_port *ap)
2369{
2370 ata_do_eh(ap, mv_prereset, ata_std_softreset,
2371 mv_hardreset, mv_postreset);
2372}
2373
2374static void mv_post_int_cmd(struct ata_queued_cmd *qc)
2375{
2376 mv_stop_dma(qc->ap);
2377}
2378
2379static void mv_eh_freeze(struct ata_port *ap)
2380{
2381 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
2382 unsigned int hc = (ap->port_no > 3) ? 1 : 0;
2383 u32 tmp, mask;
2384 unsigned int shift;
2385
2386 /* FIXME: handle coalescing completion events properly */
2387
2388 shift = ap->port_no * 2;
2389 if (hc > 0)
2390 shift++;
2391
2392 mask = 0x3 << shift;
2393
2394 /* disable assertion of portN err, done events */
2395 tmp = readl(mmio + HC_MAIN_IRQ_MASK_OFS);
2396 writelfl(tmp & ~mask, mmio + HC_MAIN_IRQ_MASK_OFS);
2397}
2398
2399static void mv_eh_thaw(struct ata_port *ap)
2400{
2401 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
2402 unsigned int hc = (ap->port_no > 3) ? 1 : 0;
2403 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2404 void __iomem *port_mmio = mv_ap_base(ap);
2405 u32 tmp, mask, hc_irq_cause;
2406 unsigned int shift, hc_port_no = ap->port_no;
2407
2408 /* FIXME: handle coalescing completion events properly */
2409
2410 shift = ap->port_no * 2;
2411 if (hc > 0) {
2412 shift++;
2413 hc_port_no -= 4;
2414 }
2415
2416 mask = 0x3 << shift;
2417
2418 /* clear EDMA errors on this port */
2419 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2420
2421 /* clear pending irq events */
2422 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
2423 hc_irq_cause &= ~(1 << hc_port_no); /* clear CRPB-done */
2424 hc_irq_cause &= ~(1 << (hc_port_no + 8)); /* clear Device int */
2425 writel(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2426
2427 /* enable assertion of portN err, done events */
2428 tmp = readl(mmio + HC_MAIN_IRQ_MASK_OFS);
2429 writelfl(tmp | mask, mmio + HC_MAIN_IRQ_MASK_OFS);
31961943
BR		 2430}
2431
05b308e1
BR		 2432/**
2433 * mv_port_init - Perform some early initialization on a single port.
2434 * @port: libata data structure storing shadow register addresses
2435 * @port_mmio: base address of the port
2436 *
2437 * Initialize shadow register mmio addresses, clear outstanding
2438 * interrupts on the port, and unmask interrupts for the future
2439 * start of the port.
2440 *
2441 * LOCKING:
2442 * Inherited from caller.
2443 */
31961943 2444static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2445{
0d5ff566 2446 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2447 unsigned serr_ofs;
2448
8b260248 2449 /* PIO related setup
31961943
BR		 2450 */
2451 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2452 port->error_addr =
31961943
BR		 2453 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2454 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2455 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2456 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2457 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2458 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2459 port->status_addr =
31961943
BR		 2460 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2461 /* special case: control/altstatus doesn't have ATA_REG_ address */
2462 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2463
2464 /* unused: */
8d9db2d2 2465 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2466
31961943
BR		 2467 /* Clear any currently outstanding port interrupt conditions */
2468 serr_ofs = mv_scr_offset(SCR_ERROR);
2469 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2470 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2471
646a4da5
ML		 2472 /* unmask all non-transient EDMA error interrupts */
2473 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2474
8b260248 2475 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2476 readl(port_mmio + EDMA_CFG_OFS),
2477 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2478 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2479}
2480
4447d351 2481static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2482{
4447d351
TH		 2483 struct pci_dev *pdev = to_pci_dev(host->dev);
2484 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2485 u32 hp_flags = hpriv->hp_flags;
2486
5796d1c4 2487 switch (board_idx) {
47c2b677
JG		 2488 case chip_5080:
2489 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2490 hp_flags |= MV_HP_GEN_I;
47c2b677 2491
44c10138 2492 switch (pdev->revision) {
47c2b677
JG		 2493 case 0x1:
2494 hp_flags |= MV_HP_ERRATA_50XXB0;
2495 break;
2496 case 0x3:
2497 hp_flags |= MV_HP_ERRATA_50XXB2;
2498 break;
2499 default:
2500 dev_printk(KERN_WARNING, &pdev->dev,
2501 "Applying 50XXB2 workarounds to unknown rev\n");
2502 hp_flags |= MV_HP_ERRATA_50XXB2;
2503 break;
2504 }
2505 break;
2506
bca1c4eb
JG		 2507 case chip_504x:
2508 case chip_508x:
47c2b677 2509 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2510 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2511
44c10138 2512 switch (pdev->revision) {
47c2b677
JG		 2513 case 0x0:
2514 hp_flags |= MV_HP_ERRATA_50XXB0;
2515 break;
2516 case 0x3:
2517 hp_flags |= MV_HP_ERRATA_50XXB2;
2518 break;
2519 default:
2520 dev_printk(KERN_WARNING, &pdev->dev,
2521 "Applying B2 workarounds to unknown rev\n");
2522 hp_flags |= MV_HP_ERRATA_50XXB2;
2523 break;
bca1c4eb
JG		 2524 }
2525 break;
2526
2527 case chip_604x:
2528 case chip_608x:
47c2b677 2529 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2530 hp_flags |= MV_HP_GEN_II;
47c2b677 2531
44c10138 2532 switch (pdev->revision) {
47c2b677
JG		 2533 case 0x7:
2534 hp_flags |= MV_HP_ERRATA_60X1B2;
2535 break;
2536 case 0x9:
2537 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2538 break;
2539 default:
2540 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2541 "Applying B2 workarounds to unknown rev\n");
2542 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2543 break;
2544 }
2545 break;
2546
e4e7b892 2547 case chip_7042:
02a121da 2548 hp_flags |= MV_HP_PCIE;
306b30f7
ML		 2549 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2550 (pdev->device == 0x2300 || pdev->device == 0x2310))
2551 {
4e520033
ML		 2552 /*
2553 * Highpoint RocketRAID PCIe 23xx series cards:
2554 *
2555 * Unconfigured drives are treated as "Legacy"
2556 * by the BIOS, and it overwrites sector 8 with
2557 * a "Lgcy" metadata block prior to Linux boot.
2558 *
2559 * Configured drives (RAID or JBOD) leave sector 8
2560 * alone, but instead overwrite a high numbered
2561 * sector for the RAID metadata. This sector can
2562 * be determined exactly, by truncating the physical
2563 * drive capacity to a nice even GB value.
2564 *
2565 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2566 *
2567 * Warn the user, lest they think we're just buggy.
2568 */
2569 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2570 " BIOS CORRUPTS DATA on all attached drives,"
2571 " regardless of if/how they are configured."
2572 " BEWARE!\n");
2573 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2574 " use sectors 8-9 on \"Legacy\" drives,"
2575 " and avoid the final two gigabytes on"
2576 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2577 }
e4e7b892
JG		 2578 case chip_6042:
2579 hpriv->ops = &mv6xxx_ops;
e4e7b892
JG		 2580 hp_flags |= MV_HP_GEN_IIE;
2581
44c10138 2582 switch (pdev->revision) {
e4e7b892
JG		 2583 case 0x0:
2584 hp_flags |= MV_HP_ERRATA_XX42A0;
2585 break;
2586 case 0x1:
2587 hp_flags |= MV_HP_ERRATA_60X1C0;
2588 break;
2589 default:
2590 dev_printk(KERN_WARNING, &pdev->dev,
2591 "Applying 60X1C0 workarounds to unknown rev\n");
2592 hp_flags |= MV_HP_ERRATA_60X1C0;
2593 break;
2594 }
2595 break;
2596
bca1c4eb 2597 default:
5796d1c4
JG		 2598 dev_printk(KERN_ERR, &pdev->dev,
2599 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 2600 return 1;
2601 }
2602
2603 hpriv->hp_flags = hp_flags;
02a121da
ML		 2604 if (hp_flags & MV_HP_PCIE) {
2605 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
2606 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
2607 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
2608 } else {
2609 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
2610 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
2611 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
2612 }
bca1c4eb
JG		 2613
2614 return 0;
2615}
2616
05b308e1 2617/**
47c2b677 2618 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 2619 * @host: ATA host to initialize
2620 * @board_idx: controller index
05b308e1
BR		 2621 *
2622 * If possible, do an early global reset of the host. Then do
2623 * our port init and clear/unmask all/relevant host interrupts.
2624 *
2625 * LOCKING:
2626 * Inherited from caller.
2627 */
4447d351 2628static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 2629{
2630 int rc = 0, n_hc, port, hc;
4447d351
TH		 2631 struct pci_dev *pdev = to_pci_dev(host->dev);
2632 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
2633 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb 2634
47c2b677
JG		 2635 /* global interrupt mask */
2636 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2637
4447d351 2638 rc = mv_chip_id(host, board_idx);
bca1c4eb
JG		 2639 if (rc)
2640 goto done;
2641
4447d351 2642 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 2643
4447d351 2644 for (port = 0; port < host->n_ports; port++)
47c2b677 2645 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 2646
c9d39130 2647 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 2648 if (rc)
20f733e7 2649 goto done;
20f733e7 2650
522479fb
JG		 2651 hpriv->ops->reset_flash(hpriv, mmio);
2652 hpriv->ops->reset_bus(pdev, mmio);
47c2b677 2653 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 2654
4447d351 2655 for (port = 0; port < host->n_ports; port++) {
ee9ccdf7 2656 if (IS_GEN_II(hpriv)) {
c9d39130
JG		 2657 void __iomem *port_mmio = mv_port_base(mmio, port);
2658
2a47ce06 2659 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
eb46d684
ML		 2660 ifctl |= (1 << 7); /* enable gen2i speed */
2661 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2a47ce06
JG		 2662 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2663 }
2664
c9d39130 2665 hpriv->ops->phy_errata(hpriv, mmio, port);
2a47ce06
JG		 2666 }
2667
4447d351 2668 for (port = 0; port < host->n_ports; port++) {
cbcdd875 2669 struct ata_port *ap = host->ports[port];
2a47ce06 2670 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 2671 unsigned int offset = port_mmio - mmio;
2672
2673 mv_port_init(&ap->ioaddr, port_mmio);
2674
2675 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
2676 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
20f733e7
BR		 2677 }
2678
2679 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 2680 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2681
2682 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2683 "(before clear)=0x%08x\n", hc,
2684 readl(hc_mmio + HC_CFG_OFS),
2685 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2686
2687 /* Clear any currently outstanding hc interrupt conditions */
2688 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 2689 }
2690
31961943 2691 /* Clear any currently outstanding host interrupt conditions */
02a121da 2692 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943
BR		 2693
2694 /* and unmask interrupt generation for host regs */
02a121da 2695 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
fb621e2f 2696
ee9ccdf7 2697 if (IS_GEN_I(hpriv))
fb621e2f
JG		 2698 writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
2699 else
2700 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
20f733e7
BR		 2701
2702 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
8b260248 2703 "PCI int cause/mask=0x%08x/0x%08x\n",
20f733e7
BR		 2704 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2705 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
02a121da
ML		 2706 readl(mmio + hpriv->irq_cause_ofs),
2707 readl(mmio + hpriv->irq_mask_ofs));
bca1c4eb 2708
31961943 2709done:
20f733e7
BR		 2710 return rc;
2711}
2712
05b308e1
BR		 2713/**
2714 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 2715 * @host: ATA host to print info about
05b308e1
BR		 2716 *
2717 * FIXME: complete this.
2718 *
2719 * LOCKING:
2720 * Inherited from caller.
2721 */
4447d351 2722static void mv_print_info(struct ata_host *host)
31961943 2723{
4447d351
TH		 2724 struct pci_dev *pdev = to_pci_dev(host->dev);
2725 struct mv_host_priv *hpriv = host->private_data;
44c10138 2726 u8 scc;
c1e4fe71 2727 const char *scc_s, *gen;
31961943
BR		 2728
2729 /* Use this to determine the HW stepping of the chip so we know
2730 * what errata to workaround
2731 */
31961943
BR		 2732 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2733 if (scc == 0)
2734 scc_s = "SCSI";
2735 else if (scc == 0x01)
2736 scc_s = "RAID";
2737 else
c1e4fe71
JG		 2738 scc_s = "?";
2739
2740 if (IS_GEN_I(hpriv))
2741 gen = "I";
2742 else if (IS_GEN_II(hpriv))
2743 gen = "II";
2744 else if (IS_GEN_IIE(hpriv))
2745 gen = "IIE";
2746 else
2747 gen = "?";
31961943 2748
a9524a76 2749 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 2750 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
2751 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 2752 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2753}
2754
05b308e1
BR		 2755/**
2756 * mv_init_one - handle a positive probe of a Marvell host
2757 * @pdev: PCI device found
2758 * @ent: PCI device ID entry for the matched host
2759 *
2760 * LOCKING:
2761 * Inherited from caller.
2762 */
20f733e7
BR		 2763static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2764{
2dcb407e 2765 static int printed_version;
20f733e7 2766 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 2767 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
2768 struct ata_host *host;
2769 struct mv_host_priv *hpriv;
2770 int n_ports, rc;
20f733e7 2771
a9524a76
JG		 2772 if (!printed_version++)
2773 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 2774
4447d351
TH		 2775 /* allocate host */
2776 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
2777
2778 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2779 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2780 if (!host || !hpriv)
2781 return -ENOMEM;
2782 host->private_data = hpriv;
2783
2784 /* acquire resources */
24dc5f33
TH		 2785 rc = pcim_enable_device(pdev);
2786 if (rc)
20f733e7 2787 return rc;
20f733e7 2788
0d5ff566
TH		 2789 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2790 if (rc == -EBUSY)
24dc5f33 2791 pcim_pin_device(pdev);
0d5ff566 2792 if (rc)
24dc5f33 2793 return rc;
4447d351 2794 host->iomap = pcim_iomap_table(pdev);
20f733e7 2795
d88184fb
JG		 2796 rc = pci_go_64(pdev);
2797 if (rc)
2798 return rc;
2799
20f733e7 2800 /* initialize adapter */
4447d351 2801 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 2802 if (rc)
2803 return rc;
20f733e7 2804
31961943 2805 /* Enable interrupts */
6a59dcf8 2806 if (msi && pci_enable_msi(pdev))
31961943 2807 pci_intx(pdev, 1);
20f733e7 2808
31961943 2809 mv_dump_pci_cfg(pdev, 0x68);
4447d351 2810 mv_print_info(host);
20f733e7 2811
4447d351 2812 pci_set_master(pdev);
ea8b4db9 2813 pci_try_set_mwi(pdev);
4447d351 2814 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 2815 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7
BR		 2816}
2817
2818static int __init mv_init(void)
2819{
b7887196 2820 return pci_register_driver(&mv_pci_driver);
20f733e7
BR		 2821}
2822
2823static void __exit mv_exit(void)
2824{
2825 pci_unregister_driver(&mv_pci_driver);
2826}
2827
2828MODULE_AUTHOR("Brett Russ");
2829MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2830MODULE_LICENSE("GPL");
2831MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2832MODULE_VERSION(DRV_VERSION);
2833
ddef9bb3
JG		 2834module_param(msi, int, 0444);
2835MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2836
20f733e7
BR		 2837module_init(mv_init);
2838module_exit(mv_exit);
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