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sata_mv errata workaround for sata25 part 1
[mirror_ubuntu-artful-kernel.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
4a05e209 54
20f733e7
BR		 55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
8d8b6004 62#include <linux/dmapool.h>
20f733e7 63#include <linux/dma-mapping.h>
a9524a76 64#include <linux/device.h>
f351b2d6
SB		 65#include <linux/platform_device.h>
66#include <linux/ata_platform.h>
15a32632 67#include <linux/mbus.h>
20f733e7 68#include <scsi/scsi_host.h>
193515d5 69#include <scsi/scsi_cmnd.h>
6c08772e 70#include <scsi/scsi_device.h>
20f733e7 71#include <linux/libata.h>
20f733e7
BR		 72
73#define DRV_NAME "sata_mv"
1fd2e1c2 74#define DRV_VERSION "1.20"
20f733e7
BR		 75
76enum {
77 /* BAR's are enumerated in terms of pci_resource_start() terms */
78 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
79 MV_IO_BAR = 2, /* offset 0x18: IO space */
80 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
81
82 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
83 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
84
85 MV_PCI_REG_BASE = 0,
86 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 87 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
88 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
89 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
90 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
92
20f733e7 93 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 94 MV_FLASH_CTL_OFS = 0x1046c,
95 MV_GPIO_PORT_CTL_OFS = 0x104f0,
96 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 97
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
101 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
102
31961943
BR		 103 MV_MAX_Q_DEPTH = 32,
104 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
105
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
109 */
110 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
111 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 112 MV_MAX_SG_CT = 256,
31961943 113 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 114
352fab70 115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 116 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 117 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 120
121 /* Host Flags */
122 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
123 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 124 /* SoC integrated controllers, no PCI interface */
e12bef50 125 MV_FLAG_SOC = (1 << 28),
7bb3c529 126
c5d3e45a 127 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 128 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
129 ATA_FLAG_PIO_POLLING,
47c2b677 130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 131
31961943
BR		 132 CRQB_FLAG_READ = (1 << 0),
133 CRQB_TAG_SHIFT = 1,
c5d3e45a 134 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 135 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 136 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 137 CRQB_CMD_ADDR_SHIFT = 8,
138 CRQB_CMD_CS = (0x2 << 11),
139 CRQB_CMD_LAST = (1 << 15),
140
141 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 142 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 144
145 EPRD_FLAG_END_OF_TBL = (1 << 31),
146
20f733e7
BR		 147 /* PCI interface registers */
148
31961943 149 PCI_COMMAND_OFS = 0xc00,
8e7decdb 150 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 151
20f733e7
BR		 152 PCI_MAIN_CMD_STS_OFS = 0xd30,
153 STOP_PCI_MASTER = (1 << 2),
154 PCI_MASTER_EMPTY = (1 << 3),
155 GLOB_SFT_RST = (1 << 4),
156
8e7decdb
ML		 157 MV_PCI_MODE_OFS = 0xd00,
158 MV_PCI_MODE_MASK = 0x30,
159
522479fb
JG		 160 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
161 MV_PCI_DISC_TIMER = 0xd04,
162 MV_PCI_MSI_TRIGGER = 0xc38,
163 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 164 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 165 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
166 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
167 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
168 MV_PCI_ERR_COMMAND = 0x1d50,
169
02a121da
ML		 170 PCI_IRQ_CAUSE_OFS = 0x1d58,
171 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 172 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
173
02a121da
ML		 174 PCIE_IRQ_CAUSE_OFS = 0x1900,
175 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 176 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 177
7368f919
ML		 178 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
179 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
180 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
181 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
182 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 183 ERR_IRQ = (1 << 0), /* shift by port # */
184 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 185 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
186 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
187 PCI_ERR = (1 << 18),
188 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
189 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 190 PORTS_0_3_COAL_DONE = (1 << 8),
191 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 192 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
193 GPIO_INT = (1 << 22),
194 SELF_INT = (1 << 23),
195 TWSI_INT = (1 << 24),
196 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 197 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 198 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
8b260248 199 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
f9f7fe01 200 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
20f733e7
BR		 201 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
202 HC_MAIN_RSVD),
fb621e2f
JG		 203 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
204 HC_MAIN_RSVD_5),
f351b2d6 205 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
20f733e7
BR		 206
207 /* SATAHC registers */
208 HC_CFG_OFS = 0,
209
210 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 211 DMA_IRQ = (1 << 0), /* shift by port # */
212 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 213 DEV_IRQ = (1 << 8), /* shift by port # */
214
215 /* Shadow block registers */
31961943
BR		 216 SHD_BLK_OFS = 0x100,
217 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 218
219 /* SATA registers */
220 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
221 SATA_ACTIVE_OFS = 0x350,
0c58912e 222 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
17c5aab5 223
e12bef50 224 LTMODE_OFS = 0x30c,
17c5aab5
ML		 225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
226
47c2b677 227 PHY_MODE3 = 0x310,
bca1c4eb
JG		 228 PHY_MODE4 = 0x314,
229 PHY_MODE2 = 0x330,
e12bef50 230 SATA_IFCTL_OFS = 0x344,
8e7decdb 231 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 234
8e7decdb
ML		 235 FISCFG_OFS = 0x360,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 238
c9d39130 239 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 243
244 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 245
246 /* Port registers */
247 EDMA_CFG_OFS = 0,
0c58912e
ML		 248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 255
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 272
6c1153e0 273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
278
6c1153e0 279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 280
6c1153e0 281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
287
6c1153e0 288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 289
6c1153e0 290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 293
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 297 EDMA_ERR_LNK_CTRL_TX,
646a4da5 298
bdd4ddde
JG		 299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
300 EDMA_ERR_PRD_PAR |
301 EDMA_ERR_DEV_DCON |
302 EDMA_ERR_DEV_CON |
303 EDMA_ERR_SERR |
304 EDMA_ERR_SELF_DIS |
6c1153e0 305 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 306 EDMA_ERR_CRPB_PAR |
307 EDMA_ERR_INTRL_PAR |
308 EDMA_ERR_IORDY |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
e12bef50 313
bdd4ddde
JG		 314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
315 EDMA_ERR_PRD_PAR |
316 EDMA_ERR_DEV_DCON |
317 EDMA_ERR_DEV_CON |
318 EDMA_ERR_OVERRUN_5 |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
6c1153e0 321 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 322 EDMA_ERR_CRPB_PAR |
323 EDMA_ERR_INTRL_PAR |
324 EDMA_ERR_IORDY,
20f733e7 325
31961943
BR		 326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 328
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
331
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 335 EDMA_RSP_Q_PTR_SHIFT = 3,
336
0ea9e179
JG		 337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
341
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 345
8e7decdb
ML		 346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
348
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 350
352fab70
ML		 351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
352
31961943
BR		 353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892 359 MV_HP_ERRATA_XX42A0 = (1 << 5),
0ea9e179
JG		 360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
20f733e7 365
31961943 366 /* Port private flags (pp_flags) */
0ea9e179 367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
20f733e7
BR		 369};
370
ee9ccdf7
JG		 371#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
372#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 373#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 374#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
7bb3c529 375#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
bca1c4eb 376
15a32632
LB		 377#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
378#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
379
095fec88 380enum {
baf14aa1
JG		 381 /* DMA boundary 0xffff is required by the s/g splitting
382 * we need on /length/ in mv_fill-sg().
383 */
384 MV_DMA_BOUNDARY = 0xffffU,
095fec88 385
0ea9e179
JG		 386 /* mask of register bits containing lower 32 bits
387 * of EDMA request queue DMA address
388 */
095fec88
JG		 389 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
390
0ea9e179 391 /* ditto, for response queue */
095fec88
JG		 392 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
393};
394
522479fb
JG		 395enum chip_type {
396 chip_504x,
397 chip_508x,
398 chip_5080,
399 chip_604x,
400 chip_608x,
e4e7b892
JG		 401 chip_6042,
402 chip_7042,
f351b2d6 403 chip_soc,
522479fb
JG		 404};
405
31961943
BR		 406/* Command ReQuest Block: 32B */
407struct mv_crqb {
e1469874
ML		 408 __le32 sg_addr;
409 __le32 sg_addr_hi;
410 __le16 ctrl_flags;
411 __le16 ata_cmd[11];
31961943 412};
20f733e7 413
e4e7b892 414struct mv_crqb_iie {
e1469874
ML		 415 __le32 addr;
416 __le32 addr_hi;
417 __le32 flags;
418 __le32 len;
419 __le32 ata_cmd[4];
e4e7b892
JG		 420};
421
31961943
BR		 422/* Command ResPonse Block: 8B */
423struct mv_crpb {
e1469874
ML		 424 __le16 id;
425 __le16 flags;
426 __le32 tmstmp;
20f733e7
BR		 427};
428
31961943
BR		 429/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
430struct mv_sg {
e1469874
ML		 431 __le32 addr;
432 __le32 flags_size;
433 __le32 addr_hi;
434 __le32 reserved;
31961943 435};
20f733e7 436
31961943
BR		 437struct mv_port_priv {
438 struct mv_crqb *crqb;
439 dma_addr_t crqb_dma;
440 struct mv_crpb *crpb;
441 dma_addr_t crpb_dma;
eb73d558
ML		 442 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
443 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 444
445 unsigned int req_idx;
446 unsigned int resp_idx;
447
31961943
BR		 448 u32 pp_flags;
449};
450
bca1c4eb
JG		 451struct mv_port_signal {
452 u32 amps;
453 u32 pre;
454};
455
02a121da
ML		 456struct mv_host_priv {
457 u32 hp_flags;
458 struct mv_port_signal signal[8];
459 const struct mv_hw_ops *ops;
f351b2d6
SB		 460 int n_ports;
461 void __iomem *base;
7368f919
ML		 462 void __iomem *main_irq_cause_addr;
463 void __iomem *main_irq_mask_addr;
02a121da
ML		 464 u32 irq_cause_ofs;
465 u32 irq_mask_ofs;
466 u32 unmask_all_irqs;
da2fa9ba
ML		 467 /*
468 * These consistent DMA memory pools give us guaranteed
469 * alignment for hardware-accessed data structures,
470 * and less memory waste in accomplishing the alignment.
471 */
472 struct dma_pool *crqb_pool;
473 struct dma_pool *crpb_pool;
474 struct dma_pool *sg_tbl_pool;
02a121da
ML		 475};
476
47c2b677 477struct mv_hw_ops {
2a47ce06
JG		 478 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
479 unsigned int port);
47c2b677
JG		 480 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
481 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
482 void __iomem *mmio);
c9d39130
JG		 483 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
484 unsigned int n_hc);
522479fb 485 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 486 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 487};
488
da3dbb17
TH		 489static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
490static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
491static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
492static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 493static int mv_port_start(struct ata_port *ap);
494static void mv_port_stop(struct ata_port *ap);
3e4a1391 495static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 496static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 497static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 498static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 499static int mv_hardreset(struct ata_link *link, unsigned int *class,
500 unsigned long deadline);
bdd4ddde
JG		 501static void mv_eh_freeze(struct ata_port *ap);
502static void mv_eh_thaw(struct ata_port *ap);
f273827e 503static void mv6_dev_config(struct ata_device *dev);
20f733e7 504
2a47ce06
JG		 505static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
506 unsigned int port);
47c2b677
JG		 507static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
508static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
509 void __iomem *mmio);
c9d39130
JG		 510static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
511 unsigned int n_hc);
522479fb 512static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 513static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 514
2a47ce06
JG		 515static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
516 unsigned int port);
47c2b677
JG		 517static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
518static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
519 void __iomem *mmio);
c9d39130
JG		 520static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
521 unsigned int n_hc);
522479fb 522static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 523static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
524 void __iomem *mmio);
525static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
526 void __iomem *mmio);
527static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
528 void __iomem *mmio, unsigned int n_hc);
529static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
530 void __iomem *mmio);
531static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 532static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 533static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 534 unsigned int port_no);
e12bef50 535static int mv_stop_edma(struct ata_port *ap);
b562468c 536static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 537static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 538
e49856d8
ML		 539static void mv_pmp_select(struct ata_port *ap, int pmp);
540static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
541 unsigned long deadline);
542static int mv_softreset(struct ata_link *link, unsigned int *class,
543 unsigned long deadline);
47c2b677 544
eb73d558
ML		 545/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
546 * because we have to allow room for worst case splitting of
547 * PRDs for 64K boundaries in mv_fill_sg().
548 */
c5d3e45a 549static struct scsi_host_template mv5_sht = {
68d1d07b 550 ATA_BASE_SHT(DRV_NAME),
baf14aa1 551 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 552 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 553};
554
555static struct scsi_host_template mv6_sht = {
68d1d07b 556 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 557 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 558 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 559 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 560};
561
029cfd6b
TH		 562static struct ata_port_operations mv5_ops = {
563 .inherits = &ata_sff_port_ops,
c9d39130 564
3e4a1391 565 .qc_defer = mv_qc_defer,
c9d39130
JG		 566 .qc_prep = mv_qc_prep,
567 .qc_issue = mv_qc_issue,
c9d39130 568
bdd4ddde
JG		 569 .freeze = mv_eh_freeze,
570 .thaw = mv_eh_thaw,
a1efdaba 571 .hardreset = mv_hardreset,
a1efdaba 572 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 573 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 574
c9d39130
JG		 575 .scr_read = mv5_scr_read,
576 .scr_write = mv5_scr_write,
577
578 .port_start = mv_port_start,
579 .port_stop = mv_port_stop,
c9d39130
JG		 580};
581
029cfd6b
TH		 582static struct ata_port_operations mv6_ops = {
583 .inherits = &mv5_ops,
f273827e 584 .dev_config = mv6_dev_config,
20f733e7
BR		 585 .scr_read = mv_scr_read,
586 .scr_write = mv_scr_write,
587
e49856d8
ML		 588 .pmp_hardreset = mv_pmp_hardreset,
589 .pmp_softreset = mv_softreset,
590 .softreset = mv_softreset,
591 .error_handler = sata_pmp_error_handler,
20f733e7
BR		 592};
593
029cfd6b
TH		 594static struct ata_port_operations mv_iie_ops = {
595 .inherits = &mv6_ops,
596 .dev_config = ATA_OP_NULL,
e4e7b892 597 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 598};
599
98ac62de 600static const struct ata_port_info mv_port_info[] = {
20f733e7 601 { /* chip_504x */
cca3974e 602 .flags = MV_COMMON_FLAGS,
31961943 603 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 604 .udma_mask = ATA_UDMA6,
c9d39130 605 .port_ops = &mv5_ops,
20f733e7
BR		 606 },
607 { /* chip_508x */
c5d3e45a 608 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 609 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 610 .udma_mask = ATA_UDMA6,
c9d39130 611 .port_ops = &mv5_ops,
20f733e7 612 },
47c2b677 613 { /* chip_5080 */
c5d3e45a 614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 615 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 616 .udma_mask = ATA_UDMA6,
c9d39130 617 .port_ops = &mv5_ops,
47c2b677 618 },
20f733e7 619 { /* chip_604x */
138bfdd0 620 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 621 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 622 ATA_FLAG_NCQ,
31961943 623 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 624 .udma_mask = ATA_UDMA6,
c9d39130 625 .port_ops = &mv6_ops,
20f733e7
BR		 626 },
627 { /* chip_608x */
c5d3e45a 628 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 629 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 630 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 631 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 632 .udma_mask = ATA_UDMA6,
c9d39130 633 .port_ops = &mv6_ops,
20f733e7 634 },
e4e7b892 635 { /* chip_6042 */
138bfdd0 636 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 637 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 638 ATA_FLAG_NCQ,
e4e7b892 639 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 640 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 641 .port_ops = &mv_iie_ops,
642 },
643 { /* chip_7042 */
138bfdd0 644 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 645 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 646 ATA_FLAG_NCQ,
e4e7b892 647 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 648 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 649 .port_ops = &mv_iie_ops,
650 },
f351b2d6 651 { /* chip_soc */
02c1f32f 652 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 653 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
02c1f32f 654 ATA_FLAG_NCQ | MV_FLAG_SOC,
17c5aab5
ML		 655 .pio_mask = 0x1f, /* pio0-4 */
656 .udma_mask = ATA_UDMA6,
657 .port_ops = &mv_iie_ops,
f351b2d6 658 },
20f733e7
BR		 659};
660
3b7d697d 661static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 662 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
665 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 666 /* RocketRAID 1740/174x have different identifiers */
667 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
668 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 669
670 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
671 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
673 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
674 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
675
676 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
677
d9f9c6bc
FA		 678 /* Adaptec 1430SA */
679 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
680
02a121da 681 /* Marvell 7042 support */
6a3d586d
MT		 682 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
683
02a121da
ML		 684 /* Highpoint RocketRAID PCIe series */
685 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
686 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
687
2d2744fc 688 { } /* terminate list */
20f733e7
BR		 689};
690
47c2b677
JG		 691static const struct mv_hw_ops mv5xxx_ops = {
692 .phy_errata = mv5_phy_errata,
693 .enable_leds = mv5_enable_leds,
694 .read_preamp = mv5_read_preamp,
695 .reset_hc = mv5_reset_hc,
522479fb
JG		 696 .reset_flash = mv5_reset_flash,
697 .reset_bus = mv5_reset_bus,
47c2b677
JG		 698};
699
700static const struct mv_hw_ops mv6xxx_ops = {
701 .phy_errata = mv6_phy_errata,
702 .enable_leds = mv6_enable_leds,
703 .read_preamp = mv6_read_preamp,
704 .reset_hc = mv6_reset_hc,
522479fb
JG		 705 .reset_flash = mv6_reset_flash,
706 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 707};
708
f351b2d6
SB		 709static const struct mv_hw_ops mv_soc_ops = {
710 .phy_errata = mv6_phy_errata,
711 .enable_leds = mv_soc_enable_leds,
712 .read_preamp = mv_soc_read_preamp,
713 .reset_hc = mv_soc_reset_hc,
714 .reset_flash = mv_soc_reset_flash,
715 .reset_bus = mv_soc_reset_bus,
716};
717
20f733e7
BR		 718/*
719 * Functions
720 */
721
722static inline void writelfl(unsigned long data, void __iomem *addr)
723{
724 writel(data, addr);
725 (void) readl(addr); /* flush to avoid PCI posted write */
726}
727
c9d39130
JG		 728static inline unsigned int mv_hc_from_port(unsigned int port)
729{
730 return port >> MV_PORT_HC_SHIFT;
731}
732
733static inline unsigned int mv_hardport_from_port(unsigned int port)
734{
735 return port & MV_PORT_MASK;
736}
737
1cfd19ae
ML		 738/*
739 * Consolidate some rather tricky bit shift calculations.
740 * This is hot-path stuff, so not a function.
741 * Simple code, with two return values, so macro rather than inline.
742 *
743 * port is the sole input, in range 0..7.
7368f919
ML		 744 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
745 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 746 *
747 * Note that port and hardport may be the same variable in some cases.
748 */
749#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
750{ \
751 shift = mv_hc_from_port(port) * HC_SHIFT; \
752 hardport = mv_hardport_from_port(port); \
753 shift += hardport * 2; \
754}
755
352fab70
ML		 756static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
757{
758 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
759}
760
c9d39130
JG		 761static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
762 unsigned int port)
763{
764 return mv_hc_base(base, mv_hc_from_port(port));
765}
766
20f733e7
BR		 767static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
768{
c9d39130 769 return mv_hc_base_from_port(base, port) +
8b260248 770 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 771 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 772}
773
e12bef50
ML		 774static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
775{
776 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
777 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
778
779 return hc_mmio + ofs;
780}
781
f351b2d6
SB		 782static inline void __iomem *mv_host_base(struct ata_host *host)
783{
784 struct mv_host_priv *hpriv = host->private_data;
785 return hpriv->base;
786}
787
20f733e7
BR		 788static inline void __iomem *mv_ap_base(struct ata_port *ap)
789{
f351b2d6 790 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 791}
792
cca3974e 793static inline int mv_get_hc_count(unsigned long port_flags)
31961943 794{
cca3974e 795 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 796}
797
c5d3e45a
JG		 798static void mv_set_edma_ptrs(void __iomem *port_mmio,
799 struct mv_host_priv *hpriv,
800 struct mv_port_priv *pp)
801{
bdd4ddde
JG		 802 u32 index;
803
c5d3e45a
JG		 804 /*
805 * initialize request queue
806 */
fcfb1f77
ML		 807 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
808 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 809
c5d3e45a
JG		 810 WARN_ON(pp->crqb_dma & 0x3ff);
811 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 812 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a
JG		 813 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
814
815 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 816 writelfl((pp->crqb_dma & 0xffffffff) | index,
c5d3e45a
JG		 817 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
818 else
bdd4ddde 819 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 820
821 /*
822 * initialize response queue
823 */
fcfb1f77
ML		 824 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
825 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 826
c5d3e45a
JG		 827 WARN_ON(pp->crpb_dma & 0xff);
828 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
829
830 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 831 writelfl((pp->crpb_dma & 0xffffffff) | index,
c5d3e45a
JG		 832 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
833 else
bdd4ddde 834 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
c5d3e45a 835
bdd4ddde 836 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 837 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 838}
839
05b308e1
BR		 840/**
841 * mv_start_dma - Enable eDMA engine
842 * @base: port base address
843 * @pp: port private data
844 *
beec7dbc
TH		 845 * Verify the local cache of the eDMA state is accurate with a
846 * WARN_ON.
05b308e1
BR		 847 *
848 * LOCKING:
849 * Inherited from caller.
850 */
0c58912e 851static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 852 struct mv_port_priv *pp, u8 protocol)
20f733e7 853{
72109168
ML		 854 int want_ncq = (protocol == ATA_PROT_NCQ);
855
856 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
857 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
858 if (want_ncq != using_ncq)
b562468c 859 mv_stop_edma(ap);
72109168 860 }
c5d3e45a 861 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 862 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 863 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 864 void __iomem *hc_mmio = mv_hc_base_from_port(
352fab70 865 mv_host_base(ap->host), hardport);
0c58912e
ML		 866 u32 hc_irq_cause, ipending;
867
bdd4ddde 868 /* clear EDMA event indicators, if any */
f630d562 869 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 870
0c58912e
ML		 871 /* clear EDMA interrupt indicator, if any */
872 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
352fab70 873 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
0c58912e
ML		 874 if (hc_irq_cause & ipending) {
875 writelfl(hc_irq_cause & ~ipending,
876 hc_mmio + HC_IRQ_CAUSE_OFS);
877 }
878
e12bef50 879 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 880
881 /* clear FIS IRQ Cause */
882 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
883
f630d562 884 mv_set_edma_ptrs(port_mmio, hpriv, pp);
bdd4ddde 885
f630d562 886 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 887 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
888 }
20f733e7
BR		 889}
890
9b2c4e0b
ML		 891static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
892{
893 void __iomem *port_mmio = mv_ap_base(ap);
894 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
895 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
896 int i;
897
898 /*
899 * Wait for the EDMA engine to finish transactions in progress.
900 */
901 for (i = 0; i < timeout; ++i) {
902 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
903 if ((edma_stat & empty_idle) == empty_idle)
904 break;
905 udelay(per_loop);
906 }
907 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
908}
909
05b308e1 910/**
e12bef50 911 * mv_stop_edma_engine - Disable eDMA engine
b562468c 912 * @port_mmio: io base address
05b308e1
BR		 913 *
914 * LOCKING:
915 * Inherited from caller.
916 */
b562468c 917static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 918{
b562468c 919 int i;
31961943 920
b562468c
ML		 921 /* Disable eDMA. The disable bit auto clears. */
922 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 923
b562468c
ML		 924 /* Wait for the chip to confirm eDMA is off. */
925 for (i = 10000; i > 0; i--) {
926 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 927 if (!(reg & EDMA_EN))
b562468c
ML		 928 return 0;
929 udelay(10);
31961943 930 }
b562468c 931 return -EIO;
20f733e7
BR		 932}
933
e12bef50 934static int mv_stop_edma(struct ata_port *ap)
0ea9e179 935{
b562468c
ML		 936 void __iomem *port_mmio = mv_ap_base(ap);
937 struct mv_port_priv *pp = ap->private_data;
0ea9e179 938
b562468c
ML		 939 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
940 return 0;
941 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 942 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 943 if (mv_stop_edma_engine(port_mmio)) {
944 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
945 return -EIO;
946 }
947 return 0;
0ea9e179
JG		 948}
949
8a70f8dc 950#ifdef ATA_DEBUG
31961943 951static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 952{
31961943
BR		 953 int b, w;
954 for (b = 0; b < bytes; ) {
955 DPRINTK("%p: ", start + b);
956 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 957 printk("%08x ", readl(start + b));
31961943
BR		 958 b += sizeof(u32);
959 }
960 printk("\n");
961 }
31961943 962}
8a70f8dc
JG		 963#endif
964
31961943
BR		 965static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
966{
967#ifdef ATA_DEBUG
968 int b, w;
969 u32 dw;
970 for (b = 0; b < bytes; ) {
971 DPRINTK("%02x: ", b);
972 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 973 (void) pci_read_config_dword(pdev, b, &dw);
974 printk("%08x ", dw);
31961943
BR		 975 b += sizeof(u32);
976 }
977 printk("\n");
978 }
979#endif
980}
981static void mv_dump_all_regs(void __iomem *mmio_base, int port,
982 struct pci_dev *pdev)
983{
984#ifdef ATA_DEBUG
8b260248 985 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 986 port >> MV_PORT_HC_SHIFT);
987 void __iomem *port_base;
988 int start_port, num_ports, p, start_hc, num_hcs, hc;
989
990 if (0 > port) {
991 start_hc = start_port = 0;
992 num_ports = 8; /* shld be benign for 4 port devs */
993 num_hcs = 2;
994 } else {
995 start_hc = port >> MV_PORT_HC_SHIFT;
996 start_port = port;
997 num_ports = num_hcs = 1;
998 }
8b260248 999 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1000 num_ports > 1 ? num_ports - 1 : start_port);
1001
1002 if (NULL != pdev) {
1003 DPRINTK("PCI config space regs:\n");
1004 mv_dump_pci_cfg(pdev, 0x68);
1005 }
1006 DPRINTK("PCI regs:\n");
1007 mv_dump_mem(mmio_base+0xc00, 0x3c);
1008 mv_dump_mem(mmio_base+0xd00, 0x34);
1009 mv_dump_mem(mmio_base+0xf00, 0x4);
1010 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1011 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1012 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1013 DPRINTK("HC regs (HC %i):\n", hc);
1014 mv_dump_mem(hc_base, 0x1c);
1015 }
1016 for (p = start_port; p < start_port + num_ports; p++) {
1017 port_base = mv_port_base(mmio_base, p);
2dcb407e 1018 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1019 mv_dump_mem(port_base, 0x54);
2dcb407e 1020 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1021 mv_dump_mem(port_base+0x300, 0x60);
1022 }
1023#endif
20f733e7
BR		 1024}
1025
1026static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1027{
1028 unsigned int ofs;
1029
1030 switch (sc_reg_in) {
1031 case SCR_STATUS:
1032 case SCR_CONTROL:
1033 case SCR_ERROR:
1034 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1035 break;
1036 case SCR_ACTIVE:
1037 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1038 break;
1039 default:
1040 ofs = 0xffffffffU;
1041 break;
1042 }
1043 return ofs;
1044}
1045
da3dbb17 1046static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1047{
1048 unsigned int ofs = mv_scr_offset(sc_reg_in);
1049
da3dbb17
TH		 1050 if (ofs != 0xffffffffU) {
1051 *val = readl(mv_ap_base(ap) + ofs);
1052 return 0;
1053 } else
1054 return -EINVAL;
20f733e7
BR		 1055}
1056
da3dbb17 1057static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1058{
1059 unsigned int ofs = mv_scr_offset(sc_reg_in);
1060
da3dbb17 1061 if (ofs != 0xffffffffU) {
20f733e7 1062 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1063 return 0;
1064 } else
1065 return -EINVAL;
20f733e7
BR		 1066}
1067
f273827e
ML		 1068static void mv6_dev_config(struct ata_device *adev)
1069{
1070 /*
e49856d8
ML		 1071 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1072 *
1073 * Gen-II does not support NCQ over a port multiplier
1074 * (no FIS-based switching).
1075 *
f273827e
ML		 1076 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1077 * See mv_qc_prep() for more info.
1078 */
e49856d8 1079 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1080 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1081 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1082 ata_dev_printk(adev, KERN_INFO,
1083 "NCQ disabled for command-based switching\n");
1084 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1085 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1086 ata_dev_printk(adev, KERN_INFO,
1087 "max_sectors limited to %u for NCQ\n",
1088 adev->max_sectors);
1089 }
e49856d8 1090 }
f273827e
ML		 1091}
1092
3e4a1391
ML		 1093static int mv_qc_defer(struct ata_queued_cmd *qc)
1094{
1095 struct ata_link *link = qc->dev->link;
1096 struct ata_port *ap = link->ap;
1097 struct mv_port_priv *pp = ap->private_data;
1098
1099 /*
1100 * If the port is completely idle, then allow the new qc.
1101 */
1102 if (ap->nr_active_links == 0)
1103 return 0;
1104
1105 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1106 /*
1107 * The port is operating in host queuing mode (EDMA).
1108 * It can accomodate a new qc if the qc protocol
1109 * is compatible with the current host queue mode.
1110 */
1111 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1112 /*
1113 * The host queue (EDMA) is in NCQ mode.
1114 * If the new qc is also an NCQ command,
1115 * then allow the new qc.
1116 */
1117 if (qc->tf.protocol == ATA_PROT_NCQ)
1118 return 0;
1119 } else {
1120 /*
1121 * The host queue (EDMA) is in non-NCQ, DMA mode.
1122 * If the new qc is also a non-NCQ, DMA command,
1123 * then allow the new qc.
1124 */
1125 if (qc->tf.protocol == ATA_PROT_DMA)
1126 return 0;
1127 }
1128 }
1129 return ATA_DEFER_PORT;
1130}
1131
e49856d8
ML		 1132static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs)
1133{
8e7decdb 1134 u32 old_fiscfg, new_fiscfg, old_ltmode, new_ltmode;
e49856d8
ML		 1135 /*
1136 * Various bit settings required for operation
1137 * in FIS-based switching (fbs) mode on GenIIe:
1138 */
8e7decdb 1139 old_fiscfg = readl(port_mmio + FISCFG_OFS);
e49856d8
ML		 1140 old_ltmode = readl(port_mmio + LTMODE_OFS);
1141 if (enable_fbs) {
8e7decdb 1142 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
e49856d8
ML		 1143 new_ltmode = old_ltmode | LTMODE_BIT8;
1144 } else { /* disable fbs */
8e7decdb 1145 new_fiscfg = old_fiscfg & ~FISCFG_SINGLE_SYNC;
e49856d8
ML		 1146 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1147 }
8e7decdb
ML		 1148 if (new_fiscfg != old_fiscfg)
1149 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1150 if (new_ltmode != old_ltmode)
1151 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
f273827e
ML		 1152}
1153
dd2890f6
ML		 1154static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1155{
1156 struct mv_host_priv *hpriv = ap->host->private_data;
1157 u32 old, new;
1158
1159 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1160 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1161 if (want_ncq)
1162 new = old | (1 << 22);
1163 else
1164 new = old & ~(1 << 22);
1165 if (new != old)
1166 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1167}
1168
e12bef50 1169static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1170{
0c58912e 1171 u32 cfg;
e12bef50
ML		 1172 struct mv_port_priv *pp = ap->private_data;
1173 struct mv_host_priv *hpriv = ap->host->private_data;
1174 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1175
1176 /* set up non-NCQ EDMA configuration */
0c58912e 1177 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
e4e7b892 1178
0c58912e 1179 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1180 cfg |= (1 << 8); /* enab config burst size mask */
1181
dd2890f6 1182 else if (IS_GEN_II(hpriv)) {
e4e7b892 1183 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1184 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1185
dd2890f6 1186 } else if (IS_GEN_IIE(hpriv)) {
e728eabe
JG		 1187 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1188 cfg |= (1 << 22); /* enab 4-entry host queue cache */
616d4a98
ML		 1189 if (HAS_PCI(ap->host))
1190 cfg |= (1 << 18); /* enab early completion */
1191 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1192 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e49856d8
ML		 1193
1194 if (want_ncq && sata_pmp_attached(ap)) {
1195 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1196 mv_config_fbs(port_mmio, 1);
1197 } else {
1198 mv_config_fbs(port_mmio, 0);
1199 }
e4e7b892
JG		 1200 }
1201
72109168
ML		 1202 if (want_ncq) {
1203 cfg |= EDMA_CFG_NCQ;
1204 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1205 } else
1206 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1207
e4e7b892
JG		 1208 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1209}
1210
da2fa9ba
ML		 1211static void mv_port_free_dma_mem(struct ata_port *ap)
1212{
1213 struct mv_host_priv *hpriv = ap->host->private_data;
1214 struct mv_port_priv *pp = ap->private_data;
eb73d558 1215 int tag;
da2fa9ba
ML		 1216
1217 if (pp->crqb) {
1218 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1219 pp->crqb = NULL;
1220 }
1221 if (pp->crpb) {
1222 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1223 pp->crpb = NULL;
1224 }
eb73d558
ML		 1225 /*
1226 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1227 * For later hardware, we have one unique sg_tbl per NCQ tag.
1228 */
1229 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1230 if (pp->sg_tbl[tag]) {
1231 if (tag == 0 || !IS_GEN_I(hpriv))
1232 dma_pool_free(hpriv->sg_tbl_pool,
1233 pp->sg_tbl[tag],
1234 pp->sg_tbl_dma[tag]);
1235 pp->sg_tbl[tag] = NULL;
1236 }
da2fa9ba
ML		 1237 }
1238}
1239
05b308e1
BR		 1240/**
1241 * mv_port_start - Port specific init/start routine.
1242 * @ap: ATA channel to manipulate
1243 *
1244 * Allocate and point to DMA memory, init port private memory,
1245 * zero indices.
1246 *
1247 * LOCKING:
1248 * Inherited from caller.
1249 */
31961943
BR		 1250static int mv_port_start(struct ata_port *ap)
1251{
cca3974e
JG		 1252 struct device *dev = ap->host->dev;
1253 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1254 struct mv_port_priv *pp;
dde20207 1255 int tag;
31961943 1256
24dc5f33 1257 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1258 if (!pp)
24dc5f33 1259 return -ENOMEM;
da2fa9ba 1260 ap->private_data = pp;
31961943 1261
da2fa9ba
ML		 1262 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1263 if (!pp->crqb)
1264 return -ENOMEM;
1265 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1266
da2fa9ba
ML		 1267 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1268 if (!pp->crpb)
1269 goto out_port_free_dma_mem;
1270 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1271
eb73d558
ML		 1272 /*
1273 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1274 * For later hardware, we need one unique sg_tbl per NCQ tag.
1275 */
1276 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1277 if (tag == 0 || !IS_GEN_I(hpriv)) {
1278 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1279 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1280 if (!pp->sg_tbl[tag])
1281 goto out_port_free_dma_mem;
1282 } else {
1283 pp->sg_tbl[tag] = pp->sg_tbl[0];
1284 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1285 }
1286 }
31961943 1287 return 0;
da2fa9ba
ML		 1288
1289out_port_free_dma_mem:
1290 mv_port_free_dma_mem(ap);
1291 return -ENOMEM;
31961943
BR		 1292}
1293
05b308e1
BR		 1294/**
1295 * mv_port_stop - Port specific cleanup/stop routine.
1296 * @ap: ATA channel to manipulate
1297 *
1298 * Stop DMA, cleanup port memory.
1299 *
1300 * LOCKING:
cca3974e 1301 * This routine uses the host lock to protect the DMA stop.
05b308e1 1302 */
31961943
BR		 1303static void mv_port_stop(struct ata_port *ap)
1304{
e12bef50 1305 mv_stop_edma(ap);
da2fa9ba 1306 mv_port_free_dma_mem(ap);
31961943
BR		 1307}
1308
05b308e1
BR		 1309/**
1310 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1311 * @qc: queued command whose SG list to source from
1312 *
1313 * Populate the SG list and mark the last entry.
1314 *
1315 * LOCKING:
1316 * Inherited from caller.
1317 */
6c08772e 1318static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1319{
1320 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1321 struct scatterlist *sg;
3be6cbd7 1322 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1323 unsigned int si;
31961943 1324
eb73d558 1325 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1326 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1327 dma_addr_t addr = sg_dma_address(sg);
1328 u32 sg_len = sg_dma_len(sg);
22374677 1329
4007b493
OJ		 1330 while (sg_len) {
1331 u32 offset = addr & 0xffff;
1332 u32 len = sg_len;
22374677 1333
4007b493
OJ		 1334 if ((offset + sg_len > 0x10000))
1335 len = 0x10000 - offset;
1336
1337 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1338 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1339 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1340
1341 sg_len -= len;
1342 addr += len;
1343
3be6cbd7 1344 last_sg = mv_sg;
4007b493 1345 mv_sg++;
4007b493 1346 }
31961943 1347 }
3be6cbd7
JG		 1348
1349 if (likely(last_sg))
1350 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1351}
1352
5796d1c4 1353static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1354{
559eedad 1355 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1356 (last ? CRQB_CMD_LAST : 0);
559eedad 1357 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1358}
1359
05b308e1
BR		 1360/**
1361 * mv_qc_prep - Host specific command preparation.
1362 * @qc: queued command to prepare
1363 *
1364 * This routine simply redirects to the general purpose routine
1365 * if command is not DMA. Else, it handles prep of the CRQB
1366 * (command request block), does some sanity checking, and calls
1367 * the SG load routine.
1368 *
1369 * LOCKING:
1370 * Inherited from caller.
1371 */
31961943
BR		 1372static void mv_qc_prep(struct ata_queued_cmd *qc)
1373{
1374 struct ata_port *ap = qc->ap;
1375 struct mv_port_priv *pp = ap->private_data;
e1469874 1376 __le16 *cw;
31961943
BR		 1377 struct ata_taskfile *tf;
1378 u16 flags = 0;
a6432436 1379 unsigned in_index;
31961943 1380
138bfdd0
ML		 1381 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1382 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1383 return;
20f733e7 1384
31961943
BR		 1385 /* Fill in command request block
1386 */
e4e7b892 1387 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1388 flags |= CRQB_FLAG_READ;
beec7dbc 1389 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1390 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1391 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1392
bdd4ddde 1393 /* get current queue index from software */
fcfb1f77 1394 in_index = pp->req_idx;
a6432436
ML		 1395
1396 pp->crqb[in_index].sg_addr =
eb73d558 1397 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1398 pp->crqb[in_index].sg_addr_hi =
eb73d558 1399 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1400 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1401
a6432436 1402 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1403 tf = &qc->tf;
1404
1405 /* Sadly, the CRQB cannot accomodate all registers--there are
1406 * only 11 bytes...so we must pick and choose required
1407 * registers based on the command. So, we drop feature and
1408 * hob_feature for [RW] DMA commands, but they are needed for
1409 * NCQ. NCQ will drop hob_nsect.
20f733e7 1410 */
31961943
BR		 1411 switch (tf->command) {
1412 case ATA_CMD_READ:
1413 case ATA_CMD_READ_EXT:
1414 case ATA_CMD_WRITE:
1415 case ATA_CMD_WRITE_EXT:
c15d85c8 1416 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1417 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1418 break;
31961943
BR		 1419 case ATA_CMD_FPDMA_READ:
1420 case ATA_CMD_FPDMA_WRITE:
8b260248 1421 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1422 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1423 break;
31961943
BR		 1424 default:
1425 /* The only other commands EDMA supports in non-queued and
1426 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1427 * of which are defined/used by Linux. If we get here, this
1428 * driver needs work.
1429 *
1430 * FIXME: modify libata to give qc_prep a return value and
1431 * return error here.
1432 */
1433 BUG_ON(tf->command);
1434 break;
1435 }
1436 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1437 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1438 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1439 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1440 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1441 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1442 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1443 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1444 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1445
e4e7b892
JG		 1446 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1447 return;
1448 mv_fill_sg(qc);
1449}
1450
1451/**
1452 * mv_qc_prep_iie - Host specific command preparation.
1453 * @qc: queued command to prepare
1454 *
1455 * This routine simply redirects to the general purpose routine
1456 * if command is not DMA. Else, it handles prep of the CRQB
1457 * (command request block), does some sanity checking, and calls
1458 * the SG load routine.
1459 *
1460 * LOCKING:
1461 * Inherited from caller.
1462 */
1463static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1464{
1465 struct ata_port *ap = qc->ap;
1466 struct mv_port_priv *pp = ap->private_data;
1467 struct mv_crqb_iie *crqb;
1468 struct ata_taskfile *tf;
a6432436 1469 unsigned in_index;
e4e7b892
JG		 1470 u32 flags = 0;
1471
138bfdd0
ML		 1472 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1473 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1474 return;
1475
e12bef50 1476 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1477 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1478 flags |= CRQB_FLAG_READ;
1479
beec7dbc 1480 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1481 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1482 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1483 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1484
bdd4ddde 1485 /* get current queue index from software */
fcfb1f77 1486 in_index = pp->req_idx;
a6432436
ML		 1487
1488 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1489 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1490 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1491 crqb->flags = cpu_to_le32(flags);
1492
1493 tf = &qc->tf;
1494 crqb->ata_cmd[0] = cpu_to_le32(
1495 (tf->command << 16) |
1496 (tf->feature << 24)
1497 );
1498 crqb->ata_cmd[1] = cpu_to_le32(
1499 (tf->lbal << 0) |
1500 (tf->lbam << 8) |
1501 (tf->lbah << 16) |
1502 (tf->device << 24)
1503 );
1504 crqb->ata_cmd[2] = cpu_to_le32(
1505 (tf->hob_lbal << 0) |
1506 (tf->hob_lbam << 8) |
1507 (tf->hob_lbah << 16) |
1508 (tf->hob_feature << 24)
1509 );
1510 crqb->ata_cmd[3] = cpu_to_le32(
1511 (tf->nsect << 0) |
1512 (tf->hob_nsect << 8)
1513 );
1514
1515 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1516 return;
31961943
BR		 1517 mv_fill_sg(qc);
1518}
1519
05b308e1
BR		 1520/**
1521 * mv_qc_issue - Initiate a command to the host
1522 * @qc: queued command to start
1523 *
1524 * This routine simply redirects to the general purpose routine
1525 * if command is not DMA. Else, it sanity checks our local
1526 * caches of the request producer/consumer indices then enables
1527 * DMA and bumps the request producer index.
1528 *
1529 * LOCKING:
1530 * Inherited from caller.
1531 */
9a3d9eb0 1532static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1533{
c5d3e45a
JG		 1534 struct ata_port *ap = qc->ap;
1535 void __iomem *port_mmio = mv_ap_base(ap);
1536 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1537 u32 in_index;
31961943 1538
138bfdd0
ML		 1539 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1540 (qc->tf.protocol != ATA_PROT_NCQ)) {
17c5aab5
ML		 1541 /*
1542 * We're about to send a non-EDMA capable command to the
31961943
BR		 1543 * port. Turn off EDMA so there won't be problems accessing
1544 * shadow block, etc registers.
1545 */
b562468c 1546 mv_stop_edma(ap);
e49856d8 1547 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1548 return ata_sff_qc_issue(qc);
31961943
BR		 1549 }
1550
72109168 1551 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1552
fcfb1f77
ML		 1553 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1554 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1555
1556 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1557 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1558 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1559
1560 return 0;
1561}
1562
8f767f8a
ML		 1563static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1564{
1565 struct mv_port_priv *pp = ap->private_data;
1566 struct ata_queued_cmd *qc;
1567
1568 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1569 return NULL;
1570 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1571 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1572 qc = NULL;
1573 return qc;
1574}
1575
1576static void mv_unexpected_intr(struct ata_port *ap)
1577{
1578 struct mv_port_priv *pp = ap->private_data;
1579 struct ata_eh_info *ehi = &ap->link.eh_info;
1580 char *when = "";
1581
1582 /*
1583 * We got a device interrupt from something that
1584 * was supposed to be using EDMA or polling.
1585 */
1586 ata_ehi_clear_desc(ehi);
1587 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1588 when = " while EDMA enabled";
1589 } else {
1590 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1591 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1592 when = " while polling";
1593 }
1594 ata_ehi_push_desc(ehi, "unexpected device interrupt%s", when);
1595 ehi->err_mask |= AC_ERR_OTHER;
1596 ehi->action |= ATA_EH_RESET;
1597 ata_port_freeze(ap);
1598}
1599
05b308e1
BR		 1600/**
1601 * mv_err_intr - Handle error interrupts on the port
1602 * @ap: ATA channel to manipulate
8d07379d 1603 * @qc: affected command (non-NCQ), or NULL
05b308e1 1604 *
8d07379d
ML		 1605 * Most cases require a full reset of the chip's state machine,
1606 * which also performs a COMRESET.
1607 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1608 *
1609 * LOCKING:
1610 * Inherited from caller.
1611 */
bdd4ddde 1612static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
31961943
BR		 1613{
1614 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde
JG		 1615 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1616 struct mv_port_priv *pp = ap->private_data;
1617 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1618 unsigned int action = 0, err_mask = 0;
9af5c9c9 1619 struct ata_eh_info *ehi = &ap->link.eh_info;
20f733e7 1620
bdd4ddde 1621 ata_ehi_clear_desc(ehi);
20f733e7 1622
8d07379d
ML		 1623 /*
1624 * Read and clear the err_cause bits. This won't actually
1625 * clear for some errors (eg. SError), but we will be doing
1626 * a hard reset in those cases regardless, which *will* clear it.
1627 */
bdd4ddde 1628 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
8d07379d 1629 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1630
352fab70 1631 ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause);
bdd4ddde
JG		 1632
1633 /*
352fab70 1634 * All generations share these EDMA error cause bits:
bdd4ddde 1635 */
bdd4ddde
JG		 1636 if (edma_err_cause & EDMA_ERR_DEV)
1637 err_mask |= AC_ERR_DEV;
1638 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1639 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1640 EDMA_ERR_INTRL_PAR)) {
1641 err_mask |= AC_ERR_ATA_BUS;
cf480626 1642 action |= ATA_EH_RESET;
b64bbc39 1643 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1644 }
1645 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1646 ata_ehi_hotplugged(ehi);
1647 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1648 "dev disconnect" : "dev connect");
cf480626 1649 action |= ATA_EH_RESET;
bdd4ddde
JG		 1650 }
1651
352fab70
ML		 1652 /*
1653 * Gen-I has a different SELF_DIS bit,
1654 * different FREEZE bits, and no SERR bit:
1655 */
ee9ccdf7 1656 if (IS_GEN_I(hpriv)) {
bdd4ddde 1657 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1658 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1659 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1660 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1661 }
1662 } else {
1663 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1664 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1665 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1666 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1667 }
bdd4ddde 1668 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1669 /*
1670 * Ensure that we read our own SCR, not a pmp link SCR:
1671 */
1672 ap->ops->scr_read(ap, SCR_ERROR, &serr);
1673 /*
1674 * Don't clear SError here; leave it for libata-eh:
1675 */
1676 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1677 err_mask |= AC_ERR_ATA_BUS;
cf480626 1678 action |= ATA_EH_RESET;
bdd4ddde 1679 }
afb0edd9 1680 }
20f733e7 1681
bdd4ddde
JG		 1682 if (!err_mask) {
1683 err_mask = AC_ERR_OTHER;
cf480626 1684 action |= ATA_EH_RESET;
bdd4ddde
JG		 1685 }
1686
1687 ehi->serror |= serr;
1688 ehi->action |= action;
1689
1690 if (qc)
1691 qc->err_mask |= err_mask;
1692 else
1693 ehi->err_mask |= err_mask;
1694
1695 if (edma_err_cause & eh_freeze_mask)
1696 ata_port_freeze(ap);
1697 else
1698 ata_port_abort(ap);
1699}
1700
fcfb1f77
ML		 1701static void mv_process_crpb_response(struct ata_port *ap,
1702 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1703{
1704 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1705
1706 if (qc) {
1707 u8 ata_status;
1708 u16 edma_status = le16_to_cpu(response->flags);
1709 /*
1710 * edma_status from a response queue entry:
1711 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1712 * MSB is saved ATA status from command completion.
1713 */
1714 if (!ncq_enabled) {
1715 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1716 if (err_cause) {
1717 /*
1718 * Error will be seen/handled by mv_err_intr().
1719 * So do nothing at all here.
1720 */
1721 return;
1722 }
1723 }
1724 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1725 qc->err_mask |= ac_err_mask(ata_status);
1726 ata_qc_complete(qc);
1727 } else {
1728 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1729 __func__, tag);
1730 }
1731}
1732
1733static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 1734{
1735 void __iomem *port_mmio = mv_ap_base(ap);
1736 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 1737 u32 in_index;
bdd4ddde 1738 bool work_done = false;
fcfb1f77 1739 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 1740
fcfb1f77 1741 /* Get the hardware queue position index */
bdd4ddde
JG		 1742 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1743 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1744
fcfb1f77
ML		 1745 /* Process new responses from since the last time we looked */
1746 while (in_index != pp->resp_idx) {
6c1153e0 1747 unsigned int tag;
fcfb1f77 1748 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 1749
fcfb1f77 1750 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 1751
fcfb1f77
ML		 1752 if (IS_GEN_I(hpriv)) {
1753 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 1754 tag = ap->link.active_tag;
fcfb1f77
ML		 1755 } else {
1756 /* Gen II/IIE: get command tag from CRPB entry */
1757 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 1758 }
fcfb1f77 1759 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 1760 work_done = true;
bdd4ddde
JG		 1761 }
1762
352fab70 1763 /* Update the software queue position index in hardware */
bdd4ddde
JG		 1764 if (work_done)
1765 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 1766 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 1767 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 1768}
1769
05b308e1
BR		 1770/**
1771 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 1772 * @host: host specific structure
7368f919 1773 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 1774 *
1775 * LOCKING:
1776 * Inherited from caller.
1777 */
7368f919 1778static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 1779{
f351b2d6 1780 struct mv_host_priv *hpriv = host->private_data;
a3718c1f
ML		 1781 void __iomem *mmio = hpriv->base, *hc_mmio = NULL;
1782 u32 hc_irq_cause = 0;
1783 unsigned int handled = 0, port;
20f733e7 1784
a3718c1f 1785 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 1786 struct ata_port *ap = host->ports[port];
8f71efe2 1787 struct mv_port_priv *pp;
a3718c1f
ML		 1788 unsigned int shift, hardport, port_cause;
1789 /*
1790 * When we move to the second hc, flag our cached
1791 * copies of hc_mmio (and hc_irq_cause) as invalid again.
1792 */
1793 if (port == MV_PORTS_PER_HC)
1794 hc_mmio = NULL;
1795 /*
1796 * Do nothing if port is not interrupting or is disabled:
1797 */
1798 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
7368f919 1799 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
a3718c1f 1800 if (!port_cause || !ap || (ap->flags & ATA_FLAG_DISABLED))
a2c91a88 1801 continue;
a3718c1f
ML		 1802 /*
1803 * Each hc within the host has its own hc_irq_cause register.
1804 * We defer reading it until we know we need it, right now:
1805 *
1806 * FIXME later: we don't really need to read this register
1807 * (some logic changes required below if we go that way),
1808 * because it doesn't tell us anything new. But we do need
1809 * to write to it, outside the top of this loop,
1810 * to reset the interrupt triggers for next time.
1811 */
1812 if (!hc_mmio) {
1813 hc_mmio = mv_hc_base_from_port(mmio, port);
1814 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1815 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1816 handled = 1;
1817 }
8f767f8a
ML		 1818 /*
1819 * Process completed CRPB response(s) before other events.
1820 */
a3718c1f 1821 pp = ap->private_data;
8f767f8a
ML		 1822 if (hc_irq_cause & (DMA_IRQ << hardport)) {
1823 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN)
fcfb1f77 1824 mv_process_crpb_entries(ap, pp);
8f767f8a
ML		 1825 }
1826 /*
1827 * Handle chip-reported errors, or continue on to handle PIO.
1828 */
1829 if (unlikely(port_cause & ERR_IRQ)) {
1830 mv_err_intr(ap, mv_get_active_qc(ap));
1831 } else if (hc_irq_cause & (DEV_IRQ << hardport)) {
1832 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1833 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
1834 if (qc) {
1835 ata_sff_host_intr(ap, qc);
1836 continue;
1837 }
1838 }
1839 mv_unexpected_intr(ap);
20f733e7
BR		 1840 }
1841 }
a3718c1f 1842 return handled;
20f733e7
BR		 1843}
1844
a3718c1f 1845static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 1846{
02a121da 1847 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 1848 struct ata_port *ap;
1849 struct ata_queued_cmd *qc;
1850 struct ata_eh_info *ehi;
1851 unsigned int i, err_mask, printed = 0;
1852 u32 err_cause;
1853
02a121da 1854 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 1855
1856 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
1857 err_cause);
1858
1859 DPRINTK("All regs @ PCI error\n");
1860 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1861
02a121da 1862 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 1863
1864 for (i = 0; i < host->n_ports; i++) {
1865 ap = host->ports[i];
936fd732 1866 if (!ata_link_offline(&ap->link)) {
9af5c9c9 1867 ehi = &ap->link.eh_info;
bdd4ddde
JG		 1868 ata_ehi_clear_desc(ehi);
1869 if (!printed++)
1870 ata_ehi_push_desc(ehi,
1871 "PCI err cause 0x%08x", err_cause);
1872 err_mask = AC_ERR_HOST_BUS;
cf480626 1873 ehi->action = ATA_EH_RESET;
9af5c9c9 1874 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 1875 if (qc)
1876 qc->err_mask |= err_mask;
1877 else
1878 ehi->err_mask |= err_mask;
1879
1880 ata_port_freeze(ap);
1881 }
1882 }
a3718c1f 1883 return 1; /* handled */
bdd4ddde
JG		 1884}
1885
05b308e1 1886/**
c5d3e45a 1887 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 1888 * @irq: unused
1889 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 1890 *
1891 * Read the read only register to determine if any host
1892 * controllers have pending interrupts. If so, call lower level
1893 * routine to handle. Also check for PCI errors which are only
1894 * reported here.
1895 *
8b260248 1896 * LOCKING:
cca3974e 1897 * This routine holds the host lock while processing pending
05b308e1
BR		 1898 * interrupts.
1899 */
7d12e780 1900static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 1901{
cca3974e 1902 struct ata_host *host = dev_instance;
f351b2d6 1903 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 1904 unsigned int handled = 0;
7368f919 1905 u32 main_irq_cause, main_irq_mask;
20f733e7 1906
646a4da5 1907 spin_lock(&host->lock);
7368f919
ML		 1908 main_irq_cause = readl(hpriv->main_irq_cause_addr);
1909 main_irq_mask = readl(hpriv->main_irq_mask_addr);
352fab70
ML		 1910 /*
1911 * Deal with cases where we either have nothing pending, or have read
1912 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 1913 */
7368f919
ML		 1914 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
1915 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
a3718c1f
ML		 1916 handled = mv_pci_error(host, hpriv->base);
1917 else
7368f919 1918 handled = mv_host_intr(host, main_irq_cause);
bdd4ddde 1919 }
cca3974e 1920 spin_unlock(&host->lock);
20f733e7
BR		 1921 return IRQ_RETVAL(handled);
1922}
1923
c9d39130
JG		 1924static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1925{
1926 unsigned int ofs;
1927
1928 switch (sc_reg_in) {
1929 case SCR_STATUS:
1930 case SCR_ERROR:
1931 case SCR_CONTROL:
1932 ofs = sc_reg_in * sizeof(u32);
1933 break;
1934 default:
1935 ofs = 0xffffffffU;
1936 break;
1937 }
1938 return ofs;
1939}
1940
da3dbb17 1941static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 1942{
f351b2d6
SB		 1943 struct mv_host_priv *hpriv = ap->host->private_data;
1944 void __iomem *mmio = hpriv->base;
0d5ff566 1945 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1946 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1947
da3dbb17
TH		 1948 if (ofs != 0xffffffffU) {
1949 *val = readl(addr + ofs);
1950 return 0;
1951 } else
1952 return -EINVAL;
c9d39130
JG		 1953}
1954
da3dbb17 1955static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 1956{
f351b2d6
SB		 1957 struct mv_host_priv *hpriv = ap->host->private_data;
1958 void __iomem *mmio = hpriv->base;
0d5ff566 1959 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1960 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1961
da3dbb17 1962 if (ofs != 0xffffffffU) {
0d5ff566 1963 writelfl(val, addr + ofs);
da3dbb17
TH		 1964 return 0;
1965 } else
1966 return -EINVAL;
c9d39130
JG		 1967}
1968
7bb3c529 1969static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 1970{
7bb3c529 1971 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 1972 int early_5080;
1973
44c10138 1974 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 1975
1976 if (!early_5080) {
1977 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1978 tmp |= (1 << 0);
1979 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1980 }
1981
7bb3c529 1982 mv_reset_pci_bus(host, mmio);
522479fb
JG		 1983}
1984
1985static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1986{
8e7decdb 1987 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 1988}
1989
47c2b677 1990static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1991 void __iomem *mmio)
1992{
c9d39130
JG		 1993 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1994 u32 tmp;
1995
1996 tmp = readl(phy_mmio + MV5_PHY_MODE);
1997
1998 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1999 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2000}
2001
47c2b677 2002static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2003{
522479fb
JG		 2004 u32 tmp;
2005
8e7decdb 2006 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2007
2008 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2009
2010 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2011 tmp |= ~(1 << 0);
2012 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2013}
2014
2a47ce06
JG		 2015static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2016 unsigned int port)
bca1c4eb 2017{
c9d39130
JG		 2018 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2019 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2020 u32 tmp;
2021 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2022
2023 if (fix_apm_sq) {
8e7decdb 2024 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2025 tmp |= (1 << 19);
8e7decdb 2026 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2027
8e7decdb 2028 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2029 tmp &= ~0x3;
2030 tmp |= 0x1;
8e7decdb 2031 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2032 }
2033
2034 tmp = readl(phy_mmio + MV5_PHY_MODE);
2035 tmp &= ~mask;
2036 tmp |= hpriv->signal[port].pre;
2037 tmp |= hpriv->signal[port].amps;
2038 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2039}
2040
c9d39130
JG		 2041
2042#undef ZERO
2043#define ZERO(reg) writel(0, port_mmio + (reg))
2044static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2045 unsigned int port)
2046{
2047 void __iomem *port_mmio = mv_port_base(mmio, port);
2048
e12bef50 2049 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2050
2051 ZERO(0x028); /* command */
2052 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2053 ZERO(0x004); /* timer */
2054 ZERO(0x008); /* irq err cause */
2055 ZERO(0x00c); /* irq err mask */
2056 ZERO(0x010); /* rq bah */
2057 ZERO(0x014); /* rq inp */
2058 ZERO(0x018); /* rq outp */
2059 ZERO(0x01c); /* respq bah */
2060 ZERO(0x024); /* respq outp */
2061 ZERO(0x020); /* respq inp */
2062 ZERO(0x02c); /* test control */
8e7decdb 2063 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2064}
2065#undef ZERO
2066
2067#define ZERO(reg) writel(0, hc_mmio + (reg))
2068static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2069 unsigned int hc)
47c2b677 2070{
c9d39130
JG		 2071 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2072 u32 tmp;
2073
2074 ZERO(0x00c);
2075 ZERO(0x010);
2076 ZERO(0x014);
2077 ZERO(0x018);
2078
2079 tmp = readl(hc_mmio + 0x20);
2080 tmp &= 0x1c1c1c1c;
2081 tmp |= 0x03030303;
2082 writel(tmp, hc_mmio + 0x20);
2083}
2084#undef ZERO
2085
2086static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2087 unsigned int n_hc)
2088{
2089 unsigned int hc, port;
2090
2091 for (hc = 0; hc < n_hc; hc++) {
2092 for (port = 0; port < MV_PORTS_PER_HC; port++)
2093 mv5_reset_hc_port(hpriv, mmio,
2094 (hc * MV_PORTS_PER_HC) + port);
2095
2096 mv5_reset_one_hc(hpriv, mmio, hc);
2097 }
2098
2099 return 0;
47c2b677
JG		 2100}
2101
101ffae2
JG		 2102#undef ZERO
2103#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2104static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2105{
02a121da 2106 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2107 u32 tmp;
2108
8e7decdb 2109 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2110 tmp &= 0xff00ffff;
8e7decdb 2111 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2112
2113 ZERO(MV_PCI_DISC_TIMER);
2114 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2115 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
7368f919 2116 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
101ffae2 2117 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2118 ZERO(hpriv->irq_cause_ofs);
2119 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2120 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2121 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2122 ZERO(MV_PCI_ERR_ATTRIBUTE);
2123 ZERO(MV_PCI_ERR_COMMAND);
2124}
2125#undef ZERO
2126
2127static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2128{
2129 u32 tmp;
2130
2131 mv5_reset_flash(hpriv, mmio);
2132
8e7decdb 2133 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2134 tmp &= 0x3;
2135 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2136 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2137}
2138
2139/**
2140 * mv6_reset_hc - Perform the 6xxx global soft reset
2141 * @mmio: base address of the HBA
2142 *
2143 * This routine only applies to 6xxx parts.
2144 *
2145 * LOCKING:
2146 * Inherited from caller.
2147 */
c9d39130
JG		 2148static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2149 unsigned int n_hc)
101ffae2
JG		 2150{
2151 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2152 int i, rc = 0;
2153 u32 t;
2154
2155 /* Following procedure defined in PCI "main command and status
2156 * register" table.
2157 */
2158 t = readl(reg);
2159 writel(t | STOP_PCI_MASTER, reg);
2160
2161 for (i = 0; i < 1000; i++) {
2162 udelay(1);
2163 t = readl(reg);
2dcb407e 2164 if (PCI_MASTER_EMPTY & t)
101ffae2 2165 break;
101ffae2
JG		 2166 }
2167 if (!(PCI_MASTER_EMPTY & t)) {
2168 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2169 rc = 1;
2170 goto done;
2171 }
2172
2173 /* set reset */
2174 i = 5;
2175 do {
2176 writel(t | GLOB_SFT_RST, reg);
2177 t = readl(reg);
2178 udelay(1);
2179 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2180
2181 if (!(GLOB_SFT_RST & t)) {
2182 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2183 rc = 1;
2184 goto done;
2185 }
2186
2187 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2188 i = 5;
2189 do {
2190 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2191 t = readl(reg);
2192 udelay(1);
2193 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2194
2195 if (GLOB_SFT_RST & t) {
2196 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2197 rc = 1;
2198 }
2199done:
2200 return rc;
2201}
2202
47c2b677 2203static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2204 void __iomem *mmio)
2205{
2206 void __iomem *port_mmio;
2207 u32 tmp;
2208
8e7decdb 2209 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2210 if ((tmp & (1 << 0)) == 0) {
47c2b677 2211 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2212 hpriv->signal[idx].pre = 0x1 << 5;
2213 return;
2214 }
2215
2216 port_mmio = mv_port_base(mmio, idx);
2217 tmp = readl(port_mmio + PHY_MODE2);
2218
2219 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2220 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2221}
2222
47c2b677 2223static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2224{
8e7decdb 2225 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2226}
2227
c9d39130 2228static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2229 unsigned int port)
bca1c4eb 2230{
c9d39130
JG		 2231 void __iomem *port_mmio = mv_port_base(mmio, port);
2232
bca1c4eb 2233 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2234 int fix_phy_mode2 =
2235 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2236 int fix_phy_mode4 =
47c2b677
JG		 2237 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2238 u32 m2, tmp;
2239
2240 if (fix_phy_mode2) {
2241 m2 = readl(port_mmio + PHY_MODE2);
2242 m2 &= ~(1 << 16);
2243 m2 |= (1 << 31);
2244 writel(m2, port_mmio + PHY_MODE2);
2245
2246 udelay(200);
2247
2248 m2 = readl(port_mmio + PHY_MODE2);
2249 m2 &= ~((1 << 16) | (1 << 31));
2250 writel(m2, port_mmio + PHY_MODE2);
2251
2252 udelay(200);
2253 }
2254
2255 /* who knows what this magic does */
2256 tmp = readl(port_mmio + PHY_MODE3);
2257 tmp &= ~0x7F800000;
2258 tmp |= 0x2A800000;
2259 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2260
2261 if (fix_phy_mode4) {
47c2b677 2262 u32 m4;
bca1c4eb
JG		 2263
2264 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 2265
2266 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2267 tmp = readl(port_mmio + PHY_MODE3);
bca1c4eb 2268
e12bef50 2269 /* workaround for errata FEr SATA#10 (part 1) */
bca1c4eb
JG		 2270 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2271
2272 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 2273
2274 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2275 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2276 }
2277
2278 /* Revert values of pre-emphasis and signal amps to the saved ones */
2279 m2 = readl(port_mmio + PHY_MODE2);
2280
2281 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2282 m2 |= hpriv->signal[port].amps;
2283 m2 |= hpriv->signal[port].pre;
47c2b677 2284 m2 &= ~(1 << 16);
bca1c4eb 2285
e4e7b892
JG		 2286 /* according to mvSata 3.6.1, some IIE values are fixed */
2287 if (IS_GEN_IIE(hpriv)) {
2288 m2 &= ~0xC30FF01F;
2289 m2 |= 0x0000900F;
2290 }
2291
bca1c4eb
JG		 2292 writel(m2, port_mmio + PHY_MODE2);
2293}
2294
f351b2d6
SB		 2295/* TODO: use the generic LED interface to configure the SATA Presence */
2296/* & Acitivy LEDs on the board */
2297static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2298 void __iomem *mmio)
2299{
2300 return;
2301}
2302
2303static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2304 void __iomem *mmio)
2305{
2306 void __iomem *port_mmio;
2307 u32 tmp;
2308
2309 port_mmio = mv_port_base(mmio, idx);
2310 tmp = readl(port_mmio + PHY_MODE2);
2311
2312 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2313 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2314}
2315
2316#undef ZERO
2317#define ZERO(reg) writel(0, port_mmio + (reg))
2318static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2319 void __iomem *mmio, unsigned int port)
2320{
2321 void __iomem *port_mmio = mv_port_base(mmio, port);
2322
e12bef50 2323 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2324
2325 ZERO(0x028); /* command */
2326 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2327 ZERO(0x004); /* timer */
2328 ZERO(0x008); /* irq err cause */
2329 ZERO(0x00c); /* irq err mask */
2330 ZERO(0x010); /* rq bah */
2331 ZERO(0x014); /* rq inp */
2332 ZERO(0x018); /* rq outp */
2333 ZERO(0x01c); /* respq bah */
2334 ZERO(0x024); /* respq outp */
2335 ZERO(0x020); /* respq inp */
2336 ZERO(0x02c); /* test control */
8e7decdb 2337 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2338}
2339
2340#undef ZERO
2341
2342#define ZERO(reg) writel(0, hc_mmio + (reg))
2343static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2344 void __iomem *mmio)
2345{
2346 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2347
2348 ZERO(0x00c);
2349 ZERO(0x010);
2350 ZERO(0x014);
2351
2352}
2353
2354#undef ZERO
2355
2356static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2357 void __iomem *mmio, unsigned int n_hc)
2358{
2359 unsigned int port;
2360
2361 for (port = 0; port < hpriv->n_ports; port++)
2362 mv_soc_reset_hc_port(hpriv, mmio, port);
2363
2364 mv_soc_reset_one_hc(hpriv, mmio);
2365
2366 return 0;
2367}
2368
2369static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2370 void __iomem *mmio)
2371{
2372 return;
2373}
2374
2375static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2376{
2377 return;
2378}
2379
8e7decdb 2380static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2381{
8e7decdb 2382 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2383
8e7decdb 2384 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2385 if (want_gen2i)
8e7decdb
ML		 2386 ifcfg |= (1 << 7); /* enable gen2i speed */
2387 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2388}
2389
e12bef50 2390static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2391 unsigned int port_no)
2392{
2393 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2394
8e7decdb
ML		 2395 /*
2396 * The datasheet warns against setting EDMA_RESET when EDMA is active
2397 * (but doesn't say what the problem might be). So we first try
2398 * to disable the EDMA engine before doing the EDMA_RESET operation.
2399 */
0d8be5cb 2400 mv_stop_edma_engine(port_mmio);
8e7decdb 2401 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2402
b67a1064 2403 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2404 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2405 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2406 }
b67a1064 2407 /*
8e7decdb 2408 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2409 * link, and physical layers. It resets all SATA interface registers
2410 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2411 */
8e7decdb 2412 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2413 udelay(25); /* allow reset propagation */
c9d39130
JG		 2414 writelfl(0, port_mmio + EDMA_CMD_OFS);
2415
2416 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2417
ee9ccdf7 2418 if (IS_GEN_I(hpriv))
c9d39130
JG		 2419 mdelay(1);
2420}
2421
e49856d8 2422static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2423{
e49856d8
ML		 2424 if (sata_pmp_supported(ap)) {
2425 void __iomem *port_mmio = mv_ap_base(ap);
2426 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2427 int old = reg & 0xf;
22374677 2428
e49856d8
ML		 2429 if (old != pmp) {
2430 reg = (reg & ~0xf) | pmp;
2431 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2432 }
22374677 2433 }
20f733e7
BR		 2434}
2435
e49856d8
ML		 2436static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2437 unsigned long deadline)
22374677 2438{
e49856d8
ML		 2439 mv_pmp_select(link->ap, sata_srst_pmp(link));
2440 return sata_std_hardreset(link, class, deadline);
2441}
bdd4ddde 2442
e49856d8
ML		 2443static int mv_softreset(struct ata_link *link, unsigned int *class,
2444 unsigned long deadline)
2445{
2446 mv_pmp_select(link->ap, sata_srst_pmp(link));
2447 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2448}
2449
cc0680a5 2450static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2451 unsigned long deadline)
31961943 2452{
cc0680a5 2453 struct ata_port *ap = link->ap;
bdd4ddde 2454 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2455 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2456 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2457 int rc, attempts = 0, extra = 0;
2458 u32 sstatus;
2459 bool online;
31961943 2460
e12bef50 2461 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2462 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2463
0d8be5cb
ML		 2464 /* Workaround for errata FEr SATA#10 (part 2) */
2465 do {
17c5aab5
ML		 2466 const unsigned long *timing =
2467 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2468
17c5aab5
ML		 2469 rc = sata_link_hardreset(link, timing, deadline + extra,
2470 &online, NULL);
2471 if (rc)
0d8be5cb 2472 return rc;
0d8be5cb
ML		 2473 sata_scr_read(link, SCR_STATUS, &sstatus);
2474 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2475 /* Force 1.5gb/s link speed and try again */
8e7decdb 2476 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2477 if (time_after(jiffies + HZ, deadline))
2478 extra = HZ; /* only extend it once, max */
2479 }
2480 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2481
17c5aab5 2482 return rc;
bdd4ddde
JG		 2483}
2484
bdd4ddde
JG		 2485static void mv_eh_freeze(struct ata_port *ap)
2486{
f351b2d6 2487 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae 2488 unsigned int shift, hardport, port = ap->port_no;
7368f919 2489 u32 main_irq_mask;
bdd4ddde
JG		 2490
2491 /* FIXME: handle coalescing completion events properly */
2492
1cfd19ae
ML		 2493 mv_stop_edma(ap);
2494 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2495
bdd4ddde 2496 /* disable assertion of portN err, done events */
7368f919
ML		 2497 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2498 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2499 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
bdd4ddde
JG		 2500}
2501
2502static void mv_eh_thaw(struct ata_port *ap)
2503{
f351b2d6 2504 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae
ML		 2505 unsigned int shift, hardport, port = ap->port_no;
2506 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2507 void __iomem *port_mmio = mv_ap_base(ap);
7368f919 2508 u32 main_irq_mask, hc_irq_cause;
bdd4ddde
JG		 2509
2510 /* FIXME: handle coalescing completion events properly */
2511
1cfd19ae 2512 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2513
bdd4ddde
JG		 2514 /* clear EDMA errors on this port */
2515 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2516
2517 /* clear pending irq events */
2518 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1cfd19ae
ML		 2519 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2520 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde
JG		 2521
2522 /* enable assertion of portN err, done events */
7368f919
ML		 2523 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2524 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2525 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
31961943
BR		 2526}
2527
05b308e1
BR		 2528/**
2529 * mv_port_init - Perform some early initialization on a single port.
2530 * @port: libata data structure storing shadow register addresses
2531 * @port_mmio: base address of the port
2532 *
2533 * Initialize shadow register mmio addresses, clear outstanding
2534 * interrupts on the port, and unmask interrupts for the future
2535 * start of the port.
2536 *
2537 * LOCKING:
2538 * Inherited from caller.
2539 */
31961943 2540static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2541{
0d5ff566 2542 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2543 unsigned serr_ofs;
2544
8b260248 2545 /* PIO related setup
31961943
BR		 2546 */
2547 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2548 port->error_addr =
31961943
BR		 2549 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2550 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2551 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2552 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2553 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2554 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2555 port->status_addr =
31961943
BR		 2556 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2557 /* special case: control/altstatus doesn't have ATA_REG_ address */
2558 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2559
2560 /* unused: */
8d9db2d2 2561 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2562
31961943
BR		 2563 /* Clear any currently outstanding port interrupt conditions */
2564 serr_ofs = mv_scr_offset(SCR_ERROR);
2565 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2566 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2567
646a4da5
ML		 2568 /* unmask all non-transient EDMA error interrupts */
2569 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2570
8b260248 2571 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2572 readl(port_mmio + EDMA_CFG_OFS),
2573 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2574 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2575}
2576
616d4a98
ML		 2577static unsigned int mv_in_pcix_mode(struct ata_host *host)
2578{
2579 struct mv_host_priv *hpriv = host->private_data;
2580 void __iomem *mmio = hpriv->base;
2581 u32 reg;
2582
2583 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2584 return 0; /* not PCI-X capable */
2585 reg = readl(mmio + MV_PCI_MODE_OFS);
2586 if ((reg & MV_PCI_MODE_MASK) == 0)
2587 return 0; /* conventional PCI mode */
2588 return 1; /* chip is in PCI-X mode */
2589}
2590
2591static int mv_pci_cut_through_okay(struct ata_host *host)
2592{
2593 struct mv_host_priv *hpriv = host->private_data;
2594 void __iomem *mmio = hpriv->base;
2595 u32 reg;
2596
2597 if (!mv_in_pcix_mode(host)) {
2598 reg = readl(mmio + PCI_COMMAND_OFS);
2599 if (reg & PCI_COMMAND_MRDTRIG)
2600 return 0; /* not okay */
2601 }
2602 return 1; /* okay */
2603}
2604
4447d351 2605static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2606{
4447d351
TH		 2607 struct pci_dev *pdev = to_pci_dev(host->dev);
2608 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2609 u32 hp_flags = hpriv->hp_flags;
2610
5796d1c4 2611 switch (board_idx) {
47c2b677
JG		 2612 case chip_5080:
2613 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2614 hp_flags |= MV_HP_GEN_I;
47c2b677 2615
44c10138 2616 switch (pdev->revision) {
47c2b677
JG		 2617 case 0x1:
2618 hp_flags |= MV_HP_ERRATA_50XXB0;
2619 break;
2620 case 0x3:
2621 hp_flags |= MV_HP_ERRATA_50XXB2;
2622 break;
2623 default:
2624 dev_printk(KERN_WARNING, &pdev->dev,
2625 "Applying 50XXB2 workarounds to unknown rev\n");
2626 hp_flags |= MV_HP_ERRATA_50XXB2;
2627 break;
2628 }
2629 break;
2630
bca1c4eb
JG		 2631 case chip_504x:
2632 case chip_508x:
47c2b677 2633 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2634 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2635
44c10138 2636 switch (pdev->revision) {
47c2b677
JG		 2637 case 0x0:
2638 hp_flags |= MV_HP_ERRATA_50XXB0;
2639 break;
2640 case 0x3:
2641 hp_flags |= MV_HP_ERRATA_50XXB2;
2642 break;
2643 default:
2644 dev_printk(KERN_WARNING, &pdev->dev,
2645 "Applying B2 workarounds to unknown rev\n");
2646 hp_flags |= MV_HP_ERRATA_50XXB2;
2647 break;
bca1c4eb
JG		 2648 }
2649 break;
2650
2651 case chip_604x:
2652 case chip_608x:
47c2b677 2653 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2654 hp_flags |= MV_HP_GEN_II;
47c2b677 2655
44c10138 2656 switch (pdev->revision) {
47c2b677
JG		 2657 case 0x7:
2658 hp_flags |= MV_HP_ERRATA_60X1B2;
2659 break;
2660 case 0x9:
2661 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2662 break;
2663 default:
2664 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2665 "Applying B2 workarounds to unknown rev\n");
2666 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2667 break;
2668 }
2669 break;
2670
e4e7b892 2671 case chip_7042:
616d4a98 2672 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2673 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2674 (pdev->device == 0x2300 || pdev->device == 0x2310))
2675 {
4e520033
ML		 2676 /*
2677 * Highpoint RocketRAID PCIe 23xx series cards:
2678 *
2679 * Unconfigured drives are treated as "Legacy"
2680 * by the BIOS, and it overwrites sector 8 with
2681 * a "Lgcy" metadata block prior to Linux boot.
2682 *
2683 * Configured drives (RAID or JBOD) leave sector 8
2684 * alone, but instead overwrite a high numbered
2685 * sector for the RAID metadata. This sector can
2686 * be determined exactly, by truncating the physical
2687 * drive capacity to a nice even GB value.
2688 *
2689 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2690 *
2691 * Warn the user, lest they think we're just buggy.
2692 */
2693 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2694 " BIOS CORRUPTS DATA on all attached drives,"
2695 " regardless of if/how they are configured."
2696 " BEWARE!\n");
2697 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2698 " use sectors 8-9 on \"Legacy\" drives,"
2699 " and avoid the final two gigabytes on"
2700 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2701 }
8e7decdb 2702 /* drop through */
e4e7b892
JG		 2703 case chip_6042:
2704 hpriv->ops = &mv6xxx_ops;
e4e7b892 2705 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 2706 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2707 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 2708
44c10138 2709 switch (pdev->revision) {
e4e7b892
JG		 2710 case 0x0:
2711 hp_flags |= MV_HP_ERRATA_XX42A0;
2712 break;
2713 case 0x1:
2714 hp_flags |= MV_HP_ERRATA_60X1C0;
2715 break;
2716 default:
2717 dev_printk(KERN_WARNING, &pdev->dev,
2718 "Applying 60X1C0 workarounds to unknown rev\n");
2719 hp_flags |= MV_HP_ERRATA_60X1C0;
2720 break;
2721 }
2722 break;
f351b2d6
SB		 2723 case chip_soc:
2724 hpriv->ops = &mv_soc_ops;
2725 hp_flags |= MV_HP_ERRATA_60X1C0;
2726 break;
e4e7b892 2727
bca1c4eb 2728 default:
f351b2d6 2729 dev_printk(KERN_ERR, host->dev,
5796d1c4 2730 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 2731 return 1;
2732 }
2733
2734 hpriv->hp_flags = hp_flags;
02a121da
ML		 2735 if (hp_flags & MV_HP_PCIE) {
2736 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
2737 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
2738 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
2739 } else {
2740 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
2741 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
2742 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
2743 }
bca1c4eb
JG		 2744
2745 return 0;
2746}
2747
05b308e1 2748/**
47c2b677 2749 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 2750 * @host: ATA host to initialize
2751 * @board_idx: controller index
05b308e1
BR		 2752 *
2753 * If possible, do an early global reset of the host. Then do
2754 * our port init and clear/unmask all/relevant host interrupts.
2755 *
2756 * LOCKING:
2757 * Inherited from caller.
2758 */
4447d351 2759static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 2760{
2761 int rc = 0, n_hc, port, hc;
4447d351 2762 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 2763 void __iomem *mmio = hpriv->base;
47c2b677 2764
4447d351 2765 rc = mv_chip_id(host, board_idx);
bca1c4eb 2766 if (rc)
352fab70 2767 goto done;
f351b2d6
SB		 2768
2769 if (HAS_PCI(host)) {
7368f919
ML		 2770 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
2771 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 2772 } else {
7368f919
ML		 2773 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
2774 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 2775 }
352fab70
ML		 2776
2777 /* global interrupt mask: 0 == mask everything */
7368f919 2778 writel(0, hpriv->main_irq_mask_addr);
bca1c4eb 2779
4447d351 2780 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 2781
4447d351 2782 for (port = 0; port < host->n_ports; port++)
47c2b677 2783 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 2784
c9d39130 2785 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 2786 if (rc)
20f733e7 2787 goto done;
20f733e7 2788
522479fb 2789 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 2790 hpriv->ops->reset_bus(host, mmio);
47c2b677 2791 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 2792
4447d351 2793 for (port = 0; port < host->n_ports; port++) {
cbcdd875 2794 struct ata_port *ap = host->ports[port];
2a47ce06 2795 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 2796
2797 mv_port_init(&ap->ioaddr, port_mmio);
2798
7bb3c529 2799#ifdef CONFIG_PCI
f351b2d6
SB		 2800 if (HAS_PCI(host)) {
2801 unsigned int offset = port_mmio - mmio;
2802 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
2803 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
2804 }
7bb3c529 2805#endif
20f733e7
BR		 2806 }
2807
2808 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 2809 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2810
2811 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2812 "(before clear)=0x%08x\n", hc,
2813 readl(hc_mmio + HC_CFG_OFS),
2814 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2815
2816 /* Clear any currently outstanding hc interrupt conditions */
2817 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 2818 }
2819
f351b2d6
SB		 2820 if (HAS_PCI(host)) {
2821 /* Clear any currently outstanding host interrupt conditions */
2822 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 2823
f351b2d6
SB		 2824 /* and unmask interrupt generation for host regs */
2825 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
2826 if (IS_GEN_I(hpriv))
2827 writelfl(~HC_MAIN_MASKED_IRQS_5,
7368f919 2828 hpriv->main_irq_mask_addr);
f351b2d6
SB		 2829 else
2830 writelfl(~HC_MAIN_MASKED_IRQS,
7368f919 2831 hpriv->main_irq_mask_addr);
f351b2d6
SB		 2832
2833 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2834 "PCI int cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 2835 readl(hpriv->main_irq_cause_addr),
2836 readl(hpriv->main_irq_mask_addr),
f351b2d6
SB		 2837 readl(mmio + hpriv->irq_cause_ofs),
2838 readl(mmio + hpriv->irq_mask_ofs));
2839 } else {
2840 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
7368f919 2841 hpriv->main_irq_mask_addr);
f351b2d6 2842 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 2843 readl(hpriv->main_irq_cause_addr),
2844 readl(hpriv->main_irq_mask_addr));
f351b2d6
SB		 2845 }
2846done:
2847 return rc;
2848}
fb621e2f 2849
fbf14e2f
BB		 2850static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
2851{
2852 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
2853 MV_CRQB_Q_SZ, 0);
2854 if (!hpriv->crqb_pool)
2855 return -ENOMEM;
2856
2857 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
2858 MV_CRPB_Q_SZ, 0);
2859 if (!hpriv->crpb_pool)
2860 return -ENOMEM;
2861
2862 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
2863 MV_SG_TBL_SZ, 0);
2864 if (!hpriv->sg_tbl_pool)
2865 return -ENOMEM;
2866
2867 return 0;
2868}
2869
15a32632
LB		 2870static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
2871 struct mbus_dram_target_info *dram)
2872{
2873 int i;
2874
2875 for (i = 0; i < 4; i++) {
2876 writel(0, hpriv->base + WINDOW_CTRL(i));
2877 writel(0, hpriv->base + WINDOW_BASE(i));
2878 }
2879
2880 for (i = 0; i < dram->num_cs; i++) {
2881 struct mbus_dram_window *cs = dram->cs + i;
2882
2883 writel(((cs->size - 1) & 0xffff0000) |
2884 (cs->mbus_attr << 8) |
2885 (dram->mbus_dram_target_id << 4) | 1,
2886 hpriv->base + WINDOW_CTRL(i));
2887 writel(cs->base, hpriv->base + WINDOW_BASE(i));
2888 }
2889}
2890
f351b2d6
SB		 2891/**
2892 * mv_platform_probe - handle a positive probe of an soc Marvell
2893 * host
2894 * @pdev: platform device found
2895 *
2896 * LOCKING:
2897 * Inherited from caller.
2898 */
2899static int mv_platform_probe(struct platform_device *pdev)
2900{
2901 static int printed_version;
2902 const struct mv_sata_platform_data *mv_platform_data;
2903 const struct ata_port_info *ppi[] =
2904 { &mv_port_info[chip_soc], NULL };
2905 struct ata_host *host;
2906 struct mv_host_priv *hpriv;
2907 struct resource *res;
2908 int n_ports, rc;
20f733e7 2909
f351b2d6
SB		 2910 if (!printed_version++)
2911 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 2912
f351b2d6
SB		 2913 /*
2914 * Simple resource validation ..
2915 */
2916 if (unlikely(pdev->num_resources != 2)) {
2917 dev_err(&pdev->dev, "invalid number of resources\n");
2918 return -EINVAL;
2919 }
2920
2921 /*
2922 * Get the register base first
2923 */
2924 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2925 if (res == NULL)
2926 return -EINVAL;
2927
2928 /* allocate host */
2929 mv_platform_data = pdev->dev.platform_data;
2930 n_ports = mv_platform_data->n_ports;
2931
2932 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2933 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2934
2935 if (!host || !hpriv)
2936 return -ENOMEM;
2937 host->private_data = hpriv;
2938 hpriv->n_ports = n_ports;
2939
2940 host->iomap = NULL;
f1cb0ea1
SB		 2941 hpriv->base = devm_ioremap(&pdev->dev, res->start,
2942 res->end - res->start + 1);
f351b2d6
SB		 2943 hpriv->base -= MV_SATAHC0_REG_BASE;
2944
15a32632
LB		 2945 /*
2946 * (Re-)program MBUS remapping windows if we are asked to.
2947 */
2948 if (mv_platform_data->dram != NULL)
2949 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
2950
fbf14e2f
BB		 2951 rc = mv_create_dma_pools(hpriv, &pdev->dev);
2952 if (rc)
2953 return rc;
2954
f351b2d6
SB		 2955 /* initialize adapter */
2956 rc = mv_init_host(host, chip_soc);
2957 if (rc)
2958 return rc;
2959
2960 dev_printk(KERN_INFO, &pdev->dev,
2961 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
2962 host->n_ports);
2963
2964 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
2965 IRQF_SHARED, &mv6_sht);
2966}
2967
2968/*
2969 *
2970 * mv_platform_remove - unplug a platform interface
2971 * @pdev: platform device
2972 *
2973 * A platform bus SATA device has been unplugged. Perform the needed
2974 * cleanup. Also called on module unload for any active devices.
2975 */
2976static int __devexit mv_platform_remove(struct platform_device *pdev)
2977{
2978 struct device *dev = &pdev->dev;
2979 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 2980
2981 ata_host_detach(host);
f351b2d6 2982 return 0;
20f733e7
BR		 2983}
2984
f351b2d6
SB		 2985static struct platform_driver mv_platform_driver = {
2986 .probe = mv_platform_probe,
2987 .remove = __devexit_p(mv_platform_remove),
2988 .driver = {
2989 .name = DRV_NAME,
2990 .owner = THIS_MODULE,
2991 },
2992};
2993
2994
7bb3c529 2995#ifdef CONFIG_PCI
f351b2d6
SB		 2996static int mv_pci_init_one(struct pci_dev *pdev,
2997 const struct pci_device_id *ent);
2998
7bb3c529
SB		 2999
3000static struct pci_driver mv_pci_driver = {
3001 .name = DRV_NAME,
3002 .id_table = mv_pci_tbl,
f351b2d6 3003 .probe = mv_pci_init_one,
7bb3c529
SB		 3004 .remove = ata_pci_remove_one,
3005};
3006
3007/*
3008 * module options
3009 */
3010static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3011
3012
3013/* move to PCI layer or libata core? */
3014static int pci_go_64(struct pci_dev *pdev)
3015{
3016 int rc;
3017
3018 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3019 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3020 if (rc) {
3021 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3022 if (rc) {
3023 dev_printk(KERN_ERR, &pdev->dev,
3024 "64-bit DMA enable failed\n");
3025 return rc;
3026 }
3027 }
3028 } else {
3029 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3030 if (rc) {
3031 dev_printk(KERN_ERR, &pdev->dev,
3032 "32-bit DMA enable failed\n");
3033 return rc;
3034 }
3035 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3036 if (rc) {
3037 dev_printk(KERN_ERR, &pdev->dev,
3038 "32-bit consistent DMA enable failed\n");
3039 return rc;
3040 }
3041 }
3042
3043 return rc;
3044}
3045
05b308e1
BR		 3046/**
3047 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3048 * @host: ATA host to print info about
05b308e1
BR		 3049 *
3050 * FIXME: complete this.
3051 *
3052 * LOCKING:
3053 * Inherited from caller.
3054 */
4447d351 3055static void mv_print_info(struct ata_host *host)
31961943 3056{
4447d351
TH		 3057 struct pci_dev *pdev = to_pci_dev(host->dev);
3058 struct mv_host_priv *hpriv = host->private_data;
44c10138 3059 u8 scc;
c1e4fe71 3060 const char *scc_s, *gen;
31961943
BR		 3061
3062 /* Use this to determine the HW stepping of the chip so we know
3063 * what errata to workaround
3064 */
31961943
BR		 3065 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3066 if (scc == 0)
3067 scc_s = "SCSI";
3068 else if (scc == 0x01)
3069 scc_s = "RAID";
3070 else
c1e4fe71
JG		 3071 scc_s = "?";
3072
3073 if (IS_GEN_I(hpriv))
3074 gen = "I";
3075 else if (IS_GEN_II(hpriv))
3076 gen = "II";
3077 else if (IS_GEN_IIE(hpriv))
3078 gen = "IIE";
3079 else
3080 gen = "?";
31961943 3081
a9524a76 3082 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3083 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3084 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3085 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3086}
3087
05b308e1 3088/**
f351b2d6 3089 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3090 * @pdev: PCI device found
3091 * @ent: PCI device ID entry for the matched host
3092 *
3093 * LOCKING:
3094 * Inherited from caller.
3095 */
f351b2d6
SB		 3096static int mv_pci_init_one(struct pci_dev *pdev,
3097 const struct pci_device_id *ent)
20f733e7 3098{
2dcb407e 3099 static int printed_version;
20f733e7 3100 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3101 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3102 struct ata_host *host;
3103 struct mv_host_priv *hpriv;
3104 int n_ports, rc;
20f733e7 3105
a9524a76
JG		 3106 if (!printed_version++)
3107 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3108
4447d351
TH		 3109 /* allocate host */
3110 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3111
3112 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3113 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3114 if (!host || !hpriv)
3115 return -ENOMEM;
3116 host->private_data = hpriv;
f351b2d6 3117 hpriv->n_ports = n_ports;
4447d351
TH		 3118
3119 /* acquire resources */
24dc5f33
TH		 3120 rc = pcim_enable_device(pdev);
3121 if (rc)
20f733e7 3122 return rc;
20f733e7 3123
0d5ff566
TH		 3124 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3125 if (rc == -EBUSY)
24dc5f33 3126 pcim_pin_device(pdev);
0d5ff566 3127 if (rc)
24dc5f33 3128 return rc;
4447d351 3129 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3130 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3131
d88184fb
JG		 3132 rc = pci_go_64(pdev);
3133 if (rc)
3134 return rc;
3135
da2fa9ba
ML		 3136 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3137 if (rc)
3138 return rc;
3139
20f733e7 3140 /* initialize adapter */
4447d351 3141 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3142 if (rc)
3143 return rc;
20f733e7 3144
31961943 3145 /* Enable interrupts */
6a59dcf8 3146 if (msi && pci_enable_msi(pdev))
31961943 3147 pci_intx(pdev, 1);
20f733e7 3148
31961943 3149 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3150 mv_print_info(host);
20f733e7 3151
4447d351 3152 pci_set_master(pdev);
ea8b4db9 3153 pci_try_set_mwi(pdev);
4447d351 3154 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3155 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3156}
7bb3c529 3157#endif
20f733e7 3158
f351b2d6
SB		 3159static int mv_platform_probe(struct platform_device *pdev);
3160static int __devexit mv_platform_remove(struct platform_device *pdev);
3161
20f733e7
BR		 3162static int __init mv_init(void)
3163{
7bb3c529
SB		 3164 int rc = -ENODEV;
3165#ifdef CONFIG_PCI
3166 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3167 if (rc < 0)
3168 return rc;
3169#endif
3170 rc = platform_driver_register(&mv_platform_driver);
3171
3172#ifdef CONFIG_PCI
3173 if (rc < 0)
3174 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3175#endif
3176 return rc;
20f733e7
BR		 3177}
3178
3179static void __exit mv_exit(void)
3180{
7bb3c529 3181#ifdef CONFIG_PCI
20f733e7 3182 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3183#endif
f351b2d6 3184 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3185}
3186
3187MODULE_AUTHOR("Brett Russ");
3188MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3189MODULE_LICENSE("GPL");
3190MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3191MODULE_VERSION(DRV_VERSION);
17c5aab5 3192MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3193
7bb3c529 3194#ifdef CONFIG_PCI
ddef9bb3
JG		 3195module_param(msi, int, 0444);
3196MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3197#endif
ddef9bb3 3198
20f733e7
BR		 3199module_init(mv_init);
3200module_exit(mv_exit);
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