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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
a9524a76 | 41 | #include <linux/device.h> |
1da177e4 | 42 | #include <scsi/scsi_host.h> |
193515d5 | 43 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
44 | #include <linux/libata.h> |
45 | #include <asm/io.h> | |
46 | #include "sata_promise.h" | |
47 | ||
48 | #define DRV_NAME "sata_promise" | |
6340f019 | 49 | #define DRV_VERSION "1.04" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | |
54 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
55 | PDC_TBG_MODE = 0x41, /* TBG mode */ | |
56 | PDC_FLASH_CTL = 0x44, /* Flash control register */ | |
57 | PDC_PCI_CTL = 0x48, /* PCI control and status register */ | |
58 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ | |
59 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
60 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 61 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
1da177e4 LT |
62 | PDC_SLEW_CTL = 0x470, /* slew rate control reg */ |
63 | ||
64 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
65 | (1<<8) | (1<<9) | (1<<10), | |
66 | ||
67 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
68 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 69 | board_20619 = 2, /* FastTrak TX4000 */ |
5a46fe89 | 70 | board_20771 = 3, /* FastTrak TX2300 */ |
6340f019 LK |
71 | board_2057x = 4, /* SATAII150 Tx2plus */ |
72 | board_40518 = 5, /* SATAII150 Tx4 */ | |
1da177e4 | 73 | |
6340f019 | 74 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 LT |
75 | |
76 | PDC_RESET = (1 << 11), /* HDMA reset */ | |
50630195 JG |
77 | |
78 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST | | |
3d0a59c0 JG |
79 | ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | |
80 | ATA_FLAG_PIO_POLLING, | |
1da177e4 LT |
81 | }; |
82 | ||
83 | ||
84 | struct pdc_port_priv { | |
85 | u8 *pkt; | |
86 | dma_addr_t pkt_dma; | |
87 | }; | |
88 | ||
6340f019 LK |
89 | struct pdc_host_priv { |
90 | int hotplug_offset; | |
91 | }; | |
92 | ||
1da177e4 LT |
93 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); |
94 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
95 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
7d12e780 | 96 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance); |
1da177e4 LT |
97 | static void pdc_eng_timeout(struct ata_port *ap); |
98 | static int pdc_port_start(struct ata_port *ap); | |
99 | static void pdc_port_stop(struct ata_port *ap); | |
2cba582a JG |
100 | static void pdc_pata_phy_reset(struct ata_port *ap); |
101 | static void pdc_sata_phy_reset(struct ata_port *ap); | |
1da177e4 | 102 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
103 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
104 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
1da177e4 | 105 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 106 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
cca3974e | 107 | static void pdc_host_stop(struct ata_host *host); |
1da177e4 | 108 | |
374b1873 | 109 | |
193515d5 | 110 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
111 | .module = THIS_MODULE, |
112 | .name = DRV_NAME, | |
113 | .ioctl = ata_scsi_ioctl, | |
114 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
115 | .can_queue = ATA_DEF_QUEUE, |
116 | .this_id = ATA_SHT_THIS_ID, | |
117 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
118 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
119 | .emulated = ATA_SHT_EMULATED, | |
120 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
121 | .proc_name = DRV_NAME, | |
122 | .dma_boundary = ATA_DMA_BOUNDARY, | |
123 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 124 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 125 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
126 | }; |
127 | ||
057ace5e | 128 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
129 | .port_disable = ata_port_disable, |
130 | .tf_load = pdc_tf_load_mmio, | |
131 | .tf_read = ata_tf_read, | |
132 | .check_status = ata_check_status, | |
133 | .exec_command = pdc_exec_command_mmio, | |
134 | .dev_select = ata_std_dev_select, | |
2cba582a JG |
135 | |
136 | .phy_reset = pdc_sata_phy_reset, | |
137 | ||
1da177e4 LT |
138 | .qc_prep = pdc_qc_prep, |
139 | .qc_issue = pdc_qc_issue_prot, | |
140 | .eng_timeout = pdc_eng_timeout, | |
a6b2c5d4 | 141 | .data_xfer = ata_mmio_data_xfer, |
1da177e4 LT |
142 | .irq_handler = pdc_interrupt, |
143 | .irq_clear = pdc_irq_clear, | |
2cba582a | 144 | |
1da177e4 LT |
145 | .scr_read = pdc_sata_scr_read, |
146 | .scr_write = pdc_sata_scr_write, | |
147 | .port_start = pdc_port_start, | |
148 | .port_stop = pdc_port_stop, | |
6340f019 | 149 | .host_stop = pdc_host_stop, |
1da177e4 LT |
150 | }; |
151 | ||
057ace5e | 152 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
153 | .port_disable = ata_port_disable, |
154 | .tf_load = pdc_tf_load_mmio, | |
155 | .tf_read = ata_tf_read, | |
156 | .check_status = ata_check_status, | |
157 | .exec_command = pdc_exec_command_mmio, | |
158 | .dev_select = ata_std_dev_select, | |
159 | ||
160 | .phy_reset = pdc_pata_phy_reset, | |
161 | ||
162 | .qc_prep = pdc_qc_prep, | |
163 | .qc_issue = pdc_qc_issue_prot, | |
a6b2c5d4 | 164 | .data_xfer = ata_mmio_data_xfer, |
2cba582a JG |
165 | .eng_timeout = pdc_eng_timeout, |
166 | .irq_handler = pdc_interrupt, | |
167 | .irq_clear = pdc_irq_clear, | |
168 | ||
169 | .port_start = pdc_port_start, | |
170 | .port_stop = pdc_port_stop, | |
6340f019 | 171 | .host_stop = pdc_host_stop, |
2cba582a JG |
172 | }; |
173 | ||
98ac62de | 174 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
175 | /* board_2037x */ |
176 | { | |
177 | .sht = &pdc_ata_sht, | |
cca3974e | 178 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
179 | .pio_mask = 0x1f, /* pio0-4 */ |
180 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
181 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 182 | .port_ops = &pdc_sata_ops, |
1da177e4 LT |
183 | }, |
184 | ||
185 | /* board_20319 */ | |
186 | { | |
187 | .sht = &pdc_ata_sht, | |
cca3974e | 188 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
189 | .pio_mask = 0x1f, /* pio0-4 */ |
190 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
191 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 192 | .port_ops = &pdc_sata_ops, |
1da177e4 | 193 | }, |
f497ba73 TL |
194 | |
195 | /* board_20619 */ | |
196 | { | |
197 | .sht = &pdc_ata_sht, | |
cca3974e | 198 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, |
f497ba73 TL |
199 | .pio_mask = 0x1f, /* pio0-4 */ |
200 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
201 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 202 | .port_ops = &pdc_pata_ops, |
f497ba73 | 203 | }, |
5a46fe89 YI |
204 | |
205 | /* board_20771 */ | |
206 | { | |
207 | .sht = &pdc_ata_sht, | |
cca3974e | 208 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
5a46fe89 YI |
209 | .pio_mask = 0x1f, /* pio0-4 */ |
210 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
211 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
212 | .port_ops = &pdc_sata_ops, | |
213 | }, | |
6340f019 LK |
214 | |
215 | /* board_2057x */ | |
216 | { | |
217 | .sht = &pdc_ata_sht, | |
cca3974e | 218 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
6340f019 LK |
219 | .pio_mask = 0x1f, /* pio0-4 */ |
220 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
221 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
222 | .port_ops = &pdc_sata_ops, | |
223 | }, | |
224 | ||
225 | /* board_40518 */ | |
226 | { | |
227 | .sht = &pdc_ata_sht, | |
cca3974e | 228 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
6340f019 LK |
229 | .pio_mask = 0x1f, /* pio0-4 */ |
230 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
231 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
232 | .port_ops = &pdc_sata_ops, | |
233 | }, | |
1da177e4 LT |
234 | }; |
235 | ||
3b7d697d | 236 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 JG |
237 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
238 | { PCI_VDEVICE(PROMISE, 0x3570), board_2037x }, | |
239 | { PCI_VDEVICE(PROMISE, 0x3571), board_2037x }, | |
240 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, | |
241 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
242 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
243 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, | |
244 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, | |
245 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2037x }, | |
246 | ||
247 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
248 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
249 | { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, | |
250 | { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, | |
251 | { PCI_VDEVICE(PROMISE, 0x3d17), board_20319 }, | |
252 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, | |
253 | ||
254 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 255 | |
8419dc8a JG |
256 | /* TODO: remove all associated board_20771 code, as it completely |
257 | * duplicates board_2037x code, unless reason for separation can be | |
258 | * divined. | |
259 | */ | |
260 | #if 0 | |
54bb3a94 | 261 | { PCI_VDEVICE(PROMISE, 0x3570), board_20771 }, |
8419dc8a JG |
262 | #endif |
263 | ||
1da177e4 LT |
264 | { } /* terminate list */ |
265 | }; | |
266 | ||
267 | ||
268 | static struct pci_driver pdc_ata_pci_driver = { | |
269 | .name = DRV_NAME, | |
270 | .id_table = pdc_ata_pci_tbl, | |
271 | .probe = pdc_ata_init_one, | |
272 | .remove = ata_pci_remove_one, | |
273 | }; | |
274 | ||
275 | ||
276 | static int pdc_port_start(struct ata_port *ap) | |
277 | { | |
cca3974e | 278 | struct device *dev = ap->host->dev; |
1da177e4 LT |
279 | struct pdc_port_priv *pp; |
280 | int rc; | |
281 | ||
282 | rc = ata_port_start(ap); | |
283 | if (rc) | |
284 | return rc; | |
285 | ||
6340f019 | 286 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
1da177e4 LT |
287 | if (!pp) { |
288 | rc = -ENOMEM; | |
289 | goto err_out; | |
290 | } | |
1da177e4 LT |
291 | |
292 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
293 | if (!pp->pkt) { | |
294 | rc = -ENOMEM; | |
295 | goto err_out_kfree; | |
296 | } | |
297 | ||
298 | ap->private_data = pp; | |
299 | ||
300 | return 0; | |
301 | ||
302 | err_out_kfree: | |
303 | kfree(pp); | |
304 | err_out: | |
305 | ata_port_stop(ap); | |
306 | return rc; | |
307 | } | |
308 | ||
309 | ||
310 | static void pdc_port_stop(struct ata_port *ap) | |
311 | { | |
cca3974e | 312 | struct device *dev = ap->host->dev; |
1da177e4 LT |
313 | struct pdc_port_priv *pp = ap->private_data; |
314 | ||
315 | ap->private_data = NULL; | |
316 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
317 | kfree(pp); | |
318 | ata_port_stop(ap); | |
319 | } | |
320 | ||
321 | ||
cca3974e | 322 | static void pdc_host_stop(struct ata_host *host) |
6340f019 | 323 | { |
cca3974e | 324 | struct pdc_host_priv *hp = host->private_data; |
6340f019 | 325 | |
cca3974e | 326 | ata_pci_host_stop(host); |
6340f019 LK |
327 | |
328 | kfree(hp); | |
329 | } | |
330 | ||
331 | ||
1da177e4 LT |
332 | static void pdc_reset_port(struct ata_port *ap) |
333 | { | |
ea6ba10b | 334 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
335 | unsigned int i; |
336 | u32 tmp; | |
337 | ||
338 | for (i = 11; i > 0; i--) { | |
339 | tmp = readl(mmio); | |
340 | if (tmp & PDC_RESET) | |
341 | break; | |
342 | ||
343 | udelay(100); | |
344 | ||
345 | tmp |= PDC_RESET; | |
346 | writel(tmp, mmio); | |
347 | } | |
348 | ||
349 | tmp &= ~PDC_RESET; | |
350 | writel(tmp, mmio); | |
351 | readl(mmio); /* flush */ | |
352 | } | |
353 | ||
2cba582a | 354 | static void pdc_sata_phy_reset(struct ata_port *ap) |
1da177e4 LT |
355 | { |
356 | pdc_reset_port(ap); | |
357 | sata_phy_reset(ap); | |
358 | } | |
359 | ||
d3fb4e8d | 360 | static void pdc_pata_cbl_detect(struct ata_port *ap) |
2cba582a | 361 | { |
d3fb4e8d JG |
362 | u8 tmp; |
363 | void __iomem *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; | |
364 | ||
365 | tmp = readb(mmio); | |
366 | ||
367 | if (tmp & 0x01) { | |
368 | ap->cbl = ATA_CBL_PATA40; | |
369 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
370 | } else | |
371 | ap->cbl = ATA_CBL_PATA80; | |
372 | } | |
2cba582a | 373 | |
d3fb4e8d JG |
374 | static void pdc_pata_phy_reset(struct ata_port *ap) |
375 | { | |
376 | pdc_pata_cbl_detect(ap); | |
2cba582a JG |
377 | pdc_reset_port(ap); |
378 | ata_port_probe(ap); | |
379 | ata_bus_reset(ap); | |
380 | } | |
381 | ||
1da177e4 LT |
382 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
383 | { | |
384 | if (sc_reg > SCR_CONTROL) | |
385 | return 0xffffffffU; | |
b181d3b0 | 386 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
387 | } |
388 | ||
389 | ||
390 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
391 | u32 val) | |
392 | { | |
393 | if (sc_reg > SCR_CONTROL) | |
394 | return; | |
b181d3b0 | 395 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
396 | } |
397 | ||
398 | static void pdc_qc_prep(struct ata_queued_cmd *qc) | |
399 | { | |
400 | struct pdc_port_priv *pp = qc->ap->private_data; | |
401 | unsigned int i; | |
402 | ||
403 | VPRINTK("ENTER\n"); | |
404 | ||
405 | switch (qc->tf.protocol) { | |
406 | case ATA_PROT_DMA: | |
407 | ata_qc_prep(qc); | |
408 | /* fall through */ | |
409 | ||
410 | case ATA_PROT_NODATA: | |
411 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
412 | qc->dev->devno, pp->pkt); | |
413 | ||
414 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
415 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
416 | else | |
417 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
418 | ||
419 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
420 | break; | |
421 | ||
422 | default: | |
423 | break; | |
424 | } | |
425 | } | |
426 | ||
427 | static void pdc_eng_timeout(struct ata_port *ap) | |
428 | { | |
cca3974e | 429 | struct ata_host *host = ap->host; |
1da177e4 LT |
430 | u8 drv_stat; |
431 | struct ata_queued_cmd *qc; | |
b8f6153e | 432 | unsigned long flags; |
1da177e4 LT |
433 | |
434 | DPRINTK("ENTER\n"); | |
435 | ||
cca3974e | 436 | spin_lock_irqsave(&host->lock, flags); |
b8f6153e | 437 | |
1da177e4 | 438 | qc = ata_qc_from_tag(ap, ap->active_tag); |
1da177e4 | 439 | |
1da177e4 LT |
440 | switch (qc->tf.protocol) { |
441 | case ATA_PROT_DMA: | |
442 | case ATA_PROT_NODATA: | |
f15a1daf | 443 | ata_port_printk(ap, KERN_ERR, "command timeout\n"); |
a7dac447 | 444 | drv_stat = ata_wait_idle(ap); |
a22e2eb0 | 445 | qc->err_mask |= __ac_err_mask(drv_stat); |
1da177e4 LT |
446 | break; |
447 | ||
448 | default: | |
449 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
450 | ||
f15a1daf TH |
451 | ata_port_printk(ap, KERN_ERR, |
452 | "unknown timeout, cmd 0x%x stat 0x%x\n", | |
453 | qc->tf.command, drv_stat); | |
1da177e4 | 454 | |
a22e2eb0 | 455 | qc->err_mask |= ac_err_mask(drv_stat); |
1da177e4 LT |
456 | break; |
457 | } | |
458 | ||
cca3974e | 459 | spin_unlock_irqrestore(&host->lock, flags); |
f6379020 | 460 | ata_eh_qc_complete(qc); |
1da177e4 LT |
461 | DPRINTK("EXIT\n"); |
462 | } | |
463 | ||
464 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
465 | struct ata_queued_cmd *qc) | |
466 | { | |
a22e2eb0 | 467 | unsigned int handled = 0; |
1da177e4 | 468 | u32 tmp; |
ea6ba10b | 469 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
470 | |
471 | tmp = readl(mmio); | |
472 | if (tmp & PDC_ERR_MASK) { | |
a22e2eb0 | 473 | qc->err_mask |= AC_ERR_DEV; |
1da177e4 LT |
474 | pdc_reset_port(ap); |
475 | } | |
476 | ||
477 | switch (qc->tf.protocol) { | |
478 | case ATA_PROT_DMA: | |
479 | case ATA_PROT_NODATA: | |
a22e2eb0 AL |
480 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
481 | ata_qc_complete(qc); | |
1da177e4 LT |
482 | handled = 1; |
483 | break; | |
484 | ||
485 | default: | |
ee500aab AL |
486 | ap->stats.idle_irq++; |
487 | break; | |
1da177e4 LT |
488 | } |
489 | ||
ee500aab | 490 | return handled; |
1da177e4 LT |
491 | } |
492 | ||
493 | static void pdc_irq_clear(struct ata_port *ap) | |
494 | { | |
cca3974e JG |
495 | struct ata_host *host = ap->host; |
496 | void __iomem *mmio = host->mmio_base; | |
1da177e4 LT |
497 | |
498 | readl(mmio + PDC_INT_SEQMASK); | |
499 | } | |
500 | ||
7d12e780 | 501 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance) |
1da177e4 | 502 | { |
cca3974e | 503 | struct ata_host *host = dev_instance; |
1da177e4 LT |
504 | struct ata_port *ap; |
505 | u32 mask = 0; | |
506 | unsigned int i, tmp; | |
507 | unsigned int handled = 0; | |
ea6ba10b | 508 | void __iomem *mmio_base; |
1da177e4 LT |
509 | |
510 | VPRINTK("ENTER\n"); | |
511 | ||
cca3974e | 512 | if (!host || !host->mmio_base) { |
1da177e4 LT |
513 | VPRINTK("QUICK EXIT\n"); |
514 | return IRQ_NONE; | |
515 | } | |
516 | ||
cca3974e | 517 | mmio_base = host->mmio_base; |
1da177e4 LT |
518 | |
519 | /* reading should also clear interrupts */ | |
520 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
521 | ||
522 | if (mask == 0xffffffff) { | |
523 | VPRINTK("QUICK EXIT 2\n"); | |
524 | return IRQ_NONE; | |
525 | } | |
6340f019 | 526 | |
cca3974e | 527 | spin_lock(&host->lock); |
6340f019 | 528 | |
1da177e4 LT |
529 | mask &= 0xffff; /* only 16 tags possible */ |
530 | if (!mask) { | |
531 | VPRINTK("QUICK EXIT 3\n"); | |
6340f019 | 532 | goto done_irq; |
1da177e4 LT |
533 | } |
534 | ||
1da177e4 LT |
535 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
536 | ||
cca3974e | 537 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 538 | VPRINTK("port %u\n", i); |
cca3974e | 539 | ap = host->ports[i]; |
1da177e4 | 540 | tmp = mask & (1 << (i + 1)); |
c1389503 | 541 | if (tmp && ap && |
029f5468 | 542 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
543 | struct ata_queued_cmd *qc; |
544 | ||
545 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 546 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
547 | handled += pdc_host_intr(ap, qc); |
548 | } | |
549 | } | |
550 | ||
1da177e4 LT |
551 | VPRINTK("EXIT\n"); |
552 | ||
6340f019 | 553 | done_irq: |
cca3974e | 554 | spin_unlock(&host->lock); |
1da177e4 LT |
555 | return IRQ_RETVAL(handled); |
556 | } | |
557 | ||
558 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
559 | { | |
560 | struct ata_port *ap = qc->ap; | |
561 | struct pdc_port_priv *pp = ap->private_data; | |
562 | unsigned int port_no = ap->port_no; | |
563 | u8 seq = (u8) (port_no + 1); | |
564 | ||
565 | VPRINTK("ENTER, ap %p\n", ap); | |
566 | ||
cca3974e JG |
567 | writel(0x00000001, ap->host->mmio_base + (seq * 4)); |
568 | readl(ap->host->mmio_base + (seq * 4)); /* flush */ | |
1da177e4 LT |
569 | |
570 | pp->pkt[2] = seq; | |
571 | wmb(); /* flush PRD, pkt writes */ | |
b181d3b0 AV |
572 | writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
573 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
574 | } |
575 | ||
9a3d9eb0 | 576 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
577 | { |
578 | switch (qc->tf.protocol) { | |
579 | case ATA_PROT_DMA: | |
580 | case ATA_PROT_NODATA: | |
581 | pdc_packet_start(qc); | |
582 | return 0; | |
583 | ||
584 | case ATA_PROT_ATAPI_DMA: | |
585 | BUG(); | |
586 | break; | |
587 | ||
588 | default: | |
589 | break; | |
590 | } | |
591 | ||
592 | return ata_qc_issue_prot(qc); | |
593 | } | |
594 | ||
057ace5e | 595 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
596 | { |
597 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
598 | tf->protocol == ATA_PROT_NODATA); | |
599 | ata_tf_load(ap, tf); | |
600 | } | |
601 | ||
602 | ||
057ace5e | 603 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
604 | { |
605 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
606 | tf->protocol == ATA_PROT_NODATA); | |
607 | ata_exec_command(ap, tf); | |
608 | } | |
609 | ||
610 | ||
611 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
612 | { | |
613 | port->cmd_addr = base; | |
614 | port->data_addr = base; | |
615 | port->feature_addr = | |
616 | port->error_addr = base + 0x4; | |
617 | port->nsect_addr = base + 0x8; | |
618 | port->lbal_addr = base + 0xc; | |
619 | port->lbam_addr = base + 0x10; | |
620 | port->lbah_addr = base + 0x14; | |
621 | port->device_addr = base + 0x18; | |
622 | port->command_addr = | |
623 | port->status_addr = base + 0x1c; | |
624 | port->altstatus_addr = | |
625 | port->ctl_addr = base + 0x38; | |
626 | } | |
627 | ||
628 | ||
629 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
630 | { | |
ea6ba10b | 631 | void __iomem *mmio = pe->mmio_base; |
6340f019 LK |
632 | struct pdc_host_priv *hp = pe->private_data; |
633 | int hotplug_offset = hp->hotplug_offset; | |
1da177e4 LT |
634 | u32 tmp; |
635 | ||
636 | /* | |
637 | * Except for the hotplug stuff, this is voodoo from the | |
638 | * Promise driver. Label this entire section | |
639 | * "TODO: figure out why we do this" | |
640 | */ | |
641 | ||
642 | /* change FIFO_SHD to 8 dwords, enable BMR_BURST */ | |
643 | tmp = readl(mmio + PDC_FLASH_CTL); | |
644 | tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */ | |
645 | writel(tmp, mmio + PDC_FLASH_CTL); | |
646 | ||
647 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
648 | tmp = readl(mmio + hotplug_offset); |
649 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 LT |
650 | |
651 | /* mask plug/unplug ints */ | |
6340f019 LK |
652 | tmp = readl(mmio + hotplug_offset); |
653 | writel(tmp | 0xff0000, mmio + hotplug_offset); | |
1da177e4 LT |
654 | |
655 | /* reduce TBG clock to 133 Mhz. */ | |
656 | tmp = readl(mmio + PDC_TBG_MODE); | |
657 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
658 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
659 | writel(tmp, mmio + PDC_TBG_MODE); | |
660 | ||
661 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
662 | msleep(10); | |
663 | ||
664 | /* adjust slew rate control register. */ | |
665 | tmp = readl(mmio + PDC_SLEW_CTL); | |
666 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
667 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
668 | writel(tmp, mmio + PDC_SLEW_CTL); | |
669 | } | |
670 | ||
671 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
672 | { | |
673 | static int printed_version; | |
674 | struct ata_probe_ent *probe_ent = NULL; | |
6340f019 | 675 | struct pdc_host_priv *hp; |
1da177e4 | 676 | unsigned long base; |
ea6ba10b | 677 | void __iomem *mmio_base; |
1da177e4 LT |
678 | unsigned int board_idx = (unsigned int) ent->driver_data; |
679 | int pci_dev_busy = 0; | |
680 | int rc; | |
681 | ||
682 | if (!printed_version++) | |
a9524a76 | 683 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 684 | |
1da177e4 LT |
685 | rc = pci_enable_device(pdev); |
686 | if (rc) | |
687 | return rc; | |
688 | ||
689 | rc = pci_request_regions(pdev, DRV_NAME); | |
690 | if (rc) { | |
691 | pci_dev_busy = 1; | |
692 | goto err_out; | |
693 | } | |
694 | ||
695 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
696 | if (rc) | |
697 | goto err_out_regions; | |
698 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
699 | if (rc) | |
700 | goto err_out_regions; | |
701 | ||
6340f019 | 702 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
1da177e4 LT |
703 | if (probe_ent == NULL) { |
704 | rc = -ENOMEM; | |
705 | goto err_out_regions; | |
706 | } | |
707 | ||
1da177e4 LT |
708 | probe_ent->dev = pci_dev_to_dev(pdev); |
709 | INIT_LIST_HEAD(&probe_ent->node); | |
710 | ||
374b1873 | 711 | mmio_base = pci_iomap(pdev, 3, 0); |
1da177e4 LT |
712 | if (mmio_base == NULL) { |
713 | rc = -ENOMEM; | |
714 | goto err_out_free_ent; | |
715 | } | |
716 | base = (unsigned long) mmio_base; | |
717 | ||
6340f019 LK |
718 | hp = kzalloc(sizeof(*hp), GFP_KERNEL); |
719 | if (hp == NULL) { | |
720 | rc = -ENOMEM; | |
721 | goto err_out_free_ent; | |
722 | } | |
723 | ||
724 | /* Set default hotplug offset */ | |
725 | hp->hotplug_offset = PDC_SATA_PLUG_CSR; | |
726 | probe_ent->private_data = hp; | |
727 | ||
1da177e4 | 728 | probe_ent->sht = pdc_port_info[board_idx].sht; |
cca3974e | 729 | probe_ent->port_flags = pdc_port_info[board_idx].flags; |
1da177e4 LT |
730 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; |
731 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
732 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
733 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
734 | ||
735 | probe_ent->irq = pdev->irq; | |
1d6f359a | 736 | probe_ent->irq_flags = IRQF_SHARED; |
1da177e4 LT |
737 | probe_ent->mmio_base = mmio_base; |
738 | ||
739 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
740 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
741 | ||
742 | probe_ent->port[0].scr_addr = base + 0x400; | |
743 | probe_ent->port[1].scr_addr = base + 0x500; | |
744 | ||
745 | /* notice 4-port boards */ | |
746 | switch (board_idx) { | |
6340f019 LK |
747 | case board_40518: |
748 | /* Override hotplug offset for SATAII150 */ | |
749 | hp->hotplug_offset = PDC2_SATA_PLUG_CSR; | |
750 | /* Fall through */ | |
1da177e4 LT |
751 | case board_20319: |
752 | probe_ent->n_ports = 4; | |
753 | ||
754 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
755 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
756 | ||
757 | probe_ent->port[2].scr_addr = base + 0x600; | |
758 | probe_ent->port[3].scr_addr = base + 0x700; | |
759 | break; | |
6340f019 LK |
760 | case board_2057x: |
761 | /* Override hotplug offset for SATAII150 */ | |
762 | hp->hotplug_offset = PDC2_SATA_PLUG_CSR; | |
763 | /* Fall through */ | |
1da177e4 | 764 | case board_2037x: |
6c9e5eb5 | 765 | probe_ent->n_ports = 2; |
1da177e4 | 766 | break; |
5a46fe89 YI |
767 | case board_20771: |
768 | probe_ent->n_ports = 2; | |
769 | break; | |
f497ba73 TL |
770 | case board_20619: |
771 | probe_ent->n_ports = 4; | |
772 | ||
773 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
774 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
775 | ||
776 | probe_ent->port[2].scr_addr = base + 0x600; | |
777 | probe_ent->port[3].scr_addr = base + 0x700; | |
6c9e5eb5 | 778 | break; |
1da177e4 LT |
779 | default: |
780 | BUG(); | |
781 | break; | |
782 | } | |
783 | ||
784 | pci_set_master(pdev); | |
785 | ||
786 | /* initialize adapter */ | |
787 | pdc_host_init(board_idx, probe_ent); | |
788 | ||
6340f019 LK |
789 | /* FIXME: Need any other frees than hp? */ |
790 | if (!ata_device_add(probe_ent)) | |
791 | kfree(hp); | |
792 | ||
1da177e4 LT |
793 | kfree(probe_ent); |
794 | ||
795 | return 0; | |
796 | ||
797 | err_out_free_ent: | |
798 | kfree(probe_ent); | |
799 | err_out_regions: | |
800 | pci_release_regions(pdev); | |
801 | err_out: | |
802 | if (!pci_dev_busy) | |
803 | pci_disable_device(pdev); | |
804 | return rc; | |
805 | } | |
806 | ||
807 | ||
808 | static int __init pdc_ata_init(void) | |
809 | { | |
b7887196 | 810 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
811 | } |
812 | ||
813 | ||
814 | static void __exit pdc_ata_exit(void) | |
815 | { | |
816 | pci_unregister_driver(&pdc_ata_pci_driver); | |
817 | } | |
818 | ||
819 | ||
820 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 821 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
822 | MODULE_LICENSE("GPL"); |
823 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
824 | MODULE_VERSION(DRV_VERSION); | |
825 | ||
826 | module_init(pdc_ata_init); | |
827 | module_exit(pdc_ata_exit); |