]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * sata_qstor.c - Pacific Digital Corporation QStor SATA | |
3 | * | |
4 | * Maintained by: Mark Lord <mlord@pobox.com> | |
5 | * | |
6 | * Copyright 2005 Pacific Digital Corporation. | |
7 | * (OSL/GPL code release authorized by Jalil Fadavi). | |
8 | * | |
af36d7f0 JG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; see the file COPYING. If not, write to | |
22 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | * | |
24 | * | |
25 | * libata documentation is available via 'make {ps|pdf}docs', | |
26 | * as Documentation/DocBook/libata.* | |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/blkdev.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/sched.h> | |
a9524a76 | 38 | #include <linux/device.h> |
1da177e4 LT |
39 | #include <scsi/scsi_host.h> |
40 | #include <asm/io.h> | |
41 | #include <linux/libata.h> | |
42 | ||
43 | #define DRV_NAME "sata_qstor" | |
af64371a | 44 | #define DRV_VERSION "0.06" |
1da177e4 LT |
45 | |
46 | enum { | |
47 | QS_PORTS = 4, | |
48 | QS_MAX_PRD = LIBATA_MAX_PRD, | |
49 | QS_CPB_ORDER = 6, | |
50 | QS_CPB_BYTES = (1 << QS_CPB_ORDER), | |
51 | QS_PRD_BYTES = QS_MAX_PRD * 16, | |
52 | QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES, | |
53 | ||
1da177e4 LT |
54 | /* global register offsets */ |
55 | QS_HCF_CNFG3 = 0x0003, /* host configuration offset */ | |
56 | QS_HID_HPHY = 0x0004, /* host physical interface info */ | |
57 | QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */ | |
58 | QS_HST_SFF = 0x0100, /* host status fifo offset */ | |
59 | QS_HVS_SERD3 = 0x0393, /* PHY enable offset */ | |
60 | ||
61 | /* global control bits */ | |
62 | QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */ | |
63 | QS_CNFG3_GSRST = 0x01, /* global chip reset */ | |
64 | QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/ | |
65 | ||
66 | /* per-channel register offsets */ | |
67 | QS_CCF_CPBA = 0x0710, /* chan CPB base address */ | |
68 | QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */ | |
69 | QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */ | |
70 | QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */ | |
71 | QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */ | |
72 | QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */ | |
73 | QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */ | |
74 | QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */ | |
75 | QS_CCT_CFF = 0x0a00, /* chan command fifo offset */ | |
76 | ||
77 | /* channel control bits */ | |
78 | QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */ | |
79 | QS_CTR0_CLER = (1 << 2), /* clear channel errors */ | |
80 | QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */ | |
81 | QS_CTR1_RCHN = (1 << 4), /* reset channel logic */ | |
82 | QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */ | |
83 | ||
84 | /* pkt sub-field headers */ | |
85 | QS_HCB_HDR = 0x01, /* Host Control Block header */ | |
86 | QS_DCB_HDR = 0x02, /* Device Control Block header */ | |
87 | ||
88 | /* pkt HCB flag bits */ | |
89 | QS_HF_DIRO = (1 << 0), /* data DIRection Out */ | |
90 | QS_HF_DAT = (1 << 3), /* DATa pkt */ | |
91 | QS_HF_IEN = (1 << 4), /* Interrupt ENable */ | |
92 | QS_HF_VLD = (1 << 5), /* VaLiD pkt */ | |
93 | ||
94 | /* pkt DCB flag bits */ | |
95 | QS_DF_PORD = (1 << 2), /* Pio OR Dma */ | |
96 | QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */ | |
97 | ||
98 | /* PCI device IDs */ | |
99 | board_2068_idx = 0, /* QStor 4-port SATA/RAID */ | |
100 | }; | |
101 | ||
0420dd12 AV |
102 | enum { |
103 | QS_DMA_BOUNDARY = ~0UL | |
104 | }; | |
105 | ||
1da177e4 LT |
106 | typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t; |
107 | ||
108 | struct qs_port_priv { | |
109 | u8 *pkt; | |
110 | dma_addr_t pkt_dma; | |
111 | qs_state_t state; | |
112 | }; | |
113 | ||
114 | static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
115 | static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
116 | static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
117 | static irqreturn_t qs_intr (int irq, void *dev_instance, struct pt_regs *regs); | |
118 | static int qs_port_start(struct ata_port *ap); | |
cca3974e | 119 | static void qs_host_stop(struct ata_host *host); |
1da177e4 LT |
120 | static void qs_port_stop(struct ata_port *ap); |
121 | static void qs_phy_reset(struct ata_port *ap); | |
122 | static void qs_qc_prep(struct ata_queued_cmd *qc); | |
9a3d9eb0 | 123 | static unsigned int qs_qc_issue(struct ata_queued_cmd *qc); |
1da177e4 | 124 | static int qs_check_atapi_dma(struct ata_queued_cmd *qc); |
b73fc89f | 125 | static void qs_bmdma_stop(struct ata_queued_cmd *qc); |
1da177e4 LT |
126 | static u8 qs_bmdma_status(struct ata_port *ap); |
127 | static void qs_irq_clear(struct ata_port *ap); | |
128 | static void qs_eng_timeout(struct ata_port *ap); | |
129 | ||
193515d5 | 130 | static struct scsi_host_template qs_ata_sht = { |
1da177e4 LT |
131 | .module = THIS_MODULE, |
132 | .name = DRV_NAME, | |
133 | .ioctl = ata_scsi_ioctl, | |
134 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
135 | .can_queue = ATA_DEF_QUEUE, |
136 | .this_id = ATA_SHT_THIS_ID, | |
137 | .sg_tablesize = QS_MAX_PRD, | |
1da177e4 LT |
138 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
139 | .emulated = ATA_SHT_EMULATED, | |
140 | //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING, | |
141 | .use_clustering = ENABLE_CLUSTERING, | |
142 | .proc_name = DRV_NAME, | |
143 | .dma_boundary = QS_DMA_BOUNDARY, | |
144 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 145 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 LT |
146 | .bios_param = ata_std_bios_param, |
147 | }; | |
148 | ||
057ace5e | 149 | static const struct ata_port_operations qs_ata_ops = { |
1da177e4 LT |
150 | .port_disable = ata_port_disable, |
151 | .tf_load = ata_tf_load, | |
152 | .tf_read = ata_tf_read, | |
153 | .check_status = ata_check_status, | |
154 | .check_atapi_dma = qs_check_atapi_dma, | |
155 | .exec_command = ata_exec_command, | |
156 | .dev_select = ata_std_dev_select, | |
157 | .phy_reset = qs_phy_reset, | |
158 | .qc_prep = qs_qc_prep, | |
159 | .qc_issue = qs_qc_issue, | |
a6b2c5d4 | 160 | .data_xfer = ata_mmio_data_xfer, |
1da177e4 LT |
161 | .eng_timeout = qs_eng_timeout, |
162 | .irq_handler = qs_intr, | |
163 | .irq_clear = qs_irq_clear, | |
164 | .scr_read = qs_scr_read, | |
165 | .scr_write = qs_scr_write, | |
166 | .port_start = qs_port_start, | |
167 | .port_stop = qs_port_stop, | |
168 | .host_stop = qs_host_stop, | |
169 | .bmdma_stop = qs_bmdma_stop, | |
170 | .bmdma_status = qs_bmdma_status, | |
171 | }; | |
172 | ||
98ac62de | 173 | static const struct ata_port_info qs_port_info[] = { |
1da177e4 LT |
174 | /* board_2068_idx */ |
175 | { | |
176 | .sht = &qs_ata_sht, | |
cca3974e | 177 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
1da177e4 LT |
178 | ATA_FLAG_SATA_RESET | |
179 | //FIXME ATA_FLAG_SRST | | |
e50362ec | 180 | ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, |
1da177e4 LT |
181 | .pio_mask = 0x10, /* pio4 */ |
182 | .udma_mask = 0x7f, /* udma0-6 */ | |
183 | .port_ops = &qs_ata_ops, | |
184 | }, | |
185 | }; | |
186 | ||
3b7d697d | 187 | static const struct pci_device_id qs_ata_pci_tbl[] = { |
2d2744fc | 188 | { PCI_VDEVICE(PDC, 0x2068), board_2068_idx }, |
1da177e4 LT |
189 | |
190 | { } /* terminate list */ | |
191 | }; | |
192 | ||
193 | static struct pci_driver qs_ata_pci_driver = { | |
194 | .name = DRV_NAME, | |
195 | .id_table = qs_ata_pci_tbl, | |
196 | .probe = qs_ata_init_one, | |
197 | .remove = ata_pci_remove_one, | |
198 | }; | |
199 | ||
200 | static int qs_check_atapi_dma(struct ata_queued_cmd *qc) | |
201 | { | |
202 | return 1; /* ATAPI DMA not supported */ | |
203 | } | |
204 | ||
d18d36b4 | 205 | static void qs_bmdma_stop(struct ata_queued_cmd *qc) |
1da177e4 LT |
206 | { |
207 | /* nothing */ | |
208 | } | |
209 | ||
210 | static u8 qs_bmdma_status(struct ata_port *ap) | |
211 | { | |
212 | return 0; | |
213 | } | |
214 | ||
215 | static void qs_irq_clear(struct ata_port *ap) | |
216 | { | |
217 | /* nothing */ | |
218 | } | |
219 | ||
220 | static inline void qs_enter_reg_mode(struct ata_port *ap) | |
221 | { | |
cca3974e | 222 | u8 __iomem *chan = ap->host->mmio_base + (ap->port_no * 0x4000); |
1da177e4 LT |
223 | |
224 | writeb(QS_CTR0_REG, chan + QS_CCT_CTR0); | |
225 | readb(chan + QS_CCT_CTR0); /* flush */ | |
226 | } | |
227 | ||
228 | static inline void qs_reset_channel_logic(struct ata_port *ap) | |
229 | { | |
cca3974e | 230 | u8 __iomem *chan = ap->host->mmio_base + (ap->port_no * 0x4000); |
1da177e4 LT |
231 | |
232 | writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1); | |
233 | readb(chan + QS_CCT_CTR0); /* flush */ | |
234 | qs_enter_reg_mode(ap); | |
235 | } | |
236 | ||
237 | static void qs_phy_reset(struct ata_port *ap) | |
238 | { | |
239 | struct qs_port_priv *pp = ap->private_data; | |
240 | ||
241 | pp->state = qs_state_idle; | |
242 | qs_reset_channel_logic(ap); | |
243 | sata_phy_reset(ap); | |
244 | } | |
245 | ||
246 | static void qs_eng_timeout(struct ata_port *ap) | |
247 | { | |
248 | struct qs_port_priv *pp = ap->private_data; | |
249 | ||
250 | if (pp->state != qs_state_idle) /* healthy paranoia */ | |
251 | pp->state = qs_state_mmio; | |
252 | qs_reset_channel_logic(ap); | |
253 | ata_eng_timeout(ap); | |
254 | } | |
255 | ||
256 | static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
257 | { | |
258 | if (sc_reg > SCR_CONTROL) | |
259 | return ~0U; | |
260 | return readl((void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8))); | |
261 | } | |
262 | ||
263 | static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
264 | { | |
265 | if (sc_reg > SCR_CONTROL) | |
266 | return; | |
267 | writel(val, (void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8))); | |
268 | } | |
269 | ||
828d09de | 270 | static unsigned int qs_fill_sg(struct ata_queued_cmd *qc) |
1da177e4 | 271 | { |
cedc9a47 | 272 | struct scatterlist *sg; |
1da177e4 LT |
273 | struct ata_port *ap = qc->ap; |
274 | struct qs_port_priv *pp = ap->private_data; | |
275 | unsigned int nelem; | |
276 | u8 *prd = pp->pkt + QS_CPB_BYTES; | |
277 | ||
beec7dbc | 278 | WARN_ON(qc->__sg == NULL); |
f131883e | 279 | WARN_ON(qc->n_elem == 0 && qc->pad_len == 0); |
1da177e4 | 280 | |
cedc9a47 JG |
281 | nelem = 0; |
282 | ata_for_each_sg(sg, qc) { | |
1da177e4 LT |
283 | u64 addr; |
284 | u32 len; | |
285 | ||
286 | addr = sg_dma_address(sg); | |
287 | *(__le64 *)prd = cpu_to_le64(addr); | |
288 | prd += sizeof(u64); | |
289 | ||
290 | len = sg_dma_len(sg); | |
291 | *(__le32 *)prd = cpu_to_le32(len); | |
292 | prd += sizeof(u64); | |
293 | ||
294 | VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem, | |
295 | (unsigned long long)addr, len); | |
cedc9a47 | 296 | nelem++; |
1da177e4 | 297 | } |
828d09de JG |
298 | |
299 | return nelem; | |
1da177e4 LT |
300 | } |
301 | ||
302 | static void qs_qc_prep(struct ata_queued_cmd *qc) | |
303 | { | |
304 | struct qs_port_priv *pp = qc->ap->private_data; | |
305 | u8 dflags = QS_DF_PORD, *buf = pp->pkt; | |
306 | u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD; | |
307 | u64 addr; | |
828d09de | 308 | unsigned int nelem; |
1da177e4 LT |
309 | |
310 | VPRINTK("ENTER\n"); | |
311 | ||
312 | qs_enter_reg_mode(qc->ap); | |
313 | if (qc->tf.protocol != ATA_PROT_DMA) { | |
314 | ata_qc_prep(qc); | |
315 | return; | |
316 | } | |
317 | ||
828d09de | 318 | nelem = qs_fill_sg(qc); |
1da177e4 LT |
319 | |
320 | if ((qc->tf.flags & ATA_TFLAG_WRITE)) | |
321 | hflags |= QS_HF_DIRO; | |
322 | if ((qc->tf.flags & ATA_TFLAG_LBA48)) | |
323 | dflags |= QS_DF_ELBA; | |
324 | ||
325 | /* host control block (HCB) */ | |
326 | buf[ 0] = QS_HCB_HDR; | |
327 | buf[ 1] = hflags; | |
328 | *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nsect * ATA_SECT_SIZE); | |
828d09de | 329 | *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem); |
1da177e4 LT |
330 | addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES; |
331 | *(__le64 *)(&buf[16]) = cpu_to_le64(addr); | |
332 | ||
333 | /* device control block (DCB) */ | |
334 | buf[24] = QS_DCB_HDR; | |
335 | buf[28] = dflags; | |
336 | ||
337 | /* frame information structure (FIS) */ | |
338 | ata_tf_to_fis(&qc->tf, &buf[32], 0); | |
339 | } | |
340 | ||
341 | static inline void qs_packet_start(struct ata_queued_cmd *qc) | |
342 | { | |
343 | struct ata_port *ap = qc->ap; | |
cca3974e | 344 | u8 __iomem *chan = ap->host->mmio_base + (ap->port_no * 0x4000); |
1da177e4 LT |
345 | |
346 | VPRINTK("ENTER, ap %p\n", ap); | |
347 | ||
348 | writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0); | |
349 | wmb(); /* flush PRDs and pkt to memory */ | |
350 | writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF); | |
351 | readl(chan + QS_CCT_CFF); /* flush */ | |
352 | } | |
353 | ||
9a3d9eb0 | 354 | static unsigned int qs_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
355 | { |
356 | struct qs_port_priv *pp = qc->ap->private_data; | |
357 | ||
358 | switch (qc->tf.protocol) { | |
359 | case ATA_PROT_DMA: | |
360 | ||
361 | pp->state = qs_state_pkt; | |
362 | qs_packet_start(qc); | |
363 | return 0; | |
364 | ||
365 | case ATA_PROT_ATAPI_DMA: | |
366 | BUG(); | |
367 | break; | |
368 | ||
369 | default: | |
370 | break; | |
371 | } | |
372 | ||
373 | pp->state = qs_state_mmio; | |
374 | return ata_qc_issue_prot(qc); | |
375 | } | |
376 | ||
cca3974e | 377 | static inline unsigned int qs_intr_pkt(struct ata_host *host) |
1da177e4 LT |
378 | { |
379 | unsigned int handled = 0; | |
380 | u8 sFFE; | |
cca3974e | 381 | u8 __iomem *mmio_base = host->mmio_base; |
1da177e4 LT |
382 | |
383 | do { | |
384 | u32 sff0 = readl(mmio_base + QS_HST_SFF); | |
385 | u32 sff1 = readl(mmio_base + QS_HST_SFF + 4); | |
386 | u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */ | |
387 | sFFE = sff1 >> 31; /* empty flag */ | |
388 | ||
389 | if (sEVLD) { | |
390 | u8 sDST = sff0 >> 16; /* dev status */ | |
391 | u8 sHST = sff1 & 0x3f; /* host status */ | |
392 | unsigned int port_no = (sff1 >> 8) & 0x03; | |
cca3974e | 393 | struct ata_port *ap = host->ports[port_no]; |
1da177e4 LT |
394 | |
395 | DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n", | |
396 | sff1, sff0, port_no, sHST, sDST); | |
397 | handled = 1; | |
029f5468 | 398 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
399 | struct ata_queued_cmd *qc; |
400 | struct qs_port_priv *pp = ap->private_data; | |
401 | if (!pp || pp->state != qs_state_pkt) | |
402 | continue; | |
403 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 404 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
1da177e4 | 405 | switch (sHST) { |
a7dac447 | 406 | case 0: /* successful CPB */ |
1da177e4 LT |
407 | case 3: /* device error */ |
408 | pp->state = qs_state_idle; | |
409 | qs_enter_reg_mode(qc->ap); | |
a22e2eb0 AL |
410 | qc->err_mask |= ac_err_mask(sDST); |
411 | ata_qc_complete(qc); | |
1da177e4 LT |
412 | break; |
413 | default: | |
414 | break; | |
415 | } | |
416 | } | |
417 | } | |
418 | } | |
419 | } while (!sFFE); | |
420 | return handled; | |
421 | } | |
422 | ||
cca3974e | 423 | static inline unsigned int qs_intr_mmio(struct ata_host *host) |
1da177e4 LT |
424 | { |
425 | unsigned int handled = 0, port_no; | |
426 | ||
cca3974e | 427 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
1da177e4 | 428 | struct ata_port *ap; |
cca3974e | 429 | ap = host->ports[port_no]; |
c1389503 | 430 | if (ap && |
029f5468 | 431 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
432 | struct ata_queued_cmd *qc; |
433 | struct qs_port_priv *pp = ap->private_data; | |
434 | if (!pp || pp->state != qs_state_mmio) | |
435 | continue; | |
436 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 437 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
1da177e4 LT |
438 | |
439 | /* check main status, clearing INTRQ */ | |
ac19bff2 | 440 | u8 status = ata_check_status(ap); |
1da177e4 LT |
441 | if ((status & ATA_BUSY)) |
442 | continue; | |
443 | DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n", | |
444 | ap->id, qc->tf.protocol, status); | |
8a60a071 | 445 | |
1da177e4 LT |
446 | /* complete taskfile transaction */ |
447 | pp->state = qs_state_idle; | |
a22e2eb0 AL |
448 | qc->err_mask |= ac_err_mask(status); |
449 | ata_qc_complete(qc); | |
1da177e4 LT |
450 | handled = 1; |
451 | } | |
452 | } | |
453 | } | |
454 | return handled; | |
455 | } | |
456 | ||
457 | static irqreturn_t qs_intr(int irq, void *dev_instance, struct pt_regs *regs) | |
458 | { | |
cca3974e | 459 | struct ata_host *host = dev_instance; |
1da177e4 LT |
460 | unsigned int handled = 0; |
461 | ||
462 | VPRINTK("ENTER\n"); | |
463 | ||
cca3974e JG |
464 | spin_lock(&host->lock); |
465 | handled = qs_intr_pkt(host) | qs_intr_mmio(host); | |
466 | spin_unlock(&host->lock); | |
1da177e4 LT |
467 | |
468 | VPRINTK("EXIT\n"); | |
469 | ||
470 | return IRQ_RETVAL(handled); | |
471 | } | |
472 | ||
473 | static void qs_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
474 | { | |
475 | port->cmd_addr = | |
476 | port->data_addr = base + 0x400; | |
477 | port->error_addr = | |
478 | port->feature_addr = base + 0x408; /* hob_feature = 0x409 */ | |
479 | port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */ | |
480 | port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */ | |
481 | port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */ | |
482 | port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */ | |
483 | port->device_addr = base + 0x430; | |
484 | port->status_addr = | |
485 | port->command_addr = base + 0x438; | |
486 | port->altstatus_addr = | |
487 | port->ctl_addr = base + 0x440; | |
488 | port->scr_addr = base + 0xc00; | |
489 | } | |
490 | ||
491 | static int qs_port_start(struct ata_port *ap) | |
492 | { | |
cca3974e | 493 | struct device *dev = ap->host->dev; |
1da177e4 | 494 | struct qs_port_priv *pp; |
cca3974e | 495 | void __iomem *mmio_base = ap->host->mmio_base; |
1da177e4 LT |
496 | void __iomem *chan = mmio_base + (ap->port_no * 0x4000); |
497 | u64 addr; | |
498 | int rc; | |
499 | ||
500 | rc = ata_port_start(ap); | |
501 | if (rc) | |
502 | return rc; | |
503 | qs_enter_reg_mode(ap); | |
82ca76b6 | 504 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
1da177e4 LT |
505 | if (!pp) { |
506 | rc = -ENOMEM; | |
507 | goto err_out; | |
508 | } | |
509 | pp->pkt = dma_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma, | |
510 | GFP_KERNEL); | |
511 | if (!pp->pkt) { | |
512 | rc = -ENOMEM; | |
513 | goto err_out_kfree; | |
514 | } | |
515 | memset(pp->pkt, 0, QS_PKT_BYTES); | |
516 | ap->private_data = pp; | |
517 | ||
518 | addr = (u64)pp->pkt_dma; | |
519 | writel((u32) addr, chan + QS_CCF_CPBA); | |
520 | writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4); | |
521 | return 0; | |
522 | ||
523 | err_out_kfree: | |
524 | kfree(pp); | |
525 | err_out: | |
526 | ata_port_stop(ap); | |
527 | return rc; | |
528 | } | |
529 | ||
530 | static void qs_port_stop(struct ata_port *ap) | |
531 | { | |
cca3974e | 532 | struct device *dev = ap->host->dev; |
1da177e4 LT |
533 | struct qs_port_priv *pp = ap->private_data; |
534 | ||
535 | if (pp != NULL) { | |
536 | ap->private_data = NULL; | |
537 | if (pp->pkt != NULL) | |
538 | dma_free_coherent(dev, QS_PKT_BYTES, pp->pkt, | |
539 | pp->pkt_dma); | |
540 | kfree(pp); | |
541 | } | |
542 | ata_port_stop(ap); | |
543 | } | |
544 | ||
cca3974e | 545 | static void qs_host_stop(struct ata_host *host) |
1da177e4 | 546 | { |
cca3974e JG |
547 | void __iomem *mmio_base = host->mmio_base; |
548 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1da177e4 LT |
549 | |
550 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ | |
551 | writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */ | |
aa8f0dc6 | 552 | |
374b1873 | 553 | pci_iounmap(pdev, mmio_base); |
1da177e4 LT |
554 | } |
555 | ||
556 | static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
557 | { | |
558 | void __iomem *mmio_base = pe->mmio_base; | |
559 | unsigned int port_no; | |
560 | ||
561 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ | |
562 | writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */ | |
563 | ||
564 | /* reset each channel in turn */ | |
565 | for (port_no = 0; port_no < pe->n_ports; ++port_no) { | |
566 | u8 __iomem *chan = mmio_base + (port_no * 0x4000); | |
567 | writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1); | |
568 | writeb(QS_CTR0_REG, chan + QS_CCT_CTR0); | |
569 | readb(chan + QS_CCT_CTR0); /* flush */ | |
570 | } | |
571 | writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */ | |
572 | ||
573 | for (port_no = 0; port_no < pe->n_ports; ++port_no) { | |
574 | u8 __iomem *chan = mmio_base + (port_no * 0x4000); | |
575 | /* set FIFO depths to same settings as Windows driver */ | |
576 | writew(32, chan + QS_CFC_HUFT); | |
577 | writew(32, chan + QS_CFC_HDFT); | |
578 | writew(10, chan + QS_CFC_DUFT); | |
579 | writew( 8, chan + QS_CFC_DDFT); | |
580 | /* set CPB size in bytes, as a power of two */ | |
581 | writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP); | |
582 | } | |
583 | writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */ | |
584 | } | |
585 | ||
586 | /* | |
587 | * The QStor understands 64-bit buses, and uses 64-bit fields | |
588 | * for DMA pointers regardless of bus width. We just have to | |
589 | * make sure our DMA masks are set appropriately for whatever | |
590 | * bridge lies between us and the QStor, and then the DMA mapping | |
591 | * code will ensure we only ever "see" appropriate buffer addresses. | |
592 | * If we're 32-bit limited somewhere, then our 64-bit fields will | |
593 | * just end up with zeros in the upper 32-bits, without any special | |
594 | * logic required outside of this routine (below). | |
595 | */ | |
596 | static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) | |
597 | { | |
598 | u32 bus_info = readl(mmio_base + QS_HID_HPHY); | |
599 | int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT); | |
600 | ||
601 | if (have_64bit_bus && | |
602 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
603 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
604 | if (rc) { | |
605 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
606 | if (rc) { | |
a9524a76 JG |
607 | dev_printk(KERN_ERR, &pdev->dev, |
608 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
609 | return rc; |
610 | } | |
611 | } | |
612 | } else { | |
613 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
614 | if (rc) { | |
a9524a76 JG |
615 | dev_printk(KERN_ERR, &pdev->dev, |
616 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
617 | return rc; |
618 | } | |
619 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
620 | if (rc) { | |
a9524a76 JG |
621 | dev_printk(KERN_ERR, &pdev->dev, |
622 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
623 | return rc; |
624 | } | |
625 | } | |
626 | return 0; | |
627 | } | |
628 | ||
629 | static int qs_ata_init_one(struct pci_dev *pdev, | |
630 | const struct pci_device_id *ent) | |
631 | { | |
632 | static int printed_version; | |
633 | struct ata_probe_ent *probe_ent = NULL; | |
634 | void __iomem *mmio_base; | |
635 | unsigned int board_idx = (unsigned int) ent->driver_data; | |
636 | int rc, port_no; | |
637 | ||
638 | if (!printed_version++) | |
a9524a76 | 639 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
640 | |
641 | rc = pci_enable_device(pdev); | |
642 | if (rc) | |
643 | return rc; | |
644 | ||
645 | rc = pci_request_regions(pdev, DRV_NAME); | |
646 | if (rc) | |
647 | goto err_out; | |
648 | ||
649 | if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) { | |
650 | rc = -ENODEV; | |
651 | goto err_out_regions; | |
652 | } | |
653 | ||
374b1873 | 654 | mmio_base = pci_iomap(pdev, 4, 0); |
1da177e4 LT |
655 | if (mmio_base == NULL) { |
656 | rc = -ENOMEM; | |
657 | goto err_out_regions; | |
658 | } | |
659 | ||
660 | rc = qs_set_dma_masks(pdev, mmio_base); | |
661 | if (rc) | |
662 | goto err_out_iounmap; | |
663 | ||
664 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
665 | if (probe_ent == NULL) { | |
666 | rc = -ENOMEM; | |
667 | goto err_out_iounmap; | |
668 | } | |
669 | ||
670 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
671 | probe_ent->dev = pci_dev_to_dev(pdev); | |
672 | INIT_LIST_HEAD(&probe_ent->node); | |
673 | ||
674 | probe_ent->sht = qs_port_info[board_idx].sht; | |
cca3974e | 675 | probe_ent->port_flags = qs_port_info[board_idx].flags; |
1da177e4 LT |
676 | probe_ent->pio_mask = qs_port_info[board_idx].pio_mask; |
677 | probe_ent->mwdma_mask = qs_port_info[board_idx].mwdma_mask; | |
678 | probe_ent->udma_mask = qs_port_info[board_idx].udma_mask; | |
679 | probe_ent->port_ops = qs_port_info[board_idx].port_ops; | |
680 | ||
681 | probe_ent->irq = pdev->irq; | |
1d6f359a | 682 | probe_ent->irq_flags = IRQF_SHARED; |
1da177e4 LT |
683 | probe_ent->mmio_base = mmio_base; |
684 | probe_ent->n_ports = QS_PORTS; | |
685 | ||
686 | for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { | |
687 | unsigned long chan = (unsigned long)mmio_base + | |
688 | (port_no * 0x4000); | |
689 | qs_ata_setup_port(&probe_ent->port[port_no], chan); | |
690 | } | |
691 | ||
692 | pci_set_master(pdev); | |
693 | ||
694 | /* initialize adapter */ | |
695 | qs_host_init(board_idx, probe_ent); | |
696 | ||
697 | rc = ata_device_add(probe_ent); | |
698 | kfree(probe_ent); | |
699 | if (rc != QS_PORTS) | |
700 | goto err_out_iounmap; | |
701 | return 0; | |
702 | ||
703 | err_out_iounmap: | |
374b1873 | 704 | pci_iounmap(pdev, mmio_base); |
1da177e4 LT |
705 | err_out_regions: |
706 | pci_release_regions(pdev); | |
707 | err_out: | |
708 | pci_disable_device(pdev); | |
709 | return rc; | |
710 | } | |
711 | ||
712 | static int __init qs_ata_init(void) | |
713 | { | |
b7887196 | 714 | return pci_register_driver(&qs_ata_pci_driver); |
1da177e4 LT |
715 | } |
716 | ||
717 | static void __exit qs_ata_exit(void) | |
718 | { | |
719 | pci_unregister_driver(&qs_ata_pci_driver); | |
720 | } | |
721 | ||
722 | MODULE_AUTHOR("Mark Lord"); | |
723 | MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver"); | |
724 | MODULE_LICENSE("GPL"); | |
725 | MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl); | |
726 | MODULE_VERSION(DRV_VERSION); | |
727 | ||
728 | module_init(qs_ata_init); | |
729 | module_exit(qs_ata_exit); |