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1da177e4 LT |
1 | /* |
2 | * sata_qstor.c - Pacific Digital Corporation QStor SATA | |
3 | * | |
4 | * Maintained by: Mark Lord <mlord@pobox.com> | |
5 | * | |
6 | * Copyright 2005 Pacific Digital Corporation. | |
7 | * (OSL/GPL code release authorized by Jalil Fadavi). | |
8 | * | |
af36d7f0 JG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; see the file COPYING. If not, write to | |
22 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | * | |
24 | * | |
25 | * libata documentation is available via 'make {ps|pdf}docs', | |
26 | * as Documentation/DocBook/libata.* | |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/blkdev.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/interrupt.h> | |
a9524a76 | 37 | #include <linux/device.h> |
1da177e4 | 38 | #include <scsi/scsi_host.h> |
1da177e4 LT |
39 | #include <linux/libata.h> |
40 | ||
41 | #define DRV_NAME "sata_qstor" | |
2a3103ce | 42 | #define DRV_VERSION "0.09" |
1da177e4 LT |
43 | |
44 | enum { | |
0d5ff566 TH |
45 | QS_MMIO_BAR = 4, |
46 | ||
1da177e4 LT |
47 | QS_PORTS = 4, |
48 | QS_MAX_PRD = LIBATA_MAX_PRD, | |
49 | QS_CPB_ORDER = 6, | |
50 | QS_CPB_BYTES = (1 << QS_CPB_ORDER), | |
51 | QS_PRD_BYTES = QS_MAX_PRD * 16, | |
52 | QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES, | |
53 | ||
1da177e4 LT |
54 | /* global register offsets */ |
55 | QS_HCF_CNFG3 = 0x0003, /* host configuration offset */ | |
56 | QS_HID_HPHY = 0x0004, /* host physical interface info */ | |
57 | QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */ | |
58 | QS_HST_SFF = 0x0100, /* host status fifo offset */ | |
59 | QS_HVS_SERD3 = 0x0393, /* PHY enable offset */ | |
60 | ||
61 | /* global control bits */ | |
62 | QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */ | |
63 | QS_CNFG3_GSRST = 0x01, /* global chip reset */ | |
64 | QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/ | |
65 | ||
66 | /* per-channel register offsets */ | |
67 | QS_CCF_CPBA = 0x0710, /* chan CPB base address */ | |
68 | QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */ | |
69 | QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */ | |
70 | QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */ | |
71 | QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */ | |
72 | QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */ | |
73 | QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */ | |
74 | QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */ | |
75 | QS_CCT_CFF = 0x0a00, /* chan command fifo offset */ | |
76 | ||
77 | /* channel control bits */ | |
78 | QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */ | |
79 | QS_CTR0_CLER = (1 << 2), /* clear channel errors */ | |
80 | QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */ | |
81 | QS_CTR1_RCHN = (1 << 4), /* reset channel logic */ | |
82 | QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */ | |
83 | ||
84 | /* pkt sub-field headers */ | |
85 | QS_HCB_HDR = 0x01, /* Host Control Block header */ | |
86 | QS_DCB_HDR = 0x02, /* Device Control Block header */ | |
87 | ||
88 | /* pkt HCB flag bits */ | |
89 | QS_HF_DIRO = (1 << 0), /* data DIRection Out */ | |
90 | QS_HF_DAT = (1 << 3), /* DATa pkt */ | |
91 | QS_HF_IEN = (1 << 4), /* Interrupt ENable */ | |
92 | QS_HF_VLD = (1 << 5), /* VaLiD pkt */ | |
93 | ||
94 | /* pkt DCB flag bits */ | |
95 | QS_DF_PORD = (1 << 2), /* Pio OR Dma */ | |
96 | QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */ | |
97 | ||
98 | /* PCI device IDs */ | |
99 | board_2068_idx = 0, /* QStor 4-port SATA/RAID */ | |
100 | }; | |
101 | ||
0420dd12 AV |
102 | enum { |
103 | QS_DMA_BOUNDARY = ~0UL | |
104 | }; | |
105 | ||
12ee7d3c | 106 | typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t; |
1da177e4 LT |
107 | |
108 | struct qs_port_priv { | |
109 | u8 *pkt; | |
110 | dma_addr_t pkt_dma; | |
111 | qs_state_t state; | |
112 | }; | |
113 | ||
da3dbb17 TH |
114 | static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
115 | static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
5796d1c4 | 116 | static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
1da177e4 | 117 | static int qs_port_start(struct ata_port *ap); |
cca3974e | 118 | static void qs_host_stop(struct ata_host *host); |
1da177e4 | 119 | static void qs_qc_prep(struct ata_queued_cmd *qc); |
9a3d9eb0 | 120 | static unsigned int qs_qc_issue(struct ata_queued_cmd *qc); |
1da177e4 | 121 | static int qs_check_atapi_dma(struct ata_queued_cmd *qc); |
b73fc89f | 122 | static void qs_bmdma_stop(struct ata_queued_cmd *qc); |
1da177e4 | 123 | static u8 qs_bmdma_status(struct ata_port *ap); |
6004bda1 ML |
124 | static void qs_freeze(struct ata_port *ap); |
125 | static void qs_thaw(struct ata_port *ap); | |
a1efdaba | 126 | static int qs_prereset(struct ata_link *link, unsigned long deadline); |
6004bda1 | 127 | static void qs_error_handler(struct ata_port *ap); |
1da177e4 | 128 | |
193515d5 | 129 | static struct scsi_host_template qs_ata_sht = { |
68d1d07b | 130 | ATA_BASE_SHT(DRV_NAME), |
1da177e4 | 131 | .sg_tablesize = QS_MAX_PRD, |
1da177e4 | 132 | .dma_boundary = QS_DMA_BOUNDARY, |
1da177e4 LT |
133 | }; |
134 | ||
029cfd6b TH |
135 | static struct ata_port_operations qs_ata_ops = { |
136 | .inherits = &ata_sff_port_ops, | |
137 | ||
1da177e4 | 138 | .check_atapi_dma = qs_check_atapi_dma, |
029cfd6b TH |
139 | .bmdma_stop = qs_bmdma_stop, |
140 | .bmdma_status = qs_bmdma_status, | |
1da177e4 LT |
141 | .qc_prep = qs_qc_prep, |
142 | .qc_issue = qs_qc_issue, | |
029cfd6b | 143 | |
6004bda1 ML |
144 | .freeze = qs_freeze, |
145 | .thaw = qs_thaw, | |
a1efdaba TH |
146 | .prereset = qs_prereset, |
147 | .softreset = ATA_OP_NULL, | |
6004bda1 | 148 | .error_handler = qs_error_handler, |
029cfd6b TH |
149 | .post_internal_cmd = ATA_OP_NULL, |
150 | ||
1da177e4 LT |
151 | .scr_read = qs_scr_read, |
152 | .scr_write = qs_scr_write, | |
029cfd6b | 153 | |
1da177e4 | 154 | .port_start = qs_port_start, |
1da177e4 | 155 | .host_stop = qs_host_stop, |
1da177e4 LT |
156 | }; |
157 | ||
98ac62de | 158 | static const struct ata_port_info qs_port_info[] = { |
1da177e4 LT |
159 | /* board_2068_idx */ |
160 | { | |
cca3974e | 161 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
e50362ec | 162 | ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, |
1da177e4 | 163 | .pio_mask = 0x10, /* pio4 */ |
bf6263a8 | 164 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
165 | .port_ops = &qs_ata_ops, |
166 | }, | |
167 | }; | |
168 | ||
3b7d697d | 169 | static const struct pci_device_id qs_ata_pci_tbl[] = { |
2d2744fc | 170 | { PCI_VDEVICE(PDC, 0x2068), board_2068_idx }, |
1da177e4 LT |
171 | |
172 | { } /* terminate list */ | |
173 | }; | |
174 | ||
175 | static struct pci_driver qs_ata_pci_driver = { | |
176 | .name = DRV_NAME, | |
177 | .id_table = qs_ata_pci_tbl, | |
178 | .probe = qs_ata_init_one, | |
179 | .remove = ata_pci_remove_one, | |
180 | }; | |
181 | ||
0d5ff566 TH |
182 | static void __iomem *qs_mmio_base(struct ata_host *host) |
183 | { | |
184 | return host->iomap[QS_MMIO_BAR]; | |
185 | } | |
186 | ||
1da177e4 LT |
187 | static int qs_check_atapi_dma(struct ata_queued_cmd *qc) |
188 | { | |
189 | return 1; /* ATAPI DMA not supported */ | |
190 | } | |
191 | ||
d18d36b4 | 192 | static void qs_bmdma_stop(struct ata_queued_cmd *qc) |
1da177e4 LT |
193 | { |
194 | /* nothing */ | |
195 | } | |
196 | ||
197 | static u8 qs_bmdma_status(struct ata_port *ap) | |
198 | { | |
199 | return 0; | |
200 | } | |
201 | ||
1da177e4 LT |
202 | static inline void qs_enter_reg_mode(struct ata_port *ap) |
203 | { | |
0d5ff566 | 204 | u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000); |
12ee7d3c | 205 | struct qs_port_priv *pp = ap->private_data; |
1da177e4 | 206 | |
12ee7d3c | 207 | pp->state = qs_state_mmio; |
1da177e4 LT |
208 | writeb(QS_CTR0_REG, chan + QS_CCT_CTR0); |
209 | readb(chan + QS_CCT_CTR0); /* flush */ | |
210 | } | |
211 | ||
212 | static inline void qs_reset_channel_logic(struct ata_port *ap) | |
213 | { | |
0d5ff566 | 214 | u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000); |
1da177e4 LT |
215 | |
216 | writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1); | |
217 | readb(chan + QS_CCT_CTR0); /* flush */ | |
218 | qs_enter_reg_mode(ap); | |
219 | } | |
220 | ||
6004bda1 | 221 | static void qs_freeze(struct ata_port *ap) |
1da177e4 | 222 | { |
6004bda1 ML |
223 | u8 __iomem *mmio_base = qs_mmio_base(ap->host); |
224 | ||
225 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ | |
226 | qs_enter_reg_mode(ap); | |
1da177e4 LT |
227 | } |
228 | ||
6004bda1 | 229 | static void qs_thaw(struct ata_port *ap) |
1da177e4 | 230 | { |
6004bda1 ML |
231 | u8 __iomem *mmio_base = qs_mmio_base(ap->host); |
232 | ||
233 | qs_enter_reg_mode(ap); | |
234 | writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */ | |
235 | } | |
236 | ||
237 | static int qs_prereset(struct ata_link *link, unsigned long deadline) | |
238 | { | |
239 | struct ata_port *ap = link->ap; | |
240 | ||
1da177e4 | 241 | qs_reset_channel_logic(ap); |
6004bda1 | 242 | return ata_std_prereset(link, deadline); |
1da177e4 LT |
243 | } |
244 | ||
da3dbb17 | 245 | static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 LT |
246 | { |
247 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 TH |
248 | return -EINVAL; |
249 | *val = readl(ap->ioaddr.scr_addr + (sc_reg * 8)); | |
250 | return 0; | |
1da177e4 LT |
251 | } |
252 | ||
6004bda1 ML |
253 | static void qs_error_handler(struct ata_port *ap) |
254 | { | |
255 | qs_enter_reg_mode(ap); | |
a1efdaba | 256 | ata_std_error_handler(ap); |
6004bda1 ML |
257 | } |
258 | ||
da3dbb17 | 259 | static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 LT |
260 | { |
261 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 | 262 | return -EINVAL; |
0d5ff566 | 263 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 8)); |
da3dbb17 | 264 | return 0; |
1da177e4 LT |
265 | } |
266 | ||
828d09de | 267 | static unsigned int qs_fill_sg(struct ata_queued_cmd *qc) |
1da177e4 | 268 | { |
cedc9a47 | 269 | struct scatterlist *sg; |
1da177e4 LT |
270 | struct ata_port *ap = qc->ap; |
271 | struct qs_port_priv *pp = ap->private_data; | |
1da177e4 | 272 | u8 *prd = pp->pkt + QS_CPB_BYTES; |
ff2aeb1e | 273 | unsigned int si; |
1da177e4 | 274 | |
ff2aeb1e | 275 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
1da177e4 LT |
276 | u64 addr; |
277 | u32 len; | |
278 | ||
279 | addr = sg_dma_address(sg); | |
280 | *(__le64 *)prd = cpu_to_le64(addr); | |
281 | prd += sizeof(u64); | |
282 | ||
283 | len = sg_dma_len(sg); | |
284 | *(__le32 *)prd = cpu_to_le32(len); | |
285 | prd += sizeof(u64); | |
286 | ||
ff2aeb1e | 287 | VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si, |
1da177e4 LT |
288 | (unsigned long long)addr, len); |
289 | } | |
828d09de | 290 | |
ff2aeb1e | 291 | return si; |
1da177e4 LT |
292 | } |
293 | ||
294 | static void qs_qc_prep(struct ata_queued_cmd *qc) | |
295 | { | |
296 | struct qs_port_priv *pp = qc->ap->private_data; | |
297 | u8 dflags = QS_DF_PORD, *buf = pp->pkt; | |
298 | u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD; | |
299 | u64 addr; | |
828d09de | 300 | unsigned int nelem; |
1da177e4 LT |
301 | |
302 | VPRINTK("ENTER\n"); | |
303 | ||
304 | qs_enter_reg_mode(qc->ap); | |
305 | if (qc->tf.protocol != ATA_PROT_DMA) { | |
306 | ata_qc_prep(qc); | |
307 | return; | |
308 | } | |
309 | ||
828d09de | 310 | nelem = qs_fill_sg(qc); |
1da177e4 LT |
311 | |
312 | if ((qc->tf.flags & ATA_TFLAG_WRITE)) | |
313 | hflags |= QS_HF_DIRO; | |
314 | if ((qc->tf.flags & ATA_TFLAG_LBA48)) | |
315 | dflags |= QS_DF_ELBA; | |
316 | ||
317 | /* host control block (HCB) */ | |
318 | buf[ 0] = QS_HCB_HDR; | |
319 | buf[ 1] = hflags; | |
726f0785 | 320 | *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes); |
828d09de | 321 | *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem); |
1da177e4 LT |
322 | addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES; |
323 | *(__le64 *)(&buf[16]) = cpu_to_le64(addr); | |
324 | ||
325 | /* device control block (DCB) */ | |
326 | buf[24] = QS_DCB_HDR; | |
327 | buf[28] = dflags; | |
328 | ||
329 | /* frame information structure (FIS) */ | |
9977126c | 330 | ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]); |
1da177e4 LT |
331 | } |
332 | ||
333 | static inline void qs_packet_start(struct ata_queued_cmd *qc) | |
334 | { | |
335 | struct ata_port *ap = qc->ap; | |
0d5ff566 | 336 | u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000); |
1da177e4 LT |
337 | |
338 | VPRINTK("ENTER, ap %p\n", ap); | |
339 | ||
340 | writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0); | |
341 | wmb(); /* flush PRDs and pkt to memory */ | |
342 | writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF); | |
343 | readl(chan + QS_CCT_CFF); /* flush */ | |
344 | } | |
345 | ||
9a3d9eb0 | 346 | static unsigned int qs_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
347 | { |
348 | struct qs_port_priv *pp = qc->ap->private_data; | |
349 | ||
350 | switch (qc->tf.protocol) { | |
351 | case ATA_PROT_DMA: | |
1da177e4 LT |
352 | pp->state = qs_state_pkt; |
353 | qs_packet_start(qc); | |
354 | return 0; | |
355 | ||
0dc36888 | 356 | case ATAPI_PROT_DMA: |
1da177e4 LT |
357 | BUG(); |
358 | break; | |
359 | ||
360 | default: | |
361 | break; | |
362 | } | |
363 | ||
364 | pp->state = qs_state_mmio; | |
365 | return ata_qc_issue_prot(qc); | |
366 | } | |
367 | ||
6004bda1 ML |
368 | static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status) |
369 | { | |
370 | qc->err_mask |= ac_err_mask(status); | |
371 | ||
372 | if (!qc->err_mask) { | |
373 | ata_qc_complete(qc); | |
374 | } else { | |
375 | struct ata_port *ap = qc->ap; | |
376 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
377 | ||
378 | ata_ehi_clear_desc(ehi); | |
379 | ata_ehi_push_desc(ehi, "status 0x%02X", status); | |
380 | ||
381 | if (qc->err_mask == AC_ERR_DEV) | |
382 | ata_port_abort(ap); | |
383 | else | |
384 | ata_port_freeze(ap); | |
385 | } | |
386 | } | |
387 | ||
cca3974e | 388 | static inline unsigned int qs_intr_pkt(struct ata_host *host) |
1da177e4 LT |
389 | { |
390 | unsigned int handled = 0; | |
391 | u8 sFFE; | |
0d5ff566 | 392 | u8 __iomem *mmio_base = qs_mmio_base(host); |
1da177e4 LT |
393 | |
394 | do { | |
395 | u32 sff0 = readl(mmio_base + QS_HST_SFF); | |
396 | u32 sff1 = readl(mmio_base + QS_HST_SFF + 4); | |
397 | u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */ | |
398 | sFFE = sff1 >> 31; /* empty flag */ | |
399 | ||
400 | if (sEVLD) { | |
401 | u8 sDST = sff0 >> 16; /* dev status */ | |
402 | u8 sHST = sff1 & 0x3f; /* host status */ | |
403 | unsigned int port_no = (sff1 >> 8) & 0x03; | |
cca3974e | 404 | struct ata_port *ap = host->ports[port_no]; |
1da177e4 LT |
405 | |
406 | DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n", | |
407 | sff1, sff0, port_no, sHST, sDST); | |
408 | handled = 1; | |
029f5468 | 409 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
410 | struct ata_queued_cmd *qc; |
411 | struct qs_port_priv *pp = ap->private_data; | |
412 | if (!pp || pp->state != qs_state_pkt) | |
413 | continue; | |
9af5c9c9 | 414 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
e50362ec | 415 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
1da177e4 | 416 | switch (sHST) { |
a7dac447 | 417 | case 0: /* successful CPB */ |
1da177e4 | 418 | case 3: /* device error */ |
1da177e4 | 419 | qs_enter_reg_mode(qc->ap); |
6004bda1 | 420 | qs_do_or_die(qc, sDST); |
1da177e4 LT |
421 | break; |
422 | default: | |
423 | break; | |
424 | } | |
425 | } | |
426 | } | |
427 | } | |
428 | } while (!sFFE); | |
429 | return handled; | |
430 | } | |
431 | ||
cca3974e | 432 | static inline unsigned int qs_intr_mmio(struct ata_host *host) |
1da177e4 LT |
433 | { |
434 | unsigned int handled = 0, port_no; | |
435 | ||
cca3974e | 436 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
1da177e4 | 437 | struct ata_port *ap; |
cca3974e | 438 | ap = host->ports[port_no]; |
c1389503 | 439 | if (ap && |
029f5468 | 440 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 | 441 | struct ata_queued_cmd *qc; |
904c7bad | 442 | struct qs_port_priv *pp; |
9af5c9c9 | 443 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
904c7bad ML |
444 | if (!qc || !(qc->flags & ATA_QCFLAG_ACTIVE)) { |
445 | /* | |
446 | * The qstor hardware generates spurious | |
447 | * interrupts from time to time when switching | |
448 | * in and out of packet mode. | |
449 | * There's no obvious way to know if we're | |
450 | * here now due to that, so just ack the irq | |
451 | * and pretend we knew it was ours.. (ugh). | |
452 | * This does not affect packet mode. | |
453 | */ | |
454 | ata_check_status(ap); | |
1da177e4 | 455 | handled = 1; |
904c7bad | 456 | continue; |
1da177e4 | 457 | } |
904c7bad ML |
458 | pp = ap->private_data; |
459 | if (!pp || pp->state != qs_state_mmio) | |
460 | continue; | |
461 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) | |
462 | handled |= ata_host_intr(ap, qc); | |
1da177e4 LT |
463 | } |
464 | } | |
465 | return handled; | |
466 | } | |
467 | ||
7d12e780 | 468 | static irqreturn_t qs_intr(int irq, void *dev_instance) |
1da177e4 | 469 | { |
cca3974e | 470 | struct ata_host *host = dev_instance; |
1da177e4 | 471 | unsigned int handled = 0; |
904c7bad | 472 | unsigned long flags; |
1da177e4 LT |
473 | |
474 | VPRINTK("ENTER\n"); | |
475 | ||
904c7bad | 476 | spin_lock_irqsave(&host->lock, flags); |
cca3974e | 477 | handled = qs_intr_pkt(host) | qs_intr_mmio(host); |
904c7bad | 478 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
479 | |
480 | VPRINTK("EXIT\n"); | |
481 | ||
482 | return IRQ_RETVAL(handled); | |
483 | } | |
484 | ||
0d5ff566 | 485 | static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base) |
1da177e4 LT |
486 | { |
487 | port->cmd_addr = | |
488 | port->data_addr = base + 0x400; | |
489 | port->error_addr = | |
490 | port->feature_addr = base + 0x408; /* hob_feature = 0x409 */ | |
491 | port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */ | |
492 | port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */ | |
493 | port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */ | |
494 | port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */ | |
495 | port->device_addr = base + 0x430; | |
496 | port->status_addr = | |
497 | port->command_addr = base + 0x438; | |
498 | port->altstatus_addr = | |
499 | port->ctl_addr = base + 0x440; | |
500 | port->scr_addr = base + 0xc00; | |
501 | } | |
502 | ||
503 | static int qs_port_start(struct ata_port *ap) | |
504 | { | |
cca3974e | 505 | struct device *dev = ap->host->dev; |
1da177e4 | 506 | struct qs_port_priv *pp; |
0d5ff566 | 507 | void __iomem *mmio_base = qs_mmio_base(ap->host); |
1da177e4 LT |
508 | void __iomem *chan = mmio_base + (ap->port_no * 0x4000); |
509 | u64 addr; | |
510 | int rc; | |
511 | ||
512 | rc = ata_port_start(ap); | |
513 | if (rc) | |
514 | return rc; | |
24dc5f33 TH |
515 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
516 | if (!pp) | |
517 | return -ENOMEM; | |
518 | pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma, | |
519 | GFP_KERNEL); | |
520 | if (!pp->pkt) | |
521 | return -ENOMEM; | |
1da177e4 LT |
522 | memset(pp->pkt, 0, QS_PKT_BYTES); |
523 | ap->private_data = pp; | |
524 | ||
12ee7d3c | 525 | qs_enter_reg_mode(ap); |
1da177e4 LT |
526 | addr = (u64)pp->pkt_dma; |
527 | writel((u32) addr, chan + QS_CCF_CPBA); | |
528 | writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4); | |
529 | return 0; | |
1da177e4 LT |
530 | } |
531 | ||
cca3974e | 532 | static void qs_host_stop(struct ata_host *host) |
1da177e4 | 533 | { |
0d5ff566 | 534 | void __iomem *mmio_base = qs_mmio_base(host); |
1da177e4 LT |
535 | |
536 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ | |
537 | writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */ | |
538 | } | |
539 | ||
4447d351 | 540 | static void qs_host_init(struct ata_host *host, unsigned int chip_id) |
1da177e4 | 541 | { |
4447d351 | 542 | void __iomem *mmio_base = host->iomap[QS_MMIO_BAR]; |
1da177e4 LT |
543 | unsigned int port_no; |
544 | ||
545 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ | |
546 | writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */ | |
547 | ||
548 | /* reset each channel in turn */ | |
4447d351 | 549 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
1da177e4 LT |
550 | u8 __iomem *chan = mmio_base + (port_no * 0x4000); |
551 | writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1); | |
552 | writeb(QS_CTR0_REG, chan + QS_CCT_CTR0); | |
553 | readb(chan + QS_CCT_CTR0); /* flush */ | |
554 | } | |
555 | writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */ | |
556 | ||
4447d351 | 557 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
1da177e4 LT |
558 | u8 __iomem *chan = mmio_base + (port_no * 0x4000); |
559 | /* set FIFO depths to same settings as Windows driver */ | |
560 | writew(32, chan + QS_CFC_HUFT); | |
561 | writew(32, chan + QS_CFC_HDFT); | |
562 | writew(10, chan + QS_CFC_DUFT); | |
563 | writew( 8, chan + QS_CFC_DDFT); | |
564 | /* set CPB size in bytes, as a power of two */ | |
565 | writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP); | |
566 | } | |
567 | writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */ | |
568 | } | |
569 | ||
570 | /* | |
571 | * The QStor understands 64-bit buses, and uses 64-bit fields | |
572 | * for DMA pointers regardless of bus width. We just have to | |
573 | * make sure our DMA masks are set appropriately for whatever | |
574 | * bridge lies between us and the QStor, and then the DMA mapping | |
575 | * code will ensure we only ever "see" appropriate buffer addresses. | |
576 | * If we're 32-bit limited somewhere, then our 64-bit fields will | |
577 | * just end up with zeros in the upper 32-bits, without any special | |
578 | * logic required outside of this routine (below). | |
579 | */ | |
580 | static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) | |
581 | { | |
582 | u32 bus_info = readl(mmio_base + QS_HID_HPHY); | |
583 | int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT); | |
584 | ||
585 | if (have_64bit_bus && | |
586 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
587 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
588 | if (rc) { | |
589 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
590 | if (rc) { | |
a9524a76 JG |
591 | dev_printk(KERN_ERR, &pdev->dev, |
592 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
593 | return rc; |
594 | } | |
595 | } | |
596 | } else { | |
597 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
598 | if (rc) { | |
a9524a76 JG |
599 | dev_printk(KERN_ERR, &pdev->dev, |
600 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
601 | return rc; |
602 | } | |
603 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
604 | if (rc) { | |
a9524a76 JG |
605 | dev_printk(KERN_ERR, &pdev->dev, |
606 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
607 | return rc; |
608 | } | |
609 | } | |
610 | return 0; | |
611 | } | |
612 | ||
613 | static int qs_ata_init_one(struct pci_dev *pdev, | |
614 | const struct pci_device_id *ent) | |
615 | { | |
616 | static int printed_version; | |
1da177e4 | 617 | unsigned int board_idx = (unsigned int) ent->driver_data; |
4447d351 TH |
618 | const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL }; |
619 | struct ata_host *host; | |
1da177e4 LT |
620 | int rc, port_no; |
621 | ||
622 | if (!printed_version++) | |
a9524a76 | 623 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 624 | |
4447d351 TH |
625 | /* alloc host */ |
626 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS); | |
627 | if (!host) | |
628 | return -ENOMEM; | |
629 | ||
630 | /* acquire resources and fill host */ | |
24dc5f33 | 631 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
632 | if (rc) |
633 | return rc; | |
634 | ||
0d5ff566 | 635 | if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0) |
24dc5f33 | 636 | return -ENODEV; |
1da177e4 | 637 | |
0d5ff566 TH |
638 | rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME); |
639 | if (rc) | |
640 | return rc; | |
4447d351 | 641 | host->iomap = pcim_iomap_table(pdev); |
1da177e4 | 642 | |
4447d351 | 643 | rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]); |
1da177e4 | 644 | if (rc) |
24dc5f33 | 645 | return rc; |
1da177e4 | 646 | |
4447d351 | 647 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
cbcdd875 TH |
648 | struct ata_port *ap = host->ports[port_no]; |
649 | unsigned int offset = port_no * 0x4000; | |
650 | void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset; | |
651 | ||
652 | qs_ata_setup_port(&ap->ioaddr, chan); | |
653 | ||
654 | ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio"); | |
655 | ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port"); | |
1da177e4 LT |
656 | } |
657 | ||
1da177e4 | 658 | /* initialize adapter */ |
4447d351 | 659 | qs_host_init(host, board_idx); |
1da177e4 | 660 | |
4447d351 TH |
661 | pci_set_master(pdev); |
662 | return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED, | |
663 | &qs_ata_sht); | |
1da177e4 LT |
664 | } |
665 | ||
666 | static int __init qs_ata_init(void) | |
667 | { | |
b7887196 | 668 | return pci_register_driver(&qs_ata_pci_driver); |
1da177e4 LT |
669 | } |
670 | ||
671 | static void __exit qs_ata_exit(void) | |
672 | { | |
673 | pci_unregister_driver(&qs_ata_pci_driver); | |
674 | } | |
675 | ||
676 | MODULE_AUTHOR("Mark Lord"); | |
677 | MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver"); | |
678 | MODULE_LICENSE("GPL"); | |
679 | MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl); | |
680 | MODULE_VERSION(DRV_VERSION); | |
681 | ||
682 | module_init(qs_ata_init); | |
683 | module_exit(qs_ata_exit); |