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c82ee6d3 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * sata_sil.c - Silicon Image SATA | |
4 | * | |
8c3d3d4b | 5 | * Maintained by: Tejun Heo <tj@kernel.org> |
1da177e4 LT |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org |
7 | * on emails. | |
8 | * | |
af36d7f0 | 9 | * Copyright 2003-2005 Red Hat, Inc. |
1da177e4 LT |
10 | * Copyright 2003 Benjamin Herrenschmidt |
11 | * | |
af36d7f0 | 12 | * libata documentation is available via 'make {ps|pdf}docs', |
19285f3c | 13 | * as Documentation/driver-api/libata.rst |
1da177e4 | 14 | * |
953d1137 JG |
15 | * Documentation for SiI 3112: |
16 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
17 | * | |
18 | * Other errata and documentation available under NDA. | |
1da177e4 LT |
19 | */ |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
1da177e4 LT |
24 | #include <linux/blkdev.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/interrupt.h> | |
a9524a76 | 27 | #include <linux/device.h> |
1da177e4 LT |
28 | #include <scsi/scsi_host.h> |
29 | #include <linux/libata.h> | |
1737ef75 | 30 | #include <linux/dmi.h> |
1da177e4 LT |
31 | |
32 | #define DRV_NAME "sata_sil" | |
c7e324f1 RH |
33 | #define DRV_VERSION "2.4" |
34 | ||
35 | #define SIL_DMA_BOUNDARY 0x7fffffffUL | |
1da177e4 LT |
36 | |
37 | enum { | |
0d5ff566 TH |
38 | SIL_MMIO_BAR = 5, |
39 | ||
e653a1e6 TH |
40 | /* |
41 | * host flags | |
42 | */ | |
201ce859 | 43 | SIL_FLAG_NO_SATA_IRQ = (1 << 28), |
e4e10e3e | 44 | SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), |
e4deec63 | 45 | SIL_FLAG_MOD15WRITE = (1 << 30), |
20888d83 | 46 | |
9cbe056f | 47 | SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA, |
e4deec63 | 48 | |
e653a1e6 TH |
49 | /* |
50 | * Controller IDs | |
51 | */ | |
1da177e4 | 52 | sil_3112 = 0, |
201ce859 TH |
53 | sil_3112_no_sata_irq = 1, |
54 | sil_3512 = 2, | |
55 | sil_3114 = 3, | |
1da177e4 | 56 | |
e653a1e6 TH |
57 | /* |
58 | * Register offsets | |
59 | */ | |
1da177e4 | 60 | SIL_SYSCFG = 0x48, |
e653a1e6 TH |
61 | |
62 | /* | |
63 | * Register bits | |
64 | */ | |
65 | /* SYSCFG */ | |
1da177e4 LT |
66 | SIL_MASK_IDE0_INT = (1 << 22), |
67 | SIL_MASK_IDE1_INT = (1 << 23), | |
68 | SIL_MASK_IDE2_INT = (1 << 24), | |
69 | SIL_MASK_IDE3_INT = (1 << 25), | |
70 | SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, | |
71 | SIL_MASK_4PORT = SIL_MASK_2PORT | | |
72 | SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, | |
73 | ||
e653a1e6 | 74 | /* BMDMA/BMDMA2 */ |
1da177e4 | 75 | SIL_INTR_STEERING = (1 << 1), |
e653a1e6 | 76 | |
20888d83 TH |
77 | SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ |
78 | SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ | |
79 | SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ | |
80 | SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ | |
81 | SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ | |
82 | SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ | |
83 | SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ | |
84 | SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ | |
85 | SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ | |
86 | SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ | |
87 | ||
88 | /* SIEN */ | |
89 | SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ | |
90 | ||
e653a1e6 TH |
91 | /* |
92 | * Others | |
93 | */ | |
1da177e4 LT |
94 | SIL_QUIRK_MOD15WRITE = (1 << 0), |
95 | SIL_QUIRK_UDMA5MAX = (1 << 1), | |
96 | }; | |
97 | ||
5796d1c4 | 98 | static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
58eb8cd5 | 99 | #ifdef CONFIG_PM_SLEEP |
afb5a7cb | 100 | static int sil_pci_device_resume(struct pci_dev *pdev); |
281d426c | 101 | #endif |
cd0d3bbc | 102 | static void sil_dev_config(struct ata_device *dev); |
82ef04fb TH |
103 | static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
104 | static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); | |
0260731f | 105 | static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed); |
95364f36 | 106 | static enum ata_completion_errors sil_qc_prep(struct ata_queued_cmd *qc); |
c7e324f1 RH |
107 | static void sil_bmdma_setup(struct ata_queued_cmd *qc); |
108 | static void sil_bmdma_start(struct ata_queued_cmd *qc); | |
109 | static void sil_bmdma_stop(struct ata_queued_cmd *qc); | |
f6aae27e TH |
110 | static void sil_freeze(struct ata_port *ap); |
111 | static void sil_thaw(struct ata_port *ap); | |
1da177e4 | 112 | |
374b1873 | 113 | |
3b7d697d | 114 | static const struct pci_device_id sil_pci_tbl[] = { |
54bb3a94 JG |
115 | { PCI_VDEVICE(CMD, 0x3112), sil_3112 }, |
116 | { PCI_VDEVICE(CMD, 0x0240), sil_3112 }, | |
117 | { PCI_VDEVICE(CMD, 0x3512), sil_3512 }, | |
118 | { PCI_VDEVICE(CMD, 0x3114), sil_3114 }, | |
119 | { PCI_VDEVICE(ATI, 0x436e), sil_3112 }, | |
120 | { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq }, | |
121 | { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq }, | |
122 | ||
1da177e4 LT |
123 | { } /* terminate list */ |
124 | }; | |
125 | ||
126 | ||
127 | /* TODO firmware versions should be added - eric */ | |
128 | static const struct sil_drivelist { | |
5796d1c4 | 129 | const char *product; |
1da177e4 LT |
130 | unsigned int quirk; |
131 | } sil_blacklist [] = { | |
132 | { "ST320012AS", SIL_QUIRK_MOD15WRITE }, | |
133 | { "ST330013AS", SIL_QUIRK_MOD15WRITE }, | |
134 | { "ST340017AS", SIL_QUIRK_MOD15WRITE }, | |
135 | { "ST360015AS", SIL_QUIRK_MOD15WRITE }, | |
1da177e4 LT |
136 | { "ST380023AS", SIL_QUIRK_MOD15WRITE }, |
137 | { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, | |
1da177e4 LT |
138 | { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, |
139 | { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, | |
140 | { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, | |
141 | { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, | |
142 | { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, | |
9f9c47f0 | 143 | { "TOSHIBA MK2561GSYN", SIL_QUIRK_MOD15WRITE }, |
1da177e4 LT |
144 | { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, |
145 | { } | |
146 | }; | |
147 | ||
148 | static struct pci_driver sil_pci_driver = { | |
149 | .name = DRV_NAME, | |
150 | .id_table = sil_pci_tbl, | |
151 | .probe = sil_init_one, | |
152 | .remove = ata_pci_remove_one, | |
58eb8cd5 | 153 | #ifdef CONFIG_PM_SLEEP |
afb5a7cb TH |
154 | .suspend = ata_pci_device_suspend, |
155 | .resume = sil_pci_device_resume, | |
281d426c | 156 | #endif |
1da177e4 LT |
157 | }; |
158 | ||
193515d5 | 159 | static struct scsi_host_template sil_sht = { |
c7e324f1 RH |
160 | ATA_BASE_SHT(DRV_NAME), |
161 | /** These controllers support Large Block Transfer which allows | |
162 | transfer chunks up to 2GB and which cross 64KB boundaries, | |
163 | therefore the DMA limits are more relaxed than standard ATA SFF. */ | |
164 | .dma_boundary = SIL_DMA_BOUNDARY, | |
165 | .sg_tablesize = ATA_MAX_PRD | |
1da177e4 LT |
166 | }; |
167 | ||
029cfd6b | 168 | static struct ata_port_operations sil_ops = { |
31f80112 | 169 | .inherits = &ata_bmdma32_port_ops, |
1da177e4 | 170 | .dev_config = sil_dev_config, |
9d2c7c75 | 171 | .set_mode = sil_set_mode, |
c7e324f1 RH |
172 | .bmdma_setup = sil_bmdma_setup, |
173 | .bmdma_start = sil_bmdma_start, | |
174 | .bmdma_stop = sil_bmdma_stop, | |
175 | .qc_prep = sil_qc_prep, | |
f6aae27e TH |
176 | .freeze = sil_freeze, |
177 | .thaw = sil_thaw, | |
1da177e4 LT |
178 | .scr_read = sil_scr_read, |
179 | .scr_write = sil_scr_write, | |
1da177e4 LT |
180 | }; |
181 | ||
98ac62de | 182 | static const struct ata_port_info sil_port_info[] = { |
1da177e4 | 183 | /* sil_3112 */ |
e4deec63 | 184 | { |
cca3974e | 185 | .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE, |
14bdef98 EIB |
186 | .pio_mask = ATA_PIO4, |
187 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 188 | .udma_mask = ATA_UDMA5, |
e4deec63 | 189 | .port_ops = &sil_ops, |
0ee304d5 | 190 | }, |
201ce859 TH |
191 | /* sil_3112_no_sata_irq */ |
192 | { | |
cca3974e | 193 | .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE | |
201ce859 | 194 | SIL_FLAG_NO_SATA_IRQ, |
14bdef98 EIB |
195 | .pio_mask = ATA_PIO4, |
196 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 197 | .udma_mask = ATA_UDMA5, |
201ce859 TH |
198 | .port_ops = &sil_ops, |
199 | }, | |
0ee304d5 | 200 | /* sil_3512 */ |
1da177e4 | 201 | { |
cca3974e | 202 | .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
14bdef98 EIB |
203 | .pio_mask = ATA_PIO4, |
204 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 205 | .udma_mask = ATA_UDMA5, |
0ee304d5 TH |
206 | .port_ops = &sil_ops, |
207 | }, | |
208 | /* sil_3114 */ | |
1da177e4 | 209 | { |
cca3974e | 210 | .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
14bdef98 EIB |
211 | .pio_mask = ATA_PIO4, |
212 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 213 | .udma_mask = ATA_UDMA5, |
1da177e4 LT |
214 | .port_ops = &sil_ops, |
215 | }, | |
216 | }; | |
217 | ||
218 | /* per-port register offsets */ | |
219 | /* TODO: we can probably calculate rather than use a table */ | |
220 | static const struct { | |
221 | unsigned long tf; /* ATA taskfile register block */ | |
222 | unsigned long ctl; /* ATA control/altstatus register block */ | |
223 | unsigned long bmdma; /* DMA register block */ | |
20888d83 | 224 | unsigned long bmdma2; /* DMA register block #2 */ |
48d4ef2a | 225 | unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ |
1da177e4 LT |
226 | unsigned long scr; /* SATA control register block */ |
227 | unsigned long sien; /* SATA Interrupt Enable register */ | |
228 | unsigned long xfer_mode;/* data transfer mode register */ | |
e4e10e3e | 229 | unsigned long sfis_cfg; /* SATA FIS reception config register */ |
1da177e4 LT |
230 | } sil_port[] = { |
231 | /* port 0 ... */ | |
5bcd7a00 JG |
232 | /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */ |
233 | { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, | |
234 | { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, | |
20888d83 TH |
235 | { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, |
236 | { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, | |
1da177e4 LT |
237 | /* ... port 3 */ |
238 | }; | |
239 | ||
240 | MODULE_AUTHOR("Jeff Garzik"); | |
241 | MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); | |
242 | MODULE_LICENSE("GPL"); | |
243 | MODULE_DEVICE_TABLE(pci, sil_pci_tbl); | |
244 | MODULE_VERSION(DRV_VERSION); | |
245 | ||
5796d1c4 | 246 | static int slow_down; |
51e9f2ff JG |
247 | module_param(slow_down, int, 0444); |
248 | MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); | |
249 | ||
374b1873 | 250 | |
c7e324f1 RH |
251 | static void sil_bmdma_stop(struct ata_queued_cmd *qc) |
252 | { | |
253 | struct ata_port *ap = qc->ap; | |
254 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; | |
255 | void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; | |
256 | ||
257 | /* clear start/stop bit - can safely always write 0 */ | |
258 | iowrite8(0, bmdma2); | |
259 | ||
260 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
261 | ata_sff_dma_pause(ap); | |
262 | } | |
263 | ||
264 | static void sil_bmdma_setup(struct ata_queued_cmd *qc) | |
265 | { | |
266 | struct ata_port *ap = qc->ap; | |
267 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; | |
268 | ||
269 | /* load PRD table addr. */ | |
f60d7011 | 270 | iowrite32(ap->bmdma_prd_dma, bmdma + ATA_DMA_TABLE_OFS); |
c7e324f1 RH |
271 | |
272 | /* issue r/w command */ | |
273 | ap->ops->sff_exec_command(ap, &qc->tf); | |
274 | } | |
275 | ||
276 | static void sil_bmdma_start(struct ata_queued_cmd *qc) | |
277 | { | |
278 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
279 | struct ata_port *ap = qc->ap; | |
280 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; | |
281 | void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; | |
282 | u8 dmactl = ATA_DMA_START; | |
283 | ||
284 | /* set transfer direction, start host DMA transaction | |
285 | Note: For Large Block Transfer to work, the DMA must be started | |
286 | using the bmdma2 register. */ | |
287 | if (!rw) | |
288 | dmactl |= ATA_DMA_WR; | |
289 | iowrite8(dmactl, bmdma2); | |
290 | } | |
291 | ||
292 | /* The way God intended PCI IDE scatter/gather lists to look and behave... */ | |
293 | static void sil_fill_sg(struct ata_queued_cmd *qc) | |
294 | { | |
295 | struct scatterlist *sg; | |
296 | struct ata_port *ap = qc->ap; | |
f60d7011 | 297 | struct ata_bmdma_prd *prd, *last_prd = NULL; |
c7e324f1 RH |
298 | unsigned int si; |
299 | ||
f60d7011 | 300 | prd = &ap->bmdma_prd[0]; |
c7e324f1 RH |
301 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
302 | /* Note h/w doesn't support 64-bit, so we unconditionally | |
303 | * truncate dma_addr_t to u32. | |
304 | */ | |
305 | u32 addr = (u32) sg_dma_address(sg); | |
306 | u32 sg_len = sg_dma_len(sg); | |
307 | ||
308 | prd->addr = cpu_to_le32(addr); | |
309 | prd->flags_len = cpu_to_le32(sg_len); | |
41137aa6 | 310 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len); |
c7e324f1 RH |
311 | |
312 | last_prd = prd; | |
313 | prd++; | |
314 | } | |
315 | ||
316 | if (likely(last_prd)) | |
317 | last_prd->flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
318 | } | |
319 | ||
95364f36 | 320 | static enum ata_completion_errors sil_qc_prep(struct ata_queued_cmd *qc) |
c7e324f1 RH |
321 | { |
322 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
95364f36 | 323 | return AC_ERR_OK; |
c7e324f1 RH |
324 | |
325 | sil_fill_sg(qc); | |
95364f36 JS |
326 | |
327 | return AC_ERR_OK; | |
c7e324f1 RH |
328 | } |
329 | ||
1da177e4 LT |
330 | static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) |
331 | { | |
332 | u8 cache_line = 0; | |
333 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); | |
334 | return cache_line; | |
335 | } | |
336 | ||
9d2c7c75 AC |
337 | /** |
338 | * sil_set_mode - wrap set_mode functions | |
0260731f | 339 | * @link: link to set up |
9d2c7c75 AC |
340 | * @r_failed: returned device when we fail |
341 | * | |
342 | * Wrap the libata method for device setup as after the setup we need | |
343 | * to inspect the results and do some configuration work | |
344 | */ | |
345 | ||
0260731f | 346 | static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed) |
1da177e4 | 347 | { |
0260731f TH |
348 | struct ata_port *ap = link->ap; |
349 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; | |
0d5ff566 | 350 | void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; |
0260731f | 351 | struct ata_device *dev; |
f58229f8 | 352 | u32 tmp, dev_mode[2] = { }; |
9d2c7c75 | 353 | int rc; |
a617c09f | 354 | |
0260731f | 355 | rc = ata_do_set_mode(link, r_failed); |
9d2c7c75 AC |
356 | if (rc) |
357 | return rc; | |
1da177e4 | 358 | |
1eca4365 | 359 | ata_for_each_dev(dev, link, ALL) { |
e1211e3f | 360 | if (!ata_dev_enabled(dev)) |
f58229f8 | 361 | dev_mode[dev->devno] = 0; /* PIO0/1/2 */ |
1da177e4 | 362 | else if (dev->flags & ATA_DFLAG_PIO) |
f58229f8 | 363 | dev_mode[dev->devno] = 1; /* PIO3/4 */ |
1da177e4 | 364 | else |
f58229f8 | 365 | dev_mode[dev->devno] = 3; /* UDMA */ |
1da177e4 LT |
366 | /* value 2 indicates MDMA */ |
367 | } | |
368 | ||
369 | tmp = readl(addr); | |
370 | tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); | |
371 | tmp |= dev_mode[0]; | |
372 | tmp |= (dev_mode[1] << 4); | |
373 | writel(tmp, addr); | |
374 | readl(addr); /* flush */ | |
9d2c7c75 | 375 | return 0; |
1da177e4 LT |
376 | } |
377 | ||
5796d1c4 JG |
378 | static inline void __iomem *sil_scr_addr(struct ata_port *ap, |
379 | unsigned int sc_reg) | |
1da177e4 | 380 | { |
0d5ff566 | 381 | void __iomem *offset = ap->ioaddr.scr_addr; |
1da177e4 LT |
382 | |
383 | switch (sc_reg) { | |
384 | case SCR_STATUS: | |
385 | return offset + 4; | |
386 | case SCR_ERROR: | |
387 | return offset + 8; | |
388 | case SCR_CONTROL: | |
389 | return offset; | |
390 | default: | |
391 | /* do nothing */ | |
392 | break; | |
393 | } | |
394 | ||
8d9db2d2 | 395 | return NULL; |
1da177e4 LT |
396 | } |
397 | ||
82ef04fb | 398 | static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) |
1da177e4 | 399 | { |
82ef04fb | 400 | void __iomem *mmio = sil_scr_addr(link->ap, sc_reg); |
da3dbb17 TH |
401 | |
402 | if (mmio) { | |
403 | *val = readl(mmio); | |
404 | return 0; | |
405 | } | |
406 | return -EINVAL; | |
1da177e4 LT |
407 | } |
408 | ||
82ef04fb | 409 | static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) |
1da177e4 | 410 | { |
82ef04fb | 411 | void __iomem *mmio = sil_scr_addr(link->ap, sc_reg); |
da3dbb17 TH |
412 | |
413 | if (mmio) { | |
1da177e4 | 414 | writel(val, mmio); |
da3dbb17 TH |
415 | return 0; |
416 | } | |
417 | return -EINVAL; | |
1da177e4 LT |
418 | } |
419 | ||
cbe88fbc TH |
420 | static void sil_host_intr(struct ata_port *ap, u32 bmdma2) |
421 | { | |
9af5c9c9 TH |
422 | struct ata_eh_info *ehi = &ap->link.eh_info; |
423 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
cbe88fbc TH |
424 | u8 status; |
425 | ||
e573890b | 426 | if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) { |
ebd1699e | 427 | u32 serror = 0xffffffff; |
d4c85325 TH |
428 | |
429 | /* SIEN doesn't mask SATA IRQs on some 3112s. Those | |
430 | * controllers continue to assert IRQ as long as | |
431 | * SError bits are pending. Clear SError immediately. | |
432 | */ | |
82ef04fb TH |
433 | sil_scr_read(&ap->link, SCR_ERROR, &serror); |
434 | sil_scr_write(&ap->link, SCR_ERROR, serror); | |
d4c85325 | 435 | |
8cf32ac6 TH |
436 | /* Sometimes spurious interrupts occur, double check |
437 | * it's PHYRDY CHG. | |
d4c85325 | 438 | */ |
8cf32ac6 | 439 | if (serror & SERR_PHYRDY_CHG) { |
f7fe7ad4 | 440 | ap->link.eh_info.serror |= serror; |
8cf32ac6 | 441 | goto freeze; |
d4c85325 TH |
442 | } |
443 | ||
8cf32ac6 TH |
444 | if (!(bmdma2 & SIL_DMA_COMPLETE)) |
445 | return; | |
e573890b TH |
446 | } |
447 | ||
8cf32ac6 | 448 | if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { |
e2f8fb72 | 449 | /* this sometimes happens, just clear IRQ */ |
5682ed33 | 450 | ap->ops->sff_check_status(ap); |
e2f8fb72 TH |
451 | return; |
452 | } | |
453 | ||
cbe88fbc TH |
454 | /* Check whether we are expecting interrupt in this state */ |
455 | switch (ap->hsm_task_state) { | |
456 | case HSM_ST_FIRST: | |
457 | /* Some pre-ATAPI-4 devices assert INTRQ | |
458 | * at this state when ready to receive CDB. | |
459 | */ | |
460 | ||
461 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
405e66b3 TH |
462 | * The flag was turned on only for atapi devices. No |
463 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
cbe88fbc TH |
464 | */ |
465 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
466 | goto err_hsm; | |
467 | break; | |
468 | case HSM_ST_LAST: | |
405e66b3 | 469 | if (ata_is_dma(qc->tf.protocol)) { |
cbe88fbc TH |
470 | /* clear DMA-Start bit */ |
471 | ap->ops->bmdma_stop(qc); | |
472 | ||
473 | if (bmdma2 & SIL_DMA_ERROR) { | |
474 | qc->err_mask |= AC_ERR_HOST_BUS; | |
475 | ap->hsm_task_state = HSM_ST_ERR; | |
476 | } | |
477 | } | |
478 | break; | |
479 | case HSM_ST: | |
480 | break; | |
481 | default: | |
482 | goto err_hsm; | |
483 | } | |
484 | ||
485 | /* check main status, clearing INTRQ */ | |
5682ed33 | 486 | status = ap->ops->sff_check_status(ap); |
cbe88fbc TH |
487 | if (unlikely(status & ATA_BUSY)) |
488 | goto err_hsm; | |
489 | ||
490 | /* ack bmdma irq events */ | |
37f65b8b | 491 | ata_bmdma_irq_clear(ap); |
cbe88fbc TH |
492 | |
493 | /* kick HSM in the ass */ | |
9363c382 | 494 | ata_sff_hsm_move(ap, qc, status, 0); |
cbe88fbc | 495 | |
405e66b3 | 496 | if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol)) |
ea54763f TH |
497 | ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2); |
498 | ||
cbe88fbc TH |
499 | return; |
500 | ||
501 | err_hsm: | |
502 | qc->err_mask |= AC_ERR_HSM; | |
503 | freeze: | |
504 | ata_port_freeze(ap); | |
505 | } | |
506 | ||
7d12e780 | 507 | static irqreturn_t sil_interrupt(int irq, void *dev_instance) |
cbe88fbc | 508 | { |
cca3974e | 509 | struct ata_host *host = dev_instance; |
0d5ff566 | 510 | void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; |
cbe88fbc TH |
511 | int handled = 0; |
512 | int i; | |
513 | ||
cca3974e | 514 | spin_lock(&host->lock); |
cbe88fbc | 515 | |
cca3974e JG |
516 | for (i = 0; i < host->n_ports; i++) { |
517 | struct ata_port *ap = host->ports[i]; | |
cbe88fbc TH |
518 | u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); |
519 | ||
201ce859 TH |
520 | /* turn off SATA_IRQ if not supported */ |
521 | if (ap->flags & SIL_FLAG_NO_SATA_IRQ) | |
522 | bmdma2 &= ~SIL_DMA_SATA_IRQ; | |
523 | ||
23fa9618 TH |
524 | if (bmdma2 == 0xffffffff || |
525 | !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ))) | |
cbe88fbc TH |
526 | continue; |
527 | ||
528 | sil_host_intr(ap, bmdma2); | |
529 | handled = 1; | |
530 | } | |
531 | ||
cca3974e | 532 | spin_unlock(&host->lock); |
cbe88fbc TH |
533 | |
534 | return IRQ_RETVAL(handled); | |
535 | } | |
536 | ||
f6aae27e TH |
537 | static void sil_freeze(struct ata_port *ap) |
538 | { | |
0d5ff566 | 539 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
f6aae27e TH |
540 | u32 tmp; |
541 | ||
e573890b TH |
542 | /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ |
543 | writel(0, mmio_base + sil_port[ap->port_no].sien); | |
544 | ||
f6aae27e TH |
545 | /* plug IRQ */ |
546 | tmp = readl(mmio_base + SIL_SYSCFG); | |
547 | tmp |= SIL_MASK_IDE0_INT << ap->port_no; | |
548 | writel(tmp, mmio_base + SIL_SYSCFG); | |
549 | readl(mmio_base + SIL_SYSCFG); /* flush */ | |
2fc37adb JG |
550 | |
551 | /* Ensure DMA_ENABLE is off. | |
552 | * | |
553 | * This is because the controller will not give us access to the | |
554 | * taskfile registers while a DMA is in progress | |
555 | */ | |
556 | iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE, | |
557 | ap->ioaddr.bmdma_addr); | |
558 | ||
559 | /* According to ata_bmdma_stop, an HDMA transition requires | |
560 | * on PIO cycle. But we can't read a taskfile register. | |
561 | */ | |
562 | ioread8(ap->ioaddr.bmdma_addr); | |
f6aae27e TH |
563 | } |
564 | ||
565 | static void sil_thaw(struct ata_port *ap) | |
566 | { | |
0d5ff566 | 567 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
f6aae27e TH |
568 | u32 tmp; |
569 | ||
570 | /* clear IRQ */ | |
5682ed33 | 571 | ap->ops->sff_check_status(ap); |
37f65b8b | 572 | ata_bmdma_irq_clear(ap); |
f6aae27e | 573 | |
201ce859 TH |
574 | /* turn on SATA IRQ if supported */ |
575 | if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ)) | |
576 | writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); | |
e573890b | 577 | |
f6aae27e TH |
578 | /* turn on IRQ */ |
579 | tmp = readl(mmio_base + SIL_SYSCFG); | |
580 | tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); | |
581 | writel(tmp, mmio_base + SIL_SYSCFG); | |
582 | } | |
583 | ||
1da177e4 LT |
584 | /** |
585 | * sil_dev_config - Apply device/host-specific errata fixups | |
1da177e4 LT |
586 | * @dev: Device to be examined |
587 | * | |
588 | * After the IDENTIFY [PACKET] DEVICE step is complete, and a | |
589 | * device is known to be present, this function is called. | |
590 | * We apply two errata fixups which are specific to Silicon Image, | |
591 | * a Seagate and a Maxtor fixup. | |
592 | * | |
593 | * For certain Seagate devices, we must limit the maximum sectors | |
594 | * to under 8K. | |
595 | * | |
596 | * For certain Maxtor devices, we must not program the drive | |
597 | * beyond udma5. | |
598 | * | |
599 | * Both fixups are unfairly pessimistic. As soon as I get more | |
600 | * information on these errata, I will create a more exhaustive | |
601 | * list, and apply the fixups to only the specific | |
602 | * devices/hosts/firmwares that need it. | |
603 | * | |
604 | * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted | |
605 | * The Maxtor quirk is in the blacklist, but I'm keeping the original | |
606 | * pessimistic fix for the following reasons... | |
607 | * - There seems to be less info on it, only one device gleaned off the | |
608 | * Windows driver, maybe only one is affected. More info would be greatly | |
609 | * appreciated. | |
610 | * - But then again UDMA5 is hardly anything to complain about | |
611 | */ | |
cd0d3bbc | 612 | static void sil_dev_config(struct ata_device *dev) |
1da177e4 | 613 | { |
9af5c9c9 TH |
614 | struct ata_port *ap = dev->link->ap; |
615 | int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO; | |
1da177e4 | 616 | unsigned int n, quirks = 0; |
a0cf733b | 617 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
1da177e4 | 618 | |
d98f1cd0 MP |
619 | /* This controller doesn't support trim */ |
620 | dev->horkage |= ATA_HORKAGE_NOTRIM; | |
621 | ||
a0cf733b | 622 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
1da177e4 | 623 | |
8a60a071 | 624 | for (n = 0; sil_blacklist[n].product; n++) |
2e02671d | 625 | if (!strcmp(sil_blacklist[n].product, model_num)) { |
1da177e4 LT |
626 | quirks = sil_blacklist[n].quirk; |
627 | break; | |
628 | } | |
8a60a071 | 629 | |
1da177e4 | 630 | /* limit requests to 15 sectors */ |
51e9f2ff JG |
631 | if (slow_down || |
632 | ((ap->flags & SIL_FLAG_MOD15WRITE) && | |
633 | (quirks & SIL_QUIRK_MOD15WRITE))) { | |
efdaedc4 | 634 | if (print_info) |
a9a79dfe JP |
635 | ata_dev_info(dev, |
636 | "applying Seagate errata fix (mod15write workaround)\n"); | |
b00eec1d | 637 | dev->max_sectors = 15; |
1da177e4 LT |
638 | return; |
639 | } | |
640 | ||
641 | /* limit to udma5 */ | |
642 | if (quirks & SIL_QUIRK_UDMA5MAX) { | |
efdaedc4 | 643 | if (print_info) |
a9a79dfe JP |
644 | ata_dev_info(dev, "applying Maxtor errata fix %s\n", |
645 | model_num); | |
5a529139 | 646 | dev->udma_mask &= ATA_UDMA5; |
1da177e4 LT |
647 | return; |
648 | } | |
649 | } | |
650 | ||
4447d351 | 651 | static void sil_init_controller(struct ata_host *host) |
3d8ec913 | 652 | { |
4447d351 TH |
653 | struct pci_dev *pdev = to_pci_dev(host->dev); |
654 | void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; | |
3d8ec913 TH |
655 | u8 cls; |
656 | u32 tmp; | |
657 | int i; | |
658 | ||
659 | /* Initialize FIFO PCI bus arbitration */ | |
660 | cls = sil_get_device_cache_line(pdev); | |
661 | if (cls) { | |
662 | cls >>= 3; | |
663 | cls++; /* cls = (line_size/8)+1 */ | |
4447d351 | 664 | for (i = 0; i < host->n_ports; i++) |
3d8ec913 TH |
665 | writew(cls << 8 | cls, |
666 | mmio_base + sil_port[i].fifo_cfg); | |
667 | } else | |
a44fec1f JP |
668 | dev_warn(&pdev->dev, |
669 | "cache line size not set. Driver may not function\n"); | |
3d8ec913 TH |
670 | |
671 | /* Apply R_ERR on DMA activate FIS errata workaround */ | |
4447d351 | 672 | if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) { |
3d8ec913 TH |
673 | int cnt; |
674 | ||
4447d351 | 675 | for (i = 0, cnt = 0; i < host->n_ports; i++) { |
3d8ec913 TH |
676 | tmp = readl(mmio_base + sil_port[i].sfis_cfg); |
677 | if ((tmp & 0x3) != 0x01) | |
678 | continue; | |
679 | if (!cnt) | |
a44fec1f JP |
680 | dev_info(&pdev->dev, |
681 | "Applying R_ERR on DMA activate FIS errata fix\n"); | |
3d8ec913 TH |
682 | writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); |
683 | cnt++; | |
684 | } | |
685 | } | |
686 | ||
4447d351 | 687 | if (host->n_ports == 4) { |
3d8ec913 TH |
688 | /* flip the magic "make 4 ports work" bit */ |
689 | tmp = readl(mmio_base + sil_port[2].bmdma); | |
690 | if ((tmp & SIL_INTR_STEERING) == 0) | |
691 | writel(tmp | SIL_INTR_STEERING, | |
692 | mmio_base + sil_port[2].bmdma); | |
693 | } | |
694 | } | |
695 | ||
e57db7bd RW |
696 | static bool sil_broken_system_poweroff(struct pci_dev *pdev) |
697 | { | |
698 | static const struct dmi_system_id broken_systems[] = { | |
699 | { | |
700 | .ident = "HP Compaq nx6325", | |
701 | .matches = { | |
702 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
703 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"), | |
704 | }, | |
705 | /* PCI slot number of the controller */ | |
706 | .driver_data = (void *)0x12UL, | |
707 | }, | |
708 | ||
709 | { } /* terminate list */ | |
710 | }; | |
711 | const struct dmi_system_id *dmi = dmi_first_match(broken_systems); | |
712 | ||
713 | if (dmi) { | |
714 | unsigned long slot = (unsigned long)dmi->driver_data; | |
715 | /* apply the quirk only to on-board controllers */ | |
716 | return slot == PCI_SLOT(pdev->devfn); | |
717 | } | |
718 | ||
719 | return false; | |
720 | } | |
721 | ||
5796d1c4 | 722 | static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 723 | { |
4447d351 | 724 | int board_id = ent->driver_data; |
e57db7bd RW |
725 | struct ata_port_info pi = sil_port_info[board_id]; |
726 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
4447d351 | 727 | struct ata_host *host; |
ea6ba10b | 728 | void __iomem *mmio_base; |
4447d351 | 729 | int n_ports, rc; |
1da177e4 | 730 | unsigned int i; |
1da177e4 | 731 | |
06296a1e | 732 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
1da177e4 | 733 | |
4447d351 TH |
734 | /* allocate host */ |
735 | n_ports = 2; | |
736 | if (board_id == sil_3114) | |
737 | n_ports = 4; | |
738 | ||
e57db7bd RW |
739 | if (sil_broken_system_poweroff(pdev)) { |
740 | pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN | | |
741 | ATA_FLAG_NO_HIBERNATE_SPINDOWN; | |
742 | dev_info(&pdev->dev, "quirky BIOS, skipping spindown " | |
743 | "on poweroff and hibernation\n"); | |
744 | } | |
745 | ||
4447d351 TH |
746 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
747 | if (!host) | |
748 | return -ENOMEM; | |
749 | ||
750 | /* acquire resources and fill host */ | |
24dc5f33 | 751 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
752 | if (rc) |
753 | return rc; | |
754 | ||
0d5ff566 TH |
755 | rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME); |
756 | if (rc == -EBUSY) | |
24dc5f33 | 757 | pcim_pin_device(pdev); |
0d5ff566 | 758 | if (rc) |
24dc5f33 | 759 | return rc; |
4447d351 | 760 | host->iomap = pcim_iomap_table(pdev); |
1da177e4 | 761 | |
b5e55556 | 762 | rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); |
1da177e4 | 763 | if (rc) |
24dc5f33 | 764 | return rc; |
1da177e4 | 765 | |
4447d351 | 766 | mmio_base = host->iomap[SIL_MMIO_BAR]; |
1da177e4 | 767 | |
4447d351 | 768 | for (i = 0; i < host->n_ports; i++) { |
cbcdd875 TH |
769 | struct ata_port *ap = host->ports[i]; |
770 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
4447d351 TH |
771 | |
772 | ioaddr->cmd_addr = mmio_base + sil_port[i].tf; | |
773 | ioaddr->altstatus_addr = | |
774 | ioaddr->ctl_addr = mmio_base + sil_port[i].ctl; | |
775 | ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma; | |
776 | ioaddr->scr_addr = mmio_base + sil_port[i].scr; | |
9363c382 | 777 | ata_sff_std_ports(ioaddr); |
cbcdd875 TH |
778 | |
779 | ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio"); | |
780 | ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf"); | |
1da177e4 LT |
781 | } |
782 | ||
4447d351 TH |
783 | /* initialize and activate */ |
784 | sil_init_controller(host); | |
1da177e4 | 785 | |
1da177e4 | 786 | pci_set_master(pdev); |
4447d351 TH |
787 | return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED, |
788 | &sil_sht); | |
1da177e4 LT |
789 | } |
790 | ||
58eb8cd5 | 791 | #ifdef CONFIG_PM_SLEEP |
afb5a7cb TH |
792 | static int sil_pci_device_resume(struct pci_dev *pdev) |
793 | { | |
0a86e1c8 | 794 | struct ata_host *host = pci_get_drvdata(pdev); |
553c4aa6 TH |
795 | int rc; |
796 | ||
797 | rc = ata_pci_device_do_resume(pdev); | |
798 | if (rc) | |
799 | return rc; | |
afb5a7cb | 800 | |
4447d351 | 801 | sil_init_controller(host); |
cca3974e | 802 | ata_host_resume(host); |
afb5a7cb TH |
803 | |
804 | return 0; | |
805 | } | |
281d426c | 806 | #endif |
afb5a7cb | 807 | |
2fc75da0 | 808 | module_pci_driver(sil_pci_driver); |