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1da177e4 LT |
1 | /* |
2 | * sata_sil.c - Silicon Image SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
af36d7f0 | 8 | * Copyright 2003-2005 Red Hat, Inc. |
1da177e4 LT |
9 | * Copyright 2003 Benjamin Herrenschmidt |
10 | * | |
af36d7f0 JG |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
1da177e4 | 29 | * |
953d1137 JG |
30 | * Documentation for SiI 3112: |
31 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
32 | * | |
33 | * Other errata and documentation available under NDA. | |
34 | * | |
1da177e4 LT |
35 | */ |
36 | ||
37 | #include <linux/kernel.h> | |
38 | #include <linux/module.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/blkdev.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/interrupt.h> | |
a9524a76 | 44 | #include <linux/device.h> |
1da177e4 LT |
45 | #include <scsi/scsi_host.h> |
46 | #include <linux/libata.h> | |
47 | ||
48 | #define DRV_NAME "sata_sil" | |
2a3103ce | 49 | #define DRV_VERSION "2.3" |
1da177e4 LT |
50 | |
51 | enum { | |
0d5ff566 TH |
52 | SIL_MMIO_BAR = 5, |
53 | ||
e653a1e6 TH |
54 | /* |
55 | * host flags | |
56 | */ | |
201ce859 | 57 | SIL_FLAG_NO_SATA_IRQ = (1 << 28), |
e4e10e3e | 58 | SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), |
e4deec63 | 59 | SIL_FLAG_MOD15WRITE = (1 << 30), |
20888d83 | 60 | |
cca3974e | 61 | SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
e573890b | 62 | ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME, |
e4deec63 | 63 | |
e653a1e6 TH |
64 | /* |
65 | * Controller IDs | |
66 | */ | |
1da177e4 | 67 | sil_3112 = 0, |
201ce859 TH |
68 | sil_3112_no_sata_irq = 1, |
69 | sil_3512 = 2, | |
70 | sil_3114 = 3, | |
1da177e4 | 71 | |
e653a1e6 TH |
72 | /* |
73 | * Register offsets | |
74 | */ | |
1da177e4 | 75 | SIL_SYSCFG = 0x48, |
e653a1e6 TH |
76 | |
77 | /* | |
78 | * Register bits | |
79 | */ | |
80 | /* SYSCFG */ | |
1da177e4 LT |
81 | SIL_MASK_IDE0_INT = (1 << 22), |
82 | SIL_MASK_IDE1_INT = (1 << 23), | |
83 | SIL_MASK_IDE2_INT = (1 << 24), | |
84 | SIL_MASK_IDE3_INT = (1 << 25), | |
85 | SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, | |
86 | SIL_MASK_4PORT = SIL_MASK_2PORT | | |
87 | SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, | |
88 | ||
e653a1e6 | 89 | /* BMDMA/BMDMA2 */ |
1da177e4 | 90 | SIL_INTR_STEERING = (1 << 1), |
e653a1e6 | 91 | |
20888d83 TH |
92 | SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ |
93 | SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ | |
94 | SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ | |
95 | SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ | |
96 | SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ | |
97 | SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ | |
98 | SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ | |
99 | SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ | |
100 | SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ | |
101 | SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ | |
102 | ||
103 | /* SIEN */ | |
104 | SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ | |
105 | ||
e653a1e6 TH |
106 | /* |
107 | * Others | |
108 | */ | |
1da177e4 LT |
109 | SIL_QUIRK_MOD15WRITE = (1 << 0), |
110 | SIL_QUIRK_UDMA5MAX = (1 << 1), | |
111 | }; | |
112 | ||
113 | static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
281d426c | 114 | #ifdef CONFIG_PM |
afb5a7cb | 115 | static int sil_pci_device_resume(struct pci_dev *pdev); |
281d426c | 116 | #endif |
cd0d3bbc | 117 | static void sil_dev_config(struct ata_device *dev); |
da3dbb17 TH |
118 | static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
119 | static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
9d2c7c75 | 120 | static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed); |
f6aae27e TH |
121 | static void sil_freeze(struct ata_port *ap); |
122 | static void sil_thaw(struct ata_port *ap); | |
1da177e4 | 123 | |
374b1873 | 124 | |
3b7d697d | 125 | static const struct pci_device_id sil_pci_tbl[] = { |
54bb3a94 JG |
126 | { PCI_VDEVICE(CMD, 0x3112), sil_3112 }, |
127 | { PCI_VDEVICE(CMD, 0x0240), sil_3112 }, | |
128 | { PCI_VDEVICE(CMD, 0x3512), sil_3512 }, | |
129 | { PCI_VDEVICE(CMD, 0x3114), sil_3114 }, | |
130 | { PCI_VDEVICE(ATI, 0x436e), sil_3112 }, | |
131 | { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq }, | |
132 | { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq }, | |
133 | ||
1da177e4 LT |
134 | { } /* terminate list */ |
135 | }; | |
136 | ||
137 | ||
138 | /* TODO firmware versions should be added - eric */ | |
139 | static const struct sil_drivelist { | |
140 | const char * product; | |
141 | unsigned int quirk; | |
142 | } sil_blacklist [] = { | |
143 | { "ST320012AS", SIL_QUIRK_MOD15WRITE }, | |
144 | { "ST330013AS", SIL_QUIRK_MOD15WRITE }, | |
145 | { "ST340017AS", SIL_QUIRK_MOD15WRITE }, | |
146 | { "ST360015AS", SIL_QUIRK_MOD15WRITE }, | |
1da177e4 LT |
147 | { "ST380023AS", SIL_QUIRK_MOD15WRITE }, |
148 | { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, | |
1da177e4 LT |
149 | { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, |
150 | { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, | |
151 | { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, | |
152 | { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, | |
153 | { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, | |
154 | { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, | |
155 | { } | |
156 | }; | |
157 | ||
158 | static struct pci_driver sil_pci_driver = { | |
159 | .name = DRV_NAME, | |
160 | .id_table = sil_pci_tbl, | |
161 | .probe = sil_init_one, | |
162 | .remove = ata_pci_remove_one, | |
281d426c | 163 | #ifdef CONFIG_PM |
afb5a7cb TH |
164 | .suspend = ata_pci_device_suspend, |
165 | .resume = sil_pci_device_resume, | |
281d426c | 166 | #endif |
1da177e4 LT |
167 | }; |
168 | ||
193515d5 | 169 | static struct scsi_host_template sil_sht = { |
1da177e4 LT |
170 | .module = THIS_MODULE, |
171 | .name = DRV_NAME, | |
172 | .ioctl = ata_scsi_ioctl, | |
173 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
174 | .can_queue = ATA_DEF_QUEUE, |
175 | .this_id = ATA_SHT_THIS_ID, | |
176 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
177 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
178 | .emulated = ATA_SHT_EMULATED, | |
179 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
180 | .proc_name = DRV_NAME, | |
181 | .dma_boundary = ATA_DMA_BOUNDARY, | |
182 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 183 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 184 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
185 | }; |
186 | ||
057ace5e | 187 | static const struct ata_port_operations sil_ops = { |
1da177e4 LT |
188 | .port_disable = ata_port_disable, |
189 | .dev_config = sil_dev_config, | |
190 | .tf_load = ata_tf_load, | |
191 | .tf_read = ata_tf_read, | |
192 | .check_status = ata_check_status, | |
193 | .exec_command = ata_exec_command, | |
194 | .dev_select = ata_std_dev_select, | |
9d2c7c75 | 195 | .set_mode = sil_set_mode, |
1da177e4 LT |
196 | .bmdma_setup = ata_bmdma_setup, |
197 | .bmdma_start = ata_bmdma_start, | |
198 | .bmdma_stop = ata_bmdma_stop, | |
199 | .bmdma_status = ata_bmdma_status, | |
200 | .qc_prep = ata_qc_prep, | |
201 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 202 | .data_xfer = ata_data_xfer, |
f6aae27e TH |
203 | .freeze = sil_freeze, |
204 | .thaw = sil_thaw, | |
205 | .error_handler = ata_bmdma_error_handler, | |
206 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
1da177e4 | 207 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 AI |
208 | .irq_on = ata_irq_on, |
209 | .irq_ack = ata_irq_ack, | |
1da177e4 LT |
210 | .scr_read = sil_scr_read, |
211 | .scr_write = sil_scr_write, | |
212 | .port_start = ata_port_start, | |
1da177e4 LT |
213 | }; |
214 | ||
98ac62de | 215 | static const struct ata_port_info sil_port_info[] = { |
1da177e4 | 216 | /* sil_3112 */ |
e4deec63 | 217 | { |
cca3974e | 218 | .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE, |
e4deec63 TH |
219 | .pio_mask = 0x1f, /* pio0-4 */ |
220 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 221 | .udma_mask = ATA_UDMA5, |
e4deec63 | 222 | .port_ops = &sil_ops, |
0ee304d5 | 223 | }, |
201ce859 TH |
224 | /* sil_3112_no_sata_irq */ |
225 | { | |
cca3974e | 226 | .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE | |
201ce859 TH |
227 | SIL_FLAG_NO_SATA_IRQ, |
228 | .pio_mask = 0x1f, /* pio0-4 */ | |
229 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 230 | .udma_mask = ATA_UDMA5, |
201ce859 TH |
231 | .port_ops = &sil_ops, |
232 | }, | |
0ee304d5 | 233 | /* sil_3512 */ |
1da177e4 | 234 | { |
cca3974e | 235 | .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
0ee304d5 TH |
236 | .pio_mask = 0x1f, /* pio0-4 */ |
237 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 238 | .udma_mask = ATA_UDMA5, |
0ee304d5 TH |
239 | .port_ops = &sil_ops, |
240 | }, | |
241 | /* sil_3114 */ | |
1da177e4 | 242 | { |
cca3974e | 243 | .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
1da177e4 LT |
244 | .pio_mask = 0x1f, /* pio0-4 */ |
245 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 246 | .udma_mask = ATA_UDMA5, |
1da177e4 LT |
247 | .port_ops = &sil_ops, |
248 | }, | |
249 | }; | |
250 | ||
251 | /* per-port register offsets */ | |
252 | /* TODO: we can probably calculate rather than use a table */ | |
253 | static const struct { | |
254 | unsigned long tf; /* ATA taskfile register block */ | |
255 | unsigned long ctl; /* ATA control/altstatus register block */ | |
256 | unsigned long bmdma; /* DMA register block */ | |
20888d83 | 257 | unsigned long bmdma2; /* DMA register block #2 */ |
48d4ef2a | 258 | unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ |
1da177e4 LT |
259 | unsigned long scr; /* SATA control register block */ |
260 | unsigned long sien; /* SATA Interrupt Enable register */ | |
261 | unsigned long xfer_mode;/* data transfer mode register */ | |
e4e10e3e | 262 | unsigned long sfis_cfg; /* SATA FIS reception config register */ |
1da177e4 LT |
263 | } sil_port[] = { |
264 | /* port 0 ... */ | |
5bcd7a00 JG |
265 | /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */ |
266 | { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, | |
267 | { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, | |
20888d83 TH |
268 | { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, |
269 | { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, | |
1da177e4 LT |
270 | /* ... port 3 */ |
271 | }; | |
272 | ||
273 | MODULE_AUTHOR("Jeff Garzik"); | |
274 | MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); | |
275 | MODULE_LICENSE("GPL"); | |
276 | MODULE_DEVICE_TABLE(pci, sil_pci_tbl); | |
277 | MODULE_VERSION(DRV_VERSION); | |
278 | ||
51e9f2ff JG |
279 | static int slow_down = 0; |
280 | module_param(slow_down, int, 0444); | |
281 | MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); | |
282 | ||
374b1873 | 283 | |
1da177e4 LT |
284 | static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) |
285 | { | |
286 | u8 cache_line = 0; | |
287 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); | |
288 | return cache_line; | |
289 | } | |
290 | ||
9d2c7c75 AC |
291 | /** |
292 | * sil_set_mode - wrap set_mode functions | |
293 | * @ap: port to set up | |
294 | * @r_failed: returned device when we fail | |
295 | * | |
296 | * Wrap the libata method for device setup as after the setup we need | |
297 | * to inspect the results and do some configuration work | |
298 | */ | |
299 | ||
300 | static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed) | |
1da177e4 | 301 | { |
cca3974e | 302 | struct ata_host *host = ap->host; |
1da177e4 | 303 | struct ata_device *dev; |
0d5ff566 TH |
304 | void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; |
305 | void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; | |
f58229f8 | 306 | u32 tmp, dev_mode[2] = { }; |
9d2c7c75 | 307 | int rc; |
a617c09f | 308 | |
9d2c7c75 AC |
309 | rc = ata_do_set_mode(ap, r_failed); |
310 | if (rc) | |
311 | return rc; | |
1da177e4 | 312 | |
f58229f8 | 313 | ata_link_for_each_dev(dev, &ap->link) { |
e1211e3f | 314 | if (!ata_dev_enabled(dev)) |
f58229f8 | 315 | dev_mode[dev->devno] = 0; /* PIO0/1/2 */ |
1da177e4 | 316 | else if (dev->flags & ATA_DFLAG_PIO) |
f58229f8 | 317 | dev_mode[dev->devno] = 1; /* PIO3/4 */ |
1da177e4 | 318 | else |
f58229f8 | 319 | dev_mode[dev->devno] = 3; /* UDMA */ |
1da177e4 LT |
320 | /* value 2 indicates MDMA */ |
321 | } | |
322 | ||
323 | tmp = readl(addr); | |
324 | tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); | |
325 | tmp |= dev_mode[0]; | |
326 | tmp |= (dev_mode[1] << 4); | |
327 | writel(tmp, addr); | |
328 | readl(addr); /* flush */ | |
9d2c7c75 | 329 | return 0; |
1da177e4 LT |
330 | } |
331 | ||
0d5ff566 | 332 | static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 333 | { |
0d5ff566 | 334 | void __iomem *offset = ap->ioaddr.scr_addr; |
1da177e4 LT |
335 | |
336 | switch (sc_reg) { | |
337 | case SCR_STATUS: | |
338 | return offset + 4; | |
339 | case SCR_ERROR: | |
340 | return offset + 8; | |
341 | case SCR_CONTROL: | |
342 | return offset; | |
343 | default: | |
344 | /* do nothing */ | |
345 | break; | |
346 | } | |
347 | ||
8d9db2d2 | 348 | return NULL; |
1da177e4 LT |
349 | } |
350 | ||
da3dbb17 | 351 | static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 352 | { |
0d5ff566 | 353 | void __iomem *mmio = sil_scr_addr(ap, sc_reg); |
da3dbb17 TH |
354 | |
355 | if (mmio) { | |
356 | *val = readl(mmio); | |
357 | return 0; | |
358 | } | |
359 | return -EINVAL; | |
1da177e4 LT |
360 | } |
361 | ||
da3dbb17 | 362 | static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 | 363 | { |
0d5ff566 | 364 | void __iomem *mmio = sil_scr_addr(ap, sc_reg); |
da3dbb17 TH |
365 | |
366 | if (mmio) { | |
1da177e4 | 367 | writel(val, mmio); |
da3dbb17 TH |
368 | return 0; |
369 | } | |
370 | return -EINVAL; | |
1da177e4 LT |
371 | } |
372 | ||
cbe88fbc TH |
373 | static void sil_host_intr(struct ata_port *ap, u32 bmdma2) |
374 | { | |
9af5c9c9 TH |
375 | struct ata_eh_info *ehi = &ap->link.eh_info; |
376 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
cbe88fbc TH |
377 | u8 status; |
378 | ||
e573890b | 379 | if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) { |
d4c85325 TH |
380 | u32 serror; |
381 | ||
382 | /* SIEN doesn't mask SATA IRQs on some 3112s. Those | |
383 | * controllers continue to assert IRQ as long as | |
384 | * SError bits are pending. Clear SError immediately. | |
385 | */ | |
da3dbb17 | 386 | sil_scr_read(ap, SCR_ERROR, &serror); |
d4c85325 TH |
387 | sil_scr_write(ap, SCR_ERROR, serror); |
388 | ||
389 | /* Trigger hotplug and accumulate SError only if the | |
390 | * port isn't already frozen. Otherwise, PHY events | |
391 | * during hardreset makes controllers with broken SIEN | |
392 | * repeat probing needlessly. | |
393 | */ | |
b51e9e5d | 394 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
9af5c9c9 TH |
395 | ata_ehi_hotplugged(&ap->link.eh_info); |
396 | ap->link.eh_info.serror |= serror; | |
d4c85325 TH |
397 | } |
398 | ||
e573890b TH |
399 | goto freeze; |
400 | } | |
401 | ||
e2f8fb72 | 402 | if (unlikely(!qc)) |
cbe88fbc TH |
403 | goto freeze; |
404 | ||
e2f8fb72 TH |
405 | if (unlikely(qc->tf.flags & ATA_TFLAG_POLLING)) { |
406 | /* this sometimes happens, just clear IRQ */ | |
407 | ata_chk_status(ap); | |
408 | return; | |
409 | } | |
410 | ||
cbe88fbc TH |
411 | /* Check whether we are expecting interrupt in this state */ |
412 | switch (ap->hsm_task_state) { | |
413 | case HSM_ST_FIRST: | |
414 | /* Some pre-ATAPI-4 devices assert INTRQ | |
415 | * at this state when ready to receive CDB. | |
416 | */ | |
417 | ||
418 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
419 | * The flag was turned on only for atapi devices. | |
420 | * No need to check is_atapi_taskfile(&qc->tf) again. | |
421 | */ | |
422 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
423 | goto err_hsm; | |
424 | break; | |
425 | case HSM_ST_LAST: | |
426 | if (qc->tf.protocol == ATA_PROT_DMA || | |
427 | qc->tf.protocol == ATA_PROT_ATAPI_DMA) { | |
428 | /* clear DMA-Start bit */ | |
429 | ap->ops->bmdma_stop(qc); | |
430 | ||
431 | if (bmdma2 & SIL_DMA_ERROR) { | |
432 | qc->err_mask |= AC_ERR_HOST_BUS; | |
433 | ap->hsm_task_state = HSM_ST_ERR; | |
434 | } | |
435 | } | |
436 | break; | |
437 | case HSM_ST: | |
438 | break; | |
439 | default: | |
440 | goto err_hsm; | |
441 | } | |
442 | ||
443 | /* check main status, clearing INTRQ */ | |
444 | status = ata_chk_status(ap); | |
445 | if (unlikely(status & ATA_BUSY)) | |
446 | goto err_hsm; | |
447 | ||
448 | /* ack bmdma irq events */ | |
449 | ata_bmdma_irq_clear(ap); | |
450 | ||
451 | /* kick HSM in the ass */ | |
452 | ata_hsm_move(ap, qc, status, 0); | |
453 | ||
ea54763f TH |
454 | if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || |
455 | qc->tf.protocol == ATA_PROT_ATAPI_DMA)) | |
456 | ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2); | |
457 | ||
cbe88fbc TH |
458 | return; |
459 | ||
460 | err_hsm: | |
461 | qc->err_mask |= AC_ERR_HSM; | |
462 | freeze: | |
463 | ata_port_freeze(ap); | |
464 | } | |
465 | ||
7d12e780 | 466 | static irqreturn_t sil_interrupt(int irq, void *dev_instance) |
cbe88fbc | 467 | { |
cca3974e | 468 | struct ata_host *host = dev_instance; |
0d5ff566 | 469 | void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; |
cbe88fbc TH |
470 | int handled = 0; |
471 | int i; | |
472 | ||
cca3974e | 473 | spin_lock(&host->lock); |
cbe88fbc | 474 | |
cca3974e JG |
475 | for (i = 0; i < host->n_ports; i++) { |
476 | struct ata_port *ap = host->ports[i]; | |
cbe88fbc TH |
477 | u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); |
478 | ||
479 | if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED)) | |
480 | continue; | |
481 | ||
201ce859 TH |
482 | /* turn off SATA_IRQ if not supported */ |
483 | if (ap->flags & SIL_FLAG_NO_SATA_IRQ) | |
484 | bmdma2 &= ~SIL_DMA_SATA_IRQ; | |
485 | ||
23fa9618 TH |
486 | if (bmdma2 == 0xffffffff || |
487 | !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ))) | |
cbe88fbc TH |
488 | continue; |
489 | ||
490 | sil_host_intr(ap, bmdma2); | |
491 | handled = 1; | |
492 | } | |
493 | ||
cca3974e | 494 | spin_unlock(&host->lock); |
cbe88fbc TH |
495 | |
496 | return IRQ_RETVAL(handled); | |
497 | } | |
498 | ||
f6aae27e TH |
499 | static void sil_freeze(struct ata_port *ap) |
500 | { | |
0d5ff566 | 501 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
f6aae27e TH |
502 | u32 tmp; |
503 | ||
e573890b TH |
504 | /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ |
505 | writel(0, mmio_base + sil_port[ap->port_no].sien); | |
506 | ||
f6aae27e TH |
507 | /* plug IRQ */ |
508 | tmp = readl(mmio_base + SIL_SYSCFG); | |
509 | tmp |= SIL_MASK_IDE0_INT << ap->port_no; | |
510 | writel(tmp, mmio_base + SIL_SYSCFG); | |
511 | readl(mmio_base + SIL_SYSCFG); /* flush */ | |
512 | } | |
513 | ||
514 | static void sil_thaw(struct ata_port *ap) | |
515 | { | |
0d5ff566 | 516 | void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
f6aae27e TH |
517 | u32 tmp; |
518 | ||
519 | /* clear IRQ */ | |
520 | ata_chk_status(ap); | |
521 | ata_bmdma_irq_clear(ap); | |
522 | ||
201ce859 TH |
523 | /* turn on SATA IRQ if supported */ |
524 | if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ)) | |
525 | writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); | |
e573890b | 526 | |
f6aae27e TH |
527 | /* turn on IRQ */ |
528 | tmp = readl(mmio_base + SIL_SYSCFG); | |
529 | tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); | |
530 | writel(tmp, mmio_base + SIL_SYSCFG); | |
531 | } | |
532 | ||
1da177e4 LT |
533 | /** |
534 | * sil_dev_config - Apply device/host-specific errata fixups | |
1da177e4 LT |
535 | * @dev: Device to be examined |
536 | * | |
537 | * After the IDENTIFY [PACKET] DEVICE step is complete, and a | |
538 | * device is known to be present, this function is called. | |
539 | * We apply two errata fixups which are specific to Silicon Image, | |
540 | * a Seagate and a Maxtor fixup. | |
541 | * | |
542 | * For certain Seagate devices, we must limit the maximum sectors | |
543 | * to under 8K. | |
544 | * | |
545 | * For certain Maxtor devices, we must not program the drive | |
546 | * beyond udma5. | |
547 | * | |
548 | * Both fixups are unfairly pessimistic. As soon as I get more | |
549 | * information on these errata, I will create a more exhaustive | |
550 | * list, and apply the fixups to only the specific | |
551 | * devices/hosts/firmwares that need it. | |
552 | * | |
553 | * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted | |
554 | * The Maxtor quirk is in the blacklist, but I'm keeping the original | |
555 | * pessimistic fix for the following reasons... | |
556 | * - There seems to be less info on it, only one device gleaned off the | |
557 | * Windows driver, maybe only one is affected. More info would be greatly | |
558 | * appreciated. | |
559 | * - But then again UDMA5 is hardly anything to complain about | |
560 | */ | |
cd0d3bbc | 561 | static void sil_dev_config(struct ata_device *dev) |
1da177e4 | 562 | { |
9af5c9c9 TH |
563 | struct ata_port *ap = dev->link->ap; |
564 | int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO; | |
1da177e4 | 565 | unsigned int n, quirks = 0; |
a0cf733b | 566 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
1da177e4 | 567 | |
a0cf733b | 568 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
1da177e4 | 569 | |
8a60a071 | 570 | for (n = 0; sil_blacklist[n].product; n++) |
2e02671d | 571 | if (!strcmp(sil_blacklist[n].product, model_num)) { |
1da177e4 LT |
572 | quirks = sil_blacklist[n].quirk; |
573 | break; | |
574 | } | |
8a60a071 | 575 | |
1da177e4 | 576 | /* limit requests to 15 sectors */ |
51e9f2ff JG |
577 | if (slow_down || |
578 | ((ap->flags & SIL_FLAG_MOD15WRITE) && | |
579 | (quirks & SIL_QUIRK_MOD15WRITE))) { | |
efdaedc4 TH |
580 | if (print_info) |
581 | ata_dev_printk(dev, KERN_INFO, "applying Seagate " | |
582 | "errata fix (mod15write workaround)\n"); | |
b00eec1d | 583 | dev->max_sectors = 15; |
1da177e4 LT |
584 | return; |
585 | } | |
586 | ||
587 | /* limit to udma5 */ | |
588 | if (quirks & SIL_QUIRK_UDMA5MAX) { | |
efdaedc4 TH |
589 | if (print_info) |
590 | ata_dev_printk(dev, KERN_INFO, "applying Maxtor " | |
591 | "errata fix %s\n", model_num); | |
5a529139 | 592 | dev->udma_mask &= ATA_UDMA5; |
1da177e4 LT |
593 | return; |
594 | } | |
595 | } | |
596 | ||
4447d351 | 597 | static void sil_init_controller(struct ata_host *host) |
3d8ec913 | 598 | { |
4447d351 TH |
599 | struct pci_dev *pdev = to_pci_dev(host->dev); |
600 | void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; | |
3d8ec913 TH |
601 | u8 cls; |
602 | u32 tmp; | |
603 | int i; | |
604 | ||
605 | /* Initialize FIFO PCI bus arbitration */ | |
606 | cls = sil_get_device_cache_line(pdev); | |
607 | if (cls) { | |
608 | cls >>= 3; | |
609 | cls++; /* cls = (line_size/8)+1 */ | |
4447d351 | 610 | for (i = 0; i < host->n_ports; i++) |
3d8ec913 TH |
611 | writew(cls << 8 | cls, |
612 | mmio_base + sil_port[i].fifo_cfg); | |
613 | } else | |
614 | dev_printk(KERN_WARNING, &pdev->dev, | |
615 | "cache line size not set. Driver may not function\n"); | |
616 | ||
617 | /* Apply R_ERR on DMA activate FIS errata workaround */ | |
4447d351 | 618 | if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) { |
3d8ec913 TH |
619 | int cnt; |
620 | ||
4447d351 | 621 | for (i = 0, cnt = 0; i < host->n_ports; i++) { |
3d8ec913 TH |
622 | tmp = readl(mmio_base + sil_port[i].sfis_cfg); |
623 | if ((tmp & 0x3) != 0x01) | |
624 | continue; | |
625 | if (!cnt) | |
626 | dev_printk(KERN_INFO, &pdev->dev, | |
627 | "Applying R_ERR on DMA activate " | |
628 | "FIS errata fix\n"); | |
629 | writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); | |
630 | cnt++; | |
631 | } | |
632 | } | |
633 | ||
4447d351 | 634 | if (host->n_ports == 4) { |
3d8ec913 TH |
635 | /* flip the magic "make 4 ports work" bit */ |
636 | tmp = readl(mmio_base + sil_port[2].bmdma); | |
637 | if ((tmp & SIL_INTR_STEERING) == 0) | |
638 | writel(tmp | SIL_INTR_STEERING, | |
639 | mmio_base + sil_port[2].bmdma); | |
640 | } | |
641 | } | |
642 | ||
1da177e4 LT |
643 | static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
644 | { | |
645 | static int printed_version; | |
4447d351 TH |
646 | int board_id = ent->driver_data; |
647 | const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL }; | |
648 | struct ata_host *host; | |
ea6ba10b | 649 | void __iomem *mmio_base; |
4447d351 | 650 | int n_ports, rc; |
1da177e4 | 651 | unsigned int i; |
1da177e4 LT |
652 | |
653 | if (!printed_version++) | |
a9524a76 | 654 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 655 | |
4447d351 TH |
656 | /* allocate host */ |
657 | n_ports = 2; | |
658 | if (board_id == sil_3114) | |
659 | n_ports = 4; | |
660 | ||
661 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
662 | if (!host) | |
663 | return -ENOMEM; | |
664 | ||
665 | /* acquire resources and fill host */ | |
24dc5f33 | 666 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
667 | if (rc) |
668 | return rc; | |
669 | ||
0d5ff566 TH |
670 | rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME); |
671 | if (rc == -EBUSY) | |
24dc5f33 | 672 | pcim_pin_device(pdev); |
0d5ff566 | 673 | if (rc) |
24dc5f33 | 674 | return rc; |
4447d351 | 675 | host->iomap = pcim_iomap_table(pdev); |
1da177e4 LT |
676 | |
677 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
678 | if (rc) | |
24dc5f33 | 679 | return rc; |
1da177e4 LT |
680 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
681 | if (rc) | |
24dc5f33 | 682 | return rc; |
1da177e4 | 683 | |
4447d351 | 684 | mmio_base = host->iomap[SIL_MMIO_BAR]; |
1da177e4 | 685 | |
4447d351 TH |
686 | for (i = 0; i < host->n_ports; i++) { |
687 | struct ata_ioports *ioaddr = &host->ports[i]->ioaddr; | |
688 | ||
689 | ioaddr->cmd_addr = mmio_base + sil_port[i].tf; | |
690 | ioaddr->altstatus_addr = | |
691 | ioaddr->ctl_addr = mmio_base + sil_port[i].ctl; | |
692 | ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma; | |
693 | ioaddr->scr_addr = mmio_base + sil_port[i].scr; | |
694 | ata_std_ports(ioaddr); | |
1da177e4 LT |
695 | } |
696 | ||
4447d351 TH |
697 | /* initialize and activate */ |
698 | sil_init_controller(host); | |
1da177e4 | 699 | |
1da177e4 | 700 | pci_set_master(pdev); |
4447d351 TH |
701 | return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED, |
702 | &sil_sht); | |
1da177e4 LT |
703 | } |
704 | ||
281d426c | 705 | #ifdef CONFIG_PM |
afb5a7cb TH |
706 | static int sil_pci_device_resume(struct pci_dev *pdev) |
707 | { | |
cca3974e | 708 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
553c4aa6 TH |
709 | int rc; |
710 | ||
711 | rc = ata_pci_device_do_resume(pdev); | |
712 | if (rc) | |
713 | return rc; | |
afb5a7cb | 714 | |
4447d351 | 715 | sil_init_controller(host); |
cca3974e | 716 | ata_host_resume(host); |
afb5a7cb TH |
717 | |
718 | return 0; | |
719 | } | |
281d426c | 720 | #endif |
afb5a7cb | 721 | |
1da177e4 LT |
722 | static int __init sil_init(void) |
723 | { | |
b7887196 | 724 | return pci_register_driver(&sil_pci_driver); |
1da177e4 LT |
725 | } |
726 | ||
727 | static void __exit sil_exit(void) | |
728 | { | |
729 | pci_unregister_driver(&sil_pci_driver); | |
730 | } | |
731 | ||
732 | ||
733 | module_init(sil_init); | |
734 | module_exit(sil_exit); |