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sata_sil24: implement PMP support
[mirror_ubuntu-hirsute-kernel.git] / drivers / ata / sata_sil24.c
CommitLineData
edb33667
TH		 1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
edb33667
TH		 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
a9524a76 27#include <linux/device.h>
edb33667 28#include <scsi/scsi_host.h>
193515d5 29#include <scsi/scsi_cmnd.h>
edb33667 30#include <linux/libata.h>
edb33667
TH		 31
32#define DRV_NAME "sata_sil24"
3454dc69 33#define DRV_VERSION "1.1"
edb33667 34
edb33667
TH		 35/*
36 * Port request block (PRB) 32 bytes
37 */
38struct sil24_prb {
b4772574
AD		 39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
edb33667
TH		 42 u8 fis[6 * 4];
43};
44
45/*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48struct sil24_sge {
b4772574
AD		 49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
edb33667
TH		 52};
53
54/*
55 * Port multiplier
56 */
57struct sil24_port_multiplier {
b4772574
AD		 58 __le32 diag;
59 __le32 sactive;
edb33667
TH		 60};
61
62enum {
0d5ff566
TH		 63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
edb33667
TH		 66 /*
67 * Global controller registers (128 bytes @ BAR0)
68 */
69 /* 32 bit regs */
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
71 HOST_CTRL = 0x40,
72 HOST_IRQ_STAT = 0x44,
73 HOST_PHY_CFG = 0x48,
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
79 /* 8 bit regs */
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
84 HOST_I2C_DATA = 0x7c,
85 HOST_I2C_XFER_CNT = 0x7e,
86 HOST_I2C_CTRL = 0x7f,
87
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
90
7dafc3fd
TH		 91 /* HOST_CTRL bits */
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
d2298dca 97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
7dafc3fd 98
edb33667
TH		 99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
135da345 104
28c8f3b4 105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
135da345 106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
edb33667 107
28c8f3b4 108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
c0c55908
TH		 109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
112
edb33667 113 /* 32 bit regs */
83bbecc9
TH		 114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
edb33667 119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
83bbecc9
TH		 120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
edb33667
TH		 122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
124 /* 16 bit regs */
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
131 /* 32 bit regs */
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
c0c55908 135 PORT_CONTEXT = 0x1e04,
edb33667
TH		 136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
142
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
d10cb35a 148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
28c8f3b4 149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
e382eb1d 150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
28c8f3b4 151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
e382eb1d 152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
edb33667
TH		 153
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
7dafc3fd
TH		 162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
3b9f1d0f 167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
edb33667 168
88ce7550 169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
0542925b 170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
854c73a2 171 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
88ce7550 172
edb33667
TH		 173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
177
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
181
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
64008802 202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
edb33667 203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
83bbecc9 204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
edb33667 205
d10cb35a
TH		 206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
212
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
220
edb33667
TH		 221 /*
222 * Other constants
223 */
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
d10cb35a
TH		 225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
edb33667 229
aee10a03
TH		 230 SIL24_MAX_CMDS = 31,
231
edb33667
TH		 232 /* board id */
233 BID_SIL3124 = 0,
234 BID_SIL3132 = 1,
042c21fd 235 BID_SIL3131 = 2,
edb33667 236
9466d85b
TH		 237 /* host flags */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
aee10a03 239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
854c73a2 240 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
3454dc69 241 ATA_FLAG_AN | ATA_FLAG_PMP,
0c88758b 242 SIL24_COMMON_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY,
37024e8e 243 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
9466d85b 244
edb33667
TH		 245 IRQ_STAT_4PORTS = 0xf,
246};
247
69ad185f 248struct sil24_ata_block {
edb33667
TH		 249 struct sil24_prb prb;
250 struct sil24_sge sge[LIBATA_MAX_PRD];
251};
252
69ad185f
TH		 253struct sil24_atapi_block {
254 struct sil24_prb prb;
255 u8 cdb[16];
256 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
257};
258
259union sil24_cmd_block {
260 struct sil24_ata_block ata;
261 struct sil24_atapi_block atapi;
262};
263
88ce7550
TH		 264static struct sil24_cerr_info {
265 unsigned int err_mask, action;
266 const char *desc;
267} sil24_cerr_db[] = {
268 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
269 "device error" },
270 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
271 "device error via D2H FIS" },
272 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
273 "device error via SDB FIS" },
274 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
275 "error in data FIS" },
276 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
277 "failed to transmit command FIS" },
278 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
279 "protocol mismatch" },
280 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
281 "data directon mismatch" },
282 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
283 "ran out of SGEs while writing" },
284 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
285 "ran out of SGEs while reading" },
286 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
287 "invalid data directon for ATAPI CDB" },
288 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
289 "SGT no on qword boundary" },
290 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI target abort while fetching SGT" },
292 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
293 "PCI master abort while fetching SGT" },
294 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
295 "PCI parity error while fetching SGT" },
296 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
297 "PRB not on qword boundary" },
298 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
299 "PCI target abort while fetching PRB" },
300 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
301 "PCI master abort while fetching PRB" },
302 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
303 "PCI parity error while fetching PRB" },
304 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
305 "undefined error while transferring data" },
306 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
307 "PCI target abort while transferring data" },
308 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
309 "PCI master abort while transferring data" },
310 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
311 "PCI parity error while transferring data" },
312 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
313 "FIS received while sending service FIS" },
314};
315
edb33667
TH		 316/*
317 * ap->private_data
318 *
319 * The preview driver always returned 0 for status. We emulate it
320 * here from the previous interrupt.
321 */
322struct sil24_port_priv {
69ad185f 323 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
edb33667 324 dma_addr_t cmd_block_dma; /* DMA base addr for them */
6a575fa9 325 struct ata_taskfile tf; /* Cached taskfile registers */
edb33667
TH		 326};
327
cd0d3bbc 328static void sil24_dev_config(struct ata_device *dev);
edb33667 329static u8 sil24_check_status(struct ata_port *ap);
da3dbb17
TH		 330static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
331static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
7f726d12 332static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
3454dc69 333static int sil24_qc_defer(struct ata_queued_cmd *qc);
edb33667 334static void sil24_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0 335static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
edb33667 336static void sil24_irq_clear(struct ata_port *ap);
3454dc69
TH		 337static void sil24_pmp_attach(struct ata_port *ap);
338static void sil24_pmp_detach(struct ata_port *ap);
339static int sil24_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val);
340static int sil24_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val);
88ce7550
TH		 341static void sil24_freeze(struct ata_port *ap);
342static void sil24_thaw(struct ata_port *ap);
343static void sil24_error_handler(struct ata_port *ap);
344static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
edb33667 345static int sil24_port_start(struct ata_port *ap);
edb33667 346static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
281d426c 347#ifdef CONFIG_PM
d2298dca 348static int sil24_pci_device_resume(struct pci_dev *pdev);
3454dc69 349static int sil24_port_resume(struct ata_port *ap);
281d426c 350#endif
edb33667 351
3b7d697d 352static const struct pci_device_id sil24_pci_tbl[] = {
54bb3a94
JG		 353 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
354 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
355 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
722d67b6 356 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
54bb3a94
JG		 357 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
358 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
359
1fcce839 360 { } /* terminate list */
edb33667
TH		 361};
362
363static struct pci_driver sil24_pci_driver = {
364 .name = DRV_NAME,
365 .id_table = sil24_pci_tbl,
366 .probe = sil24_init_one,
24dc5f33 367 .remove = ata_pci_remove_one,
281d426c 368#ifdef CONFIG_PM
d2298dca
TH		 369 .suspend = ata_pci_device_suspend,
370 .resume = sil24_pci_device_resume,
281d426c 371#endif
edb33667
TH		 372};
373
193515d5 374static struct scsi_host_template sil24_sht = {
edb33667
TH		 375 .module = THIS_MODULE,
376 .name = DRV_NAME,
377 .ioctl = ata_scsi_ioctl,
378 .queuecommand = ata_scsi_queuecmd,
aee10a03
TH		 379 .change_queue_depth = ata_scsi_change_queue_depth,
380 .can_queue = SIL24_MAX_CMDS,
edb33667
TH		 381 .this_id = ATA_SHT_THIS_ID,
382 .sg_tablesize = LIBATA_MAX_PRD,
edb33667
TH		 383 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
384 .emulated = ATA_SHT_EMULATED,
385 .use_clustering = ATA_SHT_USE_CLUSTERING,
386 .proc_name = DRV_NAME,
387 .dma_boundary = ATA_DMA_BOUNDARY,
388 .slave_configure = ata_scsi_slave_config,
ccf68c34 389 .slave_destroy = ata_scsi_slave_destroy,
edb33667 390 .bios_param = ata_std_bios_param,
edb33667
TH		 391};
392
057ace5e 393static const struct ata_port_operations sil24_ops = {
69ad185f
TH		 394 .dev_config = sil24_dev_config,
395
edb33667
TH		 396 .check_status = sil24_check_status,
397 .check_altstatus = sil24_check_status,
edb33667
TH		 398 .dev_select = ata_noop_dev_select,
399
7f726d12
TH		 400 .tf_read = sil24_tf_read,
401
3454dc69 402 .qc_defer = sil24_qc_defer,
edb33667
TH		 403 .qc_prep = sil24_qc_prep,
404 .qc_issue = sil24_qc_issue,
405
edb33667
TH		 406 .irq_clear = sil24_irq_clear,
407
408 .scr_read = sil24_scr_read,
409 .scr_write = sil24_scr_write,
410
3454dc69
TH		 411 .pmp_attach = sil24_pmp_attach,
412 .pmp_detach = sil24_pmp_detach,
413 .pmp_read = sil24_pmp_read,
414 .pmp_write = sil24_pmp_write,
415
88ce7550
TH		 416 .freeze = sil24_freeze,
417 .thaw = sil24_thaw,
418 .error_handler = sil24_error_handler,
419 .post_internal_cmd = sil24_post_internal_cmd,
420
edb33667 421 .port_start = sil24_port_start,
3454dc69
TH		 422
423#ifdef CONFIG_PM
424 .port_resume = sil24_port_resume,
425#endif
edb33667
TH		 426};
427
042c21fd 428/*
cca3974e 429 * Use bits 30-31 of port_flags to encode available port numbers.
042c21fd
TH		 430 * Current maxium is 4.
431 */
432#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
433#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
434
4447d351 435static const struct ata_port_info sil24_port_info[] = {
edb33667
TH		 436 /* sil_3124 */
437 {
cca3974e 438 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
37024e8e 439 SIL24_FLAG_PCIX_IRQ_WOC,
0c88758b 440 .link_flags = SIL24_COMMON_LFLAGS,
edb33667
TH		 441 .pio_mask = 0x1f, /* pio0-4 */
442 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 443 .udma_mask = ATA_UDMA5, /* udma0-5 */
edb33667
TH		 444 .port_ops = &sil24_ops,
445 },
2e9edbf8 446 /* sil_3132 */
edb33667 447 {
cca3974e 448 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
0c88758b 449 .link_flags = SIL24_COMMON_LFLAGS,
042c21fd
TH		 450 .pio_mask = 0x1f, /* pio0-4 */
451 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 452 .udma_mask = ATA_UDMA5, /* udma0-5 */
042c21fd
TH		 453 .port_ops = &sil24_ops,
454 },
455 /* sil_3131/sil_3531 */
456 {
cca3974e 457 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
0c88758b 458 .link_flags = SIL24_COMMON_LFLAGS,
edb33667
TH		 459 .pio_mask = 0x1f, /* pio0-4 */
460 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 461 .udma_mask = ATA_UDMA5, /* udma0-5 */
edb33667
TH		 462 .port_ops = &sil24_ops,
463 },
464};
465
aee10a03
TH		 466static int sil24_tag(int tag)
467{
468 if (unlikely(ata_tag_internal(tag)))
469 return 0;
470 return tag;
471}
472
cd0d3bbc 473static void sil24_dev_config(struct ata_device *dev)
69ad185f 474{
9af5c9c9 475 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
69ad185f 476
6e7846e9 477 if (dev->cdb_len == 16)
69ad185f
TH		 478 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
479 else
480 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
481}
482
e59f0dad 483static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
6a575fa9 484{
0d5ff566 485 void __iomem *port = ap->ioaddr.cmd_addr;
e59f0dad 486 struct sil24_prb __iomem *prb;
4b4a5eae 487 u8 fis[6 * 4];
6a575fa9 488
e59f0dad
TH		 489 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
490 memcpy_fromio(fis, prb->fis, sizeof(fis));
491 ata_tf_from_fis(fis, tf);
6a575fa9
TH		 492}
493
edb33667
TH		 494static u8 sil24_check_status(struct ata_port *ap)
495{
6a575fa9
TH		 496 struct sil24_port_priv *pp = ap->private_data;
497 return pp->tf.command;
edb33667
TH		 498}
499
edb33667
TH		 500static int sil24_scr_map[] = {
501 [SCR_CONTROL] = 0,
502 [SCR_STATUS] = 1,
503 [SCR_ERROR] = 2,
504 [SCR_ACTIVE] = 3,
505};
506
da3dbb17 507static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
edb33667 508{
0d5ff566 509 void __iomem *scr_addr = ap->ioaddr.scr_addr;
da3dbb17 510
edb33667 511 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 512 void __iomem *addr;
edb33667 513 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
da3dbb17
TH		 514 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
515 return 0;
edb33667 516 }
da3dbb17 517 return -EINVAL;
edb33667
TH		 518}
519
da3dbb17 520static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
edb33667 521{
0d5ff566 522 void __iomem *scr_addr = ap->ioaddr.scr_addr;
da3dbb17 523
edb33667 524 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 525 void __iomem *addr;
edb33667
TH		 526 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
527 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
da3dbb17 528 return 0;
edb33667 529 }
da3dbb17 530 return -EINVAL;
edb33667
TH		 531}
532
7f726d12
TH		 533static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
534{
535 struct sil24_port_priv *pp = ap->private_data;
536 *tf = pp->tf;
537}
538
3454dc69
TH		 539static void sil24_config_pmp(struct ata_port *ap, int attached)
540{
541 void __iomem *port = ap->ioaddr.cmd_addr;
542
543 if (attached)
544 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
545 else
546 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
547}
548
549static void sil24_clear_pmp(struct ata_port *ap)
550{
551 void __iomem *port = ap->ioaddr.cmd_addr;
552 int i;
553
554 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
555
556 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
557 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
558
559 writel(0, pmp_base + PORT_PMP_STATUS);
560 writel(0, pmp_base + PORT_PMP_QACTIVE);
561 }
562}
563
b5bc421c
TH		 564static int sil24_init_port(struct ata_port *ap)
565{
0d5ff566 566 void __iomem *port = ap->ioaddr.cmd_addr;
b5bc421c
TH		 567 u32 tmp;
568
3454dc69
TH		 569 /* clear PMP error status */
570 if (ap->nr_pmp_links)
571 sil24_clear_pmp(ap);
572
b5bc421c
TH		 573 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
574 ata_wait_register(port + PORT_CTRL_STAT,
575 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
576 tmp = ata_wait_register(port + PORT_CTRL_STAT,
577 PORT_CS_RDY, 0, 10, 100);
578
579 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
580 return -EIO;
581 return 0;
582}
583
37b99cba
TH		 584static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
585 const struct ata_taskfile *tf,
586 int is_cmd, u32 ctrl,
587 unsigned long timeout_msec)
edb33667 588{
0d5ff566 589 void __iomem *port = ap->ioaddr.cmd_addr;
ca45160d 590 struct sil24_port_priv *pp = ap->private_data;
69ad185f 591 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
ca45160d 592 dma_addr_t paddr = pp->cmd_block_dma;
37b99cba
TH		 593 u32 irq_enabled, irq_mask, irq_stat;
594 int rc;
595
596 prb->ctrl = cpu_to_le16(ctrl);
597 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
598
599 /* temporarily plug completion and error interrupts */
600 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
601 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
602
603 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
604 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
605
606 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
607 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
608 10, timeout_msec);
609
610 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
611 irq_stat >>= PORT_IRQ_RAW_SHIFT;
612
613 if (irq_stat & PORT_IRQ_COMPLETE)
614 rc = 0;
615 else {
616 /* force port into known state */
617 sil24_init_port(ap);
618
619 if (irq_stat & PORT_IRQ_ERROR)
620 rc = -EIO;
621 else
622 rc = -EBUSY;
623 }
624
625 /* restore IRQ enabled */
626 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
627
628 return rc;
629}
630
cc0680a5 631static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
975530e8 632 int pmp, unsigned long deadline)
37b99cba 633{
cc0680a5 634 struct ata_port *ap = link->ap;
37b99cba 635 unsigned long timeout_msec = 0;
e59f0dad 636 struct ata_taskfile tf;
643be977 637 const char *reason;
37b99cba 638 int rc;
ca45160d 639
07b73470
TH		 640 DPRINTK("ENTER\n");
641
cc0680a5 642 if (ata_link_offline(link)) {
10d996ad
TH		 643 DPRINTK("PHY reports no device\n");
644 *class = ATA_DEV_NONE;
645 goto out;
646 }
647
2555d6c2
TH		 648 /* put the port into known state */
649 if (sil24_init_port(ap)) {
650 reason ="port not ready";
651 goto err;
652 }
653
0eaa6058 654 /* do SRST */
37b99cba
TH		 655 if (time_after(deadline, jiffies))
656 timeout_msec = jiffies_to_msecs(deadline - jiffies);
ca45160d 657
cc0680a5 658 ata_tf_init(link->device, &tf); /* doesn't really matter */
975530e8
TH		 659 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
660 timeout_msec);
37b99cba
TH		 661 if (rc == -EBUSY) {
662 reason = "timeout";
663 goto err;
664 } else if (rc) {
665 reason = "SRST command error";
643be977 666 goto err;
07b73470 667 }
10d996ad 668
e59f0dad
TH		 669 sil24_read_tf(ap, 0, &tf);
670 *class = ata_dev_classify(&tf);
10d996ad 671
07b73470
TH		 672 if (*class == ATA_DEV_UNKNOWN)
673 *class = ATA_DEV_NONE;
ca45160d 674
10d996ad 675 out:
07b73470 676 DPRINTK("EXIT, class=%u\n", *class);
ca45160d 677 return 0;
643be977
TH		 678
679 err:
cc0680a5 680 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
643be977 681 return -EIO;
ca45160d
TH		 682}
683
cc0680a5 684static int sil24_softreset(struct ata_link *link, unsigned int *class,
975530e8
TH		 685 unsigned long deadline)
686{
3454dc69 687 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline);
975530e8
TH		 688}
689
cc0680a5 690static int sil24_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 691 unsigned long deadline)
489ff4c7 692{
cc0680a5 693 struct ata_port *ap = link->ap;
0d5ff566 694 void __iomem *port = ap->ioaddr.cmd_addr;
ecc2e2b9 695 const char *reason;
e8e008e7 696 int tout_msec, rc;
ecc2e2b9
TH		 697 u32 tmp;
698
699 /* sil24 does the right thing(tm) without any protection */
cc0680a5 700 sata_set_spd(link);
ecc2e2b9
TH		 701
702 tout_msec = 100;
cc0680a5 703 if (ata_link_online(link))
ecc2e2b9
TH		 704 tout_msec = 5000;
705
706 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
707 tmp = ata_wait_register(port + PORT_CTRL_STAT,
708 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
709
e8e008e7
TH		 710 /* SStatus oscillates between zero and valid status after
711 * DEV_RST, debounce it.
ecc2e2b9 712 */
cc0680a5 713 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
e8e008e7
TH		 714 if (rc) {
715 reason = "PHY debouncing failed";
716 goto err;
717 }
ecc2e2b9
TH		 718
719 if (tmp & PORT_CS_DEV_RST) {
cc0680a5 720 if (ata_link_offline(link))
ecc2e2b9
TH		 721 return 0;
722 reason = "link not ready";
723 goto err;
724 }
725
e8e008e7
TH		 726 /* Sil24 doesn't store signature FIS after hardreset, so we
727 * can't wait for BSY to clear. Some devices take a long time
728 * to get ready and those devices will choke if we don't wait
729 * for BSY clearance here. Tell libata to perform follow-up
730 * softreset.
ecc2e2b9 731 */
e8e008e7 732 return -EAGAIN;
ecc2e2b9
TH		 733
734 err:
cc0680a5 735 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
ecc2e2b9 736 return -EIO;
489ff4c7
TH		 737}
738
edb33667 739static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
69ad185f 740 struct sil24_sge *sge)
edb33667 741{
972c26bd 742 struct scatterlist *sg;
edb33667 743
972c26bd 744 ata_for_each_sg(sg, qc) {
edb33667
TH		 745 sge->addr = cpu_to_le64(sg_dma_address(sg));
746 sge->cnt = cpu_to_le32(sg_dma_len(sg));
972c26bd
JG		 747 if (ata_sg_is_last(sg, qc))
748 sge->flags = cpu_to_le32(SGE_TRM);
749 else
750 sge->flags = 0;
972c26bd 751 sge++;
edb33667
TH		 752 }
753}
754
3454dc69
TH		 755static int sil24_qc_defer(struct ata_queued_cmd *qc)
756{
757 struct ata_link *link = qc->dev->link;
758 struct ata_port *ap = link->ap;
759 u8 prot = qc->tf.protocol;
760 int is_atapi = (prot == ATA_PROT_ATAPI ||
761 prot == ATA_PROT_ATAPI_NODATA ||
762 prot == ATA_PROT_ATAPI_DMA);
763
764 /* ATAPI commands completing with CHECK_SENSE cause various
765 * weird problems if other commands are active. PMP DMA CS
766 * errata doesn't cover all and HSM violation occurs even with
767 * only one other device active. Always run an ATAPI command
768 * by itself.
769 */
770 if (unlikely(ap->excl_link)) {
771 if (link == ap->excl_link) {
772 if (ap->nr_active_links)
773 return ATA_DEFER_PORT;
774 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
775 } else
776 return ATA_DEFER_PORT;
777 } else if (unlikely(is_atapi)) {
778 ap->excl_link = link;
779 if (ap->nr_active_links)
780 return ATA_DEFER_PORT;
781 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
782 }
783
784 return ata_std_qc_defer(qc);
785}
786
edb33667
TH		 787static void sil24_qc_prep(struct ata_queued_cmd *qc)
788{
789 struct ata_port *ap = qc->ap;
790 struct sil24_port_priv *pp = ap->private_data;
aee10a03 791 union sil24_cmd_block *cb;
69ad185f
TH		 792 struct sil24_prb *prb;
793 struct sil24_sge *sge;
bad28a37 794 u16 ctrl = 0;
edb33667 795
aee10a03
TH		 796 cb = &pp->cmd_block[sil24_tag(qc->tag)];
797
edb33667
TH		 798 switch (qc->tf.protocol) {
799 case ATA_PROT_PIO:
800 case ATA_PROT_DMA:
aee10a03 801 case ATA_PROT_NCQ:
edb33667 802 case ATA_PROT_NODATA:
69ad185f
TH		 803 prb = &cb->ata.prb;
804 sge = cb->ata.sge;
edb33667 805 break;
69ad185f
TH		 806
807 case ATA_PROT_ATAPI:
808 case ATA_PROT_ATAPI_DMA:
809 case ATA_PROT_ATAPI_NODATA:
810 prb = &cb->atapi.prb;
811 sge = cb->atapi.sge;
812 memset(cb->atapi.cdb, 0, 32);
6e7846e9 813 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
69ad185f
TH		 814
815 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
816 if (qc->tf.flags & ATA_TFLAG_WRITE)
bad28a37 817 ctrl = PRB_CTRL_PACKET_WRITE;
69ad185f 818 else
bad28a37
TH		 819 ctrl = PRB_CTRL_PACKET_READ;
820 }
69ad185f
TH		 821 break;
822
edb33667 823 default:
69ad185f
TH		 824 prb = NULL; /* shut up, gcc */
825 sge = NULL;
edb33667
TH		 826 BUG();
827 }
828
bad28a37 829 prb->ctrl = cpu_to_le16(ctrl);
3454dc69 830 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
edb33667
TH		 831
832 if (qc->flags & ATA_QCFLAG_DMAMAP)
69ad185f 833 sil24_fill_sg(qc, sge);
edb33667
TH		 834}
835
9a3d9eb0 836static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
edb33667
TH		 837{
838 struct ata_port *ap = qc->ap;
839 struct sil24_port_priv *pp = ap->private_data;
0d5ff566 840 void __iomem *port = ap->ioaddr.cmd_addr;
aee10a03
TH		 841 unsigned int tag = sil24_tag(qc->tag);
842 dma_addr_t paddr;
843 void __iomem *activate;
edb33667 844
aee10a03
TH		 845 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
846 activate = port + PORT_CMD_ACTIVATE + tag * 8;
847
848 writel((u32)paddr, activate);
849 writel((u64)paddr >> 32, activate + 4);
26ec634c 850
edb33667
TH		 851 return 0;
852}
853
854static void sil24_irq_clear(struct ata_port *ap)
855{
856 /* unused */
857}
858
3454dc69
TH		 859static void sil24_pmp_attach(struct ata_port *ap)
860{
861 sil24_config_pmp(ap, 1);
862 sil24_init_port(ap);
863}
864
865static void sil24_pmp_detach(struct ata_port *ap)
866{
867 sil24_init_port(ap);
868 sil24_config_pmp(ap, 0);
869}
870
871static int sil24_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val)
872{
873 struct ata_port *ap = dev->link->ap;
874 struct ata_taskfile tf;
875 int rc;
876
877 sata_pmp_read_init_tf(&tf, dev, pmp, reg);
878 rc = sil24_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
879 SATA_PMP_SCR_TIMEOUT);
880 if (rc == 0) {
881 sil24_read_tf(ap, 0, &tf);
882 *r_val = sata_pmp_read_val(&tf);
883 }
884 return rc;
885}
886
887static int sil24_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val)
888{
889 struct ata_port *ap = dev->link->ap;
890 struct ata_taskfile tf;
891
892 sata_pmp_write_init_tf(&tf, dev, pmp, reg, val);
893 return sil24_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
894 SATA_PMP_SCR_TIMEOUT);
895}
896
897static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
898 unsigned long deadline)
899{
900 return sil24_do_softreset(link, class, link->pmp, deadline);
901}
902
903static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
904 unsigned long deadline)
905{
906 int rc;
907
908 rc = sil24_init_port(link->ap);
909 if (rc) {
910 ata_link_printk(link, KERN_ERR,
911 "hardreset failed (port not ready)\n");
912 return rc;
913 }
914
915 return sata_pmp_std_hardreset(link, class, deadline);
916}
917
88ce7550 918static void sil24_freeze(struct ata_port *ap)
7d1ce682 919{
0d5ff566 920 void __iomem *port = ap->ioaddr.cmd_addr;
7d1ce682 921
88ce7550
TH		 922 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
923 * PORT_IRQ_ENABLE instead.
924 */
925 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
7d1ce682
TH		 926}
927
88ce7550 928static void sil24_thaw(struct ata_port *ap)
edb33667 929{
0d5ff566 930 void __iomem *port = ap->ioaddr.cmd_addr;
edb33667
TH		 931 u32 tmp;
932
88ce7550
TH		 933 /* clear IRQ */
934 tmp = readl(port + PORT_IRQ_STAT);
935 writel(tmp, port + PORT_IRQ_STAT);
edb33667 936
88ce7550
TH		 937 /* turn IRQ back on */
938 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
edb33667
TH		 939}
940
88ce7550 941static void sil24_error_intr(struct ata_port *ap)
8746618d 942{
0d5ff566 943 void __iomem *port = ap->ioaddr.cmd_addr;
e59f0dad 944 struct sil24_port_priv *pp = ap->private_data;
3454dc69
TH		 945 struct ata_queued_cmd *qc = NULL;
946 struct ata_link *link;
947 struct ata_eh_info *ehi;
948 int abort = 0, freeze = 0;
88ce7550 949 u32 irq_stat;
8746618d 950
88ce7550 951 /* on error, we need to clear IRQ explicitly */
8746618d 952 irq_stat = readl(port + PORT_IRQ_STAT);
88ce7550 953 writel(irq_stat, port + PORT_IRQ_STAT);
ad6e90f6 954
88ce7550 955 /* first, analyze and record host port events */
3454dc69
TH		 956 link = &ap->link;
957 ehi = &link->eh_info;
88ce7550 958 ata_ehi_clear_desc(ehi);
ad6e90f6 959
88ce7550 960 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
8746618d 961
854c73a2 962 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
854c73a2 963 ata_ehi_push_desc(ehi, "SDB notify");
7d77b247 964 sata_async_notification(ap);
854c73a2
TH		 965 }
966
0542925b
TH		 967 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
968 ata_ehi_hotplugged(ehi);
b64bbc39
TH		 969 ata_ehi_push_desc(ehi, "%s",
970 irq_stat & PORT_IRQ_PHYRDY_CHG ?
971 "PHY RDY changed" : "device exchanged");
88ce7550 972 freeze = 1;
6a575fa9
TH		 973 }
974
88ce7550
TH		 975 if (irq_stat & PORT_IRQ_UNK_FIS) {
976 ehi->err_mask |= AC_ERR_HSM;
977 ehi->action |= ATA_EH_SOFTRESET;
b64bbc39 978 ata_ehi_push_desc(ehi, "unknown FIS");
88ce7550
TH		 979 freeze = 1;
980 }
981
982 /* deal with command error */
983 if (irq_stat & PORT_IRQ_ERROR) {
984 struct sil24_cerr_info *ci = NULL;
985 unsigned int err_mask = 0, action = 0;
3454dc69
TH		 986 u32 context, cerr;
987 int pmp;
988
989 abort = 1;
990
991 /* DMA Context Switch Failure in Port Multiplier Mode
992 * errata. If we have active commands to 3 or more
993 * devices, any error condition on active devices can
994 * corrupt DMA context switching.
995 */
996 if (ap->nr_active_links >= 3) {
997 ehi->err_mask |= AC_ERR_OTHER;
998 ehi->action |= ATA_EH_HARDRESET;
999 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1000 freeze = 1;
1001 }
1002
1003 /* find out the offending link and qc */
1004 if (ap->nr_pmp_links) {
1005 context = readl(port + PORT_CONTEXT);
1006 pmp = (context >> 5) & 0xf;
1007
1008 if (pmp < ap->nr_pmp_links) {
1009 link = &ap->pmp_link[pmp];
1010 ehi = &link->eh_info;
1011 qc = ata_qc_from_tag(ap, link->active_tag);
1012
1013 ata_ehi_clear_desc(ehi);
1014 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1015 irq_stat);
1016 } else {
1017 err_mask |= AC_ERR_HSM;
1018 action |= ATA_EH_HARDRESET;
1019 freeze = 1;
1020 }
1021 } else
1022 qc = ata_qc_from_tag(ap, link->active_tag);
88ce7550
TH		 1023
1024 /* analyze CMD_ERR */
1025 cerr = readl(port + PORT_CMD_ERR);
1026 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1027 ci = &sil24_cerr_db[cerr];
1028
1029 if (ci && ci->desc) {
1030 err_mask |= ci->err_mask;
1031 action |= ci->action;
b64bbc39 1032 ata_ehi_push_desc(ehi, "%s", ci->desc);
88ce7550
TH		 1033 } else {
1034 err_mask |= AC_ERR_OTHER;
1035 action |= ATA_EH_SOFTRESET;
b64bbc39 1036 ata_ehi_push_desc(ehi, "unknown command error %d",
88ce7550
TH		 1037 cerr);
1038 }
1039
1040 /* record error info */
88ce7550 1041 if (qc) {
e59f0dad 1042 sil24_read_tf(ap, qc->tag, &pp->tf);
88ce7550
TH		 1043 qc->err_mask |= err_mask;
1044 } else
1045 ehi->err_mask |= err_mask;
1046
1047 ehi->action |= action;
3454dc69
TH		 1048
1049 /* if PMP, resume */
1050 if (ap->nr_pmp_links)
1051 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
a22e2eb0 1052 }
88ce7550
TH		 1053
1054 /* freeze or abort */
1055 if (freeze)
1056 ata_port_freeze(ap);
3454dc69
TH		 1057 else if (abort) {
1058 if (qc)
1059 ata_link_abort(qc->dev->link);
1060 else
1061 ata_port_abort(ap);
1062 }
8746618d
TH		 1063}
1064
aee10a03
TH		 1065static void sil24_finish_qc(struct ata_queued_cmd *qc)
1066{
e59f0dad
TH		 1067 struct ata_port *ap = qc->ap;
1068 struct sil24_port_priv *pp = ap->private_data;
1069
aee10a03 1070 if (qc->flags & ATA_QCFLAG_RESULT_TF)
e59f0dad 1071 sil24_read_tf(ap, qc->tag, &pp->tf);
aee10a03
TH		 1072}
1073
edb33667
TH		 1074static inline void sil24_host_intr(struct ata_port *ap)
1075{
0d5ff566 1076 void __iomem *port = ap->ioaddr.cmd_addr;
aee10a03
TH		 1077 u32 slot_stat, qc_active;
1078 int rc;
edb33667 1079
228f47b9
TH		 1080 /* If PCIX_IRQ_WOC, there's an inherent race window between
1081 * clearing IRQ pending status and reading PORT_SLOT_STAT
1082 * which may cause spurious interrupts afterwards. This is
1083 * unavoidable and much better than losing interrupts which
1084 * happens if IRQ pending is cleared after reading
1085 * PORT_SLOT_STAT.
1086 */
1087 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1088 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1089
edb33667 1090 slot_stat = readl(port + PORT_SLOT_STAT);
37024e8e 1091
88ce7550
TH		 1092 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1093 sil24_error_intr(ap);
1094 return;
1095 }
1096
aee10a03
TH		 1097 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1098 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
1099 if (rc > 0)
1100 return;
1101 if (rc < 0) {
9af5c9c9 1102 struct ata_eh_info *ehi = &ap->link.eh_info;
aee10a03
TH		 1103 ehi->err_mask |= AC_ERR_HSM;
1104 ehi->action |= ATA_EH_SOFTRESET;
1105 ata_port_freeze(ap);
88ce7550
TH		 1106 return;
1107 }
1108
228f47b9
TH		 1109 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1110 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
88ce7550 1111 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
aee10a03 1112 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
9af5c9c9 1113 slot_stat, ap->link.active_tag, ap->link.sactive);
edb33667
TH		 1114}
1115
7d12e780 1116static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
edb33667 1117{
cca3974e 1118 struct ata_host *host = dev_instance;
0d5ff566 1119 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
edb33667
TH		 1120 unsigned handled = 0;
1121 u32 status;
1122 int i;
1123
0d5ff566 1124 status = readl(host_base + HOST_IRQ_STAT);
edb33667 1125
06460aea
TH		 1126 if (status == 0xffffffff) {
1127 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1128 "PCI fault or device removal?\n");
1129 goto out;
1130 }
1131
edb33667
TH		 1132 if (!(status & IRQ_STAT_4PORTS))
1133 goto out;
1134
cca3974e 1135 spin_lock(&host->lock);
edb33667 1136
cca3974e 1137 for (i = 0; i < host->n_ports; i++)
edb33667 1138 if (status & (1 << i)) {
cca3974e 1139 struct ata_port *ap = host->ports[i];
198e0fed 1140 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
825cd6dd 1141 sil24_host_intr(ap);
3cc4571c
TH		 1142 handled++;
1143 } else
1144 printk(KERN_ERR DRV_NAME
1145 ": interrupt from disabled port %d\n", i);
edb33667
TH		 1146 }
1147
cca3974e 1148 spin_unlock(&host->lock);
edb33667
TH		 1149 out:
1150 return IRQ_RETVAL(handled);
1151}
1152
88ce7550
TH		 1153static void sil24_error_handler(struct ata_port *ap)
1154{
3454dc69 1155 if (sil24_init_port(ap))
88ce7550 1156 ata_eh_freeze_port(ap);
88ce7550
TH		 1157
1158 /* perform recovery */
3454dc69
TH		 1159 sata_pmp_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
1160 ata_std_postreset, sata_pmp_std_prereset,
1161 sil24_pmp_softreset, sil24_pmp_hardreset,
1162 sata_pmp_std_postreset);
88ce7550
TH		 1163}
1164
1165static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1166{
1167 struct ata_port *ap = qc->ap;
1168
88ce7550 1169 /* make DMA engine forget about the failed command */
3454dc69
TH		 1170 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1171 ata_eh_freeze_port(ap);
88ce7550
TH		 1172}
1173
edb33667
TH		 1174static int sil24_port_start(struct ata_port *ap)
1175{
cca3974e 1176 struct device *dev = ap->host->dev;
edb33667 1177 struct sil24_port_priv *pp;
69ad185f 1178 union sil24_cmd_block *cb;
aee10a03 1179 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
edb33667 1180 dma_addr_t cb_dma;
24dc5f33 1181 int rc;
edb33667 1182
24dc5f33 1183 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
edb33667 1184 if (!pp)
24dc5f33 1185 return -ENOMEM;
edb33667 1186
6a575fa9
TH		 1187 pp->tf.command = ATA_DRDY;
1188
24dc5f33 1189 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
6037d6bb 1190 if (!cb)
24dc5f33 1191 return -ENOMEM;
edb33667
TH		 1192 memset(cb, 0, cb_size);
1193
6037d6bb
JG		 1194 rc = ata_pad_alloc(ap, dev);
1195 if (rc)
24dc5f33 1196 return rc;
6037d6bb 1197
edb33667
TH		 1198 pp->cmd_block = cb;
1199 pp->cmd_block_dma = cb_dma;
1200
1201 ap->private_data = pp;
1202
1203 return 0;
edb33667
TH		 1204}
1205
4447d351 1206static void sil24_init_controller(struct ata_host *host)
2a41a610 1207{
4447d351
TH		 1208 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1209 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
2a41a610
TH		 1210 u32 tmp;
1211 int i;
1212
1213 /* GPIO off */
1214 writel(0, host_base + HOST_FLASH_CMD);
1215
1216 /* clear global reset & mask interrupts during initialization */
1217 writel(0, host_base + HOST_CTRL);
1218
1219 /* init ports */
4447d351 1220 for (i = 0; i < host->n_ports; i++) {
2a41a610
TH		 1221 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1222
1223 /* Initial PHY setting */
1224 writel(0x20c, port + PORT_PHY_CFG);
1225
1226 /* Clear port RST */
1227 tmp = readl(port + PORT_CTRL_STAT);
1228 if (tmp & PORT_CS_PORT_RST) {
1229 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1230 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1231 PORT_CS_PORT_RST,
1232 PORT_CS_PORT_RST, 10, 100);
1233 if (tmp & PORT_CS_PORT_RST)
4447d351 1234 dev_printk(KERN_ERR, host->dev,
2a41a610
TH		 1235 "failed to clear port RST\n");
1236 }
1237
1238 /* Configure IRQ WoC */
4447d351 1239 if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC)
2a41a610
TH		 1240 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1241 else
1242 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1243
1244 /* Zero error counters. */
1245 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1246 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1247 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1248 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1249 writel(0x0000, port + PORT_CRC_ERR_CNT);
1250 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1251
1252 /* Always use 64bit activation */
1253 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1254
1255 /* Clear port multiplier enable and resume bits */
28c8f3b4
TH		 1256 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1257 port + PORT_CTRL_CLR);
2a41a610
TH		 1258 }
1259
1260 /* Turn on interrupts */
1261 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1262}
1263
edb33667
TH		 1264static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1265{
1266 static int printed_version = 0;
4447d351
TH		 1267 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1268 const struct ata_port_info *ppi[] = { &pi, NULL };
1269 void __iomem * const *iomap;
1270 struct ata_host *host;
edb33667 1271 int i, rc;
37024e8e 1272 u32 tmp;
edb33667
TH		 1273
1274 if (!printed_version++)
a9524a76 1275 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
edb33667 1276
4447d351 1277 /* acquire resources */
24dc5f33 1278 rc = pcim_enable_device(pdev);
edb33667
TH		 1279 if (rc)
1280 return rc;
1281
0d5ff566
TH		 1282 rc = pcim_iomap_regions(pdev,
1283 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1284 DRV_NAME);
edb33667 1285 if (rc)
24dc5f33 1286 return rc;
4447d351 1287 iomap = pcim_iomap_table(pdev);
edb33667 1288
4447d351
TH		 1289 /* apply workaround for completion IRQ loss on PCI-X errata */
1290 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1291 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1292 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1293 dev_printk(KERN_INFO, &pdev->dev,
1294 "Applying completion IRQ loss on PCI-X "
1295 "errata fix\n");
1296 else
1297 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1298 }
edb33667 1299
4447d351
TH		 1300 /* allocate and fill host */
1301 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1302 SIL24_FLAG2NPORTS(ppi[0]->flags));
1303 if (!host)
1304 return -ENOMEM;
1305 host->iomap = iomap;
edb33667 1306
4447d351 1307 for (i = 0; i < host->n_ports; i++) {
cbcdd875
TH		 1308 struct ata_port *ap = host->ports[i];
1309 size_t offset = ap->port_no * PORT_REGS_SIZE;
1310 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
edb33667 1311
4447d351
TH		 1312 host->ports[i]->ioaddr.cmd_addr = port;
1313 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
edb33667 1314
cbcdd875
TH		 1315 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1316 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
4447d351 1317 }
edb33667 1318
4447d351 1319 /* configure and activate the device */
26ec634c
TH		 1320 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1321 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1322 if (rc) {
1323 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1324 if (rc) {
1325 dev_printk(KERN_ERR, &pdev->dev,
1326 "64-bit DMA enable failed\n");
24dc5f33 1327 return rc;
26ec634c
TH		 1328 }
1329 }
1330 } else {
1331 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1332 if (rc) {
1333 dev_printk(KERN_ERR, &pdev->dev,
1334 "32-bit DMA enable failed\n");
24dc5f33 1335 return rc;
26ec634c
TH		 1336 }
1337 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1338 if (rc) {
1339 dev_printk(KERN_ERR, &pdev->dev,
1340 "32-bit consistent DMA enable failed\n");
24dc5f33 1341 return rc;
26ec634c 1342 }
edb33667
TH		 1343 }
1344
4447d351 1345 sil24_init_controller(host);
edb33667
TH		 1346
1347 pci_set_master(pdev);
4447d351
TH		 1348 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1349 &sil24_sht);
edb33667
TH		 1350}
1351
281d426c 1352#ifdef CONFIG_PM
d2298dca
TH		 1353static int sil24_pci_device_resume(struct pci_dev *pdev)
1354{
cca3974e 1355 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1356 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
553c4aa6 1357 int rc;
d2298dca 1358
553c4aa6
TH		 1359 rc = ata_pci_device_do_resume(pdev);
1360 if (rc)
1361 return rc;
d2298dca
TH		 1362
1363 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
0d5ff566 1364 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
d2298dca 1365
4447d351 1366 sil24_init_controller(host);
d2298dca 1367
cca3974e 1368 ata_host_resume(host);
d2298dca
TH		 1369
1370 return 0;
1371}
3454dc69
TH		 1372
1373static int sil24_port_resume(struct ata_port *ap)
1374{
1375 sil24_config_pmp(ap, ap->nr_pmp_links);
1376 return 0;
1377}
281d426c 1378#endif
d2298dca 1379
edb33667
TH		 1380static int __init sil24_init(void)
1381{
b7887196 1382 return pci_register_driver(&sil24_pci_driver);
edb33667
TH		 1383}
1384
1385static void __exit sil24_exit(void)
1386{
1387 pci_unregister_driver(&sil24_pci_driver);
1388}
1389
1390MODULE_AUTHOR("Tejun Heo");
1391MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1392MODULE_LICENSE("GPL");
1393MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1394
1395module_init(sil24_init);
1396module_exit(sil24_exit);
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