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edb33667 TH |
1 | /* |
2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers | |
3 | * | |
4 | * Copyright 2005 Tejun Heo | |
5 | * | |
6 | * Based on preview driver from Silicon Image. | |
7 | * | |
edb33667 TH |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2, or (at your option) any | |
11 | * later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/dma-mapping.h> | |
a9524a76 | 27 | #include <linux/device.h> |
edb33667 | 28 | #include <scsi/scsi_host.h> |
193515d5 | 29 | #include <scsi/scsi_cmnd.h> |
edb33667 | 30 | #include <linux/libata.h> |
edb33667 TH |
31 | |
32 | #define DRV_NAME "sata_sil24" | |
cb48cab7 | 33 | #define DRV_VERSION "0.8" |
edb33667 | 34 | |
edb33667 TH |
35 | /* |
36 | * Port request block (PRB) 32 bytes | |
37 | */ | |
38 | struct sil24_prb { | |
b4772574 AD |
39 | __le16 ctrl; |
40 | __le16 prot; | |
41 | __le32 rx_cnt; | |
edb33667 TH |
42 | u8 fis[6 * 4]; |
43 | }; | |
44 | ||
45 | /* | |
46 | * Scatter gather entry (SGE) 16 bytes | |
47 | */ | |
48 | struct sil24_sge { | |
b4772574 AD |
49 | __le64 addr; |
50 | __le32 cnt; | |
51 | __le32 flags; | |
edb33667 TH |
52 | }; |
53 | ||
54 | /* | |
55 | * Port multiplier | |
56 | */ | |
57 | struct sil24_port_multiplier { | |
b4772574 AD |
58 | __le32 diag; |
59 | __le32 sactive; | |
edb33667 TH |
60 | }; |
61 | ||
62 | enum { | |
0d5ff566 TH |
63 | SIL24_HOST_BAR = 0, |
64 | SIL24_PORT_BAR = 2, | |
65 | ||
edb33667 TH |
66 | /* |
67 | * Global controller registers (128 bytes @ BAR0) | |
68 | */ | |
69 | /* 32 bit regs */ | |
70 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ | |
71 | HOST_CTRL = 0x40, | |
72 | HOST_IRQ_STAT = 0x44, | |
73 | HOST_PHY_CFG = 0x48, | |
74 | HOST_BIST_CTRL = 0x50, | |
75 | HOST_BIST_PTRN = 0x54, | |
76 | HOST_BIST_STAT = 0x58, | |
77 | HOST_MEM_BIST_STAT = 0x5c, | |
78 | HOST_FLASH_CMD = 0x70, | |
79 | /* 8 bit regs */ | |
80 | HOST_FLASH_DATA = 0x74, | |
81 | HOST_TRANSITION_DETECT = 0x75, | |
82 | HOST_GPIO_CTRL = 0x76, | |
83 | HOST_I2C_ADDR = 0x78, /* 32 bit */ | |
84 | HOST_I2C_DATA = 0x7c, | |
85 | HOST_I2C_XFER_CNT = 0x7e, | |
86 | HOST_I2C_CTRL = 0x7f, | |
87 | ||
88 | /* HOST_SLOT_STAT bits */ | |
89 | HOST_SSTAT_ATTN = (1 << 31), | |
90 | ||
7dafc3fd TH |
91 | /* HOST_CTRL bits */ |
92 | HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ | |
93 | HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ | |
94 | HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ | |
95 | HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ | |
96 | HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ | |
d2298dca | 97 | HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ |
7dafc3fd | 98 | |
edb33667 TH |
99 | /* |
100 | * Port registers | |
101 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) | |
102 | */ | |
103 | PORT_REGS_SIZE = 0x2000, | |
135da345 | 104 | |
28c8f3b4 | 105 | PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ |
135da345 | 106 | PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ |
edb33667 | 107 | |
28c8f3b4 | 108 | PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ |
c0c55908 TH |
109 | PORT_PMP_STATUS = 0x0000, /* port device status offset */ |
110 | PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ | |
111 | PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ | |
112 | ||
edb33667 | 113 | /* 32 bit regs */ |
83bbecc9 TH |
114 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
115 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ | |
116 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ | |
117 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ | |
118 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ | |
edb33667 | 119 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
83bbecc9 TH |
120 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
121 | PORT_CMD_ERR = 0x1024, /* command error number */ | |
edb33667 TH |
122 | PORT_FIS_CFG = 0x1028, |
123 | PORT_FIFO_THRES = 0x102c, | |
124 | /* 16 bit regs */ | |
125 | PORT_DECODE_ERR_CNT = 0x1040, | |
126 | PORT_DECODE_ERR_THRESH = 0x1042, | |
127 | PORT_CRC_ERR_CNT = 0x1044, | |
128 | PORT_CRC_ERR_THRESH = 0x1046, | |
129 | PORT_HSHK_ERR_CNT = 0x1048, | |
130 | PORT_HSHK_ERR_THRESH = 0x104a, | |
131 | /* 32 bit regs */ | |
132 | PORT_PHY_CFG = 0x1050, | |
133 | PORT_SLOT_STAT = 0x1800, | |
134 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ | |
c0c55908 | 135 | PORT_CONTEXT = 0x1e04, |
edb33667 TH |
136 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ |
137 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ | |
138 | PORT_SCONTROL = 0x1f00, | |
139 | PORT_SSTATUS = 0x1f04, | |
140 | PORT_SERROR = 0x1f08, | |
141 | PORT_SACTIVE = 0x1f0c, | |
142 | ||
143 | /* PORT_CTRL_STAT bits */ | |
144 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ | |
145 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ | |
146 | PORT_CS_INIT = (1 << 2), /* port initialize */ | |
147 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ | |
d10cb35a | 148 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
28c8f3b4 | 149 | PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ |
e382eb1d | 150 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ |
28c8f3b4 | 151 | PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ |
e382eb1d | 152 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ |
edb33667 TH |
153 | |
154 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ | |
155 | /* bits[11:0] are masked */ | |
156 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ | |
157 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ | |
158 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ | |
159 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ | |
160 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ | |
161 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ | |
7dafc3fd TH |
162 | PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ |
163 | PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ | |
164 | PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ | |
165 | PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ | |
166 | PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ | |
3b9f1d0f | 167 | PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ |
edb33667 | 168 | |
88ce7550 | 169 | DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | |
0542925b TH |
170 | PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | |
171 | PORT_IRQ_UNK_FIS, | |
88ce7550 | 172 | |
edb33667 TH |
173 | /* bits[27:16] are unmasked (raw) */ |
174 | PORT_IRQ_RAW_SHIFT = 16, | |
175 | PORT_IRQ_MASKED_MASK = 0x7ff, | |
176 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), | |
177 | ||
178 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ | |
179 | PORT_IRQ_STEER_SHIFT = 30, | |
180 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), | |
181 | ||
182 | /* PORT_CMD_ERR constants */ | |
183 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ | |
184 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ | |
185 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ | |
186 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ | |
187 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ | |
188 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ | |
189 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ | |
190 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ | |
191 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ | |
192 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ | |
193 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ | |
194 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ | |
195 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ | |
196 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ | |
197 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ | |
198 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ | |
199 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ | |
200 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ | |
201 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | |
64008802 | 202 | PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ |
edb33667 | 203 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ |
83bbecc9 | 204 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
edb33667 | 205 | |
d10cb35a TH |
206 | /* bits of PRB control field */ |
207 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ | |
208 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ | |
209 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ | |
210 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ | |
211 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ | |
212 | ||
213 | /* PRB protocol field */ | |
214 | PRB_PROT_PACKET = (1 << 0), | |
215 | PRB_PROT_TCQ = (1 << 1), | |
216 | PRB_PROT_NCQ = (1 << 2), | |
217 | PRB_PROT_READ = (1 << 3), | |
218 | PRB_PROT_WRITE = (1 << 4), | |
219 | PRB_PROT_TRANSPARENT = (1 << 5), | |
220 | ||
edb33667 TH |
221 | /* |
222 | * Other constants | |
223 | */ | |
224 | SGE_TRM = (1 << 31), /* Last SGE in chain */ | |
d10cb35a TH |
225 | SGE_LNK = (1 << 30), /* linked list |
226 | Points to SGT, not SGE */ | |
227 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) | |
228 | data address ignored */ | |
edb33667 | 229 | |
aee10a03 TH |
230 | SIL24_MAX_CMDS = 31, |
231 | ||
edb33667 TH |
232 | /* board id */ |
233 | BID_SIL3124 = 0, | |
234 | BID_SIL3132 = 1, | |
042c21fd | 235 | BID_SIL3131 = 2, |
edb33667 | 236 | |
9466d85b TH |
237 | /* host flags */ |
238 | SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
aee10a03 | 239 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
0542925b | 240 | ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY, |
37024e8e | 241 | SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ |
9466d85b | 242 | |
edb33667 TH |
243 | IRQ_STAT_4PORTS = 0xf, |
244 | }; | |
245 | ||
69ad185f | 246 | struct sil24_ata_block { |
edb33667 TH |
247 | struct sil24_prb prb; |
248 | struct sil24_sge sge[LIBATA_MAX_PRD]; | |
249 | }; | |
250 | ||
69ad185f TH |
251 | struct sil24_atapi_block { |
252 | struct sil24_prb prb; | |
253 | u8 cdb[16]; | |
254 | struct sil24_sge sge[LIBATA_MAX_PRD - 1]; | |
255 | }; | |
256 | ||
257 | union sil24_cmd_block { | |
258 | struct sil24_ata_block ata; | |
259 | struct sil24_atapi_block atapi; | |
260 | }; | |
261 | ||
88ce7550 TH |
262 | static struct sil24_cerr_info { |
263 | unsigned int err_mask, action; | |
264 | const char *desc; | |
265 | } sil24_cerr_db[] = { | |
266 | [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE, | |
267 | "device error" }, | |
268 | [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE, | |
269 | "device error via D2H FIS" }, | |
270 | [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE, | |
271 | "device error via SDB FIS" }, | |
272 | [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, | |
273 | "error in data FIS" }, | |
274 | [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, | |
275 | "failed to transmit command FIS" }, | |
276 | [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
277 | "protocol mismatch" }, | |
278 | [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
279 | "data directon mismatch" }, | |
280 | [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
281 | "ran out of SGEs while writing" }, | |
282 | [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
283 | "ran out of SGEs while reading" }, | |
284 | [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
285 | "invalid data directon for ATAPI CDB" }, | |
286 | [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, | |
287 | "SGT no on qword boundary" }, | |
288 | [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
289 | "PCI target abort while fetching SGT" }, | |
290 | [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
291 | "PCI master abort while fetching SGT" }, | |
292 | [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
293 | "PCI parity error while fetching SGT" }, | |
294 | [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, | |
295 | "PRB not on qword boundary" }, | |
296 | [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
297 | "PCI target abort while fetching PRB" }, | |
298 | [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
299 | "PCI master abort while fetching PRB" }, | |
300 | [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
301 | "PCI parity error while fetching PRB" }, | |
302 | [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
303 | "undefined error while transferring data" }, | |
304 | [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
305 | "PCI target abort while transferring data" }, | |
306 | [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
307 | "PCI master abort while transferring data" }, | |
308 | [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, | |
309 | "PCI parity error while transferring data" }, | |
310 | [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET, | |
311 | "FIS received while sending service FIS" }, | |
312 | }; | |
313 | ||
edb33667 TH |
314 | /* |
315 | * ap->private_data | |
316 | * | |
317 | * The preview driver always returned 0 for status. We emulate it | |
318 | * here from the previous interrupt. | |
319 | */ | |
320 | struct sil24_port_priv { | |
69ad185f | 321 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
edb33667 | 322 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
6a575fa9 | 323 | struct ata_taskfile tf; /* Cached taskfile registers */ |
edb33667 TH |
324 | }; |
325 | ||
69ad185f | 326 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); |
edb33667 | 327 | static u8 sil24_check_status(struct ata_port *ap); |
edb33667 TH |
328 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); |
329 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); | |
7f726d12 | 330 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
edb33667 | 331 | static void sil24_qc_prep(struct ata_queued_cmd *qc); |
9a3d9eb0 | 332 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
edb33667 | 333 | static void sil24_irq_clear(struct ata_port *ap); |
7d12e780 | 334 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance); |
88ce7550 TH |
335 | static void sil24_freeze(struct ata_port *ap); |
336 | static void sil24_thaw(struct ata_port *ap); | |
337 | static void sil24_error_handler(struct ata_port *ap); | |
338 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); | |
edb33667 | 339 | static int sil24_port_start(struct ata_port *ap); |
edb33667 | 340 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
281d426c | 341 | #ifdef CONFIG_PM |
d2298dca | 342 | static int sil24_pci_device_resume(struct pci_dev *pdev); |
281d426c | 343 | #endif |
edb33667 | 344 | |
3b7d697d | 345 | static const struct pci_device_id sil24_pci_tbl[] = { |
54bb3a94 JG |
346 | { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, |
347 | { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, | |
348 | { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, | |
722d67b6 | 349 | { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, |
54bb3a94 JG |
350 | { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, |
351 | { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, | |
352 | ||
1fcce839 | 353 | { } /* terminate list */ |
edb33667 TH |
354 | }; |
355 | ||
356 | static struct pci_driver sil24_pci_driver = { | |
357 | .name = DRV_NAME, | |
358 | .id_table = sil24_pci_tbl, | |
359 | .probe = sil24_init_one, | |
24dc5f33 | 360 | .remove = ata_pci_remove_one, |
281d426c | 361 | #ifdef CONFIG_PM |
d2298dca TH |
362 | .suspend = ata_pci_device_suspend, |
363 | .resume = sil24_pci_device_resume, | |
281d426c | 364 | #endif |
edb33667 TH |
365 | }; |
366 | ||
193515d5 | 367 | static struct scsi_host_template sil24_sht = { |
edb33667 TH |
368 | .module = THIS_MODULE, |
369 | .name = DRV_NAME, | |
370 | .ioctl = ata_scsi_ioctl, | |
371 | .queuecommand = ata_scsi_queuecmd, | |
aee10a03 TH |
372 | .change_queue_depth = ata_scsi_change_queue_depth, |
373 | .can_queue = SIL24_MAX_CMDS, | |
edb33667 TH |
374 | .this_id = ATA_SHT_THIS_ID, |
375 | .sg_tablesize = LIBATA_MAX_PRD, | |
edb33667 TH |
376 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
377 | .emulated = ATA_SHT_EMULATED, | |
378 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
379 | .proc_name = DRV_NAME, | |
380 | .dma_boundary = ATA_DMA_BOUNDARY, | |
381 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 382 | .slave_destroy = ata_scsi_slave_destroy, |
edb33667 | 383 | .bios_param = ata_std_bios_param, |
438ac6d5 | 384 | #ifdef CONFIG_PM |
d2298dca TH |
385 | .suspend = ata_scsi_device_suspend, |
386 | .resume = ata_scsi_device_resume, | |
438ac6d5 | 387 | #endif |
edb33667 TH |
388 | }; |
389 | ||
057ace5e | 390 | static const struct ata_port_operations sil24_ops = { |
edb33667 TH |
391 | .port_disable = ata_port_disable, |
392 | ||
69ad185f TH |
393 | .dev_config = sil24_dev_config, |
394 | ||
edb33667 TH |
395 | .check_status = sil24_check_status, |
396 | .check_altstatus = sil24_check_status, | |
edb33667 TH |
397 | .dev_select = ata_noop_dev_select, |
398 | ||
7f726d12 TH |
399 | .tf_read = sil24_tf_read, |
400 | ||
edb33667 TH |
401 | .qc_prep = sil24_qc_prep, |
402 | .qc_issue = sil24_qc_issue, | |
403 | ||
edb33667 TH |
404 | .irq_handler = sil24_interrupt, |
405 | .irq_clear = sil24_irq_clear, | |
246ce3b6 AI |
406 | .irq_on = ata_dummy_irq_on, |
407 | .irq_ack = ata_dummy_irq_ack, | |
edb33667 TH |
408 | |
409 | .scr_read = sil24_scr_read, | |
410 | .scr_write = sil24_scr_write, | |
411 | ||
88ce7550 TH |
412 | .freeze = sil24_freeze, |
413 | .thaw = sil24_thaw, | |
414 | .error_handler = sil24_error_handler, | |
415 | .post_internal_cmd = sil24_post_internal_cmd, | |
416 | ||
edb33667 | 417 | .port_start = sil24_port_start, |
edb33667 TH |
418 | }; |
419 | ||
042c21fd | 420 | /* |
cca3974e | 421 | * Use bits 30-31 of port_flags to encode available port numbers. |
042c21fd TH |
422 | * Current maxium is 4. |
423 | */ | |
424 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) | |
425 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) | |
426 | ||
edb33667 TH |
427 | static struct ata_port_info sil24_port_info[] = { |
428 | /* sil_3124 */ | |
429 | { | |
430 | .sht = &sil24_sht, | |
cca3974e | 431 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | |
37024e8e | 432 | SIL24_FLAG_PCIX_IRQ_WOC, |
edb33667 TH |
433 | .pio_mask = 0x1f, /* pio0-4 */ |
434 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
435 | .udma_mask = 0x3f, /* udma0-5 */ | |
436 | .port_ops = &sil24_ops, | |
437 | }, | |
2e9edbf8 | 438 | /* sil_3132 */ |
edb33667 TH |
439 | { |
440 | .sht = &sil24_sht, | |
cca3974e | 441 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), |
042c21fd TH |
442 | .pio_mask = 0x1f, /* pio0-4 */ |
443 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
444 | .udma_mask = 0x3f, /* udma0-5 */ | |
445 | .port_ops = &sil24_ops, | |
446 | }, | |
447 | /* sil_3131/sil_3531 */ | |
448 | { | |
449 | .sht = &sil24_sht, | |
cca3974e | 450 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), |
edb33667 TH |
451 | .pio_mask = 0x1f, /* pio0-4 */ |
452 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
453 | .udma_mask = 0x3f, /* udma0-5 */ | |
454 | .port_ops = &sil24_ops, | |
455 | }, | |
456 | }; | |
457 | ||
aee10a03 TH |
458 | static int sil24_tag(int tag) |
459 | { | |
460 | if (unlikely(ata_tag_internal(tag))) | |
461 | return 0; | |
462 | return tag; | |
463 | } | |
464 | ||
69ad185f TH |
465 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) |
466 | { | |
0d5ff566 | 467 | void __iomem *port = ap->ioaddr.cmd_addr; |
69ad185f | 468 | |
6e7846e9 | 469 | if (dev->cdb_len == 16) |
69ad185f TH |
470 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
471 | else | |
472 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); | |
473 | } | |
474 | ||
6a575fa9 TH |
475 | static inline void sil24_update_tf(struct ata_port *ap) |
476 | { | |
477 | struct sil24_port_priv *pp = ap->private_data; | |
0d5ff566 | 478 | void __iomem *port = ap->ioaddr.cmd_addr; |
4b4a5eae AV |
479 | struct sil24_prb __iomem *prb = port; |
480 | u8 fis[6 * 4]; | |
6a575fa9 | 481 | |
4b4a5eae AV |
482 | memcpy_fromio(fis, prb->fis, 6 * 4); |
483 | ata_tf_from_fis(fis, &pp->tf); | |
6a575fa9 TH |
484 | } |
485 | ||
edb33667 TH |
486 | static u8 sil24_check_status(struct ata_port *ap) |
487 | { | |
6a575fa9 TH |
488 | struct sil24_port_priv *pp = ap->private_data; |
489 | return pp->tf.command; | |
edb33667 TH |
490 | } |
491 | ||
edb33667 TH |
492 | static int sil24_scr_map[] = { |
493 | [SCR_CONTROL] = 0, | |
494 | [SCR_STATUS] = 1, | |
495 | [SCR_ERROR] = 2, | |
496 | [SCR_ACTIVE] = 3, | |
497 | }; | |
498 | ||
499 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) | |
500 | { | |
0d5ff566 | 501 | void __iomem *scr_addr = ap->ioaddr.scr_addr; |
edb33667 | 502 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 503 | void __iomem *addr; |
edb33667 TH |
504 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
505 | return readl(scr_addr + sil24_scr_map[sc_reg] * 4); | |
506 | } | |
507 | return 0xffffffffU; | |
508 | } | |
509 | ||
510 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) | |
511 | { | |
0d5ff566 | 512 | void __iomem *scr_addr = ap->ioaddr.scr_addr; |
edb33667 | 513 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 514 | void __iomem *addr; |
edb33667 TH |
515 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
516 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); | |
517 | } | |
518 | } | |
519 | ||
7f726d12 TH |
520 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
521 | { | |
522 | struct sil24_port_priv *pp = ap->private_data; | |
523 | *tf = pp->tf; | |
524 | } | |
525 | ||
b5bc421c TH |
526 | static int sil24_init_port(struct ata_port *ap) |
527 | { | |
0d5ff566 | 528 | void __iomem *port = ap->ioaddr.cmd_addr; |
b5bc421c TH |
529 | u32 tmp; |
530 | ||
531 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); | |
532 | ata_wait_register(port + PORT_CTRL_STAT, | |
533 | PORT_CS_INIT, PORT_CS_INIT, 10, 100); | |
534 | tmp = ata_wait_register(port + PORT_CTRL_STAT, | |
535 | PORT_CS_RDY, 0, 10, 100); | |
536 | ||
537 | if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) | |
538 | return -EIO; | |
539 | return 0; | |
540 | } | |
541 | ||
2bf2cb26 | 542 | static int sil24_softreset(struct ata_port *ap, unsigned int *class) |
edb33667 | 543 | { |
0d5ff566 | 544 | void __iomem *port = ap->ioaddr.cmd_addr; |
ca45160d | 545 | struct sil24_port_priv *pp = ap->private_data; |
69ad185f | 546 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
ca45160d | 547 | dma_addr_t paddr = pp->cmd_block_dma; |
88ce7550 | 548 | u32 mask, irq_stat; |
643be977 | 549 | const char *reason; |
ca45160d | 550 | |
07b73470 TH |
551 | DPRINTK("ENTER\n"); |
552 | ||
81952c54 | 553 | if (ata_port_offline(ap)) { |
10d996ad TH |
554 | DPRINTK("PHY reports no device\n"); |
555 | *class = ATA_DEV_NONE; | |
556 | goto out; | |
557 | } | |
558 | ||
2555d6c2 TH |
559 | /* put the port into known state */ |
560 | if (sil24_init_port(ap)) { | |
561 | reason ="port not ready"; | |
562 | goto err; | |
563 | } | |
564 | ||
0eaa6058 | 565 | /* do SRST */ |
bad28a37 | 566 | prb->ctrl = cpu_to_le16(PRB_CTRL_SRST); |
28c8f3b4 | 567 | prb->fis[1] = 0; /* no PMP yet */ |
ca45160d TH |
568 | |
569 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); | |
26ec634c | 570 | writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); |
ca45160d | 571 | |
7dd29dd6 TH |
572 | mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; |
573 | irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0, | |
574 | 100, ATA_TMOUT_BOOT / HZ * 1000); | |
ca45160d | 575 | |
7dd29dd6 TH |
576 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */ |
577 | irq_stat >>= PORT_IRQ_RAW_SHIFT; | |
ca45160d | 578 | |
10d996ad | 579 | if (!(irq_stat & PORT_IRQ_COMPLETE)) { |
643be977 TH |
580 | if (irq_stat & PORT_IRQ_ERROR) |
581 | reason = "SRST command error"; | |
582 | else | |
583 | reason = "timeout"; | |
584 | goto err; | |
07b73470 | 585 | } |
10d996ad TH |
586 | |
587 | sil24_update_tf(ap); | |
588 | *class = ata_dev_classify(&pp->tf); | |
589 | ||
07b73470 TH |
590 | if (*class == ATA_DEV_UNKNOWN) |
591 | *class = ATA_DEV_NONE; | |
ca45160d | 592 | |
10d996ad | 593 | out: |
07b73470 | 594 | DPRINTK("EXIT, class=%u\n", *class); |
ca45160d | 595 | return 0; |
643be977 TH |
596 | |
597 | err: | |
f15a1daf | 598 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
643be977 | 599 | return -EIO; |
ca45160d TH |
600 | } |
601 | ||
2bf2cb26 | 602 | static int sil24_hardreset(struct ata_port *ap, unsigned int *class) |
489ff4c7 | 603 | { |
0d5ff566 | 604 | void __iomem *port = ap->ioaddr.cmd_addr; |
ecc2e2b9 | 605 | const char *reason; |
e8e008e7 | 606 | int tout_msec, rc; |
ecc2e2b9 TH |
607 | u32 tmp; |
608 | ||
609 | /* sil24 does the right thing(tm) without any protection */ | |
3c567b7d | 610 | sata_set_spd(ap); |
ecc2e2b9 TH |
611 | |
612 | tout_msec = 100; | |
81952c54 | 613 | if (ata_port_online(ap)) |
ecc2e2b9 TH |
614 | tout_msec = 5000; |
615 | ||
616 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); | |
617 | tmp = ata_wait_register(port + PORT_CTRL_STAT, | |
618 | PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec); | |
619 | ||
e8e008e7 TH |
620 | /* SStatus oscillates between zero and valid status after |
621 | * DEV_RST, debounce it. | |
ecc2e2b9 | 622 | */ |
e9c83914 | 623 | rc = sata_phy_debounce(ap, sata_deb_timing_long); |
e8e008e7 TH |
624 | if (rc) { |
625 | reason = "PHY debouncing failed"; | |
626 | goto err; | |
627 | } | |
ecc2e2b9 TH |
628 | |
629 | if (tmp & PORT_CS_DEV_RST) { | |
81952c54 | 630 | if (ata_port_offline(ap)) |
ecc2e2b9 TH |
631 | return 0; |
632 | reason = "link not ready"; | |
633 | goto err; | |
634 | } | |
635 | ||
e8e008e7 TH |
636 | /* Sil24 doesn't store signature FIS after hardreset, so we |
637 | * can't wait for BSY to clear. Some devices take a long time | |
638 | * to get ready and those devices will choke if we don't wait | |
639 | * for BSY clearance here. Tell libata to perform follow-up | |
640 | * softreset. | |
ecc2e2b9 | 641 | */ |
e8e008e7 | 642 | return -EAGAIN; |
ecc2e2b9 TH |
643 | |
644 | err: | |
f15a1daf | 645 | ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason); |
ecc2e2b9 | 646 | return -EIO; |
489ff4c7 TH |
647 | } |
648 | ||
edb33667 | 649 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, |
69ad185f | 650 | struct sil24_sge *sge) |
edb33667 | 651 | { |
972c26bd | 652 | struct scatterlist *sg; |
edb33667 | 653 | |
972c26bd | 654 | ata_for_each_sg(sg, qc) { |
edb33667 TH |
655 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
656 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); | |
972c26bd JG |
657 | if (ata_sg_is_last(sg, qc)) |
658 | sge->flags = cpu_to_le32(SGE_TRM); | |
659 | else | |
660 | sge->flags = 0; | |
972c26bd | 661 | sge++; |
edb33667 TH |
662 | } |
663 | } | |
664 | ||
665 | static void sil24_qc_prep(struct ata_queued_cmd *qc) | |
666 | { | |
667 | struct ata_port *ap = qc->ap; | |
668 | struct sil24_port_priv *pp = ap->private_data; | |
aee10a03 | 669 | union sil24_cmd_block *cb; |
69ad185f TH |
670 | struct sil24_prb *prb; |
671 | struct sil24_sge *sge; | |
bad28a37 | 672 | u16 ctrl = 0; |
edb33667 | 673 | |
aee10a03 TH |
674 | cb = &pp->cmd_block[sil24_tag(qc->tag)]; |
675 | ||
edb33667 TH |
676 | switch (qc->tf.protocol) { |
677 | case ATA_PROT_PIO: | |
678 | case ATA_PROT_DMA: | |
aee10a03 | 679 | case ATA_PROT_NCQ: |
edb33667 | 680 | case ATA_PROT_NODATA: |
69ad185f TH |
681 | prb = &cb->ata.prb; |
682 | sge = cb->ata.sge; | |
edb33667 | 683 | break; |
69ad185f TH |
684 | |
685 | case ATA_PROT_ATAPI: | |
686 | case ATA_PROT_ATAPI_DMA: | |
687 | case ATA_PROT_ATAPI_NODATA: | |
688 | prb = &cb->atapi.prb; | |
689 | sge = cb->atapi.sge; | |
690 | memset(cb->atapi.cdb, 0, 32); | |
6e7846e9 | 691 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
69ad185f TH |
692 | |
693 | if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { | |
694 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
bad28a37 | 695 | ctrl = PRB_CTRL_PACKET_WRITE; |
69ad185f | 696 | else |
bad28a37 TH |
697 | ctrl = PRB_CTRL_PACKET_READ; |
698 | } | |
69ad185f TH |
699 | break; |
700 | ||
edb33667 | 701 | default: |
69ad185f TH |
702 | prb = NULL; /* shut up, gcc */ |
703 | sge = NULL; | |
edb33667 TH |
704 | BUG(); |
705 | } | |
706 | ||
bad28a37 | 707 | prb->ctrl = cpu_to_le16(ctrl); |
edb33667 TH |
708 | ata_tf_to_fis(&qc->tf, prb->fis, 0); |
709 | ||
710 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
69ad185f | 711 | sil24_fill_sg(qc, sge); |
edb33667 TH |
712 | } |
713 | ||
9a3d9eb0 | 714 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
edb33667 TH |
715 | { |
716 | struct ata_port *ap = qc->ap; | |
717 | struct sil24_port_priv *pp = ap->private_data; | |
0d5ff566 | 718 | void __iomem *port = ap->ioaddr.cmd_addr; |
aee10a03 TH |
719 | unsigned int tag = sil24_tag(qc->tag); |
720 | dma_addr_t paddr; | |
721 | void __iomem *activate; | |
edb33667 | 722 | |
aee10a03 TH |
723 | paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); |
724 | activate = port + PORT_CMD_ACTIVATE + tag * 8; | |
725 | ||
726 | writel((u32)paddr, activate); | |
727 | writel((u64)paddr >> 32, activate + 4); | |
26ec634c | 728 | |
edb33667 TH |
729 | return 0; |
730 | } | |
731 | ||
732 | static void sil24_irq_clear(struct ata_port *ap) | |
733 | { | |
734 | /* unused */ | |
735 | } | |
736 | ||
88ce7550 | 737 | static void sil24_freeze(struct ata_port *ap) |
7d1ce682 | 738 | { |
0d5ff566 | 739 | void __iomem *port = ap->ioaddr.cmd_addr; |
7d1ce682 | 740 | |
88ce7550 TH |
741 | /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear |
742 | * PORT_IRQ_ENABLE instead. | |
743 | */ | |
744 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); | |
7d1ce682 TH |
745 | } |
746 | ||
88ce7550 | 747 | static void sil24_thaw(struct ata_port *ap) |
edb33667 | 748 | { |
0d5ff566 | 749 | void __iomem *port = ap->ioaddr.cmd_addr; |
edb33667 TH |
750 | u32 tmp; |
751 | ||
88ce7550 TH |
752 | /* clear IRQ */ |
753 | tmp = readl(port + PORT_IRQ_STAT); | |
754 | writel(tmp, port + PORT_IRQ_STAT); | |
edb33667 | 755 | |
88ce7550 TH |
756 | /* turn IRQ back on */ |
757 | writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); | |
edb33667 TH |
758 | } |
759 | ||
88ce7550 | 760 | static void sil24_error_intr(struct ata_port *ap) |
8746618d | 761 | { |
0d5ff566 | 762 | void __iomem *port = ap->ioaddr.cmd_addr; |
88ce7550 TH |
763 | struct ata_eh_info *ehi = &ap->eh_info; |
764 | int freeze = 0; | |
765 | u32 irq_stat; | |
8746618d | 766 | |
88ce7550 | 767 | /* on error, we need to clear IRQ explicitly */ |
8746618d | 768 | irq_stat = readl(port + PORT_IRQ_STAT); |
88ce7550 | 769 | writel(irq_stat, port + PORT_IRQ_STAT); |
ad6e90f6 | 770 | |
88ce7550 TH |
771 | /* first, analyze and record host port events */ |
772 | ata_ehi_clear_desc(ehi); | |
ad6e90f6 | 773 | |
88ce7550 | 774 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); |
8746618d | 775 | |
0542925b TH |
776 | if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { |
777 | ata_ehi_hotplugged(ehi); | |
778 | ata_ehi_push_desc(ehi, ", %s", | |
779 | irq_stat & PORT_IRQ_PHYRDY_CHG ? | |
780 | "PHY RDY changed" : "device exchanged"); | |
88ce7550 | 781 | freeze = 1; |
6a575fa9 TH |
782 | } |
783 | ||
88ce7550 TH |
784 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
785 | ehi->err_mask |= AC_ERR_HSM; | |
786 | ehi->action |= ATA_EH_SOFTRESET; | |
787 | ata_ehi_push_desc(ehi , ", unknown FIS"); | |
788 | freeze = 1; | |
789 | } | |
790 | ||
791 | /* deal with command error */ | |
792 | if (irq_stat & PORT_IRQ_ERROR) { | |
793 | struct sil24_cerr_info *ci = NULL; | |
794 | unsigned int err_mask = 0, action = 0; | |
795 | struct ata_queued_cmd *qc; | |
796 | u32 cerr; | |
797 | ||
798 | /* analyze CMD_ERR */ | |
799 | cerr = readl(port + PORT_CMD_ERR); | |
800 | if (cerr < ARRAY_SIZE(sil24_cerr_db)) | |
801 | ci = &sil24_cerr_db[cerr]; | |
802 | ||
803 | if (ci && ci->desc) { | |
804 | err_mask |= ci->err_mask; | |
805 | action |= ci->action; | |
806 | ata_ehi_push_desc(ehi, ", %s", ci->desc); | |
807 | } else { | |
808 | err_mask |= AC_ERR_OTHER; | |
809 | action |= ATA_EH_SOFTRESET; | |
810 | ata_ehi_push_desc(ehi, ", unknown command error %d", | |
811 | cerr); | |
812 | } | |
813 | ||
814 | /* record error info */ | |
815 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
816 | if (qc) { | |
88ce7550 TH |
817 | sil24_update_tf(ap); |
818 | qc->err_mask |= err_mask; | |
819 | } else | |
820 | ehi->err_mask |= err_mask; | |
821 | ||
822 | ehi->action |= action; | |
a22e2eb0 | 823 | } |
88ce7550 TH |
824 | |
825 | /* freeze or abort */ | |
826 | if (freeze) | |
827 | ata_port_freeze(ap); | |
828 | else | |
829 | ata_port_abort(ap); | |
8746618d TH |
830 | } |
831 | ||
aee10a03 TH |
832 | static void sil24_finish_qc(struct ata_queued_cmd *qc) |
833 | { | |
834 | if (qc->flags & ATA_QCFLAG_RESULT_TF) | |
835 | sil24_update_tf(qc->ap); | |
836 | } | |
837 | ||
edb33667 TH |
838 | static inline void sil24_host_intr(struct ata_port *ap) |
839 | { | |
0d5ff566 | 840 | void __iomem *port = ap->ioaddr.cmd_addr; |
aee10a03 TH |
841 | u32 slot_stat, qc_active; |
842 | int rc; | |
edb33667 TH |
843 | |
844 | slot_stat = readl(port + PORT_SLOT_STAT); | |
37024e8e | 845 | |
88ce7550 TH |
846 | if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { |
847 | sil24_error_intr(ap); | |
848 | return; | |
849 | } | |
850 | ||
851 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) | |
852 | writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); | |
37024e8e | 853 | |
aee10a03 TH |
854 | qc_active = slot_stat & ~HOST_SSTAT_ATTN; |
855 | rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc); | |
856 | if (rc > 0) | |
857 | return; | |
858 | if (rc < 0) { | |
859 | struct ata_eh_info *ehi = &ap->eh_info; | |
860 | ehi->err_mask |= AC_ERR_HSM; | |
861 | ehi->action |= ATA_EH_SOFTRESET; | |
862 | ata_port_freeze(ap); | |
88ce7550 TH |
863 | return; |
864 | } | |
865 | ||
866 | if (ata_ratelimit()) | |
867 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " | |
aee10a03 TH |
868 | "(slot_stat 0x%x active_tag %d sactive 0x%x)\n", |
869 | slot_stat, ap->active_tag, ap->sactive); | |
edb33667 TH |
870 | } |
871 | ||
7d12e780 | 872 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance) |
edb33667 | 873 | { |
cca3974e | 874 | struct ata_host *host = dev_instance; |
0d5ff566 | 875 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
edb33667 TH |
876 | unsigned handled = 0; |
877 | u32 status; | |
878 | int i; | |
879 | ||
0d5ff566 | 880 | status = readl(host_base + HOST_IRQ_STAT); |
edb33667 | 881 | |
06460aea TH |
882 | if (status == 0xffffffff) { |
883 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " | |
884 | "PCI fault or device removal?\n"); | |
885 | goto out; | |
886 | } | |
887 | ||
edb33667 TH |
888 | if (!(status & IRQ_STAT_4PORTS)) |
889 | goto out; | |
890 | ||
cca3974e | 891 | spin_lock(&host->lock); |
edb33667 | 892 | |
cca3974e | 893 | for (i = 0; i < host->n_ports; i++) |
edb33667 | 894 | if (status & (1 << i)) { |
cca3974e | 895 | struct ata_port *ap = host->ports[i]; |
198e0fed | 896 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { |
cca3974e | 897 | sil24_host_intr(host->ports[i]); |
3cc4571c TH |
898 | handled++; |
899 | } else | |
900 | printk(KERN_ERR DRV_NAME | |
901 | ": interrupt from disabled port %d\n", i); | |
edb33667 TH |
902 | } |
903 | ||
cca3974e | 904 | spin_unlock(&host->lock); |
edb33667 TH |
905 | out: |
906 | return IRQ_RETVAL(handled); | |
907 | } | |
908 | ||
88ce7550 TH |
909 | static void sil24_error_handler(struct ata_port *ap) |
910 | { | |
911 | struct ata_eh_context *ehc = &ap->eh_context; | |
912 | ||
913 | if (sil24_init_port(ap)) { | |
914 | ata_eh_freeze_port(ap); | |
915 | ehc->i.action |= ATA_EH_HARDRESET; | |
916 | } | |
917 | ||
918 | /* perform recovery */ | |
f5914a46 TH |
919 | ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset, |
920 | ata_std_postreset); | |
88ce7550 TH |
921 | } |
922 | ||
923 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) | |
924 | { | |
925 | struct ata_port *ap = qc->ap; | |
926 | ||
927 | if (qc->flags & ATA_QCFLAG_FAILED) | |
928 | qc->err_mask |= AC_ERR_OTHER; | |
929 | ||
930 | /* make DMA engine forget about the failed command */ | |
931 | if (qc->err_mask) | |
932 | sil24_init_port(ap); | |
933 | } | |
934 | ||
edb33667 TH |
935 | static int sil24_port_start(struct ata_port *ap) |
936 | { | |
cca3974e | 937 | struct device *dev = ap->host->dev; |
edb33667 | 938 | struct sil24_port_priv *pp; |
69ad185f | 939 | union sil24_cmd_block *cb; |
aee10a03 | 940 | size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; |
edb33667 | 941 | dma_addr_t cb_dma; |
24dc5f33 | 942 | int rc; |
edb33667 | 943 | |
24dc5f33 | 944 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
edb33667 | 945 | if (!pp) |
24dc5f33 | 946 | return -ENOMEM; |
edb33667 | 947 | |
6a575fa9 TH |
948 | pp->tf.command = ATA_DRDY; |
949 | ||
24dc5f33 | 950 | cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
6037d6bb | 951 | if (!cb) |
24dc5f33 | 952 | return -ENOMEM; |
edb33667 TH |
953 | memset(cb, 0, cb_size); |
954 | ||
6037d6bb JG |
955 | rc = ata_pad_alloc(ap, dev); |
956 | if (rc) | |
24dc5f33 | 957 | return rc; |
6037d6bb | 958 | |
edb33667 TH |
959 | pp->cmd_block = cb; |
960 | pp->cmd_block_dma = cb_dma; | |
961 | ||
962 | ap->private_data = pp; | |
963 | ||
964 | return 0; | |
edb33667 TH |
965 | } |
966 | ||
2a41a610 | 967 | static void sil24_init_controller(struct pci_dev *pdev, int n_ports, |
cca3974e | 968 | unsigned long port_flags, |
2a41a610 TH |
969 | void __iomem *host_base, |
970 | void __iomem *port_base) | |
971 | { | |
972 | u32 tmp; | |
973 | int i; | |
974 | ||
975 | /* GPIO off */ | |
976 | writel(0, host_base + HOST_FLASH_CMD); | |
977 | ||
978 | /* clear global reset & mask interrupts during initialization */ | |
979 | writel(0, host_base + HOST_CTRL); | |
980 | ||
981 | /* init ports */ | |
982 | for (i = 0; i < n_ports; i++) { | |
983 | void __iomem *port = port_base + i * PORT_REGS_SIZE; | |
984 | ||
985 | /* Initial PHY setting */ | |
986 | writel(0x20c, port + PORT_PHY_CFG); | |
987 | ||
988 | /* Clear port RST */ | |
989 | tmp = readl(port + PORT_CTRL_STAT); | |
990 | if (tmp & PORT_CS_PORT_RST) { | |
991 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
992 | tmp = ata_wait_register(port + PORT_CTRL_STAT, | |
993 | PORT_CS_PORT_RST, | |
994 | PORT_CS_PORT_RST, 10, 100); | |
995 | if (tmp & PORT_CS_PORT_RST) | |
996 | dev_printk(KERN_ERR, &pdev->dev, | |
997 | "failed to clear port RST\n"); | |
998 | } | |
999 | ||
1000 | /* Configure IRQ WoC */ | |
cca3974e | 1001 | if (port_flags & SIL24_FLAG_PCIX_IRQ_WOC) |
2a41a610 TH |
1002 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); |
1003 | else | |
1004 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
1005 | ||
1006 | /* Zero error counters. */ | |
1007 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); | |
1008 | writel(0x8000, port + PORT_CRC_ERR_THRESH); | |
1009 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); | |
1010 | writel(0x0000, port + PORT_DECODE_ERR_CNT); | |
1011 | writel(0x0000, port + PORT_CRC_ERR_CNT); | |
1012 | writel(0x0000, port + PORT_HSHK_ERR_CNT); | |
1013 | ||
1014 | /* Always use 64bit activation */ | |
1015 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); | |
1016 | ||
1017 | /* Clear port multiplier enable and resume bits */ | |
28c8f3b4 TH |
1018 | writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, |
1019 | port + PORT_CTRL_CLR); | |
2a41a610 TH |
1020 | } |
1021 | ||
1022 | /* Turn on interrupts */ | |
1023 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); | |
1024 | } | |
1025 | ||
edb33667 TH |
1026 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1027 | { | |
1028 | static int printed_version = 0; | |
24dc5f33 | 1029 | struct device *dev = &pdev->dev; |
edb33667 | 1030 | unsigned int board_id = (unsigned int)ent->driver_data; |
042c21fd | 1031 | struct ata_port_info *pinfo = &sil24_port_info[board_id]; |
24dc5f33 | 1032 | struct ata_probe_ent *probe_ent; |
24dc5f33 TH |
1033 | void __iomem *host_base; |
1034 | void __iomem *port_base; | |
edb33667 | 1035 | int i, rc; |
37024e8e | 1036 | u32 tmp; |
edb33667 TH |
1037 | |
1038 | if (!printed_version++) | |
a9524a76 | 1039 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
edb33667 | 1040 | |
24dc5f33 | 1041 | rc = pcim_enable_device(pdev); |
edb33667 TH |
1042 | if (rc) |
1043 | return rc; | |
1044 | ||
0d5ff566 TH |
1045 | rc = pcim_iomap_regions(pdev, |
1046 | (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), | |
1047 | DRV_NAME); | |
edb33667 | 1048 | if (rc) |
24dc5f33 | 1049 | return rc; |
edb33667 | 1050 | |
0d5ff566 | 1051 | /* allocate & init probe_ent */ |
24dc5f33 | 1052 | probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); |
0d5ff566 | 1053 | if (!probe_ent) |
24dc5f33 | 1054 | return -ENOMEM; |
edb33667 | 1055 | |
edb33667 TH |
1056 | probe_ent->dev = pci_dev_to_dev(pdev); |
1057 | INIT_LIST_HEAD(&probe_ent->node); | |
1058 | ||
042c21fd | 1059 | probe_ent->sht = pinfo->sht; |
cca3974e | 1060 | probe_ent->port_flags = pinfo->flags; |
042c21fd | 1061 | probe_ent->pio_mask = pinfo->pio_mask; |
fbfda6e7 | 1062 | probe_ent->mwdma_mask = pinfo->mwdma_mask; |
042c21fd TH |
1063 | probe_ent->udma_mask = pinfo->udma_mask; |
1064 | probe_ent->port_ops = pinfo->port_ops; | |
cca3974e | 1065 | probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->flags); |
edb33667 TH |
1066 | |
1067 | probe_ent->irq = pdev->irq; | |
1d6f359a | 1068 | probe_ent->irq_flags = IRQF_SHARED; |
0d5ff566 | 1069 | probe_ent->iomap = pcim_iomap_table(pdev); |
edb33667 | 1070 | |
0d5ff566 TH |
1071 | host_base = probe_ent->iomap[SIL24_HOST_BAR]; |
1072 | port_base = probe_ent->iomap[SIL24_PORT_BAR]; | |
edb33667 TH |
1073 | |
1074 | /* | |
1075 | * Configure the device | |
1076 | */ | |
26ec634c TH |
1077 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
1078 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1079 | if (rc) { | |
1080 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1081 | if (rc) { | |
1082 | dev_printk(KERN_ERR, &pdev->dev, | |
1083 | "64-bit DMA enable failed\n"); | |
24dc5f33 | 1084 | return rc; |
26ec634c TH |
1085 | } |
1086 | } | |
1087 | } else { | |
1088 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1089 | if (rc) { | |
1090 | dev_printk(KERN_ERR, &pdev->dev, | |
1091 | "32-bit DMA enable failed\n"); | |
24dc5f33 | 1092 | return rc; |
26ec634c TH |
1093 | } |
1094 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1095 | if (rc) { | |
1096 | dev_printk(KERN_ERR, &pdev->dev, | |
1097 | "32-bit consistent DMA enable failed\n"); | |
24dc5f33 | 1098 | return rc; |
26ec634c | 1099 | } |
edb33667 TH |
1100 | } |
1101 | ||
37024e8e | 1102 | /* Apply workaround for completion IRQ loss on PCI-X errata */ |
cca3974e | 1103 | if (probe_ent->port_flags & SIL24_FLAG_PCIX_IRQ_WOC) { |
37024e8e TH |
1104 | tmp = readl(host_base + HOST_CTRL); |
1105 | if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) | |
1106 | dev_printk(KERN_INFO, &pdev->dev, | |
1107 | "Applying completion IRQ loss on PCI-X " | |
1108 | "errata fix\n"); | |
1109 | else | |
cca3974e | 1110 | probe_ent->port_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; |
37024e8e TH |
1111 | } |
1112 | ||
edb33667 | 1113 | for (i = 0; i < probe_ent->n_ports; i++) { |
0d5ff566 | 1114 | void __iomem *port = port_base + i * PORT_REGS_SIZE; |
edb33667 | 1115 | |
0d5ff566 TH |
1116 | probe_ent->port[i].cmd_addr = port; |
1117 | probe_ent->port[i].scr_addr = port + PORT_SCONTROL; | |
edb33667 TH |
1118 | |
1119 | ata_std_ports(&probe_ent->port[i]); | |
edb33667 TH |
1120 | } |
1121 | ||
cca3974e | 1122 | sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags, |
2a41a610 | 1123 | host_base, port_base); |
edb33667 TH |
1124 | |
1125 | pci_set_master(pdev); | |
1126 | ||
24dc5f33 TH |
1127 | if (!ata_device_add(probe_ent)) |
1128 | return -ENODEV; | |
edb33667 | 1129 | |
24dc5f33 | 1130 | devm_kfree(dev, probe_ent); |
edb33667 | 1131 | return 0; |
edb33667 TH |
1132 | } |
1133 | ||
281d426c | 1134 | #ifdef CONFIG_PM |
d2298dca TH |
1135 | static int sil24_pci_device_resume(struct pci_dev *pdev) |
1136 | { | |
cca3974e | 1137 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 TH |
1138 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
1139 | void __iomem *port_base = host->iomap[SIL24_PORT_BAR]; | |
553c4aa6 | 1140 | int rc; |
d2298dca | 1141 | |
553c4aa6 TH |
1142 | rc = ata_pci_device_do_resume(pdev); |
1143 | if (rc) | |
1144 | return rc; | |
d2298dca TH |
1145 | |
1146 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) | |
0d5ff566 | 1147 | writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); |
d2298dca | 1148 | |
cca3974e | 1149 | sil24_init_controller(pdev, host->n_ports, host->ports[0]->flags, |
0d5ff566 | 1150 | host_base, port_base); |
d2298dca | 1151 | |
cca3974e | 1152 | ata_host_resume(host); |
d2298dca TH |
1153 | |
1154 | return 0; | |
1155 | } | |
281d426c | 1156 | #endif |
d2298dca | 1157 | |
edb33667 TH |
1158 | static int __init sil24_init(void) |
1159 | { | |
b7887196 | 1160 | return pci_register_driver(&sil24_pci_driver); |
edb33667 TH |
1161 | } |
1162 | ||
1163 | static void __exit sil24_exit(void) | |
1164 | { | |
1165 | pci_unregister_driver(&sil24_pci_driver); | |
1166 | } | |
1167 | ||
1168 | MODULE_AUTHOR("Tejun Heo"); | |
1169 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); | |
1170 | MODULE_LICENSE("GPL"); | |
1171 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); | |
1172 | ||
1173 | module_init(sil24_init); | |
1174 | module_exit(sil24_exit); |