[mirror_ubuntu-bionic-kernel.git] / drivers / ata / sata_svw.c

/*
 *  sata_svw.c - ServerWorks / Apple K2 SATA
 *
 *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
 *		   Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *  This driver probably works with non-Apple versions of the
 *  Broadcom chipset...
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi.h>
#include <linux/libata.h>

#ifdef CONFIG_PPC_OF
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif /* CONFIG_PPC_OF */

#define DRV_NAME	"sata_svw"
#define DRV_VERSION	"2.3"

enum {
	/* ap->flags bits */
	K2_FLAG_SATA_8_PORTS		= (1 << 24),
	K2_FLAG_NO_ATAPI_DMA		= (1 << 25),
	K2_FLAG_BAR_POS_3			= (1 << 26),

	/* Taskfile registers offsets */
	K2_SATA_TF_CMD_OFFSET		= 0x00,
	K2_SATA_TF_DATA_OFFSET		= 0x00,
	K2_SATA_TF_ERROR_OFFSET		= 0x04,
	K2_SATA_TF_NSECT_OFFSET		= 0x08,
	K2_SATA_TF_LBAL_OFFSET		= 0x0c,
	K2_SATA_TF_LBAM_OFFSET		= 0x10,
	K2_SATA_TF_LBAH_OFFSET		= 0x14,
	K2_SATA_TF_DEVICE_OFFSET	= 0x18,
	K2_SATA_TF_CMDSTAT_OFFSET      	= 0x1c,
	K2_SATA_TF_CTL_OFFSET		= 0x20,

	/* DMA base */
	K2_SATA_DMA_CMD_OFFSET		= 0x30,

	/* SCRs base */
	K2_SATA_SCR_STATUS_OFFSET	= 0x40,
	K2_SATA_SCR_ERROR_OFFSET	= 0x44,
	K2_SATA_SCR_CONTROL_OFFSET	= 0x48,

	/* Others */
	K2_SATA_SICR1_OFFSET		= 0x80,
	K2_SATA_SICR2_OFFSET		= 0x84,
	K2_SATA_SIM_OFFSET		= 0x88,

	/* Port stride */
	K2_SATA_PORT_OFFSET		= 0x100,

	chip_svw4			= 0,
	chip_svw8			= 1,
	chip_svw42			= 2,	/* bar 3 */
	chip_svw43			= 3,	/* bar 5 */
};

static u8 k2_stat_check_status(struct ata_port *ap);


static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
{
	u8 cmnd = qc->scsicmd->cmnd[0];

	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
		return -1;	/* ATAPI DMA not supported */
	else {
		switch (cmnd) {
		case READ_10:
		case READ_12:
		case READ_16:
		case WRITE_10:
		case WRITE_12:
		case WRITE_16:
			return 0;

		default:
			return -1;
		}

	}
}

static int k2_sata_scr_read(struct ata_link *link,
			    unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static int k2_sata_scr_write(struct ata_link *link,
			     unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}

static int k2_sata_softreset(struct ata_link *link,
			     unsigned int *class, unsigned long deadline)
{
	u8 dmactl;
	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;

	dmactl = readb(mmio + ATA_DMA_CMD);

	/* Clear the start bit */
	if (dmactl & ATA_DMA_START) {
		dmactl &= ~ATA_DMA_START;
		writeb(dmactl, mmio + ATA_DMA_CMD);
	}

	return ata_sff_softreset(link, class, deadline);
}

static int k2_sata_hardreset(struct ata_link *link,
			     unsigned int *class, unsigned long deadline)
{
	u8 dmactl;
	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;

	dmactl = readb(mmio + ATA_DMA_CMD);

	/* Clear the start bit */
	if (dmactl & ATA_DMA_START) {
		dmactl &= ~ATA_DMA_START;
		writeb(dmactl, mmio + ATA_DMA_CMD);
	}

	return sata_sff_hardreset(link, class, deadline);
}

static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	if (tf->ctl != ap->last_ctl) {
		writeb(tf->ctl, ioaddr->ctl_addr);
		ap->last_ctl = tf->ctl;
		ata_wait_idle(ap);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = k2_stat_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
	}
}

/**
 *	k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	u8 dmactl;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;

	/* load PRD table addr. */
	mb();	/* make sure PRD table writes are visible to controller */
	writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);

	/* specify data direction, triple-check start bit is clear */
	dmactl = readb(mmio + ATA_DMA_CMD);
	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
	if (!rw)
		dmactl |= ATA_DMA_WR;
	writeb(dmactl, mmio + ATA_DMA_CMD);

	/* issue r/w command if this is not a ATA DMA command*/
	if (qc->tf.protocol != ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}

/**
 *	k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;
	u8 dmactl;

	/* start host DMA transaction */
	dmactl = readb(mmio + ATA_DMA_CMD);
	writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
	/* This works around possible data corruption.

	   On certain SATA controllers that can be seen when the r/w
	   command is given to the controller before the host DMA is
	   started.

	   On a Read command, the controller would initiate the
	   command to the drive even before it sees the DMA
	   start. When there are very fast drives connected to the
	   controller, or when the data request hits in the drive
	   cache, there is the possibility that the drive returns a
	   part or all of the requested data to the controller before
	   the DMA start is issued.  In this case, the controller
	   would become confused as to what to do with the data.  In
	   the worst case when all the data is returned back to the
	   controller, the controller could hang. In other cases it
	   could return partial data returning in data
	   corruption. This problem has been seen in PPC systems and
	   can also appear on an system with very fast disks, where
	   the SATA controller is sitting behind a number of bridges,
	   and hence there is significant latency between the r/w
	   command and the start command. */
	/* issue r/w command if the access is to ATA */
	if (qc->tf.protocol == ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}


static u8 k2_stat_check_status(struct ata_port *ap)
{
	return readl(ap->ioaddr.status_addr);
}

#ifdef CONFIG_PPC_OF
static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
{
	struct ata_port *ap;
	struct device_node *np;
	int index;

	/* Find  the ata_port */
	ap = ata_shost_to_port(shost);
	if (ap == NULL)
		return 0;

	/* Find the OF node for the PCI device proper */
	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
	if (np == NULL)
		return 0;

	/* Match it to a port node */
	index = (ap == ap->host->ports[0]) ? 0 : 1;
	for (np = np->child; np != NULL; np = np->sibling) {
		const u32 *reg = of_get_property(np, "reg", NULL);
		if (!reg)
			continue;
		if (index == *reg) {
			seq_printf(m, "devspec: %s\n", np->full_name);
			break;
		}
	}
	return 0;
}
#endif /* CONFIG_PPC_OF */


static struct scsi_host_template k2_sata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
#ifdef CONFIG_PPC_OF
	.show_info		= k2_sata_show_info,
#endif
};


static struct ata_port_operations k2_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.softreset              = k2_sata_softreset,
	.hardreset              = k2_sata_hardreset,
	.sff_tf_load		= k2_sata_tf_load,
	.sff_tf_read		= k2_sata_tf_read,
	.sff_check_status	= k2_stat_check_status,
	.check_atapi_dma	= k2_sata_check_atapi_dma,
	.bmdma_setup		= k2_bmdma_setup_mmio,
	.bmdma_start		= k2_bmdma_start_mmio,
	.scr_read		= k2_sata_scr_read,
	.scr_write		= k2_sata_scr_write,
};

static const struct ata_port_info k2_port_info[] = {
	/* chip_svw4 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw8 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
				  K2_FLAG_SATA_8_PORTS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw42 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw43 */
	{
		.flags		= ATA_FLAG_SATA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
};

static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		= base + K2_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + K2_SATA_TF_DATA_OFFSET;
	port->feature_addr	=
	port->error_addr	= base + K2_SATA_TF_ERROR_OFFSET;
	port->nsect_addr	= base + K2_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + K2_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + K2_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + K2_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + K2_SATA_TF_DEVICE_OFFSET;
	port->command_addr	=
	port->status_addr	= base + K2_SATA_TF_CMDSTAT_OFFSET;
	port->altstatus_addr	=
	port->ctl_addr		= base + K2_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + K2_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + K2_SATA_SCR_STATUS_OFFSET;
}


static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct ata_port_info *ppi[] =
		{ &k2_port_info[ent->driver_data], NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int n_ports, i, rc, bar_pos;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	/* allocate host */
	n_ports = 4;
	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
		n_ports = 8;

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	if (!host)
		return -ENOMEM;

	bar_pos = 5;
	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
		bar_pos = 3;
	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/*
	 * Check if we have resources mapped at all (second function may
	 * have been disabled by firmware)
	 */
	if (pci_resource_len(pdev, bar_pos) == 0) {
		/* In IDE mode we need to pin the device to ensure that
			pcim_release does not clear the busmaster bit in config
			space, clearing causes busmaster DMA to fail on
			ports 3 & 4 */
		pcim_pin_device(pdev);
		return -ENODEV;
	}

	/* Request and iomap PCI regions */
	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	mmio_base = host->iomap[bar_pos];

	/* different controllers have different number of ports - currently 4 or 8 */
	/* All ports are on the same function. Multi-function device is no
	 * longer available. This should not be seen in any system. */
	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		unsigned int offset = i * K2_SATA_PORT_OFFSET;

		k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);

		ata_port_pbar_desc(ap, 5, -1, "mmio");
		ata_port_pbar_desc(ap, 5, offset, "port");
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;

	/* Clear a magic bit in SCR1 according to Darwin, those help
	 * some funky seagate drives (though so far, those were already
	 * set by the firmware on the machines I had access to)
	 */
	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	       mmio_base + K2_SATA_SICR1_OFFSET);

	/* Clear SATA error & interrupts we don't use */
	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
				 IRQF_SHARED, &k2_sata_sht);
}

/* 0x240 is device ID for Apple K2 device
 * 0x241 is device ID for Serverworks Frodo4
 * 0x242 is device ID for Serverworks Frodo8
 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 * controller
 * */
static const struct pci_device_id k2_sata_pci_tbl[] = {
	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },

	{ }
};

static struct pci_driver k2_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= k2_sata_pci_tbl,
	.probe			= k2_sata_init_one,
	.remove			= ata_pci_remove_one,
};

module_pci_driver(k2_sata_pci_driver);

MODULE_AUTHOR("Benjamin Herrenschmidt");
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_svw.c - ServerWorks / Apple K2 SATA
	3	*
	4	* Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
	5	* Jeff Garzik <jgarzik@pobox.com>
	6	* Please ALWAYS copy linux-ide@vger.kernel.org
	7	* on emails.
	8	*
	9	* Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
	10	*
	11	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	12	*
	13	* This driver probably works with non-Apple versions of the
	14	* Broadcom chipset...
	15	*
af36d7f0 JG	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License as published by
	19	* the Free Software Foundation; either version 2, or (at your option)
	20	* any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; see the file COPYING. If not, write to
	29	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	30	*
	31	*
	32	* libata documentation is available via 'make {ps\|pdf}docs',
	33	* as Documentation/DocBook/libata.*
	34	*
	35	* Hardware documentation available under NDA.
1da177e4 LT	36	*
	37	*/
	38
1da177e4 LT	39	#include <linux/kernel.h>
	40	#include <linux/module.h>
	41	#include <linux/pci.h>
1da177e4 LT	42	#include <linux/blkdev.h>
	43	#include <linux/delay.h>
	44	#include <linux/interrupt.h>
a9524a76	45	#include <linux/device.h>
1da177e4	46	#include <scsi/scsi_host.h>
931506d3 AS	47	#include <scsi/scsi_cmnd.h>
931506d3 AS	48	#include <scsi/scsi.h>
1da177e4 LT	49	#include <linux/libata.h>
	50
	51	#ifdef CONFIG_PPC_OF
	52	#include <asm/prom.h>
	53	#include <asm/pci-bridge.h>
	54	#endif /* CONFIG_PPC_OF */
	55
	56	#define DRV_NAME "sata_svw"
2a3103ce	57	#define DRV_VERSION "2.3"
1da177e4	58
55cca65e	59	enum {
4447d351 TH	60	/* ap->flags bits */
	61	K2_FLAG_SATA_8_PORTS = (1 << 24),
	62	K2_FLAG_NO_ATAPI_DMA = (1 << 25),
931506d3	63	K2_FLAG_BAR_POS_3 = (1 << 26),
c10340ac	64
55cca65e JG	65	/* Taskfile registers offsets */
	66	K2_SATA_TF_CMD_OFFSET = 0x00,
	67	K2_SATA_TF_DATA_OFFSET = 0x00,
	68	K2_SATA_TF_ERROR_OFFSET = 0x04,
	69	K2_SATA_TF_NSECT_OFFSET = 0x08,
	70	K2_SATA_TF_LBAL_OFFSET = 0x0c,
	71	K2_SATA_TF_LBAM_OFFSET = 0x10,
	72	K2_SATA_TF_LBAH_OFFSET = 0x14,
	73	K2_SATA_TF_DEVICE_OFFSET = 0x18,
	74	K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
	75	K2_SATA_TF_CTL_OFFSET = 0x20,
1da177e4	76
55cca65e JG	77	/* DMA base */
55cca65e JG	78	K2_SATA_DMA_CMD_OFFSET = 0x30,
1da177e4	79
55cca65e JG	80	/* SCRs base */
	81	K2_SATA_SCR_STATUS_OFFSET = 0x40,
	82	K2_SATA_SCR_ERROR_OFFSET = 0x44,
	83	K2_SATA_SCR_CONTROL_OFFSET = 0x48,
1da177e4	84
55cca65e JG	85	/* Others */
	86	K2_SATA_SICR1_OFFSET = 0x80,
	87	K2_SATA_SICR2_OFFSET = 0x84,
	88	K2_SATA_SIM_OFFSET = 0x88,
1da177e4	89
55cca65e JG	90	/* Port stride */
55cca65e JG	91	K2_SATA_PORT_OFFSET = 0x100,
c10340ac	92
931506d3 AS	93	chip_svw4 = 0,
	94	chip_svw8 = 1,
	95	chip_svw42 = 2, /* bar 3 */
	96	chip_svw43 = 3, /* bar 5 */
c10340ac JG	97	};
c10340ac JG	98
ac19bff2 JG	99	static u8 k2_stat_check_status(struct ata_port *ap);
ac19bff2 JG	100
1da177e4	101
c10340ac JG	102	static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
c10340ac JG	103	{
931506d3 AS	104	u8 cmnd = qc->scsicmd->cmnd[0];
931506d3 AS	105
c10340ac JG	106	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
c10340ac JG	107	return -1; /* ATAPI DMA not supported */
931506d3 AS	108	else {
	109	switch (cmnd) {
	110	case READ_10:
	111	case READ_12:
	112	case READ_16:
	113	case WRITE_10:
	114	case WRITE_12:
	115	case WRITE_16:
	116	return 0;
	117
	118	default:
	119	return -1;
	120	}
c10340ac	121
931506d3	122	}
c10340ac JG	123	}
c10340ac JG	124
82ef04fb TH	125	static int k2_sata_scr_read(struct ata_link *link,
82ef04fb TH	126	unsigned int sc_reg, u32 *val)
1da177e4 LT	127	{
1da177e4 LT	128	if (sc_reg > SCR_CONTROL)
da3dbb17	129	return -EINVAL;
82ef04fb	130	val = readl(link->ap->ioaddr.scr_addr + (sc_reg 4));
da3dbb17	131	return 0;
1da177e4 LT	132	}
	133
	134
82ef04fb TH	135	static int k2_sata_scr_write(struct ata_link *link,
82ef04fb TH	136	unsigned int sc_reg, u32 val)
1da177e4 LT	137	{
1da177e4 LT	138	if (sc_reg > SCR_CONTROL)
da3dbb17	139	return -EINVAL;
82ef04fb	140	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17	141	return 0;
1da177e4 LT	142	}
1da177e4 LT	143
b03e66a6 DM	144	static int k2_sata_softreset(struct ata_link *link,
	145	unsigned int *class, unsigned long deadline)
	146	{
	147	u8 dmactl;
	148	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
	149
	150	dmactl = readb(mmio + ATA_DMA_CMD);
	151
	152	/* Clear the start bit */
	153	if (dmactl & ATA_DMA_START) {
	154	dmactl &= ~ATA_DMA_START;
	155	writeb(dmactl, mmio + ATA_DMA_CMD);
	156	}
	157
	158	return ata_sff_softreset(link, class, deadline);
	159	}
	160
	161	static int k2_sata_hardreset(struct ata_link *link,
	162	unsigned int *class, unsigned long deadline)
	163	{
	164	u8 dmactl;
	165	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
	166
	167	dmactl = readb(mmio + ATA_DMA_CMD);
	168
	169	/* Clear the start bit */
	170	if (dmactl & ATA_DMA_START) {
	171	dmactl &= ~ATA_DMA_START;
	172	writeb(dmactl, mmio + ATA_DMA_CMD);
	173	}
	174
	175	return sata_sff_hardreset(link, class, deadline);
	176	}
1da177e4	177
057ace5e	178	static void k2_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	179	{
	180	struct ata_ioports *ioaddr = &ap->ioaddr;
	181	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	182
	183	if (tf->ctl != ap->last_ctl) {
0d5ff566	184	writeb(tf->ctl, ioaddr->ctl_addr);
1da177e4 LT	185	ap->last_ctl = tf->ctl;
	186	ata_wait_idle(ap);
	187	}
	188	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a	189	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
0d5ff566	190	ioaddr->feature_addr);
850a9d8a	191	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
0d5ff566	192	ioaddr->nsect_addr);
850a9d8a	193	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
0d5ff566	194	ioaddr->lbal_addr);
850a9d8a	195	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
0d5ff566	196	ioaddr->lbam_addr);
850a9d8a	197	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
0d5ff566	198	ioaddr->lbah_addr);
1da177e4	199	} else if (is_addr) {
0d5ff566 TH	200	writew(tf->feature, ioaddr->feature_addr);
	201	writew(tf->nsect, ioaddr->nsect_addr);
	202	writew(tf->lbal, ioaddr->lbal_addr);
	203	writew(tf->lbam, ioaddr->lbam_addr);
	204	writew(tf->lbah, ioaddr->lbah_addr);
1da177e4 LT	205	}
	206
	207	if (tf->flags & ATA_TFLAG_DEVICE)
0d5ff566	208	writeb(tf->device, ioaddr->device_addr);
1da177e4 LT	209
	210	ata_wait_idle(ap);
	211	}
	212
	213
	214	static void k2_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	215	{
	216	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	217	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	218
ac19bff2	219	tf->command = k2_stat_check_status(ap);
0d5ff566 TH	220	tf->device = readw(ioaddr->device_addr);
	221	feature = readw(ioaddr->error_addr);
	222	nsect = readw(ioaddr->nsect_addr);
	223	lbal = readw(ioaddr->lbal_addr);
	224	lbam = readw(ioaddr->lbam_addr);
	225	lbah = readw(ioaddr->lbah_addr);
ac19bff2 JG	226
	227	tf->feature = feature;
	228	tf->nsect = nsect;
	229	tf->lbal = lbal;
	230	tf->lbam = lbam;
	231	tf->lbah = lbah;
1da177e4 LT	232
1da177e4 LT	233	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	234	tf->hob_feature = feature >> 8;
1da177e4 LT	235	tf->hob_nsect = nsect >> 8;
	236	tf->hob_lbal = lbal >> 8;
	237	tf->hob_lbam = lbam >> 8;
	238	tf->hob_lbah = lbah >> 8;
5796d1c4	239	}
1da177e4 LT	240	}
	241
	242	/**
	243	* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
	244	* @qc: Info associated with this ATA transaction.
	245	*
	246	* LOCKING:
cca3974e	247	* spin_lock_irqsave(host lock)
1da177e4 LT	248	*/
1da177e4 LT	249
5796d1c4	250	static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	251	{
	252	struct ata_port *ap = qc->ap;
	253	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	254	u8 dmactl;
59f99880 JG	255	void __iomem *mmio = ap->ioaddr.bmdma_addr;
59f99880 JG	256
1da177e4 LT	257	/* load PRD table addr. */
1da177e4 LT	258	mb(); /* make sure PRD table writes are visible to controller */
f60d7011	259	writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
1da177e4 LT	260
	261	/* specify data direction, triple-check start bit is clear */
	262	dmactl = readb(mmio + ATA_DMA_CMD);
	263	dmactl &= ~(ATA_DMA_WR \| ATA_DMA_START);
	264	if (!rw)
	265	dmactl \|= ATA_DMA_WR;
	266	writeb(dmactl, mmio + ATA_DMA_CMD);
	267
	268	/* issue r/w command if this is not a ATA DMA command*/
	269	if (qc->tf.protocol != ATA_PROT_DMA)
5682ed33	270	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	271	}
	272
	273	/**
	274	* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
	275	* @qc: Info associated with this ATA transaction.
	276	*
	277	* LOCKING:
cca3974e	278	* spin_lock_irqsave(host lock)
1da177e4 LT	279	*/
1da177e4 LT	280
5796d1c4	281	static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	282	{
1da177e4 LT	283	struct ata_port *ap = qc->ap;
59f99880	284	void __iomem *mmio = ap->ioaddr.bmdma_addr;
1da177e4 LT	285	u8 dmactl;
	286
	287	/* start host DMA transaction */
	288	dmactl = readb(mmio + ATA_DMA_CMD);
	289	writeb(dmactl \| ATA_DMA_START, mmio + ATA_DMA_CMD);
ec6add99 PM	290	/* This works around possible data corruption.
	291
	292	On certain SATA controllers that can be seen when the r/w
	293	command is given to the controller before the host DMA is
	294	started.
	295
	296	On a Read command, the controller would initiate the
	297	command to the drive even before it sees the DMA
	298	start. When there are very fast drives connected to the
	299	controller, or when the data request hits in the drive
	300	cache, there is the possibility that the drive returns a
	301	part or all of the requested data to the controller before
	302	the DMA start is issued. In this case, the controller
	303	would become confused as to what to do with the data. In
	304	the worst case when all the data is returned back to the
	305	controller, the controller could hang. In other cases it
	306	could return partial data returning in data
	307	corruption. This problem has been seen in PPC systems and
	308	can also appear on an system with very fast disks, where
	309	the SATA controller is sitting behind a number of bridges,
	310	and hence there is significant latency between the r/w
	311	command and the start command. */
	312	/* issue r/w command if the access is to ATA */
1da177e4	313	if (qc->tf.protocol == ATA_PROT_DMA)
5682ed33	314	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	315	}
1da177e4 LT	316
8a60a071	317
1da177e4 LT	318	static u8 k2_stat_check_status(struct ata_port *ap)
1da177e4 LT	319	{
5796d1c4	320	return readl(ap->ioaddr.status_addr);
1da177e4 LT	321	}
	322
	323	#ifdef CONFIG_PPC_OF
3f025677	324	static int k2_sata_show_info(struct seq_file m, struct Scsi_Host shost)
1da177e4 LT	325	{
	326	struct ata_port *ap;
	327	struct device_node *np;
3f025677	328	int index;
1da177e4 LT	329
1da177e4 LT	330	/* Find the ata_port */
35bb94b1	331	ap = ata_shost_to_port(shost);
1da177e4 LT	332	if (ap == NULL)
	333	return 0;
	334
	335	/* Find the OF node for the PCI device proper */
cca3974e	336	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
1da177e4 LT	337	if (np == NULL)
	338	return 0;
	339
	340	/* Match it to a port node */
cca3974e	341	index = (ap == ap->host->ports[0]) ? 0 : 1;
1da177e4	342	for (np = np->child; np != NULL; np = np->sibling) {
40cd3a45	343	const u32 *reg = of_get_property(np, "reg", NULL);
1da177e4 LT	344	if (!reg)
1da177e4 LT	345	continue;
3f025677 AV	346	if (index == *reg) {
3f025677 AV	347	seq_printf(m, "devspec: %s\n", np->full_name);
1da177e4	348	break;
3f025677	349	}
1da177e4	350	}
3f025677	351	return 0;
1da177e4 LT	352	}
	353	#endif /* CONFIG_PPC_OF */
	354
	355
193515d5	356	static struct scsi_host_template k2_sata_sht = {
68d1d07b	357	ATA_BMDMA_SHT(DRV_NAME),
1da177e4	358	#ifdef CONFIG_PPC_OF
3f025677	359	.show_info = k2_sata_show_info,
1da177e4	360	#endif
1da177e4 LT	361	};
	362
	363
029cfd6b TH	364	static struct ata_port_operations k2_sata_ops = {
029cfd6b TH	365	.inherits = &ata_bmdma_port_ops,
b03e66a6 DM	366	.softreset = k2_sata_softreset,
b03e66a6 DM	367	.hardreset = k2_sata_hardreset,
5682ed33 TH	368	.sff_tf_load = k2_sata_tf_load,
	369	.sff_tf_read = k2_sata_tf_read,
	370	.sff_check_status = k2_stat_check_status,
c10340ac	371	.check_atapi_dma = k2_sata_check_atapi_dma,
1da177e4 LT	372	.bmdma_setup = k2_bmdma_setup_mmio,
1da177e4 LT	373	.bmdma_start = k2_bmdma_start_mmio,
1da177e4 LT	374	.scr_read = k2_sata_scr_read,
1da177e4 LT	375	.scr_write = k2_sata_scr_write,
1da177e4 LT	376	};
1da177e4 LT	377
4447d351	378	static const struct ata_port_info k2_port_info[] = {
931506d3	379	/* chip_svw4 */
4447d351	380	{
9cbe056f	381	.flags = ATA_FLAG_SATA \| K2_FLAG_NO_ATAPI_DMA,
14bdef98 EIB	382	.pio_mask = ATA_PIO4,
14bdef98 EIB	383	.mwdma_mask = ATA_MWDMA2,
bf6263a8	384	.udma_mask = ATA_UDMA6,
4447d351 TH	385	.port_ops = &k2_sata_ops,
4447d351 TH	386	},
931506d3	387	/* chip_svw8 */
4447d351	388	{
9cbe056f SS	389	.flags = ATA_FLAG_SATA \| K2_FLAG_NO_ATAPI_DMA \|
9cbe056f SS	390	K2_FLAG_SATA_8_PORTS,
14bdef98 EIB	391	.pio_mask = ATA_PIO4,
14bdef98 EIB	392	.mwdma_mask = ATA_MWDMA2,
bf6263a8	393	.udma_mask = ATA_UDMA6,
4447d351 TH	394	.port_ops = &k2_sata_ops,
4447d351 TH	395	},
931506d3 AS	396	/* chip_svw42 */
931506d3 AS	397	{
9cbe056f	398	.flags = ATA_FLAG_SATA \| K2_FLAG_BAR_POS_3,
14bdef98 EIB	399	.pio_mask = ATA_PIO4,
14bdef98 EIB	400	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	401	.udma_mask = ATA_UDMA6,
	402	.port_ops = &k2_sata_ops,
	403	},
	404	/* chip_svw43 */
	405	{
9cbe056f	406	.flags = ATA_FLAG_SATA,
14bdef98 EIB	407	.pio_mask = ATA_PIO4,
14bdef98 EIB	408	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	409	.udma_mask = ATA_UDMA6,
	410	.port_ops = &k2_sata_ops,
	411	},
4447d351 TH	412	};
4447d351 TH	413
0d5ff566	414	static void k2_sata_setup_port(struct ata_ioports port, void __iomem base)
1da177e4 LT	415	{
	416	port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
	417	port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
	418	port->feature_addr =
	419	port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
	420	port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
	421	port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
	422	port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
	423	port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
	424	port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
	425	port->command_addr =
	426	port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
	427	port->altstatus_addr =
	428	port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
	429	port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
	430	port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
	431	}
	432
	433
5796d1c4	434	static int k2_sata_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4	435	{
4447d351 TH	436	const struct ata_port_info *ppi[] =
	437	{ &k2_port_info[ent->driver_data], NULL };
	438	struct ata_host *host;
ea6ba10b	439	void __iomem *mmio_base;
931506d3	440	int n_ports, i, rc, bar_pos;
1da177e4	441
06296a1e	442	ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4	443
4447d351 TH	444	/* allocate host */
	445	n_ports = 4;
	446	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
	447	n_ports = 8;
	448
	449	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	450	if (!host)
	451	return -ENOMEM;
	452
931506d3 AS	453	bar_pos = 5;
	454	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
	455	bar_pos = 3;
1da177e4 LT	456	/*
	457	* If this driver happens to only be useful on Apple's K2, then
	458	* we should check that here as it has a normal Serverworks ID
	459	*/
24dc5f33	460	rc = pcim_enable_device(pdev);
1da177e4 LT	461	if (rc)
1da177e4 LT	462	return rc;
4447d351	463
1da177e4 LT	464	/*
	465	* Check if we have resources mapped at all (second function may
	466	* have been disabled by firmware)
	467	*/
931506d3 AS	468	if (pci_resource_len(pdev, bar_pos) == 0) {
	469	/* In IDE mode we need to pin the device to ensure that
	470	pcim_release does not clear the busmaster bit in config
	471	space, clearing causes busmaster DMA to fail on
	472	ports 3 & 4 */
	473	pcim_pin_device(pdev);
1da177e4	474	return -ENODEV;
931506d3	475	}
1da177e4	476
0d5ff566	477	/* Request and iomap PCI regions */
931506d3	478	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
0d5ff566	479	if (rc == -EBUSY)
24dc5f33	480	pcim_pin_device(pdev);
0d5ff566	481	if (rc)
24dc5f33	482	return rc;
4447d351	483	host->iomap = pcim_iomap_table(pdev);
931506d3	484	mmio_base = host->iomap[bar_pos];
4447d351 TH	485
	486	/* different controllers have different number of ports - currently 4 or 8 */
	487	/* All ports are on the same function. Multi-function device is no
	488	* longer available. This should not be seen in any system. */
cbcdd875 TH	489	for (i = 0; i < host->n_ports; i++) {
	490	struct ata_port *ap = host->ports[i];
	491	unsigned int offset = i * K2_SATA_PORT_OFFSET;
	492
	493	k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
	494
	495	ata_port_pbar_desc(ap, 5, -1, "mmio");
	496	ata_port_pbar_desc(ap, 5, offset, "port");
	497	}
1da177e4 LT	498
	499	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	500	if (rc)
24dc5f33	501	return rc;
1da177e4 LT	502	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1da177e4 LT	503	if (rc)
24dc5f33	504	return rc;
1da177e4	505
0d5ff566 TH	506	/* Clear a magic bit in SCR1 according to Darwin, those help
	507	* some funky seagate drives (though so far, those were already
	508	* set by the firmware on the machines I had access to)
	509	*/
	510	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	511	mmio_base + K2_SATA_SICR1_OFFSET);
	512
	513	/* Clear SATA error & interrupts we don't use */
	514	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	515	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
1da177e4 LT	516
1da177e4 LT	517	pci_set_master(pdev);
c3b28894	518	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
9363c382	519	IRQF_SHARED, &k2_sata_sht);
1da177e4 LT	520	}
1da177e4 LT	521
60bf09a3 NS	522	/* 0x240 is device ID for Apple K2 device
	523	* 0x241 is device ID for Serverworks Frodo4
	524	* 0x242 is device ID for Serverworks Frodo8
	525	* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
	526	* controller
	527	* */
3b7d697d	528	static const struct pci_device_id k2_sata_pci_tbl[] = {
931506d3	529	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
aeb74914 JG	530	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
aeb74914 JG	531	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
931506d3 AS	532	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	533	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	534	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	535	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
2d2744fc	536
1da177e4 LT	537	{ }
	538	};
	539
1da177e4 LT	540	static struct pci_driver k2_sata_pci_driver = {
	541	.name = DRV_NAME,
	542	.id_table = k2_sata_pci_tbl,
	543	.probe = k2_sata_init_one,
	544	.remove = ata_pci_remove_one,
	545	};
	546
2fc75da0	547	module_pci_driver(k2_sata_pci_driver);
1da177e4	548
1da177e4 LT	549	MODULE_AUTHOR("Benjamin Herrenschmidt");
	550	MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
	551	MODULE_LICENSE("GPL");
	552	MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
	553	MODULE_VERSION(DRV_VERSION);