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1da177e4 LT |
1 | /* |
2 | * sata_svw.c - ServerWorks / Apple K2 SATA | |
3 | * | |
4 | * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and | |
5 | * Jeff Garzik <jgarzik@pobox.com> | |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
7 | * on emails. | |
8 | * | |
9 | * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> | |
10 | * | |
11 | * Bits from Jeff Garzik, Copyright RedHat, Inc. | |
12 | * | |
13 | * This driver probably works with non-Apple versions of the | |
14 | * Broadcom chipset... | |
15 | * | |
af36d7f0 JG |
16 | * |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License as published by | |
19 | * the Free Software Foundation; either version 2, or (at your option) | |
20 | * any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; see the file COPYING. If not, write to | |
29 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | * | |
31 | * | |
32 | * libata documentation is available via 'make {ps|pdf}docs', | |
33 | * as Documentation/DocBook/libata.* | |
34 | * | |
35 | * Hardware documentation available under NDA. | |
1da177e4 LT |
36 | * |
37 | */ | |
38 | ||
1da177e4 LT |
39 | #include <linux/kernel.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/blkdev.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/interrupt.h> | |
a9524a76 | 46 | #include <linux/device.h> |
1da177e4 | 47 | #include <scsi/scsi_host.h> |
931506d3 AS |
48 | #include <scsi/scsi_cmnd.h> |
49 | #include <scsi/scsi.h> | |
1da177e4 LT |
50 | #include <linux/libata.h> |
51 | ||
52 | #ifdef CONFIG_PPC_OF | |
53 | #include <asm/prom.h> | |
54 | #include <asm/pci-bridge.h> | |
55 | #endif /* CONFIG_PPC_OF */ | |
56 | ||
57 | #define DRV_NAME "sata_svw" | |
2a3103ce | 58 | #define DRV_VERSION "2.3" |
1da177e4 | 59 | |
55cca65e | 60 | enum { |
4447d351 TH |
61 | /* ap->flags bits */ |
62 | K2_FLAG_SATA_8_PORTS = (1 << 24), | |
63 | K2_FLAG_NO_ATAPI_DMA = (1 << 25), | |
931506d3 | 64 | K2_FLAG_BAR_POS_3 = (1 << 26), |
c10340ac | 65 | |
55cca65e JG |
66 | /* Taskfile registers offsets */ |
67 | K2_SATA_TF_CMD_OFFSET = 0x00, | |
68 | K2_SATA_TF_DATA_OFFSET = 0x00, | |
69 | K2_SATA_TF_ERROR_OFFSET = 0x04, | |
70 | K2_SATA_TF_NSECT_OFFSET = 0x08, | |
71 | K2_SATA_TF_LBAL_OFFSET = 0x0c, | |
72 | K2_SATA_TF_LBAM_OFFSET = 0x10, | |
73 | K2_SATA_TF_LBAH_OFFSET = 0x14, | |
74 | K2_SATA_TF_DEVICE_OFFSET = 0x18, | |
75 | K2_SATA_TF_CMDSTAT_OFFSET = 0x1c, | |
76 | K2_SATA_TF_CTL_OFFSET = 0x20, | |
1da177e4 | 77 | |
55cca65e JG |
78 | /* DMA base */ |
79 | K2_SATA_DMA_CMD_OFFSET = 0x30, | |
1da177e4 | 80 | |
55cca65e JG |
81 | /* SCRs base */ |
82 | K2_SATA_SCR_STATUS_OFFSET = 0x40, | |
83 | K2_SATA_SCR_ERROR_OFFSET = 0x44, | |
84 | K2_SATA_SCR_CONTROL_OFFSET = 0x48, | |
1da177e4 | 85 | |
55cca65e JG |
86 | /* Others */ |
87 | K2_SATA_SICR1_OFFSET = 0x80, | |
88 | K2_SATA_SICR2_OFFSET = 0x84, | |
89 | K2_SATA_SIM_OFFSET = 0x88, | |
1da177e4 | 90 | |
55cca65e JG |
91 | /* Port stride */ |
92 | K2_SATA_PORT_OFFSET = 0x100, | |
c10340ac | 93 | |
931506d3 AS |
94 | chip_svw4 = 0, |
95 | chip_svw8 = 1, | |
96 | chip_svw42 = 2, /* bar 3 */ | |
97 | chip_svw43 = 3, /* bar 5 */ | |
c10340ac JG |
98 | }; |
99 | ||
ac19bff2 JG |
100 | static u8 k2_stat_check_status(struct ata_port *ap); |
101 | ||
1da177e4 | 102 | |
c10340ac JG |
103 | static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
104 | { | |
931506d3 AS |
105 | u8 cmnd = qc->scsicmd->cmnd[0]; |
106 | ||
c10340ac JG |
107 | if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA) |
108 | return -1; /* ATAPI DMA not supported */ | |
931506d3 AS |
109 | else { |
110 | switch (cmnd) { | |
111 | case READ_10: | |
112 | case READ_12: | |
113 | case READ_16: | |
114 | case WRITE_10: | |
115 | case WRITE_12: | |
116 | case WRITE_16: | |
117 | return 0; | |
118 | ||
119 | default: | |
120 | return -1; | |
121 | } | |
c10340ac | 122 | |
931506d3 | 123 | } |
c10340ac JG |
124 | } |
125 | ||
da3dbb17 | 126 | static int k2_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 LT |
127 | { |
128 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 TH |
129 | return -EINVAL; |
130 | *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4)); | |
131 | return 0; | |
1da177e4 LT |
132 | } |
133 | ||
134 | ||
da3dbb17 | 135 | static int k2_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 LT |
136 | { |
137 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 | 138 | return -EINVAL; |
59f99880 | 139 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 140 | return 0; |
1da177e4 LT |
141 | } |
142 | ||
143 | ||
057ace5e | 144 | static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
145 | { |
146 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
147 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
148 | ||
149 | if (tf->ctl != ap->last_ctl) { | |
0d5ff566 | 150 | writeb(tf->ctl, ioaddr->ctl_addr); |
1da177e4 LT |
151 | ap->last_ctl = tf->ctl; |
152 | ata_wait_idle(ap); | |
153 | } | |
154 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
850a9d8a | 155 | writew(tf->feature | (((u16)tf->hob_feature) << 8), |
0d5ff566 | 156 | ioaddr->feature_addr); |
850a9d8a | 157 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), |
0d5ff566 | 158 | ioaddr->nsect_addr); |
850a9d8a | 159 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), |
0d5ff566 | 160 | ioaddr->lbal_addr); |
850a9d8a | 161 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), |
0d5ff566 | 162 | ioaddr->lbam_addr); |
850a9d8a | 163 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), |
0d5ff566 | 164 | ioaddr->lbah_addr); |
1da177e4 | 165 | } else if (is_addr) { |
0d5ff566 TH |
166 | writew(tf->feature, ioaddr->feature_addr); |
167 | writew(tf->nsect, ioaddr->nsect_addr); | |
168 | writew(tf->lbal, ioaddr->lbal_addr); | |
169 | writew(tf->lbam, ioaddr->lbam_addr); | |
170 | writew(tf->lbah, ioaddr->lbah_addr); | |
1da177e4 LT |
171 | } |
172 | ||
173 | if (tf->flags & ATA_TFLAG_DEVICE) | |
0d5ff566 | 174 | writeb(tf->device, ioaddr->device_addr); |
1da177e4 LT |
175 | |
176 | ata_wait_idle(ap); | |
177 | } | |
178 | ||
179 | ||
180 | static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
181 | { | |
182 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
ac19bff2 | 183 | u16 nsect, lbal, lbam, lbah, feature; |
1da177e4 | 184 | |
ac19bff2 | 185 | tf->command = k2_stat_check_status(ap); |
0d5ff566 TH |
186 | tf->device = readw(ioaddr->device_addr); |
187 | feature = readw(ioaddr->error_addr); | |
188 | nsect = readw(ioaddr->nsect_addr); | |
189 | lbal = readw(ioaddr->lbal_addr); | |
190 | lbam = readw(ioaddr->lbam_addr); | |
191 | lbah = readw(ioaddr->lbah_addr); | |
ac19bff2 JG |
192 | |
193 | tf->feature = feature; | |
194 | tf->nsect = nsect; | |
195 | tf->lbal = lbal; | |
196 | tf->lbam = lbam; | |
197 | tf->lbah = lbah; | |
1da177e4 LT |
198 | |
199 | if (tf->flags & ATA_TFLAG_LBA48) { | |
ac19bff2 | 200 | tf->hob_feature = feature >> 8; |
1da177e4 LT |
201 | tf->hob_nsect = nsect >> 8; |
202 | tf->hob_lbal = lbal >> 8; | |
203 | tf->hob_lbam = lbam >> 8; | |
204 | tf->hob_lbah = lbah >> 8; | |
5796d1c4 | 205 | } |
1da177e4 LT |
206 | } |
207 | ||
208 | /** | |
209 | * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO) | |
210 | * @qc: Info associated with this ATA transaction. | |
211 | * | |
212 | * LOCKING: | |
cca3974e | 213 | * spin_lock_irqsave(host lock) |
1da177e4 LT |
214 | */ |
215 | ||
5796d1c4 | 216 | static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc) |
1da177e4 LT |
217 | { |
218 | struct ata_port *ap = qc->ap; | |
219 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
220 | u8 dmactl; | |
59f99880 JG |
221 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
222 | ||
1da177e4 LT |
223 | /* load PRD table addr. */ |
224 | mb(); /* make sure PRD table writes are visible to controller */ | |
225 | writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS); | |
226 | ||
227 | /* specify data direction, triple-check start bit is clear */ | |
228 | dmactl = readb(mmio + ATA_DMA_CMD); | |
229 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
230 | if (!rw) | |
231 | dmactl |= ATA_DMA_WR; | |
232 | writeb(dmactl, mmio + ATA_DMA_CMD); | |
233 | ||
234 | /* issue r/w command if this is not a ATA DMA command*/ | |
235 | if (qc->tf.protocol != ATA_PROT_DMA) | |
236 | ap->ops->exec_command(ap, &qc->tf); | |
237 | } | |
238 | ||
239 | /** | |
240 | * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO) | |
241 | * @qc: Info associated with this ATA transaction. | |
242 | * | |
243 | * LOCKING: | |
cca3974e | 244 | * spin_lock_irqsave(host lock) |
1da177e4 LT |
245 | */ |
246 | ||
5796d1c4 | 247 | static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc) |
1da177e4 LT |
248 | { |
249 | struct ata_port *ap = qc->ap; | |
59f99880 | 250 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
1da177e4 LT |
251 | u8 dmactl; |
252 | ||
253 | /* start host DMA transaction */ | |
254 | dmactl = readb(mmio + ATA_DMA_CMD); | |
255 | writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); | |
8a60a071 JG |
256 | /* There is a race condition in certain SATA controllers that can |
257 | be seen when the r/w command is given to the controller before the | |
1da177e4 LT |
258 | host DMA is started. On a Read command, the controller would initiate |
259 | the command to the drive even before it sees the DMA start. When there | |
8a60a071 | 260 | are very fast drives connected to the controller, or when the data request |
1da177e4 LT |
261 | hits in the drive cache, there is the possibility that the drive returns a part |
262 | or all of the requested data to the controller before the DMA start is issued. | |
263 | In this case, the controller would become confused as to what to do with the data. | |
264 | In the worst case when all the data is returned back to the controller, the | |
265 | controller could hang. In other cases it could return partial data returning | |
266 | in data corruption. This problem has been seen in PPC systems and can also appear | |
8a60a071 | 267 | on an system with very fast disks, where the SATA controller is sitting behind a |
1da177e4 LT |
268 | number of bridges, and hence there is significant latency between the r/w command |
269 | and the start command. */ | |
270 | /* issue r/w command if the access is to ATA*/ | |
271 | if (qc->tf.protocol == ATA_PROT_DMA) | |
272 | ap->ops->exec_command(ap, &qc->tf); | |
273 | } | |
274 | ||
8a60a071 | 275 | |
1da177e4 LT |
276 | static u8 k2_stat_check_status(struct ata_port *ap) |
277 | { | |
5796d1c4 | 278 | return readl(ap->ioaddr.status_addr); |
1da177e4 LT |
279 | } |
280 | ||
281 | #ifdef CONFIG_PPC_OF | |
282 | /* | |
283 | * k2_sata_proc_info | |
284 | * inout : decides on the direction of the dataflow and the meaning of the | |
285 | * variables | |
286 | * buffer: If inout==FALSE data is being written to it else read from it | |
287 | * *start: If inout==FALSE start of the valid data in the buffer | |
288 | * offset: If inout==FALSE offset from the beginning of the imaginary file | |
289 | * from which we start writing into the buffer | |
290 | * length: If inout==FALSE max number of bytes to be written into the buffer | |
291 | * else number of bytes in the buffer | |
292 | */ | |
293 | static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start, | |
294 | off_t offset, int count, int inout) | |
295 | { | |
296 | struct ata_port *ap; | |
297 | struct device_node *np; | |
298 | int len, index; | |
299 | ||
300 | /* Find the ata_port */ | |
35bb94b1 | 301 | ap = ata_shost_to_port(shost); |
1da177e4 LT |
302 | if (ap == NULL) |
303 | return 0; | |
304 | ||
305 | /* Find the OF node for the PCI device proper */ | |
cca3974e | 306 | np = pci_device_to_OF_node(to_pci_dev(ap->host->dev)); |
1da177e4 LT |
307 | if (np == NULL) |
308 | return 0; | |
309 | ||
310 | /* Match it to a port node */ | |
cca3974e | 311 | index = (ap == ap->host->ports[0]) ? 0 : 1; |
1da177e4 | 312 | for (np = np->child; np != NULL; np = np->sibling) { |
40cd3a45 | 313 | const u32 *reg = of_get_property(np, "reg", NULL); |
1da177e4 LT |
314 | if (!reg) |
315 | continue; | |
316 | if (index == *reg) | |
317 | break; | |
318 | } | |
319 | if (np == NULL) | |
320 | return 0; | |
321 | ||
322 | len = sprintf(page, "devspec: %s\n", np->full_name); | |
323 | ||
324 | return len; | |
325 | } | |
326 | #endif /* CONFIG_PPC_OF */ | |
327 | ||
328 | ||
193515d5 | 329 | static struct scsi_host_template k2_sata_sht = { |
1da177e4 LT |
330 | .module = THIS_MODULE, |
331 | .name = DRV_NAME, | |
332 | .ioctl = ata_scsi_ioctl, | |
333 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
334 | .can_queue = ATA_DEF_QUEUE, |
335 | .this_id = ATA_SHT_THIS_ID, | |
336 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
337 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
338 | .emulated = ATA_SHT_EMULATED, | |
339 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
340 | .proc_name = DRV_NAME, | |
341 | .dma_boundary = ATA_DMA_BOUNDARY, | |
342 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 343 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 LT |
344 | #ifdef CONFIG_PPC_OF |
345 | .proc_info = k2_sata_proc_info, | |
346 | #endif | |
347 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
348 | }; |
349 | ||
350 | ||
057ace5e | 351 | static const struct ata_port_operations k2_sata_ops = { |
1da177e4 LT |
352 | .tf_load = k2_sata_tf_load, |
353 | .tf_read = k2_sata_tf_read, | |
354 | .check_status = k2_stat_check_status, | |
355 | .exec_command = ata_exec_command, | |
356 | .dev_select = ata_std_dev_select, | |
c10340ac | 357 | .check_atapi_dma = k2_sata_check_atapi_dma, |
1da177e4 LT |
358 | .bmdma_setup = k2_bmdma_setup_mmio, |
359 | .bmdma_start = k2_bmdma_start_mmio, | |
360 | .bmdma_stop = ata_bmdma_stop, | |
361 | .bmdma_status = ata_bmdma_status, | |
362 | .qc_prep = ata_qc_prep, | |
363 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 364 | .data_xfer = ata_data_xfer, |
d7a80dad TH |
365 | .freeze = ata_bmdma_freeze, |
366 | .thaw = ata_bmdma_thaw, | |
367 | .error_handler = ata_bmdma_error_handler, | |
368 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
1da177e4 | 369 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 370 | .irq_on = ata_irq_on, |
1da177e4 LT |
371 | .scr_read = k2_sata_scr_read, |
372 | .scr_write = k2_sata_scr_write, | |
373 | .port_start = ata_port_start, | |
1da177e4 LT |
374 | }; |
375 | ||
4447d351 | 376 | static const struct ata_port_info k2_port_info[] = { |
931506d3 | 377 | /* chip_svw4 */ |
4447d351 TH |
378 | { |
379 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
380 | ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA, | |
381 | .pio_mask = 0x1f, | |
382 | .mwdma_mask = 0x07, | |
bf6263a8 | 383 | .udma_mask = ATA_UDMA6, |
4447d351 TH |
384 | .port_ops = &k2_sata_ops, |
385 | }, | |
931506d3 | 386 | /* chip_svw8 */ |
4447d351 TH |
387 | { |
388 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
389 | ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA | | |
390 | K2_FLAG_SATA_8_PORTS, | |
391 | .pio_mask = 0x1f, | |
392 | .mwdma_mask = 0x07, | |
bf6263a8 | 393 | .udma_mask = ATA_UDMA6, |
4447d351 TH |
394 | .port_ops = &k2_sata_ops, |
395 | }, | |
931506d3 AS |
396 | /* chip_svw42 */ |
397 | { | |
398 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
399 | ATA_FLAG_MMIO | K2_FLAG_BAR_POS_3, | |
400 | .pio_mask = 0x1f, | |
401 | .mwdma_mask = 0x07, | |
402 | .udma_mask = ATA_UDMA6, | |
403 | .port_ops = &k2_sata_ops, | |
404 | }, | |
405 | /* chip_svw43 */ | |
406 | { | |
407 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
408 | ATA_FLAG_MMIO, | |
409 | .pio_mask = 0x1f, | |
410 | .mwdma_mask = 0x07, | |
411 | .udma_mask = ATA_UDMA6, | |
412 | .port_ops = &k2_sata_ops, | |
413 | }, | |
4447d351 TH |
414 | }; |
415 | ||
0d5ff566 | 416 | static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) |
1da177e4 LT |
417 | { |
418 | port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; | |
419 | port->data_addr = base + K2_SATA_TF_DATA_OFFSET; | |
420 | port->feature_addr = | |
421 | port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; | |
422 | port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; | |
423 | port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; | |
424 | port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; | |
425 | port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; | |
426 | port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; | |
427 | port->command_addr = | |
428 | port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; | |
429 | port->altstatus_addr = | |
430 | port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; | |
431 | port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; | |
432 | port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; | |
433 | } | |
434 | ||
435 | ||
5796d1c4 | 436 | static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
437 | { |
438 | static int printed_version; | |
4447d351 TH |
439 | const struct ata_port_info *ppi[] = |
440 | { &k2_port_info[ent->driver_data], NULL }; | |
441 | struct ata_host *host; | |
ea6ba10b | 442 | void __iomem *mmio_base; |
931506d3 | 443 | int n_ports, i, rc, bar_pos; |
1da177e4 LT |
444 | |
445 | if (!printed_version++) | |
a9524a76 | 446 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 447 | |
4447d351 TH |
448 | /* allocate host */ |
449 | n_ports = 4; | |
450 | if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS) | |
451 | n_ports = 8; | |
452 | ||
453 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
454 | if (!host) | |
455 | return -ENOMEM; | |
456 | ||
931506d3 AS |
457 | bar_pos = 5; |
458 | if (ppi[0]->flags & K2_FLAG_BAR_POS_3) | |
459 | bar_pos = 3; | |
1da177e4 LT |
460 | /* |
461 | * If this driver happens to only be useful on Apple's K2, then | |
462 | * we should check that here as it has a normal Serverworks ID | |
463 | */ | |
24dc5f33 | 464 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
465 | if (rc) |
466 | return rc; | |
4447d351 | 467 | |
1da177e4 LT |
468 | /* |
469 | * Check if we have resources mapped at all (second function may | |
470 | * have been disabled by firmware) | |
471 | */ | |
931506d3 AS |
472 | if (pci_resource_len(pdev, bar_pos) == 0) { |
473 | /* In IDE mode we need to pin the device to ensure that | |
474 | pcim_release does not clear the busmaster bit in config | |
475 | space, clearing causes busmaster DMA to fail on | |
476 | ports 3 & 4 */ | |
477 | pcim_pin_device(pdev); | |
1da177e4 | 478 | return -ENODEV; |
931506d3 | 479 | } |
1da177e4 | 480 | |
0d5ff566 | 481 | /* Request and iomap PCI regions */ |
931506d3 | 482 | rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME); |
0d5ff566 | 483 | if (rc == -EBUSY) |
24dc5f33 | 484 | pcim_pin_device(pdev); |
0d5ff566 | 485 | if (rc) |
24dc5f33 | 486 | return rc; |
4447d351 | 487 | host->iomap = pcim_iomap_table(pdev); |
931506d3 | 488 | mmio_base = host->iomap[bar_pos]; |
4447d351 TH |
489 | |
490 | /* different controllers have different number of ports - currently 4 or 8 */ | |
491 | /* All ports are on the same function. Multi-function device is no | |
492 | * longer available. This should not be seen in any system. */ | |
cbcdd875 TH |
493 | for (i = 0; i < host->n_ports; i++) { |
494 | struct ata_port *ap = host->ports[i]; | |
495 | unsigned int offset = i * K2_SATA_PORT_OFFSET; | |
496 | ||
497 | k2_sata_setup_port(&ap->ioaddr, mmio_base + offset); | |
498 | ||
499 | ata_port_pbar_desc(ap, 5, -1, "mmio"); | |
500 | ata_port_pbar_desc(ap, 5, offset, "port"); | |
501 | } | |
1da177e4 LT |
502 | |
503 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
504 | if (rc) | |
24dc5f33 | 505 | return rc; |
1da177e4 LT |
506 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
507 | if (rc) | |
24dc5f33 | 508 | return rc; |
1da177e4 | 509 | |
0d5ff566 TH |
510 | /* Clear a magic bit in SCR1 according to Darwin, those help |
511 | * some funky seagate drives (though so far, those were already | |
512 | * set by the firmware on the machines I had access to) | |
513 | */ | |
514 | writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, | |
515 | mmio_base + K2_SATA_SICR1_OFFSET); | |
516 | ||
517 | /* Clear SATA error & interrupts we don't use */ | |
518 | writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); | |
519 | writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); | |
1da177e4 LT |
520 | |
521 | pci_set_master(pdev); | |
4447d351 TH |
522 | return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED, |
523 | &k2_sata_sht); | |
1da177e4 LT |
524 | } |
525 | ||
60bf09a3 NS |
526 | /* 0x240 is device ID for Apple K2 device |
527 | * 0x241 is device ID for Serverworks Frodo4 | |
528 | * 0x242 is device ID for Serverworks Frodo8 | |
529 | * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA | |
530 | * controller | |
531 | * */ | |
3b7d697d | 532 | static const struct pci_device_id k2_sata_pci_tbl[] = { |
931506d3 | 533 | { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 }, |
aeb74914 JG |
534 | { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 }, |
535 | { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 }, | |
931506d3 AS |
536 | { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 }, |
537 | { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 }, | |
538 | { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 }, | |
539 | { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 }, | |
2d2744fc | 540 | |
1da177e4 LT |
541 | { } |
542 | }; | |
543 | ||
1da177e4 LT |
544 | static struct pci_driver k2_sata_pci_driver = { |
545 | .name = DRV_NAME, | |
546 | .id_table = k2_sata_pci_tbl, | |
547 | .probe = k2_sata_init_one, | |
548 | .remove = ata_pci_remove_one, | |
549 | }; | |
550 | ||
1da177e4 LT |
551 | static int __init k2_sata_init(void) |
552 | { | |
b7887196 | 553 | return pci_register_driver(&k2_sata_pci_driver); |
1da177e4 LT |
554 | } |
555 | ||
1da177e4 LT |
556 | static void __exit k2_sata_exit(void) |
557 | { | |
558 | pci_unregister_driver(&k2_sata_pci_driver); | |
559 | } | |
560 | ||
1da177e4 LT |
561 | MODULE_AUTHOR("Benjamin Herrenschmidt"); |
562 | MODULE_DESCRIPTION("low-level driver for K2 SATA controller"); | |
563 | MODULE_LICENSE("GPL"); | |
564 | MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl); | |
565 | MODULE_VERSION(DRV_VERSION); | |
566 | ||
567 | module_init(k2_sata_init); | |
568 | module_exit(k2_sata_exit); |