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ata_piix: implement IOCFG bit18 quirk
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CommitLineData
1da177e4
LT
1/*
2 * sata_uli.c - ULi Electronics SATA
3 *
af36d7f0
JG
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 *
20 * libata documentation is available via 'make {ps|pdf}docs',
21 * as Documentation/DocBook/libata.*
22 *
23 * Hardware documentation available under NDA.
1da177e4
LT
24 *
25 */
26
1da177e4
LT
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/blkdev.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
a9524a76 34#include <linux/device.h>
1da177e4
LT
35#include <scsi/scsi_host.h>
36#include <linux/libata.h>
37
38#define DRV_NAME "sata_uli"
8bc3fc47 39#define DRV_VERSION "1.2"
1da177e4
LT
40
41enum {
42 uli_5289 = 0,
43 uli_5287 = 1,
44 uli_5281 = 2,
45
50106c5a
JG
46 uli_max_ports = 4,
47
1da177e4
LT
48 /* PCI configuration registers */
49 ULI5287_BASE = 0x90, /* sata0 phy SCR registers */
50 ULI5287_OFFS = 0x10, /* offset from sata0->sata1 phy regs */
51 ULI5281_BASE = 0x60, /* sata0 phy SCR registers */
52 ULI5281_OFFS = 0x60, /* offset from sata0->sata1 phy regs */
53};
54
50106c5a
JG
55struct uli_priv {
56 unsigned int scr_cfg_addr[uli_max_ports];
57};
58
1da177e4 59static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
da3dbb17
TH
60static int uli_scr_read (struct ata_port *ap, unsigned int sc_reg, u32 *val);
61static int uli_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
1da177e4 62
3b7d697d 63static const struct pci_device_id uli_pci_tbl[] = {
54bb3a94
JG
64 { PCI_VDEVICE(AL, 0x5289), uli_5289 },
65 { PCI_VDEVICE(AL, 0x5287), uli_5287 },
66 { PCI_VDEVICE(AL, 0x5281), uli_5281 },
67
1da177e4
LT
68 { } /* terminate list */
69};
70
1da177e4
LT
71static struct pci_driver uli_pci_driver = {
72 .name = DRV_NAME,
73 .id_table = uli_pci_tbl,
74 .probe = uli_init_one,
75 .remove = ata_pci_remove_one,
76};
77
193515d5 78static struct scsi_host_template uli_sht = {
1da177e4
LT
79 .module = THIS_MODULE,
80 .name = DRV_NAME,
81 .ioctl = ata_scsi_ioctl,
82 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT
83 .can_queue = ATA_DEF_QUEUE,
84 .this_id = ATA_SHT_THIS_ID,
85 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT
86 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
87 .emulated = ATA_SHT_EMULATED,
88 .use_clustering = ATA_SHT_USE_CLUSTERING,
89 .proc_name = DRV_NAME,
90 .dma_boundary = ATA_DMA_BOUNDARY,
91 .slave_configure = ata_scsi_slave_config,
ccf68c34 92 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 93 .bios_param = ata_std_bios_param,
1da177e4
LT
94};
95
057ace5e 96static const struct ata_port_operations uli_ops = {
1da177e4
LT
97 .port_disable = ata_port_disable,
98
99 .tf_load = ata_tf_load,
100 .tf_read = ata_tf_read,
101 .check_status = ata_check_status,
102 .exec_command = ata_exec_command,
103 .dev_select = ata_std_dev_select,
104
1da177e4
LT
105 .bmdma_setup = ata_bmdma_setup,
106 .bmdma_start = ata_bmdma_start,
107 .bmdma_stop = ata_bmdma_stop,
108 .bmdma_status = ata_bmdma_status,
109 .qc_prep = ata_qc_prep,
110 .qc_issue = ata_qc_issue_prot,
0d5ff566 111 .data_xfer = ata_data_xfer,
1da177e4 112
d7a80dad
TH
113 .freeze = ata_bmdma_freeze,
114 .thaw = ata_bmdma_thaw,
115 .error_handler = ata_bmdma_error_handler,
116 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4 117
1da177e4 118 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI
119 .irq_on = ata_irq_on,
120 .irq_ack = ata_irq_ack,
1da177e4
LT
121
122 .scr_read = uli_scr_read,
123 .scr_write = uli_scr_write,
124
125 .port_start = ata_port_start,
1da177e4
LT
126};
127
1626aeb8 128static const struct ata_port_info uli_port_info = {
b2a8bbe6
TH
129 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
130 ATA_FLAG_IGN_SIMPLEX,
7da79312 131 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 132 .udma_mask = ATA_UDMA6,
1da177e4
LT
133 .port_ops = &uli_ops,
134};
135
136
137MODULE_AUTHOR("Peer Chen");
138MODULE_DESCRIPTION("low-level driver for ULi Electronics SATA controller");
139MODULE_LICENSE("GPL");
140MODULE_DEVICE_TABLE(pci, uli_pci_tbl);
141MODULE_VERSION(DRV_VERSION);
142
143static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
144{
cca3974e 145 struct uli_priv *hpriv = ap->host->private_data;
50106c5a 146 return hpriv->scr_cfg_addr[ap->port_no] + (4 * sc_reg);
1da177e4
LT
147}
148
149static u32 uli_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
150{
cca3974e 151 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4
LT
152 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
153 u32 val;
154
155 pci_read_config_dword(pdev, cfg_addr, &val);
156 return val;
157}
158
159static void uli_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
160{
cca3974e 161 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4
LT
162 unsigned int cfg_addr = get_scr_cfg_addr(ap, scr);
163
164 pci_write_config_dword(pdev, cfg_addr, val);
165}
166
da3dbb17 167static int uli_scr_read (struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4
LT
168{
169 if (sc_reg > SCR_CONTROL)
da3dbb17 170 return -EINVAL;
1da177e4 171
da3dbb17
TH
172 *val = uli_scr_cfg_read(ap, sc_reg);
173 return 0;
1da177e4
LT
174}
175
da3dbb17 176static int uli_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
1da177e4
LT
177{
178 if (sc_reg > SCR_CONTROL) //SCR_CONTROL=2, SCR_ERROR=1, SCR_STATUS=0
da3dbb17 179 return -EINVAL;
1da177e4
LT
180
181 uli_scr_cfg_write(ap, sc_reg, val);
da3dbb17 182 return 0;
1da177e4
LT
183}
184
1da177e4
LT
185static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
186{
a9524a76 187 static int printed_version;
9a829ccf 188 const struct ata_port_info *ppi[] = { &uli_port_info, NULL };
1da177e4 189 unsigned int board_idx = (unsigned int) ent->driver_data;
9a829ccf 190 struct ata_host *host;
50106c5a 191 struct uli_priv *hpriv;
0d5ff566 192 void __iomem * const *iomap;
9a829ccf
TH
193 struct ata_ioports *ioaddr;
194 int n_ports, rc;
1da177e4 195
a9524a76
JG
196 if (!printed_version++)
197 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
198
24dc5f33 199 rc = pcim_enable_device(pdev);
1da177e4
LT
200 if (rc)
201 return rc;
202
9a829ccf
TH
203 n_ports = 2;
204 if (board_idx == uli_5287)
205 n_ports = 4;
1626aeb8
TH
206
207 /* allocate the host */
208 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
209 if (!host)
210 return -ENOMEM;
1da177e4 211
24dc5f33
TH
212 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
213 if (!hpriv)
214 return -ENOMEM;
9a829ccf 215 host->private_data = hpriv;
50106c5a 216
1626aeb8 217 /* the first two ports are standard SFF */
d583bc18 218 rc = ata_pci_init_sff_host(host);
1626aeb8
TH
219 if (rc)
220 return rc;
221
222 rc = ata_pci_init_bmdma(host);
223 if (rc)
224 return rc;
225
9a829ccf 226 iomap = host->iomap;
0d5ff566 227
1da177e4
LT
228 switch (board_idx) {
229 case uli_5287:
1626aeb8
TH
230 /* If there are four, the last two live right after
231 * the standard SFF ports.
232 */
50106c5a
JG
233 hpriv->scr_cfg_addr[0] = ULI5287_BASE;
234 hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
1da177e4 235
9a829ccf
TH
236 ioaddr = &host->ports[2]->ioaddr;
237 ioaddr->cmd_addr = iomap[0] + 8;
238 ioaddr->altstatus_addr =
239 ioaddr->ctl_addr = (void __iomem *)
0d5ff566 240 ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS) + 4;
9a829ccf 241 ioaddr->bmdma_addr = iomap[4] + 16;
50106c5a 242 hpriv->scr_cfg_addr[2] = ULI5287_BASE + ULI5287_OFFS*4;
9a829ccf 243 ata_std_ports(ioaddr);
1da177e4 244
9a829ccf
TH
245 ioaddr = &host->ports[3]->ioaddr;
246 ioaddr->cmd_addr = iomap[2] + 8;
247 ioaddr->altstatus_addr =
248 ioaddr->ctl_addr = (void __iomem *)
0d5ff566 249 ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS) + 4;
9a829ccf 250 ioaddr->bmdma_addr = iomap[4] + 24;
50106c5a 251 hpriv->scr_cfg_addr[3] = ULI5287_BASE + ULI5287_OFFS*5;
9a829ccf 252 ata_std_ports(ioaddr);
1da177e4
LT
253 break;
254
255 case uli_5289:
50106c5a
JG
256 hpriv->scr_cfg_addr[0] = ULI5287_BASE;
257 hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
1da177e4
LT
258 break;
259
260 case uli_5281:
50106c5a
JG
261 hpriv->scr_cfg_addr[0] = ULI5281_BASE;
262 hpriv->scr_cfg_addr[1] = ULI5281_BASE + ULI5281_OFFS;
1da177e4
LT
263 break;
264
265 default:
266 BUG();
267 break;
268 }
269
270 pci_set_master(pdev);
a04ce0ff 271 pci_intx(pdev, 1);
9a829ccf
TH
272 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
273 &uli_sht);
1da177e4
LT
274}
275
276static int __init uli_init(void)
277{
b7887196 278 return pci_register_driver(&uli_pci_driver);
1da177e4
LT
279}
280
281static void __exit uli_exit(void)
282{
283 pci_unregister_driver(&uli_pci_driver);
284}
285
286
287module_init(uli_init);
288module_exit(uli_exit);