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1da177e4 1/*
af36d7f0
JG
2 * sata_via.c - VIA Serial ATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
5796d1c4 6 * on emails.
af36d7f0
JG
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available under NDA.
31 *
32 *
af36d7f0 33 *
1da177e4
LT
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/blkdev.h>
41#include <linux/delay.h>
a9524a76 42#include <linux/device.h>
a55ab496
BH
43#include <scsi/scsi.h>
44#include <scsi/scsi_cmnd.h>
1da177e4
LT
45#include <scsi/scsi_host.h>
46#include <linux/libata.h>
1da177e4
LT
47
48#define DRV_NAME "sata_via"
a55ab496 49#define DRV_VERSION "2.6"
1da177e4 50
b9d5b89b
TH
51/*
52 * vt8251 is different from other sata controllers of VIA. It has two
53 * channels, each channel has both Master and Slave slot.
54 */
1da177e4
LT
55enum board_ids_enum {
56 vt6420,
57 vt6421,
b9d5b89b 58 vt8251,
1da177e4
LT
59};
60
61enum {
62 SATA_CHAN_ENAB = 0x40, /* SATA channel enable */
63 SATA_INT_GATE = 0x41, /* SATA interrupt gating */
64 SATA_NATIVE_MODE = 0x42, /* Native mode enable */
d73f30e1
AC
65 PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */
66 PATA_PIO_TIMING = 0xAB, /* PATA timing register */
a84471fe 67
1da177e4
LT
68 PORT0 = (1 << 1),
69 PORT1 = (1 << 0),
70 ALL_PORTS = PORT0 | PORT1,
1da177e4
LT
71
72 NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),
73
74 SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
1da177e4
LT
75};
76
5796d1c4 77static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82ef04fb
TH
78static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
79static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
b9d5b89b
TH
80static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val);
81static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val);
b78152e9 82static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf);
17234246 83static void svia_noop_freeze(struct ata_port *ap);
a1efdaba 84static int vt6420_prereset(struct ata_link *link, unsigned long deadline);
a55ab496 85static void vt6420_bmdma_start(struct ata_queued_cmd *qc);
a0fcdc02 86static int vt6421_pata_cable_detect(struct ata_port *ap);
d73f30e1
AC
87static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
88static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);
1da177e4 89
3b7d697d 90static const struct pci_device_id svia_pci_tbl[] = {
96bc103f 91 { PCI_VDEVICE(VIA, 0x5337), vt6420 },
b9d5b89b
TH
92 { PCI_VDEVICE(VIA, 0x0591), vt6420 }, /* 2 sata chnls (Master) */
93 { PCI_VDEVICE(VIA, 0x3149), vt6420 }, /* 2 sata chnls (Master) */
94 { PCI_VDEVICE(VIA, 0x3249), vt6421 }, /* 2 sata chnls, 1 pata chnl */
52df0ee0
JG
95 { PCI_VDEVICE(VIA, 0x5372), vt6420 },
96 { PCI_VDEVICE(VIA, 0x7372), vt6420 },
b9d5b89b 97 { PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */
68139520 98 { PCI_VDEVICE(VIA, 0x9000), vt8251 },
1da177e4
LT
99
100 { } /* terminate list */
101};
102
103static struct pci_driver svia_pci_driver = {
104 .name = DRV_NAME,
105 .id_table = svia_pci_tbl,
106 .probe = svia_init_one,
e1e143cf
TH
107#ifdef CONFIG_PM
108 .suspend = ata_pci_device_suspend,
109 .resume = ata_pci_device_resume,
110#endif
1da177e4
LT
111 .remove = ata_pci_remove_one,
112};
113
193515d5 114static struct scsi_host_template svia_sht = {
68d1d07b 115 ATA_BMDMA_SHT(DRV_NAME),
1da177e4
LT
116};
117
b78152e9 118static struct ata_port_operations svia_base_ops = {
029cfd6b 119 .inherits = &ata_bmdma_port_ops,
b78152e9
TH
120 .sff_tf_load = svia_tf_load,
121};
122
123static struct ata_port_operations vt6420_sata_ops = {
124 .inherits = &svia_base_ops,
17234246 125 .freeze = svia_noop_freeze,
a1efdaba 126 .prereset = vt6420_prereset,
a55ab496 127 .bmdma_start = vt6420_bmdma_start,
ac2164d5
TH
128};
129
029cfd6b 130static struct ata_port_operations vt6421_pata_ops = {
b78152e9 131 .inherits = &svia_base_ops,
029cfd6b 132 .cable_detect = vt6421_pata_cable_detect,
d73f30e1
AC
133 .set_piomode = vt6421_set_pio_mode,
134 .set_dmamode = vt6421_set_dma_mode,
d73f30e1
AC
135};
136
029cfd6b 137static struct ata_port_operations vt6421_sata_ops = {
b78152e9 138 .inherits = &svia_base_ops,
1da177e4
LT
139 .scr_read = svia_scr_read,
140 .scr_write = svia_scr_write,
1da177e4
LT
141};
142
b9d5b89b
TH
143static struct ata_port_operations vt8251_ops = {
144 .inherits = &svia_base_ops,
145 .hardreset = sata_std_hardreset,
146 .scr_read = vt8251_scr_read,
147 .scr_write = vt8251_scr_write,
148};
149
eca25dca 150static const struct ata_port_info vt6420_port_info = {
9cbe056f 151 .flags = ATA_FLAG_SATA,
14bdef98
EIB
152 .pio_mask = ATA_PIO4,
153 .mwdma_mask = ATA_MWDMA2,
bf6263a8 154 .udma_mask = ATA_UDMA6,
ac2164d5 155 .port_ops = &vt6420_sata_ops,
1da177e4
LT
156};
157
eca25dca 158static struct ata_port_info vt6421_sport_info = {
9cbe056f 159 .flags = ATA_FLAG_SATA,
14bdef98
EIB
160 .pio_mask = ATA_PIO4,
161 .mwdma_mask = ATA_MWDMA2,
bf6263a8 162 .udma_mask = ATA_UDMA6,
eca25dca
TH
163 .port_ops = &vt6421_sata_ops,
164};
165
166static struct ata_port_info vt6421_pport_info = {
9cbe056f 167 .flags = ATA_FLAG_SLAVE_POSS,
14bdef98
EIB
168 .pio_mask = ATA_PIO4,
169 /* No MWDMA */
bf6263a8 170 .udma_mask = ATA_UDMA6,
eca25dca
TH
171 .port_ops = &vt6421_pata_ops,
172};
173
b9d5b89b 174static struct ata_port_info vt8251_port_info = {
9cbe056f 175 .flags = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS,
14bdef98
EIB
176 .pio_mask = ATA_PIO4,
177 .mwdma_mask = ATA_MWDMA2,
b9d5b89b
TH
178 .udma_mask = ATA_UDMA6,
179 .port_ops = &vt8251_ops,
180};
181
1da177e4
LT
182MODULE_AUTHOR("Jeff Garzik");
183MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
184MODULE_LICENSE("GPL");
185MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
186MODULE_VERSION(DRV_VERSION);
187
82ef04fb 188static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
1da177e4
LT
189{
190 if (sc_reg > SCR_CONTROL)
da3dbb17 191 return -EINVAL;
82ef04fb 192 *val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg));
da3dbb17 193 return 0;
1da177e4
LT
194}
195
82ef04fb 196static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
1da177e4
LT
197{
198 if (sc_reg > SCR_CONTROL)
da3dbb17 199 return -EINVAL;
82ef04fb 200 iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg));
da3dbb17 201 return 0;
1da177e4
LT
202}
203
b9d5b89b
TH
204static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
205{
206 static const u8 ipm_tbl[] = { 1, 2, 6, 0 };
207 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
208 int slot = 2 * link->ap->port_no + link->pmp;
209 u32 v = 0;
210 u8 raw;
211
212 switch (scr) {
213 case SCR_STATUS:
214 pci_read_config_byte(pdev, 0xA0 + slot, &raw);
215
216 /* read the DET field, bit0 and 1 of the config byte */
217 v |= raw & 0x03;
218
219 /* read the SPD field, bit4 of the configure byte */
220 if (raw & (1 << 4))
221 v |= 0x02 << 4;
222 else
223 v |= 0x01 << 4;
224
225 /* read the IPM field, bit2 and 3 of the config byte */
226 v |= ipm_tbl[(raw >> 2) & 0x3];
227 break;
228
229 case SCR_ERROR:
230 /* devices other than 5287 uses 0xA8 as base */
231 WARN_ON(pdev->device != 0x5287);
232 pci_read_config_dword(pdev, 0xB0 + slot * 4, &v);
233 break;
234
235 case SCR_CONTROL:
236 pci_read_config_byte(pdev, 0xA4 + slot, &raw);
237
238 /* read the DET field, bit0 and bit1 */
239 v |= ((raw & 0x02) << 1) | (raw & 0x01);
240
241 /* read the IPM field, bit2 and bit3 */
242 v |= ((raw >> 2) & 0x03) << 8;
243 break;
244
245 default:
246 return -EINVAL;
247 }
248
249 *val = v;
250 return 0;
251}
252
253static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val)
254{
255 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
256 int slot = 2 * link->ap->port_no + link->pmp;
257 u32 v = 0;
258
259 switch (scr) {
260 case SCR_ERROR:
261 /* devices other than 5287 uses 0xA8 as base */
262 WARN_ON(pdev->device != 0x5287);
263 pci_write_config_dword(pdev, 0xB0 + slot * 4, val);
264 return 0;
265
266 case SCR_CONTROL:
267 /* set the DET field */
268 v |= ((val & 0x4) >> 1) | (val & 0x1);
269
270 /* set the IPM field */
271 v |= ((val >> 8) & 0x3) << 2;
272
273 pci_write_config_byte(pdev, 0xA4 + slot, v);
274 return 0;
275
276 default:
277 return -EINVAL;
278 }
279}
280
b78152e9
TH
281/**
282 * svia_tf_load - send taskfile registers to host controller
283 * @ap: Port to which output is sent
284 * @tf: ATA taskfile register set
285 *
286 * Outputs ATA taskfile to standard ATA host controller.
287 *
288 * This is to fix the internal bug of via chipsets, which will
289 * reset the device register after changing the IEN bit on ctl
290 * register.
291 */
292static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
293{
294 struct ata_taskfile ttf;
295
296 if (tf->ctl != ap->last_ctl) {
297 ttf = *tf;
298 ttf.flags |= ATA_TFLAG_DEVICE;
299 tf = &ttf;
300 }
301 ata_sff_tf_load(ap, tf);
302}
303
17234246
TH
304static void svia_noop_freeze(struct ata_port *ap)
305{
306 /* Some VIA controllers choke if ATA_NIEN is manipulated in
307 * certain way. Leave it alone and just clear pending IRQ.
308 */
5682ed33 309 ap->ops->sff_check_status(ap);
37f65b8b 310 ata_bmdma_irq_clear(ap);
17234246
TH
311}
312
ac2164d5
TH
313/**
314 * vt6420_prereset - prereset for vt6420
cc0680a5 315 * @link: target ATA link
d4b2bab4 316 * @deadline: deadline jiffies for the operation
ac2164d5
TH
317 *
318 * SCR registers on vt6420 are pieces of shit and may hang the
319 * whole machine completely if accessed with the wrong timing.
320 * To avoid such catastrophe, vt6420 doesn't provide generic SCR
321 * access operations, but uses SStatus and SControl only during
322 * boot probing in controlled way.
323 *
324 * As the old (pre EH update) probing code is proven to work, we
325 * strictly follow the access pattern.
326 *
327 * LOCKING:
328 * Kernel thread context (may sleep)
329 *
330 * RETURNS:
331 * 0 on success, -errno otherwise.
332 */
cc0680a5 333static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
ac2164d5 334{
cc0680a5 335 struct ata_port *ap = link->ap;
9af5c9c9 336 struct ata_eh_context *ehc = &ap->link.eh_context;
ac2164d5
TH
337 unsigned long timeout = jiffies + (HZ * 5);
338 u32 sstatus, scontrol;
339 int online;
340
341 /* don't do any SCR stuff if we're not loading */
68ff6e8e 342 if (!(ap->pflags & ATA_PFLAG_LOADING))
ac2164d5
TH
343 goto skip_scr;
344
a09060ff 345 /* Resume phy. This is the old SATA resume sequence */
82ef04fb
TH
346 svia_scr_write(link, SCR_CONTROL, 0x300);
347 svia_scr_read(link, SCR_CONTROL, &scontrol); /* flush */
ac2164d5
TH
348
349 /* wait for phy to become ready, if necessary */
350 do {
97750ceb 351 ata_msleep(link->ap, 200);
82ef04fb 352 svia_scr_read(link, SCR_STATUS, &sstatus);
da3dbb17 353 if ((sstatus & 0xf) != 1)
ac2164d5
TH
354 break;
355 } while (time_before(jiffies, timeout));
356
357 /* open code sata_print_link_status() */
82ef04fb
TH
358 svia_scr_read(link, SCR_STATUS, &sstatus);
359 svia_scr_read(link, SCR_CONTROL, &scontrol);
ac2164d5
TH
360
361 online = (sstatus & 0xf) == 0x3;
362
a9a79dfe
JP
363 ata_port_info(ap,
364 "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
365 online ? "up" : "down", sstatus, scontrol);
ac2164d5
TH
366
367 /* SStatus is read one more time */
82ef04fb 368 svia_scr_read(link, SCR_STATUS, &sstatus);
ac2164d5
TH
369
370 if (!online) {
371 /* tell EH to bail */
cf480626 372 ehc->i.action &= ~ATA_EH_RESET;
ac2164d5
TH
373 return 0;
374 }
375
376 skip_scr:
377 /* wait for !BSY */
705e76be 378 ata_sff_wait_ready(link, deadline);
ac2164d5
TH
379
380 return 0;
381}
382
a55ab496
BH
383static void vt6420_bmdma_start(struct ata_queued_cmd *qc)
384{
385 struct ata_port *ap = qc->ap;
386 if ((qc->tf.command == ATA_CMD_PACKET) &&
387 (qc->scsicmd->sc_data_direction == DMA_TO_DEVICE)) {
388 /* Prevents corruption on some ATAPI burners */
389 ata_sff_pause(ap);
390 }
391 ata_bmdma_start(qc);
392}
393
a0fcdc02 394static int vt6421_pata_cable_detect(struct ata_port *ap)
d73f30e1
AC
395{
396 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
397 u8 tmp;
398
399 pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
400 if (tmp & 0x10)
a0fcdc02
JG
401 return ATA_CBL_PATA40;
402 return ATA_CBL_PATA80;
d73f30e1
AC
403}
404
405static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
406{
407 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
408 static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
02d1d616
BH
409 pci_write_config_byte(pdev, PATA_PIO_TIMING - adev->devno,
410 pio_bits[adev->pio_mode - XFER_PIO_0]);
d73f30e1
AC
411}
412
413static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
414{
415 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
416 static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
02d1d616
BH
417 pci_write_config_byte(pdev, PATA_UDMA_TIMING - adev->devno,
418 udma_bits[adev->dma_mode - XFER_UDMA_0]);
d73f30e1
AC
419}
420
1da177e4
LT
421static const unsigned int svia_bar_sizes[] = {
422 8, 4, 8, 4, 16, 256
423};
424
425static const unsigned int vt6421_bar_sizes[] = {
426 16, 16, 16, 16, 32, 128
427};
428
5796d1c4 429static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port)
1da177e4
LT
430{
431 return addr + (port * 128);
432}
433
5796d1c4 434static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port)
1da177e4
LT
435{
436 return addr + (port * 64);
437}
438
eca25dca 439static void vt6421_init_addrs(struct ata_port *ap)
1da177e4 440{
eca25dca
TH
441 void __iomem * const * iomap = ap->host->iomap;
442 void __iomem *reg_addr = iomap[ap->port_no];
443 void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8);
444 struct ata_ioports *ioaddr = &ap->ioaddr;
445
446 ioaddr->cmd_addr = reg_addr;
447 ioaddr->altstatus_addr =
448 ioaddr->ctl_addr = (void __iomem *)
0d5ff566 449 ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
eca25dca
TH
450 ioaddr->bmdma_addr = bmdma_addr;
451 ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);
1da177e4 452
9363c382 453 ata_sff_std_ports(ioaddr);
cbcdd875
TH
454
455 ata_port_pbar_desc(ap, ap->port_no, -1, "port");
456 ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma");
1da177e4
LT
457}
458
eca25dca 459static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
1da177e4 460{
eca25dca
TH
461 const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
462 struct ata_host *host;
463 int rc;
f20b16ff 464
1c5afdf7 465 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
eca25dca
TH
466 if (rc)
467 return rc;
468 *r_host = host;
1da177e4 469
eca25dca
TH
470 rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
471 if (rc) {
a44fec1f 472 dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
eca25dca 473 return rc;
e1be5d73
TH
474 }
475
eca25dca
TH
476 host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
477 host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);
1da177e4 478
eca25dca 479 return 0;
1da177e4
LT
480}
481
eca25dca 482static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
1da177e4 483{
eca25dca
TH
484 const struct ata_port_info *ppi[] =
485 { &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
486 struct ata_host *host;
487 int i, rc;
488
489 *r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
490 if (!host) {
a44fec1f 491 dev_err(&pdev->dev, "failed to allocate host\n");
eca25dca
TH
492 return -ENOMEM;
493 }
1da177e4 494
8fd7d1b1 495 rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
eca25dca 496 if (rc) {
a44fec1f
JP
497 dev_err(&pdev->dev, "failed to request/iomap PCI BARs (errno=%d)\n",
498 rc);
eca25dca
TH
499 return rc;
500 }
501 host->iomap = pcim_iomap_table(pdev);
e1be5d73 502
eca25dca
TH
503 for (i = 0; i < host->n_ports; i++)
504 vt6421_init_addrs(host->ports[i]);
1da177e4 505
eca25dca
TH
506 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
507 if (rc)
508 return rc;
509 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
510 if (rc)
511 return rc;
512
513 return 0;
1da177e4
LT
514}
515
b9d5b89b
TH
516static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
517{
518 const struct ata_port_info *ppi[] = { &vt8251_port_info, NULL };
519 struct ata_host *host;
520 int i, rc;
521
1c5afdf7 522 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
b9d5b89b
TH
523 if (rc)
524 return rc;
525 *r_host = host;
526
527 rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
528 if (rc) {
a44fec1f 529 dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
b9d5b89b
TH
530 return rc;
531 }
532
533 /* 8251 hosts four sata ports as M/S of the two channels */
534 for (i = 0; i < host->n_ports; i++)
535 ata_slave_link_init(host->ports[i]);
536
537 return 0;
538}
539
b1353e4f 540static void svia_configure(struct pci_dev *pdev, int board_id)
1da177e4
LT
541{
542 u8 tmp8;
543
544 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
a44fec1f
JP
545 dev_info(&pdev->dev, "routed to hard irq line %d\n",
546 (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
1da177e4
LT
547
548 /* make sure SATA channels are enabled */
549 pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
550 if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
5b933e63
JP
551 dev_dbg(&pdev->dev, "enabling SATA channels (0x%x)\n",
552 (int)tmp8);
1da177e4
LT
553 tmp8 |= ALL_PORTS;
554 pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
555 }
556
557 /* make sure interrupts for each channel sent to us */
558 pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
559 if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
5b933e63
JP
560 dev_dbg(&pdev->dev, "enabling SATA channel interrupts (0x%x)\n",
561 (int) tmp8);
1da177e4
LT
562 tmp8 |= ALL_PORTS;
563 pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
564 }
565
566 /* make sure native mode is enabled */
567 pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
568 if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
5b933e63
JP
569 dev_dbg(&pdev->dev,
570 "enabling SATA channel native mode (0x%x)\n",
571 (int) tmp8);
1da177e4
LT
572 tmp8 |= NATIVE_MODE_ALL;
573 pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
574 }
8b27ff4c
TH
575
576 /*
b1353e4f 577 * vt6420/1 has problems talking to some drives. The following
b475a3b8
TH
578 * is the fix from Joseph Chan <JosephChan@via.com.tw>.
579 *
580 * When host issues HOLD, device may send up to 20DW of data
581 * before acknowledging it with HOLDA and the host should be
582 * able to buffer them in FIFO. Unfortunately, some WD drives
25985edc 583 * send up to 40DW before acknowledging HOLD and, in the
b475a3b8
TH
584 * default configuration, this ends up overflowing vt6421's
585 * FIFO, making the controller abort the transaction with
586 * R_ERR.
587 *
588 * Rx52[2] is the internal 128DW FIFO Flow control watermark
589 * adjusting mechanism enable bit and the default value 0
590 * means host will issue HOLD to device when the left FIFO
591 * size goes below 32DW. Setting it to 1 makes the watermark
592 * 64DW.
8b27ff4c
TH
593 *
594 * https://bugzilla.kernel.org/show_bug.cgi?id=15173
b475a3b8 595 * http://article.gmane.org/gmane.linux.ide/46352
b1353e4f 596 * http://thread.gmane.org/gmane.linux.kernel/1062139
8b27ff4c 597 */
b1353e4f 598 if (board_id == vt6420 || board_id == vt6421) {
8b27ff4c
TH
599 pci_read_config_byte(pdev, 0x52, &tmp8);
600 tmp8 |= 1 << 2;
601 pci_write_config_byte(pdev, 0x52, tmp8);
602 }
1da177e4
LT
603}
604
5796d1c4 605static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 606{
1da177e4
LT
607 unsigned int i;
608 int rc;
f1c22943 609 struct ata_host *host = NULL;
1da177e4 610 int board_id = (int) ent->driver_data;
b4482a4b 611 const unsigned *bar_sizes;
1da177e4 612
06296a1e 613 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 614
24dc5f33 615 rc = pcim_enable_device(pdev);
1da177e4
LT
616 if (rc)
617 return rc;
618
b9d5b89b 619 if (board_id == vt6421)
1da177e4 620 bar_sizes = &vt6421_bar_sizes[0];
b9d5b89b
TH
621 else
622 bar_sizes = &svia_bar_sizes[0];
1da177e4
LT
623
624 for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
625 if ((pci_resource_start(pdev, i) == 0) ||
626 (pci_resource_len(pdev, i) < bar_sizes[i])) {
a44fec1f 627 dev_err(&pdev->dev,
e29419ff
GKH
628 "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
629 i,
5796d1c4
JG
630 (unsigned long long)pci_resource_start(pdev, i),
631 (unsigned long long)pci_resource_len(pdev, i));
24dc5f33 632 return -ENODEV;
1da177e4
LT
633 }
634
b9d5b89b
TH
635 switch (board_id) {
636 case vt6420:
eca25dca 637 rc = vt6420_prepare_host(pdev, &host);
b9d5b89b
TH
638 break;
639 case vt6421:
eca25dca 640 rc = vt6421_prepare_host(pdev, &host);
b9d5b89b
TH
641 break;
642 case vt8251:
643 rc = vt8251_prepare_host(pdev, &host);
644 break;
645 default:
554d491d 646 rc = -EINVAL;
b9d5b89b 647 }
554d491d
MS
648 if (rc)
649 return rc;
1da177e4 650
b1353e4f 651 svia_configure(pdev, board_id);
1da177e4
LT
652
653 pci_set_master(pdev);
c3b28894 654 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
9363c382 655 IRQF_SHARED, &svia_sht);
1da177e4
LT
656}
657
2fc75da0 658module_pci_driver(svia_pci_driver);