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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * sata_via.c - VIA Serial ATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
1da177e4 | 6 | on emails. |
af36d7f0 JG |
7 | * |
8 | * Copyright 2003-2004 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2004 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available under NDA. | |
31 | * | |
32 | * | |
33 | * To-do list: | |
34 | * - VT6421 PATA support | |
35 | * | |
1da177e4 LT |
36 | */ |
37 | ||
38 | #include <linux/kernel.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/pci.h> | |
41 | #include <linux/init.h> | |
42 | #include <linux/blkdev.h> | |
43 | #include <linux/delay.h> | |
a9524a76 | 44 | #include <linux/device.h> |
1da177e4 LT |
45 | #include <scsi/scsi_host.h> |
46 | #include <linux/libata.h> | |
1da177e4 LT |
47 | |
48 | #define DRV_NAME "sata_via" | |
2a3103ce | 49 | #define DRV_VERSION "2.3" |
1da177e4 LT |
50 | |
51 | enum board_ids_enum { | |
52 | vt6420, | |
53 | vt6421, | |
54 | }; | |
55 | ||
56 | enum { | |
57 | SATA_CHAN_ENAB = 0x40, /* SATA channel enable */ | |
58 | SATA_INT_GATE = 0x41, /* SATA interrupt gating */ | |
59 | SATA_NATIVE_MODE = 0x42, /* Native mode enable */ | |
60 | SATA_PATA_SHARING = 0x49, /* PATA/SATA sharing func ctrl */ | |
d73f30e1 AC |
61 | PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */ |
62 | PATA_PIO_TIMING = 0xAB, /* PATA timing register */ | |
a84471fe | 63 | |
1da177e4 LT |
64 | PORT0 = (1 << 1), |
65 | PORT1 = (1 << 0), | |
66 | ALL_PORTS = PORT0 | PORT1, | |
1da177e4 LT |
67 | |
68 | NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4), | |
69 | ||
70 | SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */ | |
71 | SATA_2DEV = (1 << 5), /* SATA is master/slave */ | |
72 | }; | |
73 | ||
74 | static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
da3dbb17 TH |
75 | static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
76 | static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
17234246 | 77 | static void svia_noop_freeze(struct ata_port *ap); |
ac2164d5 | 78 | static void vt6420_error_handler(struct ata_port *ap); |
a0fcdc02 | 79 | static int vt6421_pata_cable_detect(struct ata_port *ap); |
d73f30e1 AC |
80 | static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev); |
81 | static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev); | |
1da177e4 | 82 | |
3b7d697d | 83 | static const struct pci_device_id svia_pci_tbl[] = { |
96bc103f | 84 | { PCI_VDEVICE(VIA, 0x5337), vt6420 }, |
2d2744fc JG |
85 | { PCI_VDEVICE(VIA, 0x0591), vt6420 }, |
86 | { PCI_VDEVICE(VIA, 0x3149), vt6420 }, | |
87 | { PCI_VDEVICE(VIA, 0x3249), vt6421 }, | |
52df0ee0 JG |
88 | { PCI_VDEVICE(VIA, 0x5287), vt6420 }, |
89 | { PCI_VDEVICE(VIA, 0x5372), vt6420 }, | |
90 | { PCI_VDEVICE(VIA, 0x7372), vt6420 }, | |
1da177e4 LT |
91 | |
92 | { } /* terminate list */ | |
93 | }; | |
94 | ||
95 | static struct pci_driver svia_pci_driver = { | |
96 | .name = DRV_NAME, | |
97 | .id_table = svia_pci_tbl, | |
98 | .probe = svia_init_one, | |
e1e143cf TH |
99 | #ifdef CONFIG_PM |
100 | .suspend = ata_pci_device_suspend, | |
101 | .resume = ata_pci_device_resume, | |
102 | #endif | |
1da177e4 LT |
103 | .remove = ata_pci_remove_one, |
104 | }; | |
105 | ||
193515d5 | 106 | static struct scsi_host_template svia_sht = { |
1da177e4 LT |
107 | .module = THIS_MODULE, |
108 | .name = DRV_NAME, | |
109 | .ioctl = ata_scsi_ioctl, | |
110 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
111 | .can_queue = ATA_DEF_QUEUE, |
112 | .this_id = ATA_SHT_THIS_ID, | |
113 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
114 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
115 | .emulated = ATA_SHT_EMULATED, | |
116 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
117 | .proc_name = DRV_NAME, | |
118 | .dma_boundary = ATA_DMA_BOUNDARY, | |
119 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 120 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 121 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
122 | }; |
123 | ||
ac2164d5 | 124 | static const struct ata_port_operations vt6420_sata_ops = { |
ac2164d5 TH |
125 | .tf_load = ata_tf_load, |
126 | .tf_read = ata_tf_read, | |
127 | .check_status = ata_check_status, | |
128 | .exec_command = ata_exec_command, | |
129 | .dev_select = ata_std_dev_select, | |
130 | ||
131 | .bmdma_setup = ata_bmdma_setup, | |
132 | .bmdma_start = ata_bmdma_start, | |
133 | .bmdma_stop = ata_bmdma_stop, | |
134 | .bmdma_status = ata_bmdma_status, | |
135 | ||
136 | .qc_prep = ata_qc_prep, | |
137 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 138 | .data_xfer = ata_data_xfer, |
ac2164d5 | 139 | |
17234246 | 140 | .freeze = svia_noop_freeze, |
ac2164d5 TH |
141 | .thaw = ata_bmdma_thaw, |
142 | .error_handler = vt6420_error_handler, | |
143 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
144 | ||
ac2164d5 | 145 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 146 | .irq_on = ata_irq_on, |
ac2164d5 TH |
147 | |
148 | .port_start = ata_port_start, | |
ac2164d5 TH |
149 | }; |
150 | ||
d73f30e1 | 151 | static const struct ata_port_operations vt6421_pata_ops = { |
d73f30e1 AC |
152 | .set_piomode = vt6421_set_pio_mode, |
153 | .set_dmamode = vt6421_set_dma_mode, | |
154 | ||
155 | .tf_load = ata_tf_load, | |
156 | .tf_read = ata_tf_read, | |
157 | .check_status = ata_check_status, | |
158 | .exec_command = ata_exec_command, | |
159 | .dev_select = ata_std_dev_select, | |
160 | ||
161 | .bmdma_setup = ata_bmdma_setup, | |
162 | .bmdma_start = ata_bmdma_start, | |
163 | .bmdma_stop = ata_bmdma_stop, | |
164 | .bmdma_status = ata_bmdma_status, | |
165 | ||
166 | .qc_prep = ata_qc_prep, | |
167 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 168 | .data_xfer = ata_data_xfer, |
d73f30e1 AC |
169 | |
170 | .freeze = ata_bmdma_freeze, | |
171 | .thaw = ata_bmdma_thaw, | |
a0fcdc02 | 172 | .error_handler = ata_bmdma_error_handler, |
d73f30e1 | 173 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a0fcdc02 | 174 | .cable_detect = vt6421_pata_cable_detect, |
1da177e4 | 175 | |
d73f30e1 | 176 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 177 | .irq_on = ata_irq_on, |
d73f30e1 | 178 | |
eca25dca | 179 | .port_start = ata_port_start, |
d73f30e1 AC |
180 | }; |
181 | ||
182 | static const struct ata_port_operations vt6421_sata_ops = { | |
1da177e4 LT |
183 | .tf_load = ata_tf_load, |
184 | .tf_read = ata_tf_read, | |
185 | .check_status = ata_check_status, | |
186 | .exec_command = ata_exec_command, | |
187 | .dev_select = ata_std_dev_select, | |
188 | ||
1da177e4 LT |
189 | .bmdma_setup = ata_bmdma_setup, |
190 | .bmdma_start = ata_bmdma_start, | |
191 | .bmdma_stop = ata_bmdma_stop, | |
192 | .bmdma_status = ata_bmdma_status, | |
193 | ||
194 | .qc_prep = ata_qc_prep, | |
195 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 196 | .data_xfer = ata_data_xfer, |
1da177e4 | 197 | |
40ef1d8d TH |
198 | .freeze = ata_bmdma_freeze, |
199 | .thaw = ata_bmdma_thaw, | |
a0fcdc02 | 200 | .error_handler = ata_bmdma_error_handler, |
40ef1d8d | 201 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a0fcdc02 | 202 | .cable_detect = ata_cable_sata, |
1da177e4 | 203 | |
1da177e4 | 204 | .irq_clear = ata_bmdma_irq_clear, |
246ce3b6 | 205 | .irq_on = ata_irq_on, |
1da177e4 LT |
206 | |
207 | .scr_read = svia_scr_read, | |
208 | .scr_write = svia_scr_write, | |
209 | ||
eca25dca | 210 | .port_start = ata_port_start, |
1da177e4 LT |
211 | }; |
212 | ||
eca25dca | 213 | static const struct ata_port_info vt6420_port_info = { |
cca3974e | 214 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
1da177e4 LT |
215 | .pio_mask = 0x1f, |
216 | .mwdma_mask = 0x07, | |
bf6263a8 | 217 | .udma_mask = ATA_UDMA6, |
ac2164d5 | 218 | .port_ops = &vt6420_sata_ops, |
1da177e4 LT |
219 | }; |
220 | ||
eca25dca TH |
221 | static struct ata_port_info vt6421_sport_info = { |
222 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, | |
223 | .pio_mask = 0x1f, | |
224 | .mwdma_mask = 0x07, | |
bf6263a8 | 225 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
226 | .port_ops = &vt6421_sata_ops, |
227 | }; | |
228 | ||
229 | static struct ata_port_info vt6421_pport_info = { | |
230 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_LEGACY, | |
231 | .pio_mask = 0x1f, | |
232 | .mwdma_mask = 0, | |
bf6263a8 | 233 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
234 | .port_ops = &vt6421_pata_ops, |
235 | }; | |
236 | ||
1da177e4 LT |
237 | MODULE_AUTHOR("Jeff Garzik"); |
238 | MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers"); | |
239 | MODULE_LICENSE("GPL"); | |
240 | MODULE_DEVICE_TABLE(pci, svia_pci_tbl); | |
241 | MODULE_VERSION(DRV_VERSION); | |
242 | ||
da3dbb17 | 243 | static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 LT |
244 | { |
245 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 TH |
246 | return -EINVAL; |
247 | *val = ioread32(ap->ioaddr.scr_addr + (4 * sc_reg)); | |
248 | return 0; | |
1da177e4 LT |
249 | } |
250 | ||
da3dbb17 | 251 | static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 LT |
252 | { |
253 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 | 254 | return -EINVAL; |
0d5ff566 | 255 | iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg)); |
da3dbb17 | 256 | return 0; |
1da177e4 LT |
257 | } |
258 | ||
17234246 TH |
259 | static void svia_noop_freeze(struct ata_port *ap) |
260 | { | |
261 | /* Some VIA controllers choke if ATA_NIEN is manipulated in | |
262 | * certain way. Leave it alone and just clear pending IRQ. | |
263 | */ | |
264 | ata_chk_status(ap); | |
d0259872 | 265 | ata_bmdma_irq_clear(ap); |
17234246 TH |
266 | } |
267 | ||
ac2164d5 TH |
268 | /** |
269 | * vt6420_prereset - prereset for vt6420 | |
cc0680a5 | 270 | * @link: target ATA link |
d4b2bab4 | 271 | * @deadline: deadline jiffies for the operation |
ac2164d5 TH |
272 | * |
273 | * SCR registers on vt6420 are pieces of shit and may hang the | |
274 | * whole machine completely if accessed with the wrong timing. | |
275 | * To avoid such catastrophe, vt6420 doesn't provide generic SCR | |
276 | * access operations, but uses SStatus and SControl only during | |
277 | * boot probing in controlled way. | |
278 | * | |
279 | * As the old (pre EH update) probing code is proven to work, we | |
280 | * strictly follow the access pattern. | |
281 | * | |
282 | * LOCKING: | |
283 | * Kernel thread context (may sleep) | |
284 | * | |
285 | * RETURNS: | |
286 | * 0 on success, -errno otherwise. | |
287 | */ | |
cc0680a5 | 288 | static int vt6420_prereset(struct ata_link *link, unsigned long deadline) |
ac2164d5 | 289 | { |
cc0680a5 | 290 | struct ata_port *ap = link->ap; |
9af5c9c9 | 291 | struct ata_eh_context *ehc = &ap->link.eh_context; |
ac2164d5 TH |
292 | unsigned long timeout = jiffies + (HZ * 5); |
293 | u32 sstatus, scontrol; | |
294 | int online; | |
295 | ||
296 | /* don't do any SCR stuff if we're not loading */ | |
68ff6e8e | 297 | if (!(ap->pflags & ATA_PFLAG_LOADING)) |
ac2164d5 TH |
298 | goto skip_scr; |
299 | ||
a09060ff | 300 | /* Resume phy. This is the old SATA resume sequence */ |
ac2164d5 | 301 | svia_scr_write(ap, SCR_CONTROL, 0x300); |
da3dbb17 | 302 | svia_scr_read(ap, SCR_CONTROL, &scontrol); /* flush */ |
ac2164d5 TH |
303 | |
304 | /* wait for phy to become ready, if necessary */ | |
305 | do { | |
306 | msleep(200); | |
da3dbb17 TH |
307 | svia_scr_read(ap, SCR_STATUS, &sstatus); |
308 | if ((sstatus & 0xf) != 1) | |
ac2164d5 TH |
309 | break; |
310 | } while (time_before(jiffies, timeout)); | |
311 | ||
312 | /* open code sata_print_link_status() */ | |
da3dbb17 TH |
313 | svia_scr_read(ap, SCR_STATUS, &sstatus); |
314 | svia_scr_read(ap, SCR_CONTROL, &scontrol); | |
ac2164d5 TH |
315 | |
316 | online = (sstatus & 0xf) == 0x3; | |
317 | ||
318 | ata_port_printk(ap, KERN_INFO, | |
319 | "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n", | |
320 | online ? "up" : "down", sstatus, scontrol); | |
321 | ||
322 | /* SStatus is read one more time */ | |
da3dbb17 | 323 | svia_scr_read(ap, SCR_STATUS, &sstatus); |
ac2164d5 TH |
324 | |
325 | if (!online) { | |
326 | /* tell EH to bail */ | |
327 | ehc->i.action &= ~ATA_EH_RESET_MASK; | |
328 | return 0; | |
329 | } | |
330 | ||
331 | skip_scr: | |
332 | /* wait for !BSY */ | |
d4b2bab4 | 333 | ata_wait_ready(ap, deadline); |
ac2164d5 TH |
334 | |
335 | return 0; | |
336 | } | |
337 | ||
338 | static void vt6420_error_handler(struct ata_port *ap) | |
339 | { | |
340 | return ata_bmdma_drive_eh(ap, vt6420_prereset, ata_std_softreset, | |
341 | NULL, ata_std_postreset); | |
342 | } | |
343 | ||
a0fcdc02 | 344 | static int vt6421_pata_cable_detect(struct ata_port *ap) |
d73f30e1 AC |
345 | { |
346 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
347 | u8 tmp; | |
348 | ||
349 | pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp); | |
350 | if (tmp & 0x10) | |
a0fcdc02 JG |
351 | return ATA_CBL_PATA40; |
352 | return ATA_CBL_PATA80; | |
d73f30e1 AC |
353 | } |
354 | ||
355 | static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev) | |
356 | { | |
357 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
358 | static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 }; | |
359 | pci_write_config_byte(pdev, PATA_PIO_TIMING, pio_bits[adev->pio_mode - XFER_PIO_0]); | |
360 | } | |
361 | ||
362 | static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev) | |
363 | { | |
364 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
365 | static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 }; | |
b4154d4a | 366 | pci_write_config_byte(pdev, PATA_UDMA_TIMING, udma_bits[adev->dma_mode - XFER_UDMA_0]); |
d73f30e1 AC |
367 | } |
368 | ||
1da177e4 LT |
369 | static const unsigned int svia_bar_sizes[] = { |
370 | 8, 4, 8, 4, 16, 256 | |
371 | }; | |
372 | ||
373 | static const unsigned int vt6421_bar_sizes[] = { | |
374 | 16, 16, 16, 16, 32, 128 | |
375 | }; | |
376 | ||
0d5ff566 | 377 | static void __iomem * svia_scr_addr(void __iomem *addr, unsigned int port) |
1da177e4 LT |
378 | { |
379 | return addr + (port * 128); | |
380 | } | |
381 | ||
0d5ff566 | 382 | static void __iomem * vt6421_scr_addr(void __iomem *addr, unsigned int port) |
1da177e4 LT |
383 | { |
384 | return addr + (port * 64); | |
385 | } | |
386 | ||
eca25dca | 387 | static void vt6421_init_addrs(struct ata_port *ap) |
1da177e4 | 388 | { |
eca25dca TH |
389 | void __iomem * const * iomap = ap->host->iomap; |
390 | void __iomem *reg_addr = iomap[ap->port_no]; | |
391 | void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8); | |
392 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
393 | ||
394 | ioaddr->cmd_addr = reg_addr; | |
395 | ioaddr->altstatus_addr = | |
396 | ioaddr->ctl_addr = (void __iomem *) | |
0d5ff566 | 397 | ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS); |
eca25dca TH |
398 | ioaddr->bmdma_addr = bmdma_addr; |
399 | ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no); | |
1da177e4 | 400 | |
eca25dca | 401 | ata_std_ports(ioaddr); |
1da177e4 LT |
402 | } |
403 | ||
eca25dca | 404 | static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) |
1da177e4 | 405 | { |
eca25dca TH |
406 | const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL }; |
407 | struct ata_host *host; | |
408 | int rc; | |
f20b16ff | 409 | |
d583bc18 | 410 | rc = ata_pci_prepare_sff_host(pdev, ppi, &host); |
eca25dca TH |
411 | if (rc) |
412 | return rc; | |
413 | *r_host = host; | |
1da177e4 | 414 | |
eca25dca TH |
415 | rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME); |
416 | if (rc) { | |
e1be5d73 | 417 | dev_printk(KERN_ERR, &pdev->dev, "failed to iomap PCI BAR 5\n"); |
eca25dca | 418 | return rc; |
e1be5d73 TH |
419 | } |
420 | ||
eca25dca TH |
421 | host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0); |
422 | host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1); | |
1da177e4 | 423 | |
eca25dca | 424 | return 0; |
1da177e4 LT |
425 | } |
426 | ||
eca25dca | 427 | static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) |
1da177e4 | 428 | { |
eca25dca TH |
429 | const struct ata_port_info *ppi[] = |
430 | { &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info }; | |
431 | struct ata_host *host; | |
432 | int i, rc; | |
433 | ||
434 | *r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi)); | |
435 | if (!host) { | |
436 | dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); | |
437 | return -ENOMEM; | |
438 | } | |
1da177e4 | 439 | |
8fd7d1b1 | 440 | rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME); |
eca25dca TH |
441 | if (rc) { |
442 | dev_printk(KERN_ERR, &pdev->dev, "failed to request/iomap " | |
443 | "PCI BARs (errno=%d)\n", rc); | |
444 | return rc; | |
445 | } | |
446 | host->iomap = pcim_iomap_table(pdev); | |
e1be5d73 | 447 | |
eca25dca TH |
448 | for (i = 0; i < host->n_ports; i++) |
449 | vt6421_init_addrs(host->ports[i]); | |
1da177e4 | 450 | |
eca25dca TH |
451 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
452 | if (rc) | |
453 | return rc; | |
454 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
455 | if (rc) | |
456 | return rc; | |
457 | ||
458 | return 0; | |
1da177e4 LT |
459 | } |
460 | ||
461 | static void svia_configure(struct pci_dev *pdev) | |
462 | { | |
463 | u8 tmp8; | |
464 | ||
465 | pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8); | |
a9524a76 | 466 | dev_printk(KERN_INFO, &pdev->dev, "routed to hard irq line %d\n", |
1da177e4 LT |
467 | (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f); |
468 | ||
469 | /* make sure SATA channels are enabled */ | |
470 | pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8); | |
471 | if ((tmp8 & ALL_PORTS) != ALL_PORTS) { | |
a9524a76 JG |
472 | dev_printk(KERN_DEBUG, &pdev->dev, |
473 | "enabling SATA channels (0x%x)\n", | |
474 | (int) tmp8); | |
1da177e4 LT |
475 | tmp8 |= ALL_PORTS; |
476 | pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8); | |
477 | } | |
478 | ||
479 | /* make sure interrupts for each channel sent to us */ | |
480 | pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8); | |
481 | if ((tmp8 & ALL_PORTS) != ALL_PORTS) { | |
a9524a76 JG |
482 | dev_printk(KERN_DEBUG, &pdev->dev, |
483 | "enabling SATA channel interrupts (0x%x)\n", | |
484 | (int) tmp8); | |
1da177e4 LT |
485 | tmp8 |= ALL_PORTS; |
486 | pci_write_config_byte(pdev, SATA_INT_GATE, tmp8); | |
487 | } | |
488 | ||
489 | /* make sure native mode is enabled */ | |
490 | pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8); | |
491 | if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) { | |
a9524a76 JG |
492 | dev_printk(KERN_DEBUG, &pdev->dev, |
493 | "enabling SATA channel native mode (0x%x)\n", | |
494 | (int) tmp8); | |
1da177e4 LT |
495 | tmp8 |= NATIVE_MODE_ALL; |
496 | pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8); | |
497 | } | |
498 | } | |
499 | ||
500 | static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
501 | { | |
502 | static int printed_version; | |
503 | unsigned int i; | |
504 | int rc; | |
eca25dca | 505 | struct ata_host *host; |
1da177e4 LT |
506 | int board_id = (int) ent->driver_data; |
507 | const int *bar_sizes; | |
1da177e4 LT |
508 | u8 tmp8; |
509 | ||
510 | if (!printed_version++) | |
a9524a76 | 511 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 512 | |
24dc5f33 | 513 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
514 | if (rc) |
515 | return rc; | |
516 | ||
1da177e4 LT |
517 | if (board_id == vt6420) { |
518 | pci_read_config_byte(pdev, SATA_PATA_SHARING, &tmp8); | |
519 | if (tmp8 & SATA_2DEV) { | |
a9524a76 JG |
520 | dev_printk(KERN_ERR, &pdev->dev, |
521 | "SATA master/slave not supported (0x%x)\n", | |
522 | (int) tmp8); | |
24dc5f33 | 523 | return -EIO; |
1da177e4 LT |
524 | } |
525 | ||
526 | bar_sizes = &svia_bar_sizes[0]; | |
527 | } else { | |
528 | bar_sizes = &vt6421_bar_sizes[0]; | |
529 | } | |
530 | ||
531 | for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++) | |
532 | if ((pci_resource_start(pdev, i) == 0) || | |
533 | (pci_resource_len(pdev, i) < bar_sizes[i])) { | |
a9524a76 | 534 | dev_printk(KERN_ERR, &pdev->dev, |
e29419ff GKH |
535 | "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n", |
536 | i, | |
537 | (unsigned long long)pci_resource_start(pdev, i), | |
538 | (unsigned long long)pci_resource_len(pdev, i)); | |
24dc5f33 | 539 | return -ENODEV; |
1da177e4 LT |
540 | } |
541 | ||
1da177e4 | 542 | if (board_id == vt6420) |
eca25dca | 543 | rc = vt6420_prepare_host(pdev, &host); |
1da177e4 | 544 | else |
eca25dca TH |
545 | rc = vt6421_prepare_host(pdev, &host); |
546 | if (rc) | |
547 | return rc; | |
1da177e4 LT |
548 | |
549 | svia_configure(pdev); | |
550 | ||
551 | pci_set_master(pdev); | |
eca25dca TH |
552 | return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED, |
553 | &svia_sht); | |
1da177e4 LT |
554 | } |
555 | ||
556 | static int __init svia_init(void) | |
557 | { | |
b7887196 | 558 | return pci_register_driver(&svia_pci_driver); |
1da177e4 LT |
559 | } |
560 | ||
561 | static void __exit svia_exit(void) | |
562 | { | |
563 | pci_unregister_driver(&svia_pci_driver); | |
564 | } | |
565 | ||
566 | module_init(svia_init); | |
567 | module_exit(svia_exit); |