[mirror_ubuntu-artful-kernel.git] / drivers / ata / sata_via.c

/*
 *  sata_via.c - VIA Serial ATA controllers
 *
 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 * 		   Please ALWAYS copy linux-ide@vger.kernel.org
 		   on emails.
 *
 *  Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
 *  Copyright 2003-2004 Jeff Garzik
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 *
 *  To-do list:
 *  - VT6421 PATA support
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_via"
#define DRV_VERSION	"2.3"

enum board_ids_enum {
	vt6420,
	vt6421,
};

enum {
	SATA_CHAN_ENAB		= 0x40, /* SATA channel enable */
	SATA_INT_GATE		= 0x41, /* SATA interrupt gating */
	SATA_NATIVE_MODE	= 0x42, /* Native mode enable */
	SATA_PATA_SHARING	= 0x49, /* PATA/SATA sharing func ctrl */
	PATA_UDMA_TIMING	= 0xB3, /* PATA timing for DMA/ cable detect */
	PATA_PIO_TIMING		= 0xAB, /* PATA timing register */

	PORT0			= (1 << 1),
	PORT1			= (1 << 0),
	ALL_PORTS		= PORT0 | PORT1,

	NATIVE_MODE_ALL		= (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),

	SATA_EXT_PHY		= (1 << 6), /* 0==use PATA, 1==ext phy */
	SATA_2DEV		= (1 << 5), /* SATA is master/slave */
};

static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
static void svia_noop_freeze(struct ata_port *ap);
static void vt6420_error_handler(struct ata_port *ap);
static int vt6421_pata_cable_detect(struct ata_port *ap);
static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);

static const struct pci_device_id svia_pci_tbl[] = {
	{ PCI_VDEVICE(VIA, 0x5337), vt6420 },
	{ PCI_VDEVICE(VIA, 0x0591), vt6420 },
	{ PCI_VDEVICE(VIA, 0x3149), vt6420 },
	{ PCI_VDEVICE(VIA, 0x3249), vt6421 },
	{ PCI_VDEVICE(VIA, 0x5287), vt6420 },
	{ PCI_VDEVICE(VIA, 0x5372), vt6420 },
	{ PCI_VDEVICE(VIA, 0x7372), vt6420 },

	{ }	/* terminate list */
};

static struct pci_driver svia_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= svia_pci_tbl,
	.probe			= svia_init_one,
#ifdef CONFIG_PM
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template svia_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations vt6420_sata_ops = {
	.port_disable		= ata_port_disable,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,

	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.freeze			= svia_noop_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= vt6420_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,

	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.port_start		= ata_port_start,
};

static const struct ata_port_operations vt6421_pata_ops = {
	.port_disable		= ata_port_disable,

	.set_piomode		= vt6421_set_pio_mode,
	.set_dmamode		= vt6421_set_dma_mode,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,

	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= ata_bmdma_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.cable_detect		= vt6421_pata_cable_detect,

	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.port_start		= ata_port_start,
};

static const struct ata_port_operations vt6421_sata_ops = {
	.port_disable		= ata_port_disable,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,

	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= ata_bmdma_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.cable_detect		= ata_cable_sata,

	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.scr_read		= svia_scr_read,
	.scr_write		= svia_scr_write,

	.port_start		= ata_port_start,
};

static const struct ata_port_info vt6420_port_info = {
	.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0x07,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &vt6420_sata_ops,
};

static struct ata_port_info vt6421_sport_info = {
	.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0x07,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &vt6421_sata_ops,
};

static struct ata_port_info vt6421_pport_info = {
	.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &vt6421_pata_ops,
};

MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = ioread32(ap->ioaddr.scr_addr + (4 * sc_reg));
	return 0;
}

static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg));
	return 0;
}

static void svia_noop_freeze(struct ata_port *ap)
{
	/* Some VIA controllers choke if ATA_NIEN is manipulated in
	 * certain way.  Leave it alone and just clear pending IRQ.
	 */
	ata_chk_status(ap);
	ata_bmdma_irq_clear(ap);
}

/**
 *	vt6420_prereset - prereset for vt6420
 *	@link: target ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	SCR registers on vt6420 are pieces of shit and may hang the
 *	whole machine completely if accessed with the wrong timing.
 *	To avoid such catastrophe, vt6420 doesn't provide generic SCR
 *	access operations, but uses SStatus and SControl only during
 *	boot probing in controlled way.
 *
 *	As the old (pre EH update) probing code is proven to work, we
 *	strictly follow the access pattern.
 *
 *	LOCKING:
 *	Kernel thread context (may sleep)
 *
 *	RETURNS:
 *	0 on success, -errno otherwise.
 */
static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct ata_eh_context *ehc = &ap->link.eh_context;
	unsigned long timeout = jiffies + (HZ * 5);
	u32 sstatus, scontrol;
	int online;

	/* don't do any SCR stuff if we're not loading */
	if (!(ap->pflags & ATA_PFLAG_LOADING))
		goto skip_scr;

	/* Resume phy.  This is the old SATA resume sequence */
	svia_scr_write(ap, SCR_CONTROL, 0x300);
	svia_scr_read(ap, SCR_CONTROL, &scontrol); /* flush */

	/* wait for phy to become ready, if necessary */
	do {
		msleep(200);
		svia_scr_read(ap, SCR_STATUS, &sstatus);
		if ((sstatus & 0xf) != 1)
			break;
	} while (time_before(jiffies, timeout));

	/* open code sata_print_link_status() */
	svia_scr_read(ap, SCR_STATUS, &sstatus);
	svia_scr_read(ap, SCR_CONTROL, &scontrol);

	online = (sstatus & 0xf) == 0x3;

	ata_port_printk(ap, KERN_INFO,
			"SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
			online ? "up" : "down", sstatus, scontrol);

	/* SStatus is read one more time */
	svia_scr_read(ap, SCR_STATUS, &sstatus);

	if (!online) {
		/* tell EH to bail */
		ehc->i.action &= ~ATA_EH_RESET_MASK;
		return 0;
	}

 skip_scr:
	/* wait for !BSY */
	ata_wait_ready(ap, deadline);

	return 0;
}

static void vt6420_error_handler(struct ata_port *ap)
{
	return ata_bmdma_drive_eh(ap, vt6420_prereset, ata_std_softreset,
				  NULL, ata_std_postreset);
}

static int vt6421_pata_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;

	pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
	if (tmp & 0x10)
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
	pci_write_config_byte(pdev, PATA_PIO_TIMING, pio_bits[adev->pio_mode - XFER_PIO_0]);
}

static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
	pci_write_config_byte(pdev, PATA_UDMA_TIMING, udma_bits[adev->dma_mode - XFER_UDMA_0]);
}

static const unsigned int svia_bar_sizes[] = {
	8, 4, 8, 4, 16, 256
};

static const unsigned int vt6421_bar_sizes[] = {
	16, 16, 16, 16, 32, 128
};

static void __iomem * svia_scr_addr(void __iomem *addr, unsigned int port)
{
	return addr + (port * 128);
}

static void __iomem * vt6421_scr_addr(void __iomem *addr, unsigned int port)
{
	return addr + (port * 64);
}

static void vt6421_init_addrs(struct ata_port *ap)
{
	void __iomem * const * iomap = ap->host->iomap;
	void __iomem *reg_addr = iomap[ap->port_no];
	void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8);
	struct ata_ioports *ioaddr = &ap->ioaddr;

	ioaddr->cmd_addr = reg_addr;
	ioaddr->altstatus_addr =
	ioaddr->ctl_addr = (void __iomem *)
		((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
	ioaddr->bmdma_addr = bmdma_addr;
	ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);

	ata_std_ports(ioaddr);
}

static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
{
	const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
	struct ata_host *host;
	int rc;

	rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
	if (rc)
		return rc;
	*r_host = host;

	rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
	if (rc) {
		dev_printk(KERN_ERR, &pdev->dev, "failed to iomap PCI BAR 5\n");
		return rc;
	}

	host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
	host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);

	return 0;
}

static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
{
	const struct ata_port_info *ppi[] =
		{ &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
	struct ata_host *host;
	int i, rc;

	*r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
	if (!host) {
		dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
		return -ENOMEM;
	}

	rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
	if (rc) {
		dev_printk(KERN_ERR, &pdev->dev, "failed to request/iomap "
			   "PCI BARs (errno=%d)\n", rc);
		return rc;
	}
	host->iomap = pcim_iomap_table(pdev);

	for (i = 0; i < host->n_ports; i++)
		vt6421_init_addrs(host->ports[i]);

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;

	return 0;
}

static void svia_configure(struct pci_dev *pdev)
{
	u8 tmp8;

	pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
	dev_printk(KERN_INFO, &pdev->dev, "routed to hard irq line %d\n",
	       (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);

	/* make sure SATA channels are enabled */
	pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "enabling SATA channels (0x%x)\n",
		           (int) tmp8);
		tmp8 |= ALL_PORTS;
		pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
	}

	/* make sure interrupts for each channel sent to us */
	pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "enabling SATA channel interrupts (0x%x)\n",
		           (int) tmp8);
		tmp8 |= ALL_PORTS;
		pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
	}

	/* make sure native mode is enabled */
	pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
	if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "enabling SATA channel native mode (0x%x)\n",
		           (int) tmp8);
		tmp8 |= NATIVE_MODE_ALL;
		pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
	}
}

static int svia_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	unsigned int i;
	int rc;
	struct ata_host *host;
	int board_id = (int) ent->driver_data;
	const int *bar_sizes;
	u8 tmp8;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if (board_id == vt6420) {
		pci_read_config_byte(pdev, SATA_PATA_SHARING, &tmp8);
		if (tmp8 & SATA_2DEV) {
			dev_printk(KERN_ERR, &pdev->dev,
				   "SATA master/slave not supported (0x%x)\n",
		       		   (int) tmp8);
			return -EIO;
		}

		bar_sizes = &svia_bar_sizes[0];
	} else {
		bar_sizes = &vt6421_bar_sizes[0];
	}

	for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
		if ((pci_resource_start(pdev, i) == 0) ||
		    (pci_resource_len(pdev, i) < bar_sizes[i])) {
			dev_printk(KERN_ERR, &pdev->dev,
				"invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
				i,
			        (unsigned long long)pci_resource_start(pdev, i),
			        (unsigned long long)pci_resource_len(pdev, i));
			return -ENODEV;
		}

	if (board_id == vt6420)
		rc = vt6420_prepare_host(pdev, &host);
	else
		rc = vt6421_prepare_host(pdev, &host);
	if (rc)
		return rc;

	svia_configure(pdev);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
				 &svia_sht);
}

static int __init svia_init(void)
{
	return pci_register_driver(&svia_pci_driver);
}

static void __exit svia_exit(void)
{
	pci_unregister_driver(&svia_pci_driver);
}

module_init(svia_init);
module_exit(svia_exit);
Commit	Line	Data
1da177e4	1	/*
af36d7f0 JG	2	* sata_via.c - VIA Serial ATA controllers
	3	*
	4	* Maintained by: Jeff Garzik <jgarzik@pobox.com>
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
1da177e4	6	on emails.
af36d7f0 JG	7	*
	8	* Copyright 2003-2004 Red Hat, Inc. All rights reserved.
	9	* Copyright 2003-2004 Jeff Garzik
	10	*
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2, or (at your option)
	15	* any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; see the file COPYING. If not, write to
	24	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
	26	*
	27	* libata documentation is available via 'make {ps\|pdf}docs',
	28	* as Documentation/DocBook/libata.*
	29	*
	30	* Hardware documentation available under NDA.
	31	*
	32	*
	33	* To-do list:
	34	* - VT6421 PATA support
	35	*
1da177e4 LT	36	*/
	37
	38	#include <linux/kernel.h>
	39	#include <linux/module.h>
	40	#include <linux/pci.h>
	41	#include <linux/init.h>
	42	#include <linux/blkdev.h>
	43	#include <linux/delay.h>
a9524a76	44	#include <linux/device.h>
1da177e4 LT	45	#include <scsi/scsi_host.h>
1da177e4 LT	46	#include <linux/libata.h>
1da177e4 LT	47
1da177e4 LT	48	#define DRV_NAME "sata_via"
2a3103ce	49	#define DRV_VERSION "2.3"
1da177e4 LT	50
	51	enum board_ids_enum {
	52	vt6420,
	53	vt6421,
	54	};
	55
	56	enum {
	57	SATA_CHAN_ENAB = 0x40, /* SATA channel enable */
	58	SATA_INT_GATE = 0x41, /* SATA interrupt gating */
	59	SATA_NATIVE_MODE = 0x42, /* Native mode enable */
	60	SATA_PATA_SHARING = 0x49, /* PATA/SATA sharing func ctrl */
d73f30e1 AC	61	PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */
d73f30e1 AC	62	PATA_PIO_TIMING = 0xAB, /* PATA timing register */
a84471fe	63
1da177e4 LT	64	PORT0 = (1 << 1),
	65	PORT1 = (1 << 0),
	66	ALL_PORTS = PORT0 \| PORT1,
1da177e4 LT	67
	68	NATIVE_MODE_ALL = (1 << 7) \| (1 << 6) \| (1 << 5) \| (1 << 4),
	69
	70	SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
	71	SATA_2DEV = (1 << 5), /* SATA is master/slave */
	72	};
	73
	74	static int svia_init_one (struct pci_dev pdev, const struct pci_device_id ent);
da3dbb17 TH	75	static int svia_scr_read(struct ata_port ap, unsigned int sc_reg, u32 val);
da3dbb17 TH	76	static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
17234246	77	static void svia_noop_freeze(struct ata_port *ap);
ac2164d5	78	static void vt6420_error_handler(struct ata_port *ap);
a0fcdc02	79	static int vt6421_pata_cable_detect(struct ata_port *ap);
d73f30e1 AC	80	static void vt6421_set_pio_mode(struct ata_port ap, struct ata_device adev);
d73f30e1 AC	81	static void vt6421_set_dma_mode(struct ata_port ap, struct ata_device adev);
1da177e4	82
3b7d697d	83	static const struct pci_device_id svia_pci_tbl[] = {
96bc103f	84	{ PCI_VDEVICE(VIA, 0x5337), vt6420 },
2d2744fc JG	85	{ PCI_VDEVICE(VIA, 0x0591), vt6420 },
	86	{ PCI_VDEVICE(VIA, 0x3149), vt6420 },
	87	{ PCI_VDEVICE(VIA, 0x3249), vt6421 },
52df0ee0 JG	88	{ PCI_VDEVICE(VIA, 0x5287), vt6420 },
	89	{ PCI_VDEVICE(VIA, 0x5372), vt6420 },
	90	{ PCI_VDEVICE(VIA, 0x7372), vt6420 },
1da177e4 LT	91
	92	{ } /* terminate list */
	93	};
	94
	95	static struct pci_driver svia_pci_driver = {
	96	.name = DRV_NAME,
	97	.id_table = svia_pci_tbl,
	98	.probe = svia_init_one,
e1e143cf TH	99	#ifdef CONFIG_PM
	100	.suspend = ata_pci_device_suspend,
	101	.resume = ata_pci_device_resume,
	102	#endif
1da177e4 LT	103	.remove = ata_pci_remove_one,
	104	};
	105
193515d5	106	static struct scsi_host_template svia_sht = {
1da177e4 LT	107	.module = THIS_MODULE,
	108	.name = DRV_NAME,
	109	.ioctl = ata_scsi_ioctl,
	110	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	111	.can_queue = ATA_DEF_QUEUE,
	112	.this_id = ATA_SHT_THIS_ID,
	113	.sg_tablesize = LIBATA_MAX_PRD,
1da177e4 LT	114	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	115	.emulated = ATA_SHT_EMULATED,
	116	.use_clustering = ATA_SHT_USE_CLUSTERING,
	117	.proc_name = DRV_NAME,
	118	.dma_boundary = ATA_DMA_BOUNDARY,
	119	.slave_configure = ata_scsi_slave_config,
ccf68c34	120	.slave_destroy = ata_scsi_slave_destroy,
1da177e4	121	.bios_param = ata_std_bios_param,
1da177e4 LT	122	};
1da177e4 LT	123
ac2164d5 TH	124	static const struct ata_port_operations vt6420_sata_ops = {
	125	.port_disable = ata_port_disable,
	126
	127	.tf_load = ata_tf_load,
	128	.tf_read = ata_tf_read,
	129	.check_status = ata_check_status,
	130	.exec_command = ata_exec_command,
	131	.dev_select = ata_std_dev_select,
	132
	133	.bmdma_setup = ata_bmdma_setup,
	134	.bmdma_start = ata_bmdma_start,
	135	.bmdma_stop = ata_bmdma_stop,
	136	.bmdma_status = ata_bmdma_status,
	137
	138	.qc_prep = ata_qc_prep,
	139	.qc_issue = ata_qc_issue_prot,
0d5ff566	140	.data_xfer = ata_data_xfer,
ac2164d5	141
17234246	142	.freeze = svia_noop_freeze,
ac2164d5 TH	143	.thaw = ata_bmdma_thaw,
	144	.error_handler = vt6420_error_handler,
	145	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	146
ac2164d5	147	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	148	.irq_on = ata_irq_on,
246ce3b6 AI	149	.irq_ack = ata_irq_ack,
ac2164d5 TH	150
ac2164d5 TH	151	.port_start = ata_port_start,
ac2164d5 TH	152	};
ac2164d5 TH	153
d73f30e1	154	static const struct ata_port_operations vt6421_pata_ops = {
1da177e4	155	.port_disable = ata_port_disable,
a84471fe	156
d73f30e1 AC	157	.set_piomode = vt6421_set_pio_mode,
	158	.set_dmamode = vt6421_set_dma_mode,
	159
	160	.tf_load = ata_tf_load,
	161	.tf_read = ata_tf_read,
	162	.check_status = ata_check_status,
	163	.exec_command = ata_exec_command,
	164	.dev_select = ata_std_dev_select,
	165
	166	.bmdma_setup = ata_bmdma_setup,
	167	.bmdma_start = ata_bmdma_start,
	168	.bmdma_stop = ata_bmdma_stop,
	169	.bmdma_status = ata_bmdma_status,
	170
	171	.qc_prep = ata_qc_prep,
	172	.qc_issue = ata_qc_issue_prot,
0d5ff566	173	.data_xfer = ata_data_xfer,
d73f30e1 AC	174
	175	.freeze = ata_bmdma_freeze,
	176	.thaw = ata_bmdma_thaw,
a0fcdc02	177	.error_handler = ata_bmdma_error_handler,
d73f30e1	178	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	179	.cable_detect = vt6421_pata_cable_detect,
1da177e4	180
d73f30e1	181	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	182	.irq_on = ata_irq_on,
246ce3b6 AI	183	.irq_ack = ata_irq_ack,
d73f30e1	184
eca25dca	185	.port_start = ata_port_start,
d73f30e1 AC	186	};
	187
	188	static const struct ata_port_operations vt6421_sata_ops = {
	189	.port_disable = ata_port_disable,
a84471fe	190
1da177e4 LT	191	.tf_load = ata_tf_load,
	192	.tf_read = ata_tf_read,
	193	.check_status = ata_check_status,
	194	.exec_command = ata_exec_command,
	195	.dev_select = ata_std_dev_select,
	196
1da177e4 LT	197	.bmdma_setup = ata_bmdma_setup,
	198	.bmdma_start = ata_bmdma_start,
	199	.bmdma_stop = ata_bmdma_stop,
	200	.bmdma_status = ata_bmdma_status,
	201
	202	.qc_prep = ata_qc_prep,
	203	.qc_issue = ata_qc_issue_prot,
0d5ff566	204	.data_xfer = ata_data_xfer,
1da177e4	205
40ef1d8d TH	206	.freeze = ata_bmdma_freeze,
40ef1d8d TH	207	.thaw = ata_bmdma_thaw,
a0fcdc02	208	.error_handler = ata_bmdma_error_handler,
40ef1d8d	209	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	210	.cable_detect = ata_cable_sata,
1da177e4	211
1da177e4	212	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	213	.irq_on = ata_irq_on,
246ce3b6 AI	214	.irq_ack = ata_irq_ack,
1da177e4 LT	215
	216	.scr_read = svia_scr_read,
	217	.scr_write = svia_scr_write,
	218
eca25dca	219	.port_start = ata_port_start,
1da177e4 LT	220	};
1da177e4 LT	221
eca25dca	222	static const struct ata_port_info vt6420_port_info = {
cca3974e	223	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
1da177e4 LT	224	.pio_mask = 0x1f,
1da177e4 LT	225	.mwdma_mask = 0x07,
bf6263a8	226	.udma_mask = ATA_UDMA6,
ac2164d5	227	.port_ops = &vt6420_sata_ops,
1da177e4 LT	228	};
1da177e4 LT	229
eca25dca TH	230	static struct ata_port_info vt6421_sport_info = {
	231	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
	232	.pio_mask = 0x1f,
	233	.mwdma_mask = 0x07,
bf6263a8	234	.udma_mask = ATA_UDMA6,
eca25dca TH	235	.port_ops = &vt6421_sata_ops,
	236	};
	237
	238	static struct ata_port_info vt6421_pport_info = {
	239	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_NO_LEGACY,
	240	.pio_mask = 0x1f,
	241	.mwdma_mask = 0,
bf6263a8	242	.udma_mask = ATA_UDMA6,
eca25dca TH	243	.port_ops = &vt6421_pata_ops,
	244	};
	245
1da177e4 LT	246	MODULE_AUTHOR("Jeff Garzik");
	247	MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
	248	MODULE_LICENSE("GPL");
	249	MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
	250	MODULE_VERSION(DRV_VERSION);
	251
da3dbb17	252	static int svia_scr_read(struct ata_port ap, unsigned int sc_reg, u32 val)
1da177e4 LT	253	{
1da177e4 LT	254	if (sc_reg > SCR_CONTROL)
da3dbb17 TH	255	return -EINVAL;
	256	val = ioread32(ap->ioaddr.scr_addr + (4 sc_reg));
	257	return 0;
1da177e4 LT	258	}
1da177e4 LT	259
da3dbb17	260	static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
1da177e4 LT	261	{
1da177e4 LT	262	if (sc_reg > SCR_CONTROL)
da3dbb17	263	return -EINVAL;
0d5ff566	264	iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg));
da3dbb17	265	return 0;
1da177e4 LT	266	}
1da177e4 LT	267
17234246 TH	268	static void svia_noop_freeze(struct ata_port *ap)
	269	{
	270	/* Some VIA controllers choke if ATA_NIEN is manipulated in
	271	* certain way. Leave it alone and just clear pending IRQ.
	272	*/
	273	ata_chk_status(ap);
d0259872	274	ata_bmdma_irq_clear(ap);
17234246 TH	275	}
17234246 TH	276
ac2164d5 TH	277	/**
ac2164d5 TH	278	* vt6420_prereset - prereset for vt6420
cc0680a5	279	* @link: target ATA link
d4b2bab4	280	* @deadline: deadline jiffies for the operation
ac2164d5 TH	281	*
	282	* SCR registers on vt6420 are pieces of shit and may hang the
	283	* whole machine completely if accessed with the wrong timing.
	284	* To avoid such catastrophe, vt6420 doesn't provide generic SCR
	285	* access operations, but uses SStatus and SControl only during
	286	* boot probing in controlled way.
	287	*
	288	* As the old (pre EH update) probing code is proven to work, we
	289	* strictly follow the access pattern.
	290	*
	291	* LOCKING:
	292	* Kernel thread context (may sleep)
	293	*
	294	* RETURNS:
	295	* 0 on success, -errno otherwise.
	296	*/
cc0680a5	297	static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
ac2164d5	298	{
cc0680a5	299	struct ata_port *ap = link->ap;
9af5c9c9	300	struct ata_eh_context *ehc = &ap->link.eh_context;
ac2164d5 TH	301	unsigned long timeout = jiffies + (HZ * 5);
	302	u32 sstatus, scontrol;
	303	int online;
	304
	305	/* don't do any SCR stuff if we're not loading */
68ff6e8e	306	if (!(ap->pflags & ATA_PFLAG_LOADING))
ac2164d5 TH	307	goto skip_scr;
ac2164d5 TH	308
a09060ff	309	/* Resume phy. This is the old SATA resume sequence */
ac2164d5	310	svia_scr_write(ap, SCR_CONTROL, 0x300);
da3dbb17	311	svia_scr_read(ap, SCR_CONTROL, &scontrol); /* flush */
ac2164d5 TH	312
	313	/* wait for phy to become ready, if necessary */
	314	do {
	315	msleep(200);
da3dbb17 TH	316	svia_scr_read(ap, SCR_STATUS, &sstatus);
da3dbb17 TH	317	if ((sstatus & 0xf) != 1)
ac2164d5 TH	318	break;
	319	} while (time_before(jiffies, timeout));
	320
	321	/* open code sata_print_link_status() */
da3dbb17 TH	322	svia_scr_read(ap, SCR_STATUS, &sstatus);
da3dbb17 TH	323	svia_scr_read(ap, SCR_CONTROL, &scontrol);
ac2164d5 TH	324
	325	online = (sstatus & 0xf) == 0x3;
	326
	327	ata_port_printk(ap, KERN_INFO,
	328	"SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
	329	online ? "up" : "down", sstatus, scontrol);
	330
	331	/* SStatus is read one more time */
da3dbb17	332	svia_scr_read(ap, SCR_STATUS, &sstatus);
ac2164d5 TH	333
	334	if (!online) {
	335	/* tell EH to bail */
	336	ehc->i.action &= ~ATA_EH_RESET_MASK;
	337	return 0;
	338	}
	339
	340	skip_scr:
	341	/* wait for !BSY */
d4b2bab4	342	ata_wait_ready(ap, deadline);
ac2164d5 TH	343
	344	return 0;
	345	}
	346
	347	static void vt6420_error_handler(struct ata_port *ap)
	348	{
	349	return ata_bmdma_drive_eh(ap, vt6420_prereset, ata_std_softreset,
	350	NULL, ata_std_postreset);
	351	}
	352
a0fcdc02	353	static int vt6421_pata_cable_detect(struct ata_port *ap)
d73f30e1 AC	354	{
	355	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	356	u8 tmp;
	357
	358	pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
	359	if (tmp & 0x10)
a0fcdc02 JG	360	return ATA_CBL_PATA40;
a0fcdc02 JG	361	return ATA_CBL_PATA80;
d73f30e1 AC	362	}
	363
	364	static void vt6421_set_pio_mode(struct ata_port ap, struct ata_device adev)
	365	{
	366	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	367	static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
	368	pci_write_config_byte(pdev, PATA_PIO_TIMING, pio_bits[adev->pio_mode - XFER_PIO_0]);
	369	}
	370
	371	static void vt6421_set_dma_mode(struct ata_port ap, struct ata_device adev)
	372	{
	373	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	374	static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
b4154d4a	375	pci_write_config_byte(pdev, PATA_UDMA_TIMING, udma_bits[adev->dma_mode - XFER_UDMA_0]);
d73f30e1 AC	376	}
d73f30e1 AC	377
1da177e4 LT	378	static const unsigned int svia_bar_sizes[] = {
	379	8, 4, 8, 4, 16, 256
	380	};
	381
	382	static const unsigned int vt6421_bar_sizes[] = {
	383	16, 16, 16, 16, 32, 128
	384	};
	385
0d5ff566	386	static void __iomem * svia_scr_addr(void __iomem *addr, unsigned int port)
1da177e4 LT	387	{
	388	return addr + (port * 128);
	389	}
	390
0d5ff566	391	static void __iomem * vt6421_scr_addr(void __iomem *addr, unsigned int port)
1da177e4 LT	392	{
	393	return addr + (port * 64);
	394	}
	395
eca25dca	396	static void vt6421_init_addrs(struct ata_port *ap)
1da177e4	397	{
eca25dca TH	398	void __iomem * const * iomap = ap->host->iomap;
	399	void __iomem *reg_addr = iomap[ap->port_no];
	400	void __iomem bmdma_addr = iomap[4] + (ap->port_no 8);
	401	struct ata_ioports *ioaddr = &ap->ioaddr;
	402
	403	ioaddr->cmd_addr = reg_addr;
	404	ioaddr->altstatus_addr =
	405	ioaddr->ctl_addr = (void __iomem *)
0d5ff566	406	((unsigned long)(reg_addr + 8) \| ATA_PCI_CTL_OFS);
eca25dca TH	407	ioaddr->bmdma_addr = bmdma_addr;
eca25dca TH	408	ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);
1da177e4	409
eca25dca	410	ata_std_ports(ioaddr);
1da177e4 LT	411	}
1da177e4 LT	412
eca25dca	413	static int vt6420_prepare_host(struct pci_dev pdev, struct ata_host *r_host)
1da177e4	414	{
eca25dca TH	415	const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
	416	struct ata_host *host;
	417	int rc;
f20b16ff	418
d583bc18	419	rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
eca25dca TH	420	if (rc)
	421	return rc;
	422	*r_host = host;
1da177e4	423
eca25dca TH	424	rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
eca25dca TH	425	if (rc) {
e1be5d73	426	dev_printk(KERN_ERR, &pdev->dev, "failed to iomap PCI BAR 5\n");
eca25dca	427	return rc;
e1be5d73 TH	428	}
e1be5d73 TH	429
eca25dca TH	430	host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
eca25dca TH	431	host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);
1da177e4	432
eca25dca	433	return 0;
1da177e4 LT	434	}
1da177e4 LT	435
eca25dca	436	static int vt6421_prepare_host(struct pci_dev pdev, struct ata_host *r_host)
1da177e4	437	{
eca25dca TH	438	const struct ata_port_info *ppi[] =
	439	{ &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
	440	struct ata_host *host;
	441	int i, rc;
	442
	443	*r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
	444	if (!host) {
	445	dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
	446	return -ENOMEM;
	447	}
1da177e4	448
8fd7d1b1	449	rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
eca25dca TH	450	if (rc) {
	451	dev_printk(KERN_ERR, &pdev->dev, "failed to request/iomap "
	452	"PCI BARs (errno=%d)\n", rc);
	453	return rc;
	454	}
	455	host->iomap = pcim_iomap_table(pdev);
e1be5d73	456
eca25dca TH	457	for (i = 0; i < host->n_ports; i++)
eca25dca TH	458	vt6421_init_addrs(host->ports[i]);
1da177e4	459
eca25dca TH	460	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	461	if (rc)
	462	return rc;
	463	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	464	if (rc)
	465	return rc;
	466
	467	return 0;
1da177e4 LT	468	}
	469
	470	static void svia_configure(struct pci_dev *pdev)
	471	{
	472	u8 tmp8;
	473
	474	pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
a9524a76	475	dev_printk(KERN_INFO, &pdev->dev, "routed to hard irq line %d\n",
1da177e4 LT	476	(int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
	477
	478	/* make sure SATA channels are enabled */
	479	pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
	480	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
a9524a76 JG	481	dev_printk(KERN_DEBUG, &pdev->dev,
	482	"enabling SATA channels (0x%x)\n",
	483	(int) tmp8);
1da177e4 LT	484	tmp8 \|= ALL_PORTS;
	485	pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
	486	}
	487
	488	/* make sure interrupts for each channel sent to us */
	489	pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
	490	if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
a9524a76 JG	491	dev_printk(KERN_DEBUG, &pdev->dev,
	492	"enabling SATA channel interrupts (0x%x)\n",
	493	(int) tmp8);
1da177e4 LT	494	tmp8 \|= ALL_PORTS;
	495	pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
	496	}
	497
	498	/* make sure native mode is enabled */
	499	pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
	500	if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
a9524a76 JG	501	dev_printk(KERN_DEBUG, &pdev->dev,
	502	"enabling SATA channel native mode (0x%x)\n",
	503	(int) tmp8);
1da177e4 LT	504	tmp8 \|= NATIVE_MODE_ALL;
	505	pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
	506	}
	507	}
	508
	509	static int svia_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	510	{
	511	static int printed_version;
	512	unsigned int i;
	513	int rc;
eca25dca	514	struct ata_host *host;
1da177e4 LT	515	int board_id = (int) ent->driver_data;
1da177e4 LT	516	const int *bar_sizes;
1da177e4 LT	517	u8 tmp8;
	518
	519	if (!printed_version++)
a9524a76	520	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4	521
24dc5f33	522	rc = pcim_enable_device(pdev);
1da177e4 LT	523	if (rc)
	524	return rc;
	525
1da177e4 LT	526	if (board_id == vt6420) {
	527	pci_read_config_byte(pdev, SATA_PATA_SHARING, &tmp8);
	528	if (tmp8 & SATA_2DEV) {
a9524a76 JG	529	dev_printk(KERN_ERR, &pdev->dev,
	530	"SATA master/slave not supported (0x%x)\n",
	531	(int) tmp8);
24dc5f33	532	return -EIO;
1da177e4 LT	533	}
	534
	535	bar_sizes = &svia_bar_sizes[0];
	536	} else {
	537	bar_sizes = &vt6421_bar_sizes[0];
	538	}
	539
	540	for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
	541	if ((pci_resource_start(pdev, i) == 0) \|\|
	542	(pci_resource_len(pdev, i) < bar_sizes[i])) {
a9524a76	543	dev_printk(KERN_ERR, &pdev->dev,
e29419ff GKH	544	"invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
	545	i,
	546	(unsigned long long)pci_resource_start(pdev, i),
	547	(unsigned long long)pci_resource_len(pdev, i));
24dc5f33	548	return -ENODEV;
1da177e4 LT	549	}
1da177e4 LT	550
1da177e4	551	if (board_id == vt6420)
eca25dca	552	rc = vt6420_prepare_host(pdev, &host);
1da177e4	553	else
eca25dca TH	554	rc = vt6421_prepare_host(pdev, &host);
	555	if (rc)
	556	return rc;
1da177e4 LT	557
	558	svia_configure(pdev);
	559
	560	pci_set_master(pdev);
eca25dca TH	561	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
eca25dca TH	562	&svia_sht);
1da177e4 LT	563	}
	564
	565	static int __init svia_init(void)
	566	{
b7887196	567	return pci_register_driver(&svia_pci_driver);
1da177e4 LT	568	}
	569
	570	static void __exit svia_exit(void)
	571	{
	572	pci_unregister_driver(&svia_pci_driver);
	573	}
	574
	575	module_init(svia_init);
	576	module_exit(svia_exit);