[mirror_ubuntu-artful-kernel.git] / drivers / ata / sata_vsc.c

/*
 *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
 *
 *  Maintained by:  Jeremy Higdon @ SGI
 * 		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 SGI
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Vitesse hardware documentation presumably available under NDA.
 *  Intel 31244 (same hardware interface) documentation presumably
 *  available from http://developer.intel.com/
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_vsc"
#define DRV_VERSION	"2.0"

enum {
	/* Interrupt register offsets (from chip base address) */
	VSC_SATA_INT_STAT_OFFSET	= 0x00,
	VSC_SATA_INT_MASK_OFFSET	= 0x04,

	/* Taskfile registers offsets */
	VSC_SATA_TF_CMD_OFFSET		= 0x00,
	VSC_SATA_TF_DATA_OFFSET		= 0x00,
	VSC_SATA_TF_ERROR_OFFSET	= 0x04,
	VSC_SATA_TF_FEATURE_OFFSET	= 0x06,
	VSC_SATA_TF_NSECT_OFFSET	= 0x08,
	VSC_SATA_TF_LBAL_OFFSET		= 0x0c,
	VSC_SATA_TF_LBAM_OFFSET		= 0x10,
	VSC_SATA_TF_LBAH_OFFSET		= 0x14,
	VSC_SATA_TF_DEVICE_OFFSET	= 0x18,
	VSC_SATA_TF_STATUS_OFFSET	= 0x1c,
	VSC_SATA_TF_COMMAND_OFFSET	= 0x1d,
	VSC_SATA_TF_ALTSTATUS_OFFSET	= 0x28,
	VSC_SATA_TF_CTL_OFFSET		= 0x29,

	/* DMA base */
	VSC_SATA_UP_DESCRIPTOR_OFFSET	= 0x64,
	VSC_SATA_UP_DATA_BUFFER_OFFSET	= 0x6C,
	VSC_SATA_DMA_CMD_OFFSET		= 0x70,

	/* SCRs base */
	VSC_SATA_SCR_STATUS_OFFSET	= 0x100,
	VSC_SATA_SCR_ERROR_OFFSET	= 0x104,
	VSC_SATA_SCR_CONTROL_OFFSET	= 0x108,

	/* Port stride */
	VSC_SATA_PORT_OFFSET		= 0x200,

	/* Error interrupt status bit offsets */
	VSC_SATA_INT_ERROR_CRC		= 0x40,
	VSC_SATA_INT_ERROR_T		= 0x20,
	VSC_SATA_INT_ERROR_P		= 0x10,
	VSC_SATA_INT_ERROR_R		= 0x8,
	VSC_SATA_INT_ERROR_E		= 0x4,
	VSC_SATA_INT_ERROR_M		= 0x2,
	VSC_SATA_INT_PHY_CHANGE		= 0x1,
	VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
			      VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
			      VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
			      VSC_SATA_INT_PHY_CHANGE),
};

#define is_vsc_sata_int_err(port_idx, int_status) \
	 (int_status & (VSC_SATA_INT_ERROR << (8 * port_idx)))


static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;
	return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
}


static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
			       u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return;
	writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
}


static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
{
	void __iomem *mask_addr;
	u8 mask;

	mask_addr = ap->host->mmio_base +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	mask = readb(mask_addr);
	if (ctl & ATA_NIEN)
		mask |= 0x80;
	else
		mask &= 0x7F;
	writeb(mask, mask_addr);
}


static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	/*
	 * The only thing the ctl register is used for is SRST.
	 * That is not enabled or disabled via tf_load.
	 * However, if ATA_NIEN is changed, then we need to change the interrupt register.
	 */
	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
		ap->last_ctl = tf->ctl;
		vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       (void __iomem *) ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       (void __iomem *) ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       (void __iomem *) ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       (void __iomem *) ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       (void __iomem *) ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, (void __iomem *) ioaddr->feature_addr);
		writew(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
		writew(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
		writew(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
		writew(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, (void __iomem *) ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = ata_check_status(ap);
	tf->device = readw((void __iomem *) ioaddr->device_addr);
	feature = readw((void __iomem *) ioaddr->error_addr);
	nsect = readw((void __iomem *) ioaddr->nsect_addr);
	lbal = readw((void __iomem *) ioaddr->lbal_addr);
	lbam = readw((void __iomem *) ioaddr->lbam_addr);
	lbah = readw((void __iomem *) ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
        }
}


/*
 * vsc_sata_interrupt
 *
 * Read the interrupt register and process for the devices that have them pending.
 */
static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	unsigned int i;
	unsigned int handled = 0;
	u32 int_status;

	spin_lock(&host->lock);

	int_status = readl(host->mmio_base + VSC_SATA_INT_STAT_OFFSET);

	for (i = 0; i < host->n_ports; i++) {
		if (int_status & ((u32) 0xFF << (8 * i))) {
			struct ata_port *ap;

			ap = host->ports[i];

			if (is_vsc_sata_int_err(i, int_status)) {
				u32 err_status;
				printk(KERN_DEBUG "%s: ignoring interrupt(s)\n", __FUNCTION__);
				err_status = ap ? vsc_sata_scr_read(ap, SCR_ERROR) : 0;
				vsc_sata_scr_write(ap, SCR_ERROR, err_status);
				handled++;
			}

			if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
				struct ata_queued_cmd *qc;

				qc = ata_qc_from_tag(ap, ap->active_tag);
				if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
					handled += ata_host_intr(ap, qc);
				else if (is_vsc_sata_int_err(i, int_status)) {
					/*
					 * On some chips (i.e. Intel 31244), an error
					 * interrupt will sneak in at initialization
					 * time (phy state changes).  Clearing the SCR
					 * error register is not required, but it prevents
					 * the phy state change interrupts from recurring
					 * later.
					 */
					u32 err_status;
					err_status = vsc_sata_scr_read(ap, SCR_ERROR);
					printk(KERN_DEBUG "%s: clearing interrupt, "
					       "status %x; sata err status %x\n",
					       __FUNCTION__,
					       int_status, err_status);
					vsc_sata_scr_write(ap, SCR_ERROR, err_status);
					/* Clear interrupt status */
					ata_chk_status(ap);
					handled++;
				}
			}
		}
	}

	spin_unlock(&host->lock);

	return IRQ_RETVAL(handled);
}


static struct scsi_host_template vsc_sata_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};


static const struct ata_port_operations vsc_sata_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= vsc_sata_tf_load,
	.tf_read		= vsc_sata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_mmio_data_xfer,
	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= ata_bmdma_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.irq_handler		= vsc_sata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= vsc_sata_scr_read,
	.scr_write		= vsc_sata_scr_write,
	.port_start		= ata_port_start,
};

static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
{
	port->cmd_addr		= base + VSC_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + VSC_SATA_TF_DATA_OFFSET;
	port->error_addr	= base + VSC_SATA_TF_ERROR_OFFSET;
	port->feature_addr	= base + VSC_SATA_TF_FEATURE_OFFSET;
	port->nsect_addr	= base + VSC_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + VSC_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + VSC_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + VSC_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + VSC_SATA_TF_DEVICE_OFFSET;
	port->status_addr	= base + VSC_SATA_TF_STATUS_OFFSET;
	port->command_addr	= base + VSC_SATA_TF_COMMAND_OFFSET;
	port->altstatus_addr	= base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	port->ctl_addr		= base + VSC_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + VSC_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + VSC_SATA_SCR_STATUS_OFFSET;
	writel(0, (void __iomem *) base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
	writel(0, (void __iomem *) base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
}


static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	unsigned long base;
	void __iomem *mmio_base;
	int rc;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/*
	 * Check if we have needed resource mapped.
	 */
	if (pci_resource_len(pdev, 0) == 0)
		return -ENODEV;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pcim_pin_device(pdev);
		return rc;
	}

	/*
	 * Use 32 bit DMA mask, because 64 bit address support is poor.
	 */
	rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
	if (rc)
		return rc;

	probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
	if (probe_ent == NULL)
		return -ENOMEM;
	probe_ent->dev = pci_dev_to_dev(pdev);
	INIT_LIST_HEAD(&probe_ent->node);

	mmio_base = pcim_iomap(pdev, 0, 0);
	if (mmio_base == NULL)
		return -ENOMEM;
	base = (unsigned long) mmio_base;

	/*
	 * Due to a bug in the chip, the default cache line size can't be used
	 */
	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);

	if (pci_enable_msi(pdev) == 0)
		pci_intx(pdev, 0);
	else
		probe_ent->irq_flags = IRQF_SHARED;

	probe_ent->sht = &vsc_sata_sht;
	probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				ATA_FLAG_MMIO;
	probe_ent->port_ops = &vsc_sata_ops;
	probe_ent->n_ports = 4;
	probe_ent->irq = pdev->irq;
	probe_ent->mmio_base = mmio_base;

	/* We don't care much about the PIO/UDMA masks, but the core won't like us
	 * if we don't fill these
	 */
	probe_ent->pio_mask = 0x1f;
	probe_ent->mwdma_mask = 0x07;
	probe_ent->udma_mask = 0x7f;

	/* We have 4 ports per PCI function */
	vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
	vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
	vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
	vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);

	pci_set_master(pdev);

	/*
	 * Config offset 0x98 is "Extended Control and Status Register 0"
	 * Default value is (1 << 28).  All bits except bit 28 are reserved in
	 * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
	 * If bit 28 is clear, each port has its own LED.
	 */
	pci_write_config_dword(pdev, 0x98, 0);

	if (!ata_device_add(probe_ent))
		return -ENODEV;

	devm_kfree(&pdev->dev, probe_ent);
	return 0;
}

static const struct pci_device_id vsc_sata_pci_tbl[] = {
	{ PCI_VENDOR_ID_VITESSE, 0x7174,
	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
	{ PCI_VENDOR_ID_INTEL, 0x3200,
	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },

	{ }	/* terminate list */
};

static struct pci_driver vsc_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= vsc_sata_pci_tbl,
	.probe			= vsc_sata_init_one,
	.remove			= ata_pci_remove_one,
};

static int __init vsc_sata_init(void)
{
	return pci_register_driver(&vsc_sata_pci_driver);
}

static void __exit vsc_sata_exit(void)
{
	pci_unregister_driver(&vsc_sata_pci_driver);
}

MODULE_AUTHOR("Jeremy Higdon");
MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);

module_init(vsc_sata_init);
module_exit(vsc_sata_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
	3	*
	4	* Maintained by: Jeremy Higdon @ SGI
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 SGI
	9	*
	10	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	11	*
af36d7f0 JG	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation; either version 2, or (at your option)
	16	* any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; see the file COPYING. If not, write to
	25	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	26	*
	27	*
	28	* libata documentation is available via 'make {ps\|pdf}docs',
	29	* as Documentation/DocBook/libata.*
	30	*
	31	* Vitesse hardware documentation presumably available under NDA.
	32	* Intel 31244 (same hardware interface) documentation presumably
	33	* available from http://developer.intel.com/
	34	*
1da177e4 LT	35	*/
	36
	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/pci.h>
	40	#include <linux/init.h>
	41	#include <linux/blkdev.h>
	42	#include <linux/delay.h>
	43	#include <linux/interrupt.h>
7003c05d	44	#include <linux/dma-mapping.h>
a9524a76	45	#include <linux/device.h>
1da177e4 LT	46	#include <scsi/scsi_host.h>
	47	#include <linux/libata.h>
	48
	49	#define DRV_NAME "sata_vsc"
8676ce07	50	#define DRV_VERSION "2.0"
1da177e4	51
55cca65e JG	52	enum {
	53	/* Interrupt register offsets (from chip base address) */
	54	VSC_SATA_INT_STAT_OFFSET = 0x00,
	55	VSC_SATA_INT_MASK_OFFSET = 0x04,
1da177e4	56
55cca65e JG	57	/* Taskfile registers offsets */
	58	VSC_SATA_TF_CMD_OFFSET = 0x00,
	59	VSC_SATA_TF_DATA_OFFSET = 0x00,
	60	VSC_SATA_TF_ERROR_OFFSET = 0x04,
	61	VSC_SATA_TF_FEATURE_OFFSET = 0x06,
	62	VSC_SATA_TF_NSECT_OFFSET = 0x08,
	63	VSC_SATA_TF_LBAL_OFFSET = 0x0c,
	64	VSC_SATA_TF_LBAM_OFFSET = 0x10,
	65	VSC_SATA_TF_LBAH_OFFSET = 0x14,
	66	VSC_SATA_TF_DEVICE_OFFSET = 0x18,
	67	VSC_SATA_TF_STATUS_OFFSET = 0x1c,
	68	VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
	69	VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
	70	VSC_SATA_TF_CTL_OFFSET = 0x29,
1da177e4	71
55cca65e JG	72	/* DMA base */
	73	VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
	74	VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
	75	VSC_SATA_DMA_CMD_OFFSET = 0x70,
1da177e4	76
55cca65e JG	77	/* SCRs base */
	78	VSC_SATA_SCR_STATUS_OFFSET = 0x100,
	79	VSC_SATA_SCR_ERROR_OFFSET = 0x104,
	80	VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
1da177e4	81
55cca65e JG	82	/* Port stride */
	83	VSC_SATA_PORT_OFFSET = 0x200,
	84
	85	/* Error interrupt status bit offsets */
	86	VSC_SATA_INT_ERROR_CRC = 0x40,
	87	VSC_SATA_INT_ERROR_T = 0x20,
	88	VSC_SATA_INT_ERROR_P = 0x10,
	89	VSC_SATA_INT_ERROR_R = 0x8,
	90	VSC_SATA_INT_ERROR_E = 0x4,
	91	VSC_SATA_INT_ERROR_M = 0x2,
	92	VSC_SATA_INT_PHY_CHANGE = 0x1,
	93	VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC \| VSC_SATA_INT_ERROR_T \| \
	94	VSC_SATA_INT_ERROR_P \| VSC_SATA_INT_ERROR_R \| \
	95	VSC_SATA_INT_ERROR_E \| VSC_SATA_INT_ERROR_M \| \
	96	VSC_SATA_INT_PHY_CHANGE),
7cbaa86b	97	};
c962990a	98
2ae5b30f	99	#define is_vsc_sata_int_err(port_idx, int_status) \
c962990a	100	(int_status & (VSC_SATA_INT_ERROR << (8 * port_idx)))
2ae5b30f	101
1da177e4 LT	102
	103	static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
	104	{
	105	if (sc_reg > SCR_CONTROL)
	106	return 0xffffffffU;
307e4dc2	107	return readl((void __iomem ) ap->ioaddr.scr_addr + (sc_reg 4));
1da177e4 LT	108	}
	109
	110
	111	static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
	112	u32 val)
	113	{
	114	if (sc_reg > SCR_CONTROL)
	115	return;
307e4dc2	116	writel(val, (void __iomem ) ap->ioaddr.scr_addr + (sc_reg 4));
1da177e4 LT	117	}
	118
	119
	120	static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
	121	{
307e4dc2	122	void __iomem *mask_addr;
1da177e4 LT	123	u8 mask;
1da177e4 LT	124
cca3974e	125	mask_addr = ap->host->mmio_base +
1da177e4 LT	126	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	127	mask = readb(mask_addr);
	128	if (ctl & ATA_NIEN)
	129	mask \|= 0x80;
	130	else
	131	mask &= 0x7F;
	132	writeb(mask, mask_addr);
	133	}
	134
	135
057ace5e	136	static void vsc_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	137	{
	138	struct ata_ioports *ioaddr = &ap->ioaddr;
	139	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	140
	141	/*
	142	* The only thing the ctl register is used for is SRST.
	143	* That is not enabled or disabled via tf_load.
	144	* However, if ATA_NIEN is changed, then we need to change the interrupt register.
	145	*/
	146	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
	147	ap->last_ctl = tf->ctl;
	148	vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	149	}
	150	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a JG	151	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
	152	(void __iomem *) ioaddr->feature_addr);
	153	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
	154	(void __iomem *) ioaddr->nsect_addr);
	155	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
	156	(void __iomem *) ioaddr->lbal_addr);
	157	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
	158	(void __iomem *) ioaddr->lbam_addr);
	159	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
	160	(void __iomem *) ioaddr->lbah_addr);
1da177e4	161	} else if (is_addr) {
850a9d8a JG	162	writew(tf->feature, (void __iomem *) ioaddr->feature_addr);
	163	writew(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
	164	writew(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
	165	writew(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
	166	writew(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
1da177e4 LT	167	}
	168
	169	if (tf->flags & ATA_TFLAG_DEVICE)
850a9d8a	170	writeb(tf->device, (void __iomem *) ioaddr->device_addr);
1da177e4 LT	171
	172	ata_wait_idle(ap);
	173	}
	174
	175
	176	static void vsc_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	177	{
	178	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	179	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	180
ac19bff2	181	tf->command = ata_check_status(ap);
850a9d8a JG	182	tf->device = readw((void __iomem *) ioaddr->device_addr);
	183	feature = readw((void __iomem *) ioaddr->error_addr);
	184	nsect = readw((void __iomem *) ioaddr->nsect_addr);
	185	lbal = readw((void __iomem *) ioaddr->lbal_addr);
	186	lbam = readw((void __iomem *) ioaddr->lbam_addr);
	187	lbah = readw((void __iomem *) ioaddr->lbah_addr);
ac19bff2 JG	188
	189	tf->feature = feature;
	190	tf->nsect = nsect;
	191	tf->lbal = lbal;
	192	tf->lbam = lbam;
	193	tf->lbah = lbah;
1da177e4 LT	194
1da177e4 LT	195	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	196	tf->hob_feature = feature >> 8;
1da177e4 LT	197	tf->hob_nsect = nsect >> 8;
	198	tf->hob_lbal = lbal >> 8;
	199	tf->hob_lbam = lbam >> 8;
	200	tf->hob_lbah = lbah >> 8;
	201	}
	202	}
	203
	204
	205	/*
	206	* vsc_sata_interrupt
	207	*
	208	* Read the interrupt register and process for the devices that have them pending.
	209	*/
7d12e780	210	static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
1da177e4	211	{
cca3974e	212	struct ata_host *host = dev_instance;
1da177e4 LT	213	unsigned int i;
	214	unsigned int handled = 0;
	215	u32 int_status;
	216
cca3974e	217	spin_lock(&host->lock);
1da177e4	218
cca3974e	219	int_status = readl(host->mmio_base + VSC_SATA_INT_STAT_OFFSET);
1da177e4	220
cca3974e	221	for (i = 0; i < host->n_ports; i++) {
1da177e4 LT	222	if (int_status & ((u32) 0xFF << (8 * i))) {
	223	struct ata_port *ap;
	224
cca3974e	225	ap = host->ports[i];
2ae5b30f DW	226
	227	if (is_vsc_sata_int_err(i, int_status)) {
	228	u32 err_status;
	229	printk(KERN_DEBUG "%s: ignoring interrupt(s)\n", __FUNCTION__);
	230	err_status = ap ? vsc_sata_scr_read(ap, SCR_ERROR) : 0;
	231	vsc_sata_scr_write(ap, SCR_ERROR, err_status);
	232	handled++;
	233	}
	234
029f5468	235	if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4 LT	236	struct ata_queued_cmd *qc;
	237
	238	qc = ata_qc_from_tag(ap, ap->active_tag);
e50362ec	239	if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1da177e4	240	handled += ata_host_intr(ap, qc);
84ac69e8	241	else if (is_vsc_sata_int_err(i, int_status)) {
c962990a	242	/*
2e9edbf8	243	* On some chips (i.e. Intel 31244), an error
c962990a DW	244	* interrupt will sneak in at initialization
	245	* time (phy state changes). Clearing the SCR
	246	* error register is not required, but it prevents
2e9edbf8	247	* the phy state change interrupts from recurring
c962990a DW	248	* later.
	249	*/
	250	u32 err_status;
	251	err_status = vsc_sata_scr_read(ap, SCR_ERROR);
	252	printk(KERN_DEBUG "%s: clearing interrupt, "
	253	"status %x; sata err status %x\n",
	254	__FUNCTION__,
	255	int_status, err_status);
	256	vsc_sata_scr_write(ap, SCR_ERROR, err_status);
	257	/* Clear interrupt status */
2ae5b30f DW	258	ata_chk_status(ap);
	259	handled++;
	260	}
1da177e4 LT	261	}
	262	}
	263	}
	264
cca3974e	265	spin_unlock(&host->lock);
1da177e4 LT	266
	267	return IRQ_RETVAL(handled);
	268	}
	269
	270
193515d5	271	static struct scsi_host_template vsc_sata_sht = {
1da177e4 LT	272	.module = THIS_MODULE,
	273	.name = DRV_NAME,
	274	.ioctl = ata_scsi_ioctl,
	275	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	276	.can_queue = ATA_DEF_QUEUE,
	277	.this_id = ATA_SHT_THIS_ID,
	278	.sg_tablesize = LIBATA_MAX_PRD,
1da177e4 LT	279	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	280	.emulated = ATA_SHT_EMULATED,
	281	.use_clustering = ATA_SHT_USE_CLUSTERING,
	282	.proc_name = DRV_NAME,
	283	.dma_boundary = ATA_DMA_BOUNDARY,
	284	.slave_configure = ata_scsi_slave_config,
ccf68c34	285	.slave_destroy = ata_scsi_slave_destroy,
1da177e4	286	.bios_param = ata_std_bios_param,
1da177e4 LT	287	};
	288
	289
057ace5e	290	static const struct ata_port_operations vsc_sata_ops = {
1da177e4 LT	291	.port_disable = ata_port_disable,
	292	.tf_load = vsc_sata_tf_load,
	293	.tf_read = vsc_sata_tf_read,
	294	.exec_command = ata_exec_command,
	295	.check_status = ata_check_status,
	296	.dev_select = ata_std_dev_select,
1da177e4 LT	297	.bmdma_setup = ata_bmdma_setup,
	298	.bmdma_start = ata_bmdma_start,
	299	.bmdma_stop = ata_bmdma_stop,
	300	.bmdma_status = ata_bmdma_status,
	301	.qc_prep = ata_qc_prep,
	302	.qc_issue = ata_qc_issue_prot,
a93620b8	303	.data_xfer = ata_mmio_data_xfer,
d7a80dad TH	304	.freeze = ata_bmdma_freeze,
	305	.thaw = ata_bmdma_thaw,
	306	.error_handler = ata_bmdma_error_handler,
	307	.post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4 LT	308	.irq_handler = vsc_sata_interrupt,
	309	.irq_clear = ata_bmdma_irq_clear,
	310	.scr_read = vsc_sata_scr_read,
	311	.scr_write = vsc_sata_scr_write,
	312	.port_start = ata_port_start,
1da177e4 LT	313	};
	314
	315	static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
	316	{
	317	port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
	318	port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
	319	port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
	320	port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
	321	port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
	322	port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
	323	port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
	324	port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
	325	port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
	326	port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
	327	port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
	328	port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	329	port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
	330	port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
	331	port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
850a9d8a JG	332	writel(0, (void __iomem *) base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
850a9d8a JG	333	writel(0, (void __iomem *) base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
1da177e4 LT	334	}
	335
	336
	337	static int __devinit vsc_sata_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	338	{
	339	static int printed_version;
	340	struct ata_probe_ent *probe_ent = NULL;
	341	unsigned long base;
307e4dc2	342	void __iomem *mmio_base;
1da177e4 LT	343	int rc;
	344
	345	if (!printed_version++)
a9524a76	346	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4	347
24dc5f33	348	rc = pcim_enable_device(pdev);
1da177e4 LT	349	if (rc)
	350	return rc;
	351
	352	/*
	353	* Check if we have needed resource mapped.
	354	*/
24dc5f33 TH	355	if (pci_resource_len(pdev, 0) == 0)
24dc5f33 TH	356	return -ENODEV;
1da177e4 LT	357
	358	rc = pci_request_regions(pdev, DRV_NAME);
	359	if (rc) {
24dc5f33 TH	360	pcim_pin_device(pdev);
24dc5f33 TH	361	return rc;
1da177e4 LT	362	}
	363
	364	/*
	365	* Use 32 bit DMA mask, because 64 bit address support is poor.
	366	*/
	367	rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
	368	if (rc)
24dc5f33	369	return rc;
1da177e4 LT	370	rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4 LT	371	if (rc)
24dc5f33	372	return rc;
7cbaa86b	373
24dc5f33 TH	374	probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
	375	if (probe_ent == NULL)
	376	return -ENOMEM;
1da177e4 LT	377	probe_ent->dev = pci_dev_to_dev(pdev);
	378	INIT_LIST_HEAD(&probe_ent->node);
	379
24dc5f33 TH	380	mmio_base = pcim_iomap(pdev, 0, 0);
	381	if (mmio_base == NULL)
	382	return -ENOMEM;
1da177e4 LT	383	base = (unsigned long) mmio_base;
	384
	385	/*
	386	* Due to a bug in the chip, the default cache line size can't be used
	387	*/
	388	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
	389
24dc5f33	390	if (pci_enable_msi(pdev) == 0)
7cbaa86b	391	pci_intx(pdev, 0);
7cbaa86b DW	392	else
	393	probe_ent->irq_flags = IRQF_SHARED;
	394
1da177e4	395	probe_ent->sht = &vsc_sata_sht;
cca3974e	396	probe_ent->port_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
d7a80dad	397	ATA_FLAG_MMIO;
1da177e4 LT	398	probe_ent->port_ops = &vsc_sata_ops;
	399	probe_ent->n_ports = 4;
	400	probe_ent->irq = pdev->irq;
1da177e4 LT	401	probe_ent->mmio_base = mmio_base;
	402
	403	/* We don't care much about the PIO/UDMA masks, but the core won't like us
	404	* if we don't fill these
	405	*/
	406	probe_ent->pio_mask = 0x1f;
	407	probe_ent->mwdma_mask = 0x07;
	408	probe_ent->udma_mask = 0x7f;
	409
	410	/* We have 4 ports per PCI function */
	411	vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
	412	vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
	413	vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
	414	vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
	415
	416	pci_set_master(pdev);
	417
8a60a071	418	/*
1da177e4 LT	419	* Config offset 0x98 is "Extended Control and Status Register 0"
	420	* Default value is (1 << 28). All bits except bit 28 are reserved in
	421	* DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
	422	* If bit 28 is clear, each port has its own LED.
	423	*/
	424	pci_write_config_dword(pdev, 0x98, 0);
	425
24dc5f33 TH	426	if (!ata_device_add(probe_ent))
24dc5f33 TH	427	return -ENODEV;
1da177e4	428
24dc5f33	429	devm_kfree(&pdev->dev, probe_ent);
1da177e4	430	return 0;
1da177e4 LT	431	}
1da177e4 LT	432
3b7d697d	433	static const struct pci_device_id vsc_sata_pci_tbl[] = {
438bc9c3	434	{ PCI_VENDOR_ID_VITESSE, 0x7174,
74d0a988	435	PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
438bc9c3	436	{ PCI_VENDOR_ID_INTEL, 0x3200,
74d0a988	437	PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
2d2744fc	438
438bc9c3	439	{ } /* terminate list */
1da177e4 LT	440	};
1da177e4 LT	441
1da177e4 LT	442	static struct pci_driver vsc_sata_pci_driver = {
	443	.name = DRV_NAME,
	444	.id_table = vsc_sata_pci_tbl,
	445	.probe = vsc_sata_init_one,
	446	.remove = ata_pci_remove_one,
	447	};
	448
1da177e4 LT	449	static int __init vsc_sata_init(void)
1da177e4 LT	450	{
b7887196	451	return pci_register_driver(&vsc_sata_pci_driver);
1da177e4 LT	452	}
1da177e4 LT	453
1da177e4 LT	454	static void __exit vsc_sata_exit(void)
	455	{
	456	pci_unregister_driver(&vsc_sata_pci_driver);
	457	}
	458
1da177e4 LT	459	MODULE_AUTHOR("Jeremy Higdon");
	460	MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
	461	MODULE_LICENSE("GPL");
	462	MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
	463	MODULE_VERSION(DRV_VERSION);
	464
	465	module_init(vsc_sata_init);
	466	module_exit(vsc_sata_exit);