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1da177e4 LT |
1 | /* |
2 | * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA | |
3 | * | |
4 | * Maintained by: Jeremy Higdon @ SGI | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004 SGI | |
9 | * | |
10 | * Bits from Jeff Garzik, Copyright RedHat, Inc. | |
11 | * | |
af36d7f0 JG |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2, or (at your option) | |
16 | * any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; see the file COPYING. If not, write to | |
25 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | * | |
27 | * | |
28 | * libata documentation is available via 'make {ps|pdf}docs', | |
29 | * as Documentation/DocBook/libata.* | |
30 | * | |
31 | * Vitesse hardware documentation presumably available under NDA. | |
32 | * Intel 31244 (same hardware interface) documentation presumably | |
33 | * available from http://developer.intel.com/ | |
34 | * | |
1da177e4 LT |
35 | */ |
36 | ||
37 | #include <linux/kernel.h> | |
38 | #include <linux/module.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/blkdev.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/interrupt.h> | |
7003c05d | 44 | #include <linux/dma-mapping.h> |
a9524a76 | 45 | #include <linux/device.h> |
1da177e4 LT |
46 | #include <scsi/scsi_host.h> |
47 | #include <linux/libata.h> | |
48 | ||
49 | #define DRV_NAME "sata_vsc" | |
2a3103ce | 50 | #define DRV_VERSION "2.3" |
1da177e4 | 51 | |
55cca65e | 52 | enum { |
0d5ff566 TH |
53 | VSC_MMIO_BAR = 0, |
54 | ||
55cca65e JG |
55 | /* Interrupt register offsets (from chip base address) */ |
56 | VSC_SATA_INT_STAT_OFFSET = 0x00, | |
57 | VSC_SATA_INT_MASK_OFFSET = 0x04, | |
1da177e4 | 58 | |
55cca65e JG |
59 | /* Taskfile registers offsets */ |
60 | VSC_SATA_TF_CMD_OFFSET = 0x00, | |
61 | VSC_SATA_TF_DATA_OFFSET = 0x00, | |
62 | VSC_SATA_TF_ERROR_OFFSET = 0x04, | |
63 | VSC_SATA_TF_FEATURE_OFFSET = 0x06, | |
64 | VSC_SATA_TF_NSECT_OFFSET = 0x08, | |
65 | VSC_SATA_TF_LBAL_OFFSET = 0x0c, | |
66 | VSC_SATA_TF_LBAM_OFFSET = 0x10, | |
67 | VSC_SATA_TF_LBAH_OFFSET = 0x14, | |
68 | VSC_SATA_TF_DEVICE_OFFSET = 0x18, | |
69 | VSC_SATA_TF_STATUS_OFFSET = 0x1c, | |
70 | VSC_SATA_TF_COMMAND_OFFSET = 0x1d, | |
71 | VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28, | |
72 | VSC_SATA_TF_CTL_OFFSET = 0x29, | |
1da177e4 | 73 | |
55cca65e JG |
74 | /* DMA base */ |
75 | VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64, | |
76 | VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C, | |
77 | VSC_SATA_DMA_CMD_OFFSET = 0x70, | |
1da177e4 | 78 | |
55cca65e JG |
79 | /* SCRs base */ |
80 | VSC_SATA_SCR_STATUS_OFFSET = 0x100, | |
81 | VSC_SATA_SCR_ERROR_OFFSET = 0x104, | |
82 | VSC_SATA_SCR_CONTROL_OFFSET = 0x108, | |
1da177e4 | 83 | |
55cca65e JG |
84 | /* Port stride */ |
85 | VSC_SATA_PORT_OFFSET = 0x200, | |
86 | ||
87 | /* Error interrupt status bit offsets */ | |
88 | VSC_SATA_INT_ERROR_CRC = 0x40, | |
89 | VSC_SATA_INT_ERROR_T = 0x20, | |
90 | VSC_SATA_INT_ERROR_P = 0x10, | |
91 | VSC_SATA_INT_ERROR_R = 0x8, | |
92 | VSC_SATA_INT_ERROR_E = 0x4, | |
93 | VSC_SATA_INT_ERROR_M = 0x2, | |
94 | VSC_SATA_INT_PHY_CHANGE = 0x1, | |
95 | VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \ | |
96 | VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \ | |
97 | VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \ | |
98 | VSC_SATA_INT_PHY_CHANGE), | |
7cbaa86b | 99 | }; |
c962990a | 100 | |
82ef04fb TH |
101 | static int vsc_sata_scr_read(struct ata_link *link, |
102 | unsigned int sc_reg, u32 *val) | |
1da177e4 LT |
103 | { |
104 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 | 105 | return -EINVAL; |
82ef04fb | 106 | *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 107 | return 0; |
1da177e4 LT |
108 | } |
109 | ||
110 | ||
82ef04fb TH |
111 | static int vsc_sata_scr_write(struct ata_link *link, |
112 | unsigned int sc_reg, u32 val) | |
1da177e4 LT |
113 | { |
114 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 | 115 | return -EINVAL; |
82ef04fb | 116 | writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 117 | return 0; |
1da177e4 LT |
118 | } |
119 | ||
120 | ||
ea34e45a DW |
121 | static void vsc_freeze(struct ata_port *ap) |
122 | { | |
123 | void __iomem *mask_addr; | |
124 | ||
125 | mask_addr = ap->host->iomap[VSC_MMIO_BAR] + | |
126 | VSC_SATA_INT_MASK_OFFSET + ap->port_no; | |
127 | ||
128 | writeb(0, mask_addr); | |
129 | } | |
130 | ||
131 | ||
132 | static void vsc_thaw(struct ata_port *ap) | |
133 | { | |
134 | void __iomem *mask_addr; | |
135 | ||
136 | mask_addr = ap->host->iomap[VSC_MMIO_BAR] + | |
137 | VSC_SATA_INT_MASK_OFFSET + ap->port_no; | |
138 | ||
139 | writeb(0xff, mask_addr); | |
140 | } | |
141 | ||
142 | ||
1da177e4 LT |
143 | static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl) |
144 | { | |
307e4dc2 | 145 | void __iomem *mask_addr; |
1da177e4 LT |
146 | u8 mask; |
147 | ||
0d5ff566 | 148 | mask_addr = ap->host->iomap[VSC_MMIO_BAR] + |
1da177e4 LT |
149 | VSC_SATA_INT_MASK_OFFSET + ap->port_no; |
150 | mask = readb(mask_addr); | |
151 | if (ctl & ATA_NIEN) | |
152 | mask |= 0x80; | |
153 | else | |
154 | mask &= 0x7F; | |
155 | writeb(mask, mask_addr); | |
156 | } | |
157 | ||
158 | ||
057ace5e | 159 | static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
160 | { |
161 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
162 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
163 | ||
164 | /* | |
165 | * The only thing the ctl register is used for is SRST. | |
166 | * That is not enabled or disabled via tf_load. | |
5796d1c4 JG |
167 | * However, if ATA_NIEN is changed, then we need to change |
168 | * the interrupt register. | |
1da177e4 LT |
169 | */ |
170 | if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) { | |
171 | ap->last_ctl = tf->ctl; | |
172 | vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN); | |
173 | } | |
174 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
850a9d8a | 175 | writew(tf->feature | (((u16)tf->hob_feature) << 8), |
0d5ff566 | 176 | ioaddr->feature_addr); |
850a9d8a | 177 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), |
0d5ff566 | 178 | ioaddr->nsect_addr); |
850a9d8a | 179 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), |
0d5ff566 | 180 | ioaddr->lbal_addr); |
850a9d8a | 181 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), |
0d5ff566 | 182 | ioaddr->lbam_addr); |
850a9d8a | 183 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), |
0d5ff566 | 184 | ioaddr->lbah_addr); |
1da177e4 | 185 | } else if (is_addr) { |
0d5ff566 TH |
186 | writew(tf->feature, ioaddr->feature_addr); |
187 | writew(tf->nsect, ioaddr->nsect_addr); | |
188 | writew(tf->lbal, ioaddr->lbal_addr); | |
189 | writew(tf->lbam, ioaddr->lbam_addr); | |
190 | writew(tf->lbah, ioaddr->lbah_addr); | |
1da177e4 LT |
191 | } |
192 | ||
193 | if (tf->flags & ATA_TFLAG_DEVICE) | |
0d5ff566 | 194 | writeb(tf->device, ioaddr->device_addr); |
1da177e4 LT |
195 | |
196 | ata_wait_idle(ap); | |
197 | } | |
198 | ||
199 | ||
200 | static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
201 | { | |
202 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
ac19bff2 | 203 | u16 nsect, lbal, lbam, lbah, feature; |
1da177e4 | 204 | |
9363c382 | 205 | tf->command = ata_sff_check_status(ap); |
0d5ff566 TH |
206 | tf->device = readw(ioaddr->device_addr); |
207 | feature = readw(ioaddr->error_addr); | |
208 | nsect = readw(ioaddr->nsect_addr); | |
209 | lbal = readw(ioaddr->lbal_addr); | |
210 | lbam = readw(ioaddr->lbam_addr); | |
211 | lbah = readw(ioaddr->lbah_addr); | |
ac19bff2 JG |
212 | |
213 | tf->feature = feature; | |
214 | tf->nsect = nsect; | |
215 | tf->lbal = lbal; | |
216 | tf->lbam = lbam; | |
217 | tf->lbah = lbah; | |
1da177e4 LT |
218 | |
219 | if (tf->flags & ATA_TFLAG_LBA48) { | |
ac19bff2 | 220 | tf->hob_feature = feature >> 8; |
1da177e4 LT |
221 | tf->hob_nsect = nsect >> 8; |
222 | tf->hob_lbal = lbal >> 8; | |
223 | tf->hob_lbam = lbam >> 8; | |
224 | tf->hob_lbah = lbah >> 8; | |
5796d1c4 | 225 | } |
1da177e4 LT |
226 | } |
227 | ||
ea34e45a DW |
228 | static inline void vsc_error_intr(u8 port_status, struct ata_port *ap) |
229 | { | |
230 | if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M)) | |
231 | ata_port_freeze(ap); | |
232 | else | |
233 | ata_port_abort(ap); | |
234 | } | |
235 | ||
236 | static void vsc_port_intr(u8 port_status, struct ata_port *ap) | |
237 | { | |
238 | struct ata_queued_cmd *qc; | |
239 | int handled = 0; | |
240 | ||
241 | if (unlikely(port_status & VSC_SATA_INT_ERROR)) { | |
242 | vsc_error_intr(port_status, ap); | |
243 | return; | |
244 | } | |
245 | ||
9af5c9c9 | 246 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
ea34e45a | 247 | if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING))) |
9363c382 | 248 | handled = ata_sff_host_intr(ap, qc); |
ea34e45a DW |
249 | |
250 | /* We received an interrupt during a polled command, | |
251 | * or some other spurious condition. Interrupt reporting | |
252 | * with this hardware is fairly reliable so it is safe to | |
253 | * simply clear the interrupt | |
254 | */ | |
255 | if (unlikely(!handled)) | |
5682ed33 | 256 | ap->ops->sff_check_status(ap); |
ea34e45a | 257 | } |
1da177e4 LT |
258 | |
259 | /* | |
260 | * vsc_sata_interrupt | |
261 | * | |
5796d1c4 JG |
262 | * Read the interrupt register and process for the devices that have |
263 | * them pending. | |
1da177e4 | 264 | */ |
5796d1c4 | 265 | static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance) |
1da177e4 | 266 | { |
cca3974e | 267 | struct ata_host *host = dev_instance; |
1da177e4 LT |
268 | unsigned int i; |
269 | unsigned int handled = 0; | |
ea34e45a | 270 | u32 status; |
1da177e4 | 271 | |
ea34e45a | 272 | status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET); |
1da177e4 | 273 | |
ea34e45a DW |
274 | if (unlikely(status == 0xffffffff || status == 0)) { |
275 | if (status) | |
276 | dev_printk(KERN_ERR, host->dev, | |
277 | ": IRQ status == 0xffffffff, " | |
278 | "PCI fault or device removal?\n"); | |
279 | goto out; | |
280 | } | |
1da177e4 | 281 | |
ea34e45a | 282 | spin_lock(&host->lock); |
2ae5b30f | 283 | |
ea34e45a DW |
284 | for (i = 0; i < host->n_ports; i++) { |
285 | u8 port_status = (status >> (8 * i)) & 0xff; | |
286 | if (port_status) { | |
3e4ec344 TH |
287 | vsc_port_intr(port_status, host->ports[i]); |
288 | handled++; | |
1da177e4 LT |
289 | } |
290 | } | |
291 | ||
cca3974e | 292 | spin_unlock(&host->lock); |
ea34e45a | 293 | out: |
1da177e4 LT |
294 | return IRQ_RETVAL(handled); |
295 | } | |
296 | ||
297 | ||
193515d5 | 298 | static struct scsi_host_template vsc_sata_sht = { |
68d1d07b | 299 | ATA_BMDMA_SHT(DRV_NAME), |
1da177e4 LT |
300 | }; |
301 | ||
302 | ||
029cfd6b TH |
303 | static struct ata_port_operations vsc_sata_ops = { |
304 | .inherits = &ata_bmdma_port_ops, | |
c96f1732 AC |
305 | /* The IRQ handling is not quite standard SFF behaviour so we |
306 | cannot use the default lost interrupt handler */ | |
307 | .lost_interrupt = ATA_OP_NULL, | |
5682ed33 TH |
308 | .sff_tf_load = vsc_sata_tf_load, |
309 | .sff_tf_read = vsc_sata_tf_read, | |
ea34e45a DW |
310 | .freeze = vsc_freeze, |
311 | .thaw = vsc_thaw, | |
1da177e4 LT |
312 | .scr_read = vsc_sata_scr_read, |
313 | .scr_write = vsc_sata_scr_write, | |
1da177e4 LT |
314 | }; |
315 | ||
0d5ff566 TH |
316 | static void __devinit vsc_sata_setup_port(struct ata_ioports *port, |
317 | void __iomem *base) | |
1da177e4 LT |
318 | { |
319 | port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET; | |
320 | port->data_addr = base + VSC_SATA_TF_DATA_OFFSET; | |
321 | port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET; | |
322 | port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET; | |
323 | port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET; | |
324 | port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET; | |
325 | port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET; | |
326 | port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET; | |
327 | port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET; | |
328 | port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET; | |
329 | port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET; | |
330 | port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET; | |
331 | port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET; | |
332 | port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET; | |
333 | port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET; | |
0d5ff566 TH |
334 | writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET); |
335 | writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET); | |
1da177e4 LT |
336 | } |
337 | ||
338 | ||
5796d1c4 JG |
339 | static int __devinit vsc_sata_init_one(struct pci_dev *pdev, |
340 | const struct pci_device_id *ent) | |
1da177e4 | 341 | { |
4447d351 TH |
342 | static const struct ata_port_info pi = { |
343 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
344 | ATA_FLAG_MMIO, | |
14bdef98 EIB |
345 | .pio_mask = ATA_PIO4, |
346 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 347 | .udma_mask = ATA_UDMA6, |
4447d351 TH |
348 | .port_ops = &vsc_sata_ops, |
349 | }; | |
350 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
1da177e4 | 351 | static int printed_version; |
4447d351 | 352 | struct ata_host *host; |
307e4dc2 | 353 | void __iomem *mmio_base; |
4447d351 | 354 | int i, rc; |
7de970e1 | 355 | u8 cls; |
1da177e4 LT |
356 | |
357 | if (!printed_version++) | |
a9524a76 | 358 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 359 | |
4447d351 TH |
360 | /* allocate host */ |
361 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4); | |
362 | if (!host) | |
363 | return -ENOMEM; | |
364 | ||
24dc5f33 | 365 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
366 | if (rc) |
367 | return rc; | |
368 | ||
4447d351 | 369 | /* check if we have needed resource mapped */ |
24dc5f33 TH |
370 | if (pci_resource_len(pdev, 0) == 0) |
371 | return -ENODEV; | |
1da177e4 | 372 | |
4447d351 | 373 | /* map IO regions and intialize host accordingly */ |
0d5ff566 TH |
374 | rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME); |
375 | if (rc == -EBUSY) | |
24dc5f33 | 376 | pcim_pin_device(pdev); |
0d5ff566 | 377 | if (rc) |
24dc5f33 | 378 | return rc; |
4447d351 TH |
379 | host->iomap = pcim_iomap_table(pdev); |
380 | ||
381 | mmio_base = host->iomap[VSC_MMIO_BAR]; | |
382 | ||
cbcdd875 TH |
383 | for (i = 0; i < host->n_ports; i++) { |
384 | struct ata_port *ap = host->ports[i]; | |
385 | unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET; | |
386 | ||
387 | vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset); | |
388 | ||
389 | ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio"); | |
390 | ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port"); | |
391 | } | |
1da177e4 LT |
392 | |
393 | /* | |
394 | * Use 32 bit DMA mask, because 64 bit address support is poor. | |
395 | */ | |
284901a9 | 396 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 397 | if (rc) |
24dc5f33 | 398 | return rc; |
284901a9 | 399 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 400 | if (rc) |
24dc5f33 | 401 | return rc; |
7cbaa86b | 402 | |
1da177e4 | 403 | /* |
7de970e1 ND |
404 | * Due to a bug in the chip, the default cache line size can't be |
405 | * used (unless the default is non-zero). | |
1da177e4 | 406 | */ |
7de970e1 ND |
407 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls); |
408 | if (cls == 0x00) | |
409 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80); | |
1da177e4 | 410 | |
24dc5f33 | 411 | if (pci_enable_msi(pdev) == 0) |
7cbaa86b | 412 | pci_intx(pdev, 0); |
1da177e4 | 413 | |
8a60a071 | 414 | /* |
1da177e4 LT |
415 | * Config offset 0x98 is "Extended Control and Status Register 0" |
416 | * Default value is (1 << 28). All bits except bit 28 are reserved in | |
417 | * DPA mode. If bit 28 is set, LED 0 reflects all ports' activity. | |
418 | * If bit 28 is clear, each port has its own LED. | |
419 | */ | |
420 | pci_write_config_dword(pdev, 0x98, 0); | |
421 | ||
4447d351 TH |
422 | pci_set_master(pdev); |
423 | return ata_host_activate(host, pdev->irq, vsc_sata_interrupt, | |
424 | IRQF_SHARED, &vsc_sata_sht); | |
1da177e4 LT |
425 | } |
426 | ||
3b7d697d | 427 | static const struct pci_device_id vsc_sata_pci_tbl[] = { |
438bc9c3 | 428 | { PCI_VENDOR_ID_VITESSE, 0x7174, |
74d0a988 | 429 | PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 }, |
438bc9c3 | 430 | { PCI_VENDOR_ID_INTEL, 0x3200, |
74d0a988 | 431 | PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 }, |
2d2744fc | 432 | |
438bc9c3 | 433 | { } /* terminate list */ |
1da177e4 LT |
434 | }; |
435 | ||
1da177e4 LT |
436 | static struct pci_driver vsc_sata_pci_driver = { |
437 | .name = DRV_NAME, | |
438 | .id_table = vsc_sata_pci_tbl, | |
439 | .probe = vsc_sata_init_one, | |
440 | .remove = ata_pci_remove_one, | |
441 | }; | |
442 | ||
1da177e4 LT |
443 | static int __init vsc_sata_init(void) |
444 | { | |
b7887196 | 445 | return pci_register_driver(&vsc_sata_pci_driver); |
1da177e4 LT |
446 | } |
447 | ||
1da177e4 LT |
448 | static void __exit vsc_sata_exit(void) |
449 | { | |
450 | pci_unregister_driver(&vsc_sata_pci_driver); | |
451 | } | |
452 | ||
1da177e4 LT |
453 | MODULE_AUTHOR("Jeremy Higdon"); |
454 | MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller"); | |
455 | MODULE_LICENSE("GPL"); | |
456 | MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl); | |
457 | MODULE_VERSION(DRV_VERSION); | |
458 | ||
459 | module_init(vsc_sata_init); | |
460 | module_exit(vsc_sata_exit); |